Display device

Abstract

A display device is disclosed, comprising: a substrate, the substrate including a display area and a non-display area surrounding the display area, a plurality of sub-pixels arranged in the display area, and the display area including a first non-light-emitting area and a light-emitting area; wiring disposed on the substrate; and a first reflective portion disposed on the substrate, wherein the wiring partially overlaps with the first non-light-emitting area and the light-emitting area, and the first reflective portion is located in the first non-light-emitting area. The display device of the present invention can extract light even in the first non-light-emitting area through the first reflective portion, therefore, even if the wiring partially overlaps with the first non-light-emitting area and the light-emitting area, the light efficiency is not reduced.

Description

[0001] Cross-reference to related applications

[0002] This application claims the benefit of Korean Patent Application No. 10-2024-0197394, filed on December 26, 2024, which is incorporated herein by reference as if fully set forth herein. Technical Field

[0003] This invention relates to a display device for displaying images. Background Technology

[0004] Organic light-emitting displays (OLEDs) have attracted attention as the next generation of flat panel displays due to their high response speed and low power consumption. Unlike liquid crystal displays (LCDs), they do not require a separate light source but are self-emissive, thus eliminating viewing angle issues.

[0005] The display device includes multiple sub-pixels, and each sub-pixel includes a light-emitting element layer disposed in a light-emitting area. The display device displays an image by emitting light from the light-emitting element layer.

[0006] Meanwhile, display devices have wiring for driving each of the multiple sub-pixels in the circuit area adjacent to the light-emitting area. This is because when wiring is placed in the light-emitting area, the size (or area) of the light-emitting area becomes smaller, thereby reducing luminous efficiency. Therefore, display devices are limited in terms of increasing the size (or area) of the light-emitting area due to wiring, which limits the improvement of luminous efficiency. Summary of the Invention

[0007] One aspect of the present invention aims to provide a display device in which the size (or area) of the light-emitting region can be enlarged.

[0008] One aspect of the present invention aims to provide a display device capable of improving light efficiency.

[0009] One aspect of the present invention aims to provide a display device in which the light extraction efficiency of light emitted from a light-emitting element layer can be improved.

[0010] One aspect of the present invention aims to provide a display device in which the light extraction efficiency of light emitted from a light-emitting element layer can be maximized.

[0011] One aspect of the present invention aims to provide a display device in which total power consumption can be reduced by extracting light in non-light-emitting areas.

[0012] The problems solved by the embodiments of the present invention are not limited to those described above. Other problems not mentioned above will become clear to those skilled in the art based on the following description.

[0013] In one aspect, a display device is provided, comprising: a substrate including a display area and a non-display area surrounding the display area, wherein a plurality of sub-pixels are arranged in the display area, and the display area includes a first non-light-emitting area and a light-emitting area; wiring disposed on the substrate; and a first reflective portion disposed on the substrate, wherein the wiring may partially overlap with the first non-light-emitting area and the light-emitting area, and the first reflective portion may be located in the first non-light-emitting area.

[0014] In another aspect, a display device is provided, comprising: a substrate including a plurality of pixels having a plurality of sub-pixels, the substrate including a light-emitting region disposed in each of the plurality of sub-pixels; and wiring partially overlapping the light-emitting region, wherein the substrate may further include a second non-light-emitting region located on the outer side of each of the plurality of sub-pixels, wherein the second non-light-emitting region may include: a first planarization layer disposed on the substrate; a second planarization layer disposed on the first planarization layer; a second patterned portion recessed on the second planarization layer; and a second reflective portion disposed on the second patterned portion.

[0015] The technical benefits of the present invention are not limited to those described above, and other benefits not mentioned above will be clearly understood by those skilled in the art from the following description. Attached Figure Description

[0016] The accompanying drawings, which provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. In the drawings:

[0017] Figure 1 This is a schematic plan view of a display device according to an embodiment of the present invention.

[0018] Figure 2 yes Figure 1 A schematic planar view of a single pixel is shown.

[0019] Figure 3 It is along Figure 2 The schematic cross-sectional view shown is taken along line I-I'.

[0020] Figure 4 It is along Figure 2 The schematic cross-sectional view shown is taken from line II-II'.

[0021] Figure 5 This is a schematic plan view showing a sub-pixel of a display device according to a comparative example.

[0022] Figure 6This is a schematic plan view showing a sub-pixel of a display device according to a first embodiment of the present invention.

[0023] Figure 7 This is a schematic plan view showing a sub-pixel of a display device according to a second embodiment of the present invention.

[0024] Figure 8 This is a schematic plan view showing a sub-pixel of a display device according to a third embodiment of the present invention.

[0025] Figure 9 This is a schematic plan view showing a sub-pixel of a display device according to a fourth embodiment of the present invention. Detailed Implementation

[0026] Referring now to embodiments of the invention, some examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numerals will be used throughout the drawings to refer to the same or similar parts. The advantages and features of the invention, and its implementation methods, will be elucidated by the following embodiments described with reference to the accompanying drawings.

[0027] However, the present invention may be implemented in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that the disclosure of the present invention will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

[0028] The shapes, sizes, proportions, angles, and quantities disclosed in the accompanying drawings used to describe embodiments of the present invention are merely examples, and therefore the present invention is not limited to the illustrated details.

[0029] Similar reference numerals refer to similar elements throughout. In the following description, detailed descriptions of related known functions or constructions will be omitted if it is determined that such detailed descriptions would unnecessarily obscure the focus of the invention.

[0030] In cases where terms such as "comprising," "having," or "including" are used as described in this invention, additional parts may be added unless "only" is used. Singular terms may include plural forms unless otherwise specified.

[0031] When interpreting elements, elements are interpreted to include a margin of error, even if not explicitly described. When describing positional relationships, such as when the positional relationship between two parts is described as "on," "above," "below," or "beside," one or more additional parts may be placed between these two parts, unless "exactly" or "directly" is used.

[0032] When describing temporal relationships, such as when time sequence is described as “after,” “following,” “next,” or “before,” discontinuous situations may be included unless “exactly” or “directly” is used.

[0033] It will be understood that although the terms “first,” “second,” etc., may be used in this document to describe the elements, these elements should not be limited by these terms.

[0034] These terms are used only to distinguish one element from other elements. For example, without departing from the scope of the invention, the first element may be referred to as the second element, and similarly, the second element may be referred to as the first element.

[0035] The “X-axis direction,” “Y-axis direction,” and “Z-axis direction” should not be interpreted solely by their geometric relationship of being perpendicular to each other, but rather can have a wider range of directions within the functional range of the elements of the present invention.

[0036] The term “at least one” should be understood as any and all combinations including one or more of the relevant listed items.

[0037] For example, "at least one of the first, second and third items" means: a combination of all items proposed from two or more of the first, second and third items; and the first, second or third item.

[0038] The features of the various embodiments of the present invention can be combined or integrated with each other, either partially or entirely, and can be technically interoperable and driven in various ways, as will be fully understood by those skilled in the art. The embodiments of the present invention can be implemented independently of each other, or can be implemented together in a mutually dependent relationship.

[0039] In the following, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0040] Figure 1 This is a schematic plan view of a display device according to an embodiment of the present invention. Figure 2 yes Figure 1 A schematic planar view of a single pixel is shown.

[0041] In the following text, the first direction (Y-axis direction) refers to... Figure 1 The vertical direction, the second direction (X-axis direction) represents the direction based on Figure 1 The horizontal direction, and the third direction (Z-axis direction) represents the thickness direction of the display device 100. The first direction (Y-axis direction) can be related to the data cabling DL (…). Figure 2 The direction is parallel to or perpendicular to the upper surface of the substrate 110 (as shown). The second direction (X-axis direction) can be parallel to or perpendicular to the upper surface of the gate wiring GL (as shown). Figure 2 (as shown) in a direction parallel to or parallel to the upper surface of the substrate 110.

[0042] Reference Figure 1 A display device 100 according to one embodiment of the present invention may include a display panel having a gate driver GD. The display panel may include a substrate 110 and an opposing substrate 200 bonded to each other. Figure 4 (as shown in the image).

[0043] According to one example, substrate 110 may include a display area DA and a non-display area NDA surrounding the display area DA, wherein a plurality of pixels P having a plurality of sub-pixels SP are arranged in the display area DA. Substrate 110 may also include a first non-light-emitting area NEA1, a light-emitting area EA, and wiring 120. The first non-light-emitting area NEA1, the light-emitting area EA, and wiring 120 may be disposed in the display area DA of substrate 110.

[0044] According to one example, a first non-light-emitting region NEA1 is disposed on the substrate 110, and may be disposed inside each of the plurality of sub-pixels SP. For example, as Figure 2 As shown, the first non-emitting region NEA1 can be disposed inside the emitting region EA of each of the plurality of sub-pixels SP. Therefore, the emitting region EA can be configured to be adjacent to the first non-emitting region NEA1. According to one example, wiring 120 can partially overlap with each of the first non-emitting region NEA1 and the emitting region EA.

[0045] In typical display devices, a non-light-emitting area is not provided inside each of the multiple sub-pixels (or inside the light-emitting area). If a non-light-emitting area is provided inside each of the multiple sub-pixels (or inside the light-emitting area), the size (or area) of the light-emitting area becomes smaller, thereby reducing luminous efficiency.

[0046] In contrast, even in the first non-light-emitting area NEA1 inside each of the plurality of sub-pixels SP, the display device 100 according to an embodiment of the present invention can also be illuminated by the first reflective portion 150 (in Figure 4 (As shown in the diagram) it has light extraction, thus not reducing light efficiency. Therefore, a display device 100 according to an embodiment of the present invention may have the following structural features: a first non-light-emitting area NEA1 is arranged on the inner side of each of a plurality of sub-pixels SP.

[0047] Furthermore, in typical display devices, if wiring is placed within the light-emitting area, the size (or area) of that area becomes smaller, which reduces luminous efficiency. Therefore, the wiring is placed within the circuit area. Consequently, in typical display devices, the wiring does not overlap with the light-emitting area.

[0048] In contrast, since the display device 100 according to an embodiment of the present invention can extract light even in the first non-light-emitting area NEA1 through the first reflective portion 150, the light efficiency will not be reduced even if the wiring 120 partially overlaps with the first non-light-emitting area NEA1 and the light-emitting area EA.

[0049] Furthermore, according to one embodiment of the present invention, the display device 100 is configured such that the wiring 120 partially overlaps with the light-emitting area EA and the non-light-emitting first non-light-emitting area NEA1, thereby reducing the size (or area) of the circuit area compared to a general display device, and thus allowing the size (or area) of the light-emitting area EA to be relatively enlarged (or expanded). Therefore, due to the increased size (or area) of the light-emitting area EA, the display device 100 according to one embodiment of the present invention can have improved light efficiency. Referring later... Figures 5 to 9 Provide a detailed description.

[0050] Reference Figure 1 According to one embodiment of the present invention, the display device 100 may include a source driver integrated circuit (hereinafter referred to as "IC") 170, a flexible film 171, a circuit board 180 and a timing control unit 181.

[0051] The substrate 110 may include thin-film transistors and may be a transistor array substrate, a lower substrate, a base substrate, or a first substrate. The substrate 110 may be a transparent glass substrate or a transparent plastic substrate.

[0052] The opposing substrate 200 can be bonded to the substrate 110 via an adhesive member. For example, the opposing substrate 200 has a smaller size than the substrate 110 and can be bonded to the portion of the substrate 110 other than the pad portion. The opposing substrate 200 can be an upper substrate, a second substrate, or a package substrate.

[0053] The gate driver GD provides a gate signal to the gate wiring according to the gate control signal input from the timing control unit 181. When the source driver IC170 is manufactured as a driver chip, the source driver IC170 can be packaged in a flexible film 171 according to the chip-on-film (COF) method or the chip-on-plastic (COP) method.

[0054] Pads, such as data pads, can be formed in the non-display area of ​​the display panel. Lines connecting the pads to the source driver IC 170 and lines connecting the pads to the circuit board 180 can be formed in the flexible film 171. The flexible film 171 can be attached to the pads using an anisotropic conductive film, thereby allowing the pads to be connected to the lines of the flexible film 171.

[0055] Reference Figure 1 According to one example, substrate 110 may include a display area DA and a non-display area NDA.

[0056] The display area DA is the area where images are displayed, and it can be a pixel array area, an active area, a pixel array unit, a display unit, or a screen. For example, the display area DA can be located in the center of the display panel.

[0057] According to one example, a display area DA may include gate wiring, data wiring, pixel power wiring, and a plurality of pixels P. Each of the plurality of pixels P may include a plurality of sub-pixels SP, which may be defined by the gate wiring and the data wiring. Each of the plurality of sub-pixels SP may be defined as the smallest unit area that emits actual light.

[0058] According to one example, at least four sub-pixels SP that are arranged adjacently and configured to emit light of different colors constitute a unit pixel P. A unit pixel may include, but is not limited to, red sub-pixels, green sub-pixels, blue sub-pixels, and white sub-pixels.

[0059] Each of the plurality of sub-pixels SP may include a thin-film transistor and an organic light-emitting element connected to the thin-film transistor. The sub-pixel may include an organic light-emitting layer (or light-emitting layer) inserted between a first electrode and a second electrode.

[0060] The organic light-emitting layers arranged in each of the multiple sub-pixels SP can individually emit different colors of light or collectively emit white light. For example, when the organic light-emitting layers of each of the multiple sub-pixels SP collectively emit white light, each of the red, green, and blue sub-pixels may include a color filter CF (or wavelength conversion member CF) that converts white light into different colors of light. In this case, according to one example, the white sub-pixel may not have a color filter. According to one example, the color filter CF may include a red color filter CF1 (…). Figure 4 As shown), blue filter CF2 ( Figure 4 (shown) and a green color filter (not shown).

[0061] In a display device 100 according to one embodiment of the present invention, the area provided with a red color filter CF1 may be a red sub-pixel SP1, the area provided with a blue color filter CF2 may be a blue sub-pixel SP3, the area provided with a green color filter may be a green sub-pixel SP4, and the area without a color filter may be a white sub-pixel SP2. In the present invention, the red sub-pixel SP1 may be represented as a first sub-pixel equipped to emit red light, the blue sub-pixel SP3 may be represented as a third sub-pixel equipped to emit blue light, the green sub-pixel SP4 may be represented as a fourth sub-pixel equipped to emit green light, and the white sub-pixel SP2 may be represented as a second sub-pixel equipped to emit white light.

[0062] When a gate signal is input from the gate wiring using a thin-film transistor, each of the sub-pixels SP provides a predetermined current to the organic light-emitting element according to the data voltage of the data wiring. Therefore, the light-emitting layer of each sub-pixel can emit light with a predetermined brightness according to the predetermined current.

[0063] Figure 3 It is along Figure 2 The schematic cross-sectional view shown is taken along line I-I'. Figure 4 It is along Figure 2 The schematic cross-sectional view shown is taken from line II-II'.

[0064] like Figure 2 and Figure 3 As shown, the display area DA may include a light-emitting area EA and a non-light-emitting area NEA. The light-emitting area EA is the region where the organic light-emitting element layer E emits light. The non-light-emitting area NEA is the region that does not transmit most of the light incident from the outside.

[0065] For example, the non-emitting region NEA can be a region that does not include the emitting region EA. In one example, the non-emitting region NEA may include the circuit region CA (in... Figure 3 (As shown in the figure). The circuit region CA may include a thin-film transistor 112 for driving each of the plurality of sub-pixels SP (or the organic light-emitting element layer E of each of the plurality of sub-pixels SP).

[0066] In a display device 100 according to one embodiment of the present invention, the non-light-emitting area NEA may include a first non-light-emitting area NEA1 and a second non-light-emitting area NEA2.

[0067] According to one example, the first non-luminescent area NEA1 can be set inside each of the plurality of sub-pixels SP. For example, as Figure 2 As shown, the inner side of each of the multiple sub-pixels SP can represent the inner side of the light-emitting region EA included in a sub-pixel SP. The organic light-emitting element layer E (such as...) Figure 4 (As shown) can be omitted from the first non-luminous region NEA1.

[0068] According to one example, the second non-luminescent area NEA2 can be set on the outer side of each of the multiple sub-pixels SP. For example, as Figure 2 As shown, the outer side of each of the plurality of sub-pixels SP can represent the outer side of the light-emitting region EA. The outer side of each of the plurality of sub-pixels SP can include a circuit region CA adjacent to the light-emitting region EA. In addition, the outer side of each of the plurality of sub-pixels SP can include the region between the plurality of sub-pixels SP emitting light of different colors (e.g., the pixel electrode 114 of each of the first sub-pixel SP1 and the second sub-pixel SP2).

[0069] Additionally, within the non-light-emitting area NEA, multiple pixels P and multiple lines for driving each of the multiple pixels P can be configured. According to one example, the multiple lines may include multiple first signal lines and multiple second signal lines.

[0070] Multiple first signal lines may extend in a second direction (X-axis direction). Each of the multiple first signal lines may include at least one gate wiring GL (or scan line) and a reference wiring RL.

[0071] Multiple second signal lines may extend in a first direction (Y-axis direction). These multiple second signal lines may intersect with multiple first signal lines. Each of the multiple second signal lines may include a pixel power supply line EVDD, multiple data lines DL, and a reference line RL. The multiple data lines DL may include a first data line DL1 for driving a first sub-pixel SP1, a second data line DL2 for driving a second sub-pixel SP2, a third data line DL3 for driving a third sub-pixel SP3, and a fourth data line DL4 for driving a fourth sub-pixel SP4.

[0072] Return to reference Figure 1 The non-display area NDA is the area where no image is displayed, and it can be a peripheral circuit area, a signal supply area, a non-active area, or a border area. The non-display area NDA can be configured to be located near the display area DA. That is, the non-display area NDA can be set to surround the display area DA.

[0073] A display device 100 according to one embodiment of the present invention may include a pad portion PA disposed in a non-display area NDA. The pad portion PA can be used to drive a plurality of pixels P. For example, the pad portion PA can provide power and / or signals to a plurality of pixels P disposed in the display area DA to output an image.

[0074] Based on one example, the pad portion (PA) can be based on Figure 1 It is placed in the non-display area NDA (or the first non-display area) above the display area DA. Since the first non-display area is formed above the display area DA, it can be described as the upper non-display area.

[0075] The gate driver GD provides a gate signal to the gate wiring according to the gate control signal input from the timing control unit 181. The gate driver GD can be formed on one side of the display area DA of the display panel, or formed on the non-display area NDA located outside the two sides of the display area DA according to the in-panel gate driver GIP method, such as... Figure 1 As shown.

[0076] Multiple gate drivers (GDs) are separately disposed on the left side (i.e., the second non-display area) and the right side (i.e., the third non-display area) of the display area DA. Since each of the second and third non-display areas is formed on the side of the display area DA, it can be described as a side non-display area.

[0077] According to one example, multiple gate drivers GD may be connected to multiple pixels P and multiple first signal lines for providing signals to the multiple pixels P. The multiple first signal lines may include at least one signal line for providing signals for driving the pixels P.

[0078] Multiple second signal lines may extend in a first direction (Y-axis direction). These multiple second signal lines may include a pixel power supply line EVDD and at least one data line DL to provide data voltage to pixel P. Each of the multiple second signal lines may be connected to at least one of multiple pads, a pixel power shorting bar, and a common power shorting bar. The pixel power shorting bar and the common power shorting bar may be arranged in a fourth non-display area based on the display area DA facing the pad portion PA. Since the fourth non-display area is formed below the display area DA, it can be described as a lower non-display area.

[0079] Pixel P is configured to overlap with at least one of the first signal line and the second signal line and emits predetermined light to display an image. The light-emitting area EA may correspond to the area emitting light within pixel P.

[0080] Reference Figure 3 The non-emitting area (NEA) can refer to the area within the display area (DA) that does not emit light, and can be described as a dead zone because it does not emit light. According to one example, a dead zone can be an area containing a black matrix and / or a dam, but is not limited to this, and can refer to any area that does not emit light.

[0081] According to one embodiment of the present invention, the display device 100 can reduce the size (or area) of the circuit region CA by arranging the wiring 120 in a first non-light-emitting region NEA1, which is a dead zone. Therefore, the display device 100 according to one embodiment of the present invention can reduce the size (or area) of the circuit region CA, thereby relatively increasing (or expanding) the size (or area) of the light-emitting region EA, thereby improving light efficiency.

[0082] According to one example, wiring 120 could be a data branch wiring that applies a data signal to thin-film transistor 112. Therefore, as... Figure 2 As shown, wiring 120 can be connected to each of the thin-film transistor 112 in the circuit region CA and the data wiring DL in the second non-light-emitting region NEA2. According to one example, wiring 120 may include a first wiring 121 and a second wiring 122.

[0083] like Figure 2 As shown, wiring 120 is connected to circuit region CA and can extend from circuit region CA toward reference wiring RL in a first direction (Y-axis direction). In this case, wiring 120 may partially overlap with the first non-light-emitting region NEA1 and the light-emitting region EA. For example, as Figure 2 As shown, the wiring 120 extending from the circuit area CA can sequentially pass through the light-emitting area EA (or the lower light-emitting area EA), the first non-light-emitting area NEA1, and the light-emitting area EA (or the upper light-emitting area EA), or sequentially overlap with the light-emitting area EA (or the lower light-emitting area EA), the first non-light-emitting area NEA1, and the light-emitting area EA (or the upper light-emitting area EA). The wiring 120 that sequentially passes through the light-emitting area EA, the first non-light-emitting area NEA1, and the light-emitting area EA (or sequentially overlaps with the light-emitting area EA, the first non-light-emitting area NEA1, and the light-emitting area EA) can be bent parallel to the reference wiring RL and connected to the data wiring DL (or the first data wiring DL1).

[0084] The first wiring 121 may be a wiring that partially overlaps with the first non-light-emitting area NEA1 and the light-emitting area EA. For example... Figure 2 As shown, the first wiring 121 can be a wiring arranged in a first direction (Y-axis direction). The second wiring 122 can be a wiring connected to the end of the first wiring 121 and connected to the data wiring DL (or the first data wiring DL1) in the second non-light-emitting area NEA2. That is, the second wiring 122 can be a wiring connected to the first wiring 121 and arranged in a direction different from the first wiring 121 (e.g., a second direction (X-axis direction)). The data wiring DL can be arranged between adjacent sub-pixels along the first direction (Y-axis direction), and the second wiring 122 can partially overlap with the data wiring DL.

[0085] In the following text, reference will be made to Figure 3 Describe in detail the structure of each of the multiple sub-pixels SP.

[0086] Reference Figure 3 According to one embodiment of the present invention, a display device 100 may include a buffer layer BL, a plurality of inorganic films 111, a thin film transistor 112, a color filter CF, a planarization layer 113, a pixel electrode 114, a dam 115, an organic light-emitting layer 116, a cathode 117, and an encapsulation layer 118.

[0087] Each sub-pixel SP according to one embodiment may include a plurality of inorganic films 111 disposed on the upper surface of the buffer layer BL, including a gate insulating layer 111a, an interlayer insulating layer 111b and a passivation layer 111c.

[0088] Furthermore, each sub-pixel SP may include a color filter CF disposed on a plurality of inorganic films 111, and a planarization layer 113 disposed on the color filter CF. The planarization layer 113 may include a first planarization layer 1131 and a second planarization layer 1132. The second planarization layer 1132 may be disposed on the first planarization layer 1131. The pixel electrode 114 may be disposed on the second planarization layer 1132.

[0089] Each sub-pixel SP may further include: a dam 115 covering one edge of the pixel electrode 114; an organic light-emitting layer 116 on the pixel electrode 114 and the dam 115; and a cathode 117 on the organic light-emitting layer 116. An encapsulation layer 118 may be placed on the cathode 117.

[0090] Thin-film transistors 112 used to drive sub-pixels SP can be arranged on multiple inorganic films 111. The multiple inorganic films 111 can also be represented by a layer of circuit elements.

[0091] The buffer layer BL may be included together with the gate insulating layer 111a, the interlayer insulating layer 111b, and the passivation layer 111c in a plurality of inorganic films 111. The pixel electrode 114, the organic light-emitting layer 116, and the cathode 117 may be included in the organic light-emitting element layer E.

[0092] A buffer layer BL may be formed between the substrate 110 and the gate insulating layer 111a to protect the thin-film transistor 112. The buffer layer BL may be disposed on the entire surface (or front surface) of the substrate 110. The buffer layer BL may be used to block the diffusion of material contained in the substrate 110 into the transistor layer during the high-temperature process of manufacturing the thin-film transistor 112.

[0093] The thin-film transistor 112 (or driving transistor) according to the example may include an active layer 112a, a gate 112b, a source 112c, and a drain 112d.

[0094] The active layer 112a may include a channel region, a drain region, and a source region formed in the thin-film transistor region of the circuit region CA of the sub-pixel SP. The drain region and the source region may be spaced apart from each other, with the channel region interposed therebetween.

[0095] The active layer 112a may be formed of a semiconductor material based on any one of amorphous silicon, polycrystalline silicon, oxide and organic materials.

[0096] The gate insulating layer 111a may be formed on the channel region of the active layer 112a. As an example, the gate insulating layer 111a may be formed in an island shape only on the channel region of the active layer 112a, or it may be formed on the entire front surface of the substrate 110 or the buffer layer BL that includes the active layer 112a.

[0097] The gate 112b may be formed on the gate insulating layer 111a to overlap with the channel region of the active layer 112a.

[0098] The interlayer insulating layer 111b can be formed to partially overlap with the gate 112b and the drain and source regions of the active layer 112a. The interlayer insulating layer 111b can be formed over the entire light-emitting region in the circuit region CA and the sub-pixel SP, such as... Figure 3 As shown.

[0099] The source electrode 112c can be electrically connected to the source region of the active layer 112a through a source contact hole disposed in the interlayer insulating layer that overlaps with the source region of the active layer 112a.

[0100] The drain 112d can be electrically connected to the drain region of the active layer 112a through a drain contact hole disposed in the interlayer insulating layer that overlaps with the drain region of the active layer 112a.

[0101] The drain 112d and the source 112c can be made of the same metallic material. For example, each of the drain 112d and the source 112c can be made of a single metal layer, a single alloy layer, or a multilayer of two or more layers, which may be the same as or different from the gate 112b.

[0102] In addition, the thin-film transistors disposed in the pixel area may have the characteristic that the threshold voltage is deflected by light. To prevent this, the display panel or substrate 110 may also include a light-shielding layer (LS) disposed under the active layer 112a of at least one of the thin-film transistors 112, the first switching thin-film transistor, and the second switching thin-film transistor.

[0103] A light-shielding layer (LS) is disposed between the substrate 110 and the active layer 112a to block light incident on the active layer 112a via the substrate 110, thereby minimizing the threshold voltage variation of the transistor caused by external light. Furthermore, the light-shielding layer (LS) may be disposed between the substrate 110 and the active layer 112a to prevent the thin-film transistor from being visible to the user.

[0104] A passivation layer 111c may be disposed on the substrate 110 to cover the pixel area. The passivation layer 111c covers the drain 112d, source 112c, and gate 112b of the thin-film transistor 112, as well as the buffer layer BL.

[0105] A color filter CF can be placed on the passivation layer 111c. For example, the color filter CF can be placed between multiple inorganic films 111 and the first planarization layer 1131. The color filter CF may include a red color filter CF1 arranged in the red sub-pixel SP1, a blue color filter CF2 arranged in the blue sub-pixel SP3, and a green color filter arranged in the green sub-pixel SP4. Since the white sub-pixel SP2 is configured to emit white light, it may not include a color filter.

[0106] A planarization layer 113 may be disposed on the substrate 110 to cover the passivation layer 111c and the color filter CF. According to one example, the planarization layer 113 may be placed between the substrate 110 and the pixel electrode 114. The planarization layer 113 may be formed in the entire circuit region CA and the entire light-emitting region EA in which the thin-film transistor 112 is disposed. Furthermore, the planarization layer 113 may be formed in other non-display regions NDA except for the pad portion PA of the non-display region NDA, as well as in the entire display region DA. For example, the planarization layer 113 may include an extension (or extension) extending or expanding from the display region DA into other non-display regions NDA except for the pad portion PA. Therefore, the size of the planarization layer 113 may be relatively wider than the size of the display region DA.

[0107] According to one example, the planarization layer 113 can be formed to have a relatively thick thickness, thereby providing a flat surface on the display area DA and the non-display area NDA. For example, the planarization layer 113 can be made of organic materials such as photo acrylic, benzocyclobutene, polyimide, and fluoropolymers.

[0108] The planarization layer 113 may include a first planarization layer 1131 and a second planarization layer 1132 disposed on the first planarization layer 1131. The first planarization layer 1131 may be disposed on the substrate 110. The second planarization layer 1132 may be disposed on the first planarization layer 1131. According to one example, the second planarization layer 1132 may be disposed between the first planarization layer 1131 and the pixel electrode 114.

[0109] like Figure 4 As shown, the first planarization layer 1131 is configured to cover the passivation layer 111c and the color filter CF, allowing it to be formed continuously across multiple sub-pixels SP. In contrast, the second planarization layer 1132 can be formed discontinuously by forming a first pattern portion 130 on the inner side of the multiple sub-pixels SP and a second pattern portion 140 on the outer side of the multiple sub-pixels SP (or between the multiple sub-pixels SP). Therefore, as... Figure 4 As shown, multiple second planarization layers 1132 can be arranged in an island-like manner on the first planarization layer 1131.

[0110] Reference Figure 3 and Figure 4The upper surface of the second planarization layer 1132 can be provided to be flat. Therefore, the pixel electrode 114 on the second planarization layer 1132 can also be provided as flat, and the organic light-emitting layer 116 and the cathode 117 formed thereon can also be provided in a flat form. Since the pixel electrode 114, the organic light-emitting layer 116, and the cathode 117 (i.e., the organic light-emitting element layer E) are disposed flatly in the light-emitting region EA, the thickness of the pixel electrode 114, the organic light-emitting layer 116, and the cathode 117 can be uniformly formed inside the light-emitting region EA. Therefore, the organic light-emitting layer 116 can emit light uniformly inside the light-emitting region EA without deviation.

[0111] Pixel electrode 114 may be formed on the second planarization layer 1132. For example... Figure 3 As shown, the pixel electrode 114 can be connected to the drain or source of the thin-film transistor through contact holes penetrating the first planarization layer 1131 and the passivation layer 111c. The edge portions on both sides of the pixel electrode 114 can be covered by the dike 115. Because... Figure 3 It is a sectional view in the first direction (Y-axis direction), so the embankment 115 can be set based on a plane (e.g., Figure 2 This covers the upper and lower edges of pixel electrode 114. In contrast, as shown... Figure 4 As shown, the bank 115 may not be arranged between adjacent sub-pixels SP, which increases the area of ​​the opening region, i.e., the area of ​​the light-emitting region. Therefore, a display device 100 according to an embodiment of the present invention may be provided with a bankless structure, wherein the bank 115 is not arranged between a plurality of sub-pixels SP arranged along the second direction (X-axis direction).

[0112] The pixel electrode 114 may be made of at least one of a transparent metal material and a semi-transparent metal material.

[0113] Because the display device 100 according to an embodiment of the present invention is configured as a bottom-emitting type, the pixel electrode 114 can be formed of a transparent conductive material (or TCO) such as indium tin oxide (ITO) or indium zinc oxide (IZO) that is capable of transmitting light, or a semi-transparent conductive material such as magnesium (Mg), silver (Ag), or an alloy of Mg and Ag.

[0114] Meanwhile, the material constituting the pixel electrode 114 may include MoTi. The pixel electrode 114 may be a first electrode or an anode.

[0115] The dam 115 can be a non-light-emitting area and can be positioned adjacent to the light-emitting area EA of each of the plurality of sub-pixels SP. For example, the dam 115 can be disposed in the non-light-emitting area NEA (or the second non-light-emitting area NEA2 on the upper and lower sides of the pixel electrode 114). The dam 115 can be formed to cover the edge of the pixel electrode 114. Therefore, the dam 115 can prevent the pixel electrode 114 and the cathode 117 from contacting at the edge of the pixel electrode 114. The exposed portion of the pixel electrode 114 not covered by the dam 115 can be included in the light-emitting portion (or the light-emitting area EA).

[0116] After forming the dam 115, an organic light-emitting layer 116 may be formed to cover the pixel electrode 114 and the dam 115. Therefore, the dam 115 may be partially disposed between the pixel electrode 114 and the organic light-emitting layer 116. The dam 115 may be described as a pixel-defining film. According to one example, the dam 115 may comprise organic and / or inorganic materials.

[0117] An organic light-emitting layer 116 may be formed on the pixel electrode 114 and the embankment 115. The organic light-emitting layer 116 may be placed below the cathode 117. According to one example, the organic light-emitting layer 116 may be disposed in the light-emitting region EA and the non-light-emitting region NEA (or the first non-light-emitting region NEA1 and the second non-light-emitting region NEA2). The organic light-emitting layer 116 may be disposed between the pixel electrode 114 and the cathode 117. Therefore, when a voltage is applied to each of the pixel electrode 114 and the cathode 117, an electric field is formed between the pixel electrode 114 and the cathode 117. Therefore, the organic light-emitting layer 116 can emit light. The organic light-emitting layer 116 may be formed from a common layer disposed on the embankment 115 across a plurality of sub-pixels SP.

[0118] According to one embodiment, the organic light-emitting layer 116 can be configured to emit white light. The organic light-emitting layer 116 may include multiple stacks emitting different colors of light. For example, the organic light-emitting layer 116 may include a first stack, a second stack, and a charge-generating layer (CGL) disposed between the first and second stacks. Since the light-emitting layer can be configured to emit white light, each of the plurality of sub-pixels SP may include a color filter CF suitable for the corresponding color.

[0119] The first stacked layer can be disposed on the pixel electrode 114 and can be implemented as a structure in which a hole injection layer (HIL), a hole transport layer (HTL), an emissive layer (EML(B)) and an electron transport layer (ETL) are stacked sequentially.

[0120] The charge generation layer can supply charge to the first and second stacked layers. The charge generation layer may include an N-type charge generation layer for supplying electrons to the first stacked layer and a P-type charge generation layer for supplying holes to the second stacked layer. The N-type charge generation layer may include a metallic material as a dopant.

[0121] The second stack can be disposed on the first stack and can be implemented as a structure in which a hole transport layer (HTL), a yellow-green (YG) light-emitting layer (EML(YG)) and an electron injection layer (EIL) are stacked sequentially.

[0122] In the display device 100 according to an embodiment of the present invention, since the organic light-emitting layer 116 is configured as a common layer, the first stack, the charge-generating layer, and the second stack can be distributed across a plurality of sub-pixels SP. According to another example, the organic light-emitting layer 116 may be configured as a three-layer or four-layer structure depending on the number of stacked layers.

[0123] A cathode 117 may be formed on the organic light-emitting layer 116. The cathode 117 may be disposed in the non-display area NDA (or a portion of the non-display area NDA) and the display area DA. In the display area DA, the cathode 117 may be disposed in the light-emitting area EA and the non-light-emitting area NEA (or the first non-light-emitting area NEA1 and the second non-light-emitting area NEA2). That is, the cathode 117 may be disposed to cover the entire display area DA. As a result, the cathode 117 may be disposed to have a size larger than the display area DA and smaller than the substrate 110. Therefore, the cathode 117 may be placed in the non-display area NDA (or a portion of the non-display area NDA) and the display area DA.

[0124] According to one example, the cathode 117 may comprise a metallic material. The cathode 117 can reflect light emitted from the organic light-emitting layer 116 in a plurality of sub-pixels SP toward the lower surface of the substrate 110. Therefore, the display device 100 according to one embodiment of the present invention can be implemented as a bottom-emitting display device.

[0125] The display device 100 according to one embodiment of the present invention is a bottom-emitting type and requires the light emitted from the light-emitting layer 122 to be reflected back to the substrate 110; therefore, the cathode 117 can be made of a metallic material with high reflectivity. According to one example, the cathode 117 can be formed of a metallic material with high reflectivity such as silver (Ag), aluminum (Al), a stacked structure of aluminum and titanium (Ti / Al / Ti), a stacked structure of aluminum and ITO (ITO / Al / ITO), an Ag alloy, and a stacked structure of Ag alloy and ITO (ITO / Ag alloy / ITO). The Ag alloy can be an alloy such as silver (Ag), palladium (Pd), and copper (Cu). The cathode 117 can be described using terms such as second electrode, counter electrode, and reflective electrode.

[0126] An encapsulation layer 118 is formed on the cathode 117. The encapsulation layer 118 serves to prevent oxygen or moisture from penetrating into the organic light-emitting layer 116 and the cathode 117. The encapsulation layer 118 may include multiple layers, including at least one inorganic film and at least one organic film. The encapsulation layer 118 may also contain an adsorbent material for absorbing moisture or oxygen to enhance the moisture-proof effect. For example, the adsorbent material may be a getter.

[0127] On the other hand, such as Figure 3 As shown, the encapsulation layer 118 can be disposed not only in the light-emitting area EA, but also in the non-light-emitting area NEA. The encapsulation layer 118 can be disposed between the cathode 117 and the opposing substrate 200.

[0128] In a display device 100 according to one embodiment of the present invention, the first planarization layer 1131 may be configured to have a different refractive index than the second planarization layer 1132. For example, the refractive index of the second planarization layer 1132 may be configured to be greater than the refractive index of the first planarization layer 1131. Therefore, as Figure 4 As shown, due to the refractive index difference between the second planarization layer 1132 and the first planarization layer 1131, light emitted from the organic light-emitting layer 116 and guided to the substrate 110 can be totally internally reflected, and the light path can be changed toward the first reflective portion 150 and the second reflective portion 160. Therefore, light forming a path toward the first reflective portion 150 and the second reflective portion 160 can be reflected by the first reflective portion 150 and the second reflective portion 160, and emitted in the form of front-extracted light of the light-emitting sub-pixel SP. In the following, the light reflected by the first reflective portion 150 and the second reflective portion 160 and emitted toward the substrate 110 is defined as reflected light EL.

[0129] like Figure 4 As shown, the reflected light EL may include a first reflected light EL1 and a second reflected light EL2.

[0130] The first reflected light EL1 can be emitted from the organic light-emitting layer 116, waveguided by total internal reflection between the pixel electrode 114 and the cathode 117 (and / or total internal reflection between the cathode 117 and the second planarization layer 1132), and then reflected by the first reflector 150 and the second reflector 160 before being emitted forward-extracted light onto the substrate 110. Since the first reflected light EL1 is waveguided light, it can be described as WG mode extracted light EL1.

[0131] The second reflected light EL2 can be a forward-extracted light emitted from the organic light-emitting layer 116, totally reflected at the boundary between the first planarization layer 1131 and the second planarization layer 1132, and then reflected by the first reflective portion 150 and the second reflective portion 160 and emitted onto the substrate 110. Since the second reflected light EL2 emits light that is totally reflected and disappears through the substrate 110, it can be described as substrate-mode extracted light EL2.

[0132] Meanwhile, in typical display devices, non-emitting areas are not placed within the emitting area. This is because if a non-emitting area were placed within the emitting area, the size (or area) of the emitting area would be reduced, thus decreasing luminous efficiency. Therefore, in typical display devices, non-emitting areas are not placed within the emitting area. However, light emitted from the emitting area can be totally internally reflected and waveguided between the pixel electrode and the cathode, and the waveguided light can be extinguished simultaneously through multiple total internal reflections. As the area of ​​the emitting area increases, the number of times light is extinguished through waveguides while undergoing total internal reflection increases, thus reducing luminous efficiency.

[0133] According to one embodiment of the present invention, the display device 100 has a first non-emitting region NEA1 disposed on the inner side of each of a plurality of sub-pixels SP (or the inner side of the light-emitting region EA of each of the plurality of sub-pixels SP), such that the light-emitting region EA can be partially disconnected. Therefore, the display device 100 according to one embodiment of the present invention can minimize the light dissipated through the waveguide, and instead emit the light of the waveguide to the outside through the first reflective portion 150 disposed in the first non-emitting region NEA1, thereby improving the light efficiency.

[0134] Refer again Figure 4 In a display device 100 according to one embodiment of the present invention, the first non-light-emitting area NEA1 may include a first planarization layer 1131, a second planarization layer 1132, a first patterned portion 130, and a first reflective portion 150. As described above, the first planarization layer 1131 may be disposed on a substrate 110, and the second planarization layer 1132 may be disposed on the first planarization layer 1131. The first patterned portion 130 may be disposed on the second planarization layer 1132. The first reflective portion 150 may be disposed on the first patterned portion 130.

[0135] According to one example, the first patterned portion 130 may be recessedly formed on the second planarization layer 1132. For example, the first patterned portion 130 may be formed by patterning and removing a portion of the second planarization layer 1132 located on the inner side of each of the plurality of sub-pixels SP. Thus, the first patterned portion 130 may be described as a groove, slit, trench, outer coating slit, and outer coating trench located on the inner side of each of the plurality of sub-pixels SP.

[0136] like Figure 4As shown, the first pattern portion 130 can be arranged to be spaced apart from the light-emitting area EA. According to one example, the first pattern portion 130 can be provided in the form of a slit or a groove on the inner side of a plurality of sub-pixels SP (or light-emitting portions EA). The width of the first pattern portion 130 can be formed to decrease in the direction from the first reflective portion 150 toward the substrate 110 (or in the direction from the pixel electrode 114 toward the substrate 110).

[0137] like Figure 4 As shown, the first patterned portion 130 may include: an inclined surface 130s arranged at an angle relative to the upper surface of the substrate 110; and a bottom surface 130b extending from the inclined surface 130s and arranged parallel to the upper surface of the substrate 110. The inclined surface 130s may be an inclined surface of the second planarization layer 1132. The bottom surface 130b may be a part of the upper surface 1131a of the first planarization layer 1131.

[0138] like Figure 4 As shown, the first patterned portion 130 may be provided with an inclined surface 130s of the second planarization layer 1132 and a bottom surface 130b, which serves as the upper surface of the first planarization layer 1131, but is not necessarily limited thereto. According to another example, the first patterned portion 130 may be formed only on the second planarization layer 1132. In this case, the inclined surface of the first patterned portion 130 may be the inclined surface of the second planarization layer 1132, and the bottom surface of the first patterned portion 130 may be the bottom surface of the second planarization layer 1132.

[0139] According to one example, a first reflective portion 150 may be placed on a first patterned portion 130. The first reflective portion 150 is formed of a light-reflective material, thus reflecting light emitted from the light-emitting region EA and waveguided, and / or light totally reflected at the interface between the first planarization layer 1131 and the second planarization layer 1132, towards the front side of the light-emitting sub-pixel SP. The first reflective portion 150 may be formed along the contour of the first patterned portion 130, which is recessed in the first non-light-emitting region NEA1. For example... Figure 4 As shown, the first reflective part 150 is part of the cathode 117 disposed in the first non-light-emitting area NEA1, and therefore can be indicated by reference numeral 117'.

[0140] According to one example, the first reflective portion 150 may include a first flat reflective portion 151 and a first tilted reflective portion 152. The first flat reflective portion 151 may be arranged parallel to the upper surface of the substrate 110. The first tilted reflective portion 152 may be connected to the first flat reflective portion 151 and arranged at an angle.

[0141] like Figure 4As shown, the first flat reflective portion 151 may be arranged parallel to the upper surface of the substrate 110 on the first pattern portion 130 between two light-emitting areas EA (or two light-emitting areas EA in a cross-sectional view) disposed in a sub-pixel SP (e.g., the second sub-pixel SP2) (i.e., in the first non-light-emitting area NEA1). Therefore, the first flat reflective portion 151 may be described as a flat reflective portion located inside each of the plurality of sub-pixels SP.

[0142] The first tilted reflective portion 152 may be tiltedly arranged on the first pattern portion 130 in the first non-light-emitting area NEA1. Therefore, the first tilted reflective portion 152 may be described as a side reflective portion or a tilted reflective portion located on the inner side of each of the plurality of sub-pixels SP.

[0143] Therefore, the display device 100 according to one embodiment of the present invention is provided with a reflective portion (or a first reflective portion 150) arranged in a non-light-emitting area NEA (or a first non-light-emitting area NEA1) located inside each of the plurality of sub-pixels SP, so that light extraction can be achieved even in the non-light-emitting area NEA (or the first non-light-emitting area NEA1), thereby improving light efficiency.

[0144] Reference Figure 4 In a display device 100 according to one embodiment of the present invention, the second non-light-emitting area NEA2 may include a second patterned portion 140 and a second reflective portion 160. The second patterned portion 140 may be recessedly formed on the second planarization layer 1132. The second reflective portion 160 may be disposed on the second patterned portion 140.

[0145] According to one example, the second patterned portion 140 may be recessedly formed on the second planarization layer 1132. For example, the second patterned portion 140 may be formed by patterning on the outer side of each of the plurality of sub-pixels SP and removing a portion of the second planarization layer 1132. Thus, the second patterned portion 140 may be characterized by grooves, slits, trenches, outer coating slits, and outer coating trenches on the outer side of each of the plurality of sub-pixels SP.

[0146] like Figure 4 As shown, the second patterned portion 140 can be arranged to be spaced apart from the light-emitting area EA. According to one example, the second patterned portion 140 can be provided on the outer side of a plurality of sub-pixels SP (or light-emitting areas EA) in the form of slits or grooves. The width of the second patterned portion 140 can be formed to decrease in the direction from the second reflective portion 160 toward the substrate 110 (or in the direction from the pixel electrode 114 toward the substrate 110).

[0147] like Figure 4As shown, the second patterned portion 140 may include: an inclined surface 140s arranged at an angle relative to the upper surface of the substrate 110; and a bottom surface 140b extending from the inclined surface 140s and arranged parallel to the upper surface of the substrate 110. The inclined surface 140s of the second patterned portion 140 may be an inclined surface of the second planarization layer 1132. The bottom surface 140b of the second patterned portion 140 may be a part of the upper surface 1131a of the first planarization layer 1131.

[0148] like Figure 4 As shown, the second patterned portion 140 may be provided with an inclined surface 140s of the second planarization layer 1132 and a bottom surface 140b, which serves as the upper surface of the first planarization layer 1131, but is not limited to this. According to another example, the second patterned portion 140 may be formed only on the second planarization layer 1132. In this case, the inclined surface of the second patterned portion 140 may be the inclined surface of the second planarization layer 1132, and the bottom surface of the second patterned portion 140 may be the bottom surface of the second planarization layer 1132.

[0149] According to one example, the second reflective portion 160 may be placed on the second patterned portion 140. The second reflective portion 160 is formed of a light-reflective material, thus reflecting light emitted from the light-emitting region EA and waveguided, and / or light that is totally internally reflected at the interface between the first planarization layer 1131 and the second planarization layer 1132, towards the front side of the light-emitting sub-pixel SP. The second reflective portion 160 may be formed along the contour of the second patterned portion 140, which is recessed in the second non-light-emitting region NEA2. For example... Figure 4 As shown, the second reflective portion 160 is part of the cathode 117 disposed in the second non-light-emitting area NEA2, and can therefore be indicated by reference numeral 117".

[0150] According to one example, the second reflective portion 160 may include a second flat reflective portion 161 and a second tilted reflective portion 162. The second flat reflective portion 161 may be arranged parallel to the upper surface of the substrate 110. The second tilted reflective portion 162 may be connected to the second flat reflective portion 161 and arranged at an angle.

[0151] like Figure 4 As shown, the second flat reflective portion 161 can be arranged parallel to the upper surface of the substrate 110 on the second pattern portion 140 in the second non-light-emitting area NEA2 between two sub-pixels SP (e.g., between the first sub-pixel SP1 and the second sub-pixel SP2). Therefore, the second flat reflective portion 161 can be described as a flat reflective portion located on the outer side of each of the plurality of sub-pixels SP.

[0152] The second tilted reflective portion 162 may be tiltedly arranged on the second pattern portion 140 in the second non-light-emitting area NEA2. Therefore, the second tilted reflective portion 162 may be described as a side reflective portion or a tilted reflective portion located on the outer side of each of the plurality of sub-pixels SP.

[0153] Therefore, the display device 100 according to one embodiment of the present invention is provided with a reflective portion (or a second reflective portion 160) located in a non-light-emitting area NEA (or a second non-light-emitting area NEA2) provided on the outer side of a plurality of sub-pixels SP, so that light guided toward the adjacent sub-pixels SP can be reflected by the reflective portion (or the second reflective portion 160), thereby maximizing the light extraction efficiency.

[0154] As a result, since the display device 100 according to the present invention can extract light even in the non-light-emitting area NEA through the reflective portions (or the first reflective portion 150 and the second reflective portion 160) provided on the inner and outer sides of each of the plurality of sub-pixels SP, the display device can have the same luminous efficiency or improved luminous efficiency with lower power compared to a display device without reflective portions on the inner and outer sides of each of the plurality of sub-pixels, thereby reducing the total power consumption.

[0155] Meanwhile, in a display device 100 according to an embodiment of the present invention, the size (or area) of the circuit area CA can be reduced by arranging the wiring 120 (or the first wiring 121) in the first non-light-emitting area NEA1 (which is a dead zone), thereby increasing the size (or area) of the light-emitting area EA. Therefore, as Figure 4 As shown, a display device 100 according to an embodiment of the present invention may have a structural feature in which wiring 120 (or first wiring 121) overlaps with a first flat reflective portion 151.

[0156] In a display device 100 according to an embodiment of the present invention, the width W1 of the wiring 120 (or the first wiring 121) can be set to be equal to or narrower than the width W2 of the first flat reflective portion 151. If the width W1 of the wiring 120 (or the first wiring 121) is wider than the width W2 of the first flat reflective portion 151, then the wiring 120 (or the first wiring 121) blocks the forward-emitted reflected light by being reflected by the first tilted reflective portion 152. Therefore, the display device 100 according to an embodiment of the present invention provides a width W1 of the wiring 120 (or the first wiring 121) that is equal to or narrower than the width W2 of the first flat reflective portion 151, so that the reflected light reflected and emitted by the first tilted reflective portion 152 is not blocked, thereby improving the light extraction efficiency.

[0157] Reference Figure 4 The substrate 110 may include data wiring DL (or second data wiring DL2) that partially overlaps with the second flat reflective portion 161. Figure 2 As shown, data routing DL (or second data routing DL2) can be connected to routing 120. Since routing 120 is connected to the thin-film transistor 112 in circuit region CA, data routing DL (or second data routing DL2) can be connected to the thin-film transistor 112 through routing 120. Therefore, data signals (or data voltages) applied from pad PA to data routing DL (or second data routing DL2) can be applied to the thin-film transistor 112 through routing 120.

[0158] In a display device 100 according to an embodiment of the present invention, the pixel electrode 114 of each of a plurality of sub-pixels SP can be arranged to be spaced apart from the first reflective portion 150 of each of the plurality of sub-pixels SP. For example, see reference to Figure 4 The pixel electrode 114 of the second sub-pixel SP2 can be arranged to be spaced apart from the first reflective portion 150 disposed in the first non-light-emitting area NEA1 by a predetermined distance in the second direction (X-axis direction). Since the first reflective portion 150 is the cathode 117' disposed on the first pattern portion 130, the pixel electrode 114 can be arranged such that the end of the pixel electrode 114 (or the right end of the pixel electrode 114) is spaced apart from the first point PT1 (the first point PT1 connects the upper surface of the second planarization layer 1132 and the inclined surface 130s of the first pattern portion 130) by a distance.

[0159] If the pixel electrode 114 is not positioned to be spaced apart from the first reflective portion 150, then when the pixel electrode 114 is formed, it can be formed on the inclined surface 130s of the first pattern portion 130. In this case, light emission can occur even on the inclined surface 130s of the first pattern portion 130, and the emitted light can be emitted toward sub-pixels SP of different colors (e.g., the third sub-pixel SP3), thereby causing color mixing.

[0160] Therefore, in a display device 100 according to an embodiment of the present invention, the pixel electrode 114 of each of the plurality of sub-pixels SP is arranged to be spaced apart from the first reflective portion 150, thereby preventing color mixing from occurring.

[0161] Simultaneously, the first reflective portion 150 can be partially positioned closer to the substrate 110 than the pixel electrode 114. For example, as Figure 4As shown, the first flat reflective portion 151 and the partial first tilted reflective portion 152 of the first reflective portion 150 can be positioned closer to the substrate 110 than the pixel electrode 114. The display device 100 according to one embodiment of the present invention is a bottom-emitting type, and the light extraction efficiency can be improved by the first reflective portion 150 (or the first tilted reflective portion 152) on the first pattern portion 130 recessed on the inner side of the sub-pixel SP. Therefore, the display device 100 according to one embodiment of the present invention may have the following structural feature: the first flat reflective portion 151 and the partial first tilted reflective portion 152 of the first reflective portion 150 are positioned closer to the substrate 110 than the pixel electrode 114.

[0162] Refer again Figure 4 In a display device 100 according to an embodiment of the present invention, the pixel electrode 114 of each of a plurality of sub-pixels SP can be arranged to be spaced apart from the second reflective portion 160 of each of the plurality of sub-pixels SP. For example, see reference to Figure 4 The pixel electrode 114 of the second sub-pixel SP2 can be positioned at a predetermined distance from the second reflective portion 160 disposed in the second non-light-emitting area NEA2 in the second direction (X-axis direction). Since the second reflective portion 160 is a cathode 117'' disposed on the second pattern portion 140, the pixel electrode 114 can be arranged such that the end of the pixel electrode 114 (or the left end of the pixel electrode 114) is spaced apart from the second point PT2 (the second point PT2 connects the upper surface of the second planarization layer 1132 and the inclined surface 140s of the second pattern portion 140) by a distance.

[0163] If the pixel electrode 114 is not arranged to be spaced apart from the second reflective portion 160, then when the pixel electrode 114 is formed, the pixel electrode 114 can be formed on the inclined surface 140s of the second pattern portion 140. In this case, light can be emitted even on the inclined surface 140s of the second pattern portion 140, and the emitted light can be emitted toward sub-pixels SP of different colors (e.g., the first sub-pixel SP1), thereby causing color mixing.

[0164] Therefore, in a display device 100 according to an embodiment of the present invention, color mixing can be prevented by positioning the pixel electrode 114 of each of the plurality of sub-pixels SP separately from the second reflective portion 160.

[0165] Simultaneously, the second reflective portion 160 can be partially positioned closer to the substrate 110 than the pixel electrode 114. For example, as Figure 4As shown, the second flat reflective portion 161 and the partial second tilted reflective portion 162 of the second reflective portion 160 can be positioned closer to the substrate 110 than the pixel electrode 114. The display device 100 according to one embodiment of the present invention is a bottom-emitting type, and the light extraction efficiency can be improved by the second reflective portion 160 (or the second tilted reflective portion 162) on the second pattern portion 140 recessed on the outer side of the sub-pixel SP. Therefore, the display device 100 according to one embodiment of the present invention may have the following structural feature: the second flat reflective portion 161 and the partial second tilted reflective portion 162 of the second reflective portion 160 are positioned closer to the substrate 110 than closer to the pixel electrode 114.

[0166] As a result, since the first reflective portion 150 is disposed between the pixel electrodes 114 located inside a sub-pixel SP, the display device 100 according to an embodiment of the present invention can improve light efficiency by allowing light extraction even in the first non-light-emitting area NEA1 where wiring 120 is arranged.

[0167] In addition, according to one embodiment of the present invention, the display device 100 has a second reflective portion 160 disposed between the pixel electrodes 114 of each of the plurality of sub-pixels SP that emit light of different colors, such that light guided toward adjacent sub-pixels SP can be reflected forward and upward, thereby preventing color mixing and maximizing light extraction efficiency.

[0168] Furthermore, since the display device 100 according to one embodiment of the present invention is configured such that the wiring 120 partially overlaps with the first non-light-emitting area NEA1 in which it does not emit light, the size (or area) of the circuit area can be reduced compared to a general display device, and therefore the size (or area) of the light-emitting area EA can be relatively expanded. Thus, due to the expansion of the size (or area) of the light-emitting area EA, the display device 100 according to one embodiment of the present invention can have improved light efficiency.

[0169] Figure 5 This is a schematic plan view showing a sub-pixel of a display device according to a comparative example. Figure 6 This is a schematic plan view showing a sub-pixel (e.g., first sub-pixel SP1) of a display device according to a first embodiment of the present invention.

[0170] Reference Figure 5According to the comparative example, the light-emitting area EA (or pixel electrode PE) of the display device can be disposed between the circuit area CA and the reference wiring RL along a first direction (Y-axis direction). Furthermore, according to the comparative example, the light-emitting area EA (or pixel electrode PE) of the display device can be disposed between the pixel power wiring EVDD and the data wiring DL along a second direction (X-axis direction). Therefore, the light-emitting area EA (or pixel electrode PE) of the display device according to the comparative example can be provided with a dimension (or area) having a first light-emitting length EVL1 in the first direction (Y-axis direction) and a first width EW1 in the second direction (X-axis direction).

[0171] According to the comparative example, the light-emitting region EA of the display device may be spaced apart from the reference wiring RL by a first upper length REL1 in a first direction (Y-axis direction). The first upper length REL1 may be the length of the upper process margin area used to form the reference wiring RL. Additionally, the light-emitting region EA may be spaced apart from the gate wiring GL by a first lower length BVL1 or greater. The first lower length BVL1 may be the length of the lower process margin area used to form the gate wiring GL.

[0172] Meanwhile, the circuit area CA of the display device according to the comparative example can be configured with dimensions (or area) including thin-film transistors (TFTs) and data branch wiring (BRLs). For example... Figure 5 As shown, the data branch wiring BRL may include a first data branch wiring BRL1 connected to the thin-film transistor TFT and a second data branch wiring BRL2 connected to the first data branch wiring BRL1 and the data wiring DL. The first data branch wiring BRL1 may extend in a first direction (Y-axis direction), and the second data branch wiring BRL2 may extend in a second direction (X-axis direction). Therefore, the circuit area CA of the display device according to the comparative example may be provided with a size (or area) having a first circuit length CVL1 in the first direction (Y-axis direction) and a first width EW1 in the second direction (X-axis direction).

[0173] As a result, in the case of the display device according to the comparative example, since the data branch wiring BRL is placed in the circuit area CA, there is a limitation in the size (or area) of the extended light-emitting area EA, making it difficult to improve the light efficiency.

[0174] In contrast, in a display device 100 according to an embodiment of the present invention, wiring 120 is arranged to partially overlap with a first non-light-emitting area NEA1 located inside the sub-pixel SP, such that the size (or area) of the circuit area CA can be reduced, thereby relatively expanding the size (or area) of the light-emitting area EA.

[0175] For example, such as Figure 6As shown, the first wiring 121 may extend from the thin-film transistor 112 in a first direction (Y-axis direction) and partially overlap with the light-emitting region EA and the first non-light-emitting region NEA1. Then, the first wiring 121 may be connected to a second wiring 122 located between the light-emitting region EA and the reference wiring RL. The second wiring 122 may extend in a second direction (X-axis direction) and be connected to the data wiring DL (e.g., the first data wiring DL1).

[0176] Therefore, in the display device 100 according to one embodiment of the present invention, since the second wiring 122 is arranged in the upper process margin region, the size of the circuit region CA can be reduced compared to the comparative example in which the second data branch wiring BRL2 is provided in the circuit region CA. The width of the second wiring 122 can be smaller than the width of the upper process margin region. Therefore, in the display device 100 according to one embodiment of the present invention, the second wiring 122 can be placed in the upper process margin region.

[0177] Since the second wiring 122 is arranged in the upper process margin area, the circuit area CA can be provided with a dimension (or area) having a second circuit length CVL2 in the first direction (Y-axis direction) and a second width EW2 in the second direction (X-axis direction). The second circuit length CVL2 can be a length obtained by subtracting the first lower length BVL1 from the first circuit length CVL1. The second width EW2 can be equal to the first width EW1.

[0178] Therefore, the display device 100 according to one embodiment of the present invention may have a smaller circuit region CA size (or area) than the display device according to the comparative example. Therefore, the display device 100 according to one embodiment of the present invention may have an enlarged size (or area) of the light-emitting region EA.

[0179] For example, the light-emitting area EA may be provided with a second light-emitting length EVL2 in a first direction (Y-axis direction) and a second width EW2 in a second direction (X-axis direction). The second light-emitting length EVL2 may be the sum of the first light-emitting length EVL1 and the first lower length BVL1. The second width EW2 may be the same as the first width EW1.

[0180] Meanwhile, in a display device 100 according to an embodiment of the present invention, a first non-light-emitting area NEA1 is disposed on the inner side of the light-emitting area EA, but since light extraction can be achieved through the first reflective portion 150, the reduction in light efficiency can be minimized.

[0181] As a result, the display device 100 according to one embodiment of the present invention is configured such that the wiring 120 partially overlaps with the first non-light-emitting area NEA1 and the light-emitting area EA, thereby increasing the size (or area) of the light-emitting area EA compared with the display device according to the comparative example, thereby improving the light efficiency.

[0182] Reference Figure 6 The width LW1 (or W1) of the first wiring 121 can be set to be narrower than the width of the first non-light-emitting area NEA1. If the width LW1 (or W1) of the first wiring 121 is equal to or greater than the width of the first non-light-emitting area NEA1, the light reflected by the first reflective portion 150 is blocked, thereby reducing the light efficiency. Therefore, in a display device 100 according to an embodiment of the present invention, the width LW1 (or W1) of the first wiring 121 is set to be narrower than the width of the first non-light-emitting area NEA1 to prevent a decrease in light efficiency.

[0183] The width LW2 of the second wiring 122 can be set to be less than the second upper length REL2. The second upper length REL2 can be equal to the first upper length REL1. If the width LW2 of the second wiring 122 is the same as the second upper length REL2, the manufacturing process may be difficult, and if the width of the second wiring 122 is greater than the second upper length REL2, the light-emitting area EA can be covered, which can reduce light efficiency. Therefore, the display device 100 according to an embodiment of the present invention can be manufactured in an easy manner, and the reduction in light efficiency can be prevented by setting the width LW2 of the second wiring 122 to be less than the second upper length REL2.

[0184] A display device 100 according to one embodiment of the present invention may have a pixel electrode 114 disposed in each light-emitting region EA of a plurality of sub-pixels SP. According to one example, the pixel electrode 114 may be configured as a closed-loop shape or a horseshoe shape with an opening on one side.

[0185] For example, such as Figure 6 As shown, the pixel electrode 114 can be configured in a closed loop. Here, the pixel electrode 114 may include a first pixel electrode 114a, a second pixel electrode 114b, a third pixel electrode 114c, and a fourth pixel electrode 114d.

[0186] The first pixel electrode 114a can be positioned at a distance from one side 150a of the first reflective portion 150. For example, referring to... Figure 4 One side 150a of the first reflective portion 150 may refer to the uppermost side of the first tilted reflective portion 152 located on the left side of the first flat reflective portion 151. The second pixel electrode 114b may be positioned at a distance from the other side 150b of the first reflective portion 150. (Refer to...) Figure 4The other side 150b of the first reflective portion 150 may refer to the uppermost side of the first tilted reflective portion 152 located on the right side of the first flat reflective portion 151. The third pixel electrode 114c may be connected to one side of the first pixel electrode 114a (e.g., based on...). Figure 6 The upper side of the first pixel electrode 114a) and one side of the second pixel electrode 114b (e.g., based on Figure 6 The fourth pixel electrode 114d may be connected to the other side of the first pixel electrode 114a (e.g., based on the second pixel electrode 114b above it). Figure 6 The lower side of the first pixel electrode 114a) and the other side of the second pixel electrode 114b (e.g., based on Figure 6 (The lower side of the second pixel electrode 114b).

[0187] Therefore, when viewed from a planar perspective, the display device 100 according to one embodiment of the present invention may be provided with a pixel electrode 114 for each of a plurality of sub-pixels SP in a closed-loop shape. In this case, the wiring 120 may partially overlap with two or more of the first pixel electrode 114a, the second pixel electrode 114b, the third pixel electrode 114c, and the fourth pixel electrode 114d.

[0188] For example, such as Figure 6 As shown, the gate wiring GL may partially overlap with each of the pixel power wiring EVDD and data wiring DL. The first wiring 121 may be arranged between the first pixel electrode 114a and the second pixel electrode 114b. Furthermore, the first wiring 121 may extend in a first direction (Y-axis direction). Therefore, the first wiring 121 may partially overlap with each of the third pixel electrode 114c and the fourth pixel electrode 114d. In contrast, the second wiring 122 may be connected to the first wiring 121 and arranged in a different direction from the first wiring 121. For example, the second wiring 122 may be arranged to extend in a second direction (X-axis direction) while connected to the end of the first wiring 121 protruding into the upper process margin region. Therefore, the second wiring 122 may not overlap with the pixel electrode 114. Therefore, in a display device 100 according to an embodiment of the present invention, compared to a display device according to a comparative example, the size (or area) of the light-emitting region EA can be increased by the first lower length BVL1, thereby improving light efficiency.

[0189] Meanwhile, in a display device 100 according to an embodiment of the present invention, the width LW1 (or W1) of the first wiring 121 may be narrower than the width LW2 of the second wiring 122. As described above, since the first wiring 121 partially overlaps with the first non-light-emitting area NEA1 in which the first reflective portion 150 is arranged, if the width LW1 (or W1) of the first wiring 121 is equal to or wider than the width LW2 of the second wiring 122, the light reflected by the first reflective portion 150 can be blocked. In contrast, since the second wiring 122 is arranged in an upper process margin area that is relatively wider than the width of the first non-light-emitting area NEA1 in the second direction (X-axis direction), it may be provided with a width wider than the first wiring 121. Therefore, the display device 100 according to an embodiment of the present invention may have the following structural feature: the width LW1 (or W1) of the first wiring 121 is set to be narrower than the width LW2 of the second wiring 122.

[0190] Figure 7 This is a schematic plan view showing a sub-pixel of a display device according to a second embodiment of the present invention.

[0191] Reference Figure 7 Apart from the structural changes to the pixel electrode 114 and wiring 120, the display device 100 according to the second embodiment of the present invention is similar to that described above. Figure 6 The display devices are the same. Therefore, the same reference numerals are used for the same constructions, and only the different constructions will be described below.

[0192] According to Figure 6 In the case of a display device, the first wiring 121 partially overlaps with each of the third pixel electrode 114c and the fourth pixel electrode 114d. Additionally, the second wiring 122 may be disposed in the upper process margin region so as not to overlap with the pixel electrode 114. Therefore, according to... Figure 6 In the case of a display device, compared to a comparative example where a second data branch wiring BRL2 is provided in the circuit area CA, the size of the circuit area CA can be reduced. Furthermore, according to... Figure 6 In the case of a display device, the size (or area) of the light-emitting area EA can be increased as the size of the circuit area CA decreases. For example, in accordance with... Figure 6 In the case of a display device, the light-emitting area EA may be provided with a size (or area) having a second light-emitting length EVL2 in a first direction (Y-axis direction) and a second width EW2 in a second direction (X-axis direction). The second light-emitting length EVL2 may be the sum of the first light-emitting length EVL1 and the first lower length BVL1. The second width EW2 may be equal to the first width EW1. Therefore, according to Figure 6In the case of a display device, compared with the display device according to the comparative example, the size (or area) of the light-emitting area EA can be increased, thereby improving the light efficiency.

[0193] In contrast, according to Figure 7 In the case of a display device, the first wiring 121 may partially overlap with the fourth pixel electrode 114d, and the second wiring 122 may partially overlap with the second pixel electrode 114b. For example, as Figure 7 As shown, the first wiring 121 extends from the thin-film transistor 112 and partially overlaps with the fourth pixel electrode 114d. Furthermore, the end of the first wiring 121 may be disposed in the first non-light-emitting region NEA1. The second wiring 122 may be connected to the end of the first wiring 121 in the first non-light-emitting region NEA1 and may extend in the second direction (X-axis direction) to connect to the data wiring DL (DL1). Therefore, the second wiring 122 may partially overlap with the second pixel electrode 114b. Therefore, according to... Figure 7 In the case of a display device, since the second wiring 122 is not located in the upper process margin area, the size (or area) of the light-emitting area EA can be further increased in the first direction (Y-axis direction).

[0194] For example, according to Figure 7 In the case of a display device, the light-emitting area EA may be provided with a size (or area) having a third light-emitting length EVL3 in the first direction (Y-axis direction) and a third width EW3 in the second direction (X-axis direction). The third light-emitting length EVL3 may be the sum of the first light-emitting length EVL1, the first lower length BVL1, and the first 'upper length REL1'. The first 'upper length REL1' may be shorter than the first upper length REL1. This is because when the first 'upper length REL1' is equal to or longer than the first upper length REL1, the pixel electrode 114 overlaps with the reference wiring RL, thereby reducing light efficiency. The third width EW3 may be equal to the first width EW1. Therefore, according to Figure 7 In the case of display devices, and according to Figure 6 Compared to other display devices, the size (or area) of the light-emitting area EA can be further increased in the first direction (Y-axis direction), thereby improving light efficiency.

[0195] At the same time, such as Figure 7 As shown, the circuit area CA of the display device 100 according to the second embodiment of the present invention may be provided with a dimension (or area) having a third circuit length CVL3 in the first direction (Y-axis direction) and a second width EW3 in the second direction (X-axis direction). The third circuit length CVL3 may be a length obtained by subtracting the first lower length BVL1 from the first circuit length CVL1. The third width EW3 may be equal to the first width EW1.

[0196] Figure 8 This is a schematic plan view illustrating a sub-pixel of a display device according to a third embodiment of the present invention.

[0197] Reference Figure 8 Apart from the structural change of the pixel electrode 114, the display device 100 according to the third embodiment of the present invention is similar to that described above. Figure 6 The display devices are the same. Therefore, the same reference numerals are used for the same constructions, and only the different constructions will be described below.

[0198] According to Figure 6 In the case of a display device, the pixel electrode 114 is provided in a closed-loop configuration. Therefore, according to Figure 6 In the case of a display device, the first wiring 121 partially overlaps with each of the third pixel electrode 114c and the fourth pixel electrode 114d. Additionally, the second wiring 122 may be disposed in the upper process margin region so as not to overlap with the pixel electrode 114. Therefore, according to... Figure 6 In the case of a display device, compared with the display device according to the comparative example, the size of the circuit area CA can be reduced, so the size (or area) of the light-emitting area EA can be relatively increased.

[0199] For example, according to Figure 6 In the case of a display device, the light-emitting area EA may be provided with a dimension (or area) having a second light-emitting length EVL2 in a first direction (Y-axis direction) and a second width EW2 in a second direction (X-axis direction). The second light-emitting length EVL2 may be a length obtained by adding a first lower length BVL1 to the first light-emitting length EVL1. The second width EW2 may be equal to the first width EW1. Therefore, according to Figure 6 In the case of a display device, compared with the display device according to the comparative example, the size (or area) of the light-emitting area EA can be increased, thereby improving the light efficiency.

[0200] In contrast, according to Figure 8 In the case of a display device, the pixel electrode 114 can be configured in a horseshoe shape with an opening on one side. For example, in accordance with... Figure 8 In the case of a display device, the pixel electrode 114 can be provided in a structure that omits the fourth pixel electrode 114d. Therefore, according to Figure 8 The display device 100 may be provided with pixel electrodes 114 in the form of a first pixel electrode 114a, a second pixel electrode 114b, and a third pixel electrode 114c. For example... Figure 8 As shown, since the pixel electrode 114 is set in a horseshoe shape, the first non-light-emitting area NEA1 can be connected to the second non-light-emitting area NEA2.

[0201] According to Figure 8 In the case of a display device, wiring 120 may partially overlap with one of the first pixel electrode 114a, the second pixel electrode 114b, and the third pixel electrode 114c. For example, as Figure 8 As shown, the first wiring 121 extends from the thin-film transistor 112 in a first direction (Y-axis direction) and partially overlaps with the third pixel electrode 114c. Furthermore, the end of the first wiring 121 may be disposed in an upper process margin region. A second wiring 122 may be connected to the end of the first wiring 121 that protrudes into the upper process margin region. Furthermore, the second wiring 122 may extend in a second direction (X-axis direction) to connect to the data wiring DL. Therefore, the second wiring 122 may not overlap with the pixel electrode 114. Therefore, according to... Figure 8 In the case of a display device, compared with the display device according to the comparative example, the size (or area) of the light-emitting area EA can be increased by expanding the first lower length BVL1, thereby improving the light efficiency.

[0202] For example, according to Figure 8 In the case of a display device, the light-emitting area EA may be provided with a dimension (or area) having a fourth light-emitting length EVL4 in the first direction (Y-axis direction) and a fourth width EW4 in the second direction (X-axis direction). The fourth light-emitting length EVL4 may be the sum of the first light-emitting length EVL1 and the first lower length BVL1. The fourth width EW4 may be equal to the first width EW1. Therefore, according to Figure 8 In the case of a display device, compared with the display device according to the comparative example, the size (or area) of the light-emitting area EA can be further enlarged in the first direction (Y-axis direction), thereby improving the light efficiency.

[0203] At the same time, such as Figure 8 As shown, the circuit area CA of the display device 100 according to the third embodiment of the present invention may be provided with a dimension (or area) having a fourth circuit length CVL4 in the first direction (Y-axis direction) and a fourth width EW4 in the second direction (X-axis direction). The fourth circuit length CVL4 may be a length obtained by subtracting the first lower length BVL1 from the first circuit length CVL1. The fourth width EW4 may be equal to the first width EW1.

[0204] Figure 9 This is a schematic plan view showing a sub-pixel of a display device according to a fourth embodiment of the present invention.

[0205] Reference Figure 9 Apart from the structural change of the pixel electrode 114, the display device 100 according to the fourth embodiment of the present invention is similar to that described above. Figure 7The display devices are the same. Therefore, the same reference numerals are used for the same constructions, and only the different constructions will be described below.

[0206] According to Figure 7 In the case of a display device, the pixel electrode 114 is provided in a closed-loop configuration. Therefore, according to Figure 7 In the case of a display device, the first wiring 121 may partially overlap with the fourth pixel electrode 114d, and the second wiring 122 may partially overlap with the second pixel electrode 114b. Therefore, according to Figure 7 In the case of a display device, since the second wiring 122 is not provided in the upper process margin area, the size (or area) of the light-emitting area EA can be further increased in the first direction (Y-axis direction) compared with the case where the second wiring is provided in the upper process margin area.

[0207] In contrast, according to Figure 9 In the case of a display device, the pixel electrode 114 can be configured in a horseshoe shape with an opening on one side. For example, in accordance with... Figure 9 In the case of a display device, the pixel electrode 114 can be provided in a structure that omits the fourth pixel electrode 114d. Therefore, according to Figure 9 The display device 100 may be provided with pixel electrodes 114 in the form of a first pixel electrode 114a, a second pixel electrode 114b, and a third pixel electrode 114c. For example... Figure 9 As shown, since the pixel electrode 114 is set in a horseshoe shape, the first non-light-emitting area NEA1 can be connected to the second non-light-emitting area NEA2.

[0208] According to Figure 9 In the case of a display device, wiring 120 may partially overlap with one of the first pixel electrode 114a, the second pixel electrode 114b, and the third pixel electrode 114c. For example, as Figure 9 As shown, the first wiring 121 extends from the thin-film transistor 112 in a first direction (Y-axis direction), and its end is located in the first non-light-emitting region NEA1. Therefore, the first wiring 121 does not overlap with the pixel electrode 114. The second wiring 122 can be connected to the end of the first wiring 121 in the first non-light-emitting region NEA1. Furthermore, the second wiring 122 extends in a second direction (X-axis direction) and connects to the data wiring DL (DL1). Therefore, the second wiring 122 can partially overlap with the second pixel electrode 114b. Therefore, according to... Figure 9 In the case of a display device, since the second wiring 122 is not located in the upper process margin area, the size (or area) of the light-emitting area EA can be further increased in the first direction (Y-axis direction).

[0209] For example, according to Figure 9In the case of a display device, the light-emitting area EA may be provided with a size (or area) having a fifth light-emitting length EVL5 in the first direction (Y-axis direction) and a fifth width EW5 in the second direction (X-axis direction). The fifth light-emitting length EVL5 may be the sum of the first light-emitting length EVL1, the first lower length BVL1, and the first 'upper length REL1'. The first 'upper length REL1' may be shorter than the first upper length REL1. If the first 'upper length REL1' is equal to or longer than the first upper length REL1, the pixel electrode 114 overlaps with the reference wiring RL, thereby reducing the light efficiency. The fifth width EW5 may be equal to the first width EW1. Therefore, according to Figure 9 In the case of a display device, compared with the case where the second wiring 122 is set in the upper process margin area, the size (or area) of the light-emitting area EA can be further enlarged in the first direction (Y-axis direction), thereby further improving the light efficiency.

[0210] At the same time, such as Figure 9 As shown, the circuit area CA of the display device 100 according to the fourth embodiment of the present invention may be provided with a dimension (or area) having a fifth circuit length CVL5 in the first direction (Y-axis direction) and a fifth width EW5 in the second direction (X-axis direction). The fifth circuit length CVL5 may be a length obtained by subtracting the first lower length BVL1 from the first circuit length CVL1. The fifth width EW5 may be equal to the first width EW1.

[0211] like Figure 6 As shown, compared to other embodiments, the display device 100 according to the first embodiment of the present invention can have optimal light efficiency by making the first wiring 121, which partially overlaps with the third pixel electrode 114c and the fourth pixel electrode 114d, narrower than the second wiring 122. That is, the display device 100 according to one embodiment of the present invention has two non-screen areas in which the light-emitting area EA is covered by the first wiring 121. However, since the area of ​​the non-screen areas is the smallest compared to other embodiments, the light efficiency can be optimal compared to other embodiments.

[0212] like Figure 8 As shown, the display device 100 according to the third embodiment of the present invention has only one non-screen area because the pixel electrode 114 is horseshoe-shaped, but the fourth pixel electrode 114d is omitted, so the light efficiency (or luminous efficiency) can be lower than the light efficiency (or luminous efficiency) of the display device 100 according to the first embodiment.

[0213] At the same time, such as Figure 7As shown, the display device 100 according to the second embodiment of the present invention has a pixel electrode 114 (or light-emitting area EA) in a closed-loop form, and the pixel electrode 114 (or light-emitting area EA) is provided with a size (or area) extending to a portion of the upper process margin region, thereby maximizing the area of ​​the pixel electrode 114 (or light-emitting area EA) compared to other embodiments. Therefore, compared to other embodiments, the display device 100 according to the second embodiment of the present invention has the largest area of ​​the pixel electrode 114 (or light-emitting area EA), thus exhibiting the lowest current density during driving and consequently the longest service life.

[0214] The present invention can also be described as follows.

[0215] In one aspect, a display device may include: a substrate including a display area and a non-display area surrounding the display area, a plurality of sub-pixels being arranged in the display area, and the display area including a first non-light-emitting area and a light-emitting area; wiring disposed on the substrate; and a first reflective portion disposed on the substrate, wherein the wiring may partially overlap with the first non-light-emitting area and the light-emitting area, and the first reflective portion is located in the first non-light-emitting area.

[0216] The first non-light-emitting area may be disposed on the inner side of each of the plurality of sub-pixels, and the display area may further include a second non-light-emitting area disposed on the outer side of each of the plurality of sub-pixels.

[0217] The first reflective portion may include: a first flat reflective portion arranged parallel to the upper surface of the substrate; and a first tilted reflective portion connected to the first flat reflective portion.

[0218] The display device may further include: a first planarization layer disposed on the wiring; a second planarization layer disposed on the first planarization layer; and a first patterned portion disposed on the second planarization layer, wherein the first reflective portion may be disposed on the first patterned portion, and wherein the first patterned portion may be located in the first non-light-emitting area.

[0219] The first planarization layer can be formed continuously across the multiple sub-pixels, and the second planarization layer can be arranged in an island pattern.

[0220] The display device may further include a pixel electrode disposed on the second planarization layer, wherein each of the plurality of sub-pixels may include a thin-film transistor, and the pixel electrode may be connected to the drain or source of the thin-film transistor through a contact hole through the first planarization layer.

[0221] The first patterned portion may be recessed on the second planarization layer and may be arranged to be spaced apart from the light-emitting area.

[0222] The first reflective portion may be formed along the outline of the first pattern portion that is recessed in the first non-light-emitting area.

[0223] The width of the first patterned portion can be formed to decrease in the direction from the first reflective portion toward the substrate.

[0224] The display device may further include: a second patterned portion, the second patterned portion being recessedly disposed on the second planarization layer; and a second reflective portion disposed on the second patterned portion, wherein the second patterned portion and the second reflective portion may be located in the second non-light-emitting area.

[0225] The second patterned portion may be arranged to be spaced apart from the light-emitting area, wherein the width of the second patterned portion may be formed to decrease in the direction from the second reflective portion toward the substrate.

[0226] The first planarization layer may be configured to have a different refractive index than the second planarization layer.

[0227] The first flat reflective portion and a portion of the first tilted reflective portion may be positioned closer to the substrate than the pixel electrode.

[0228] The width of the wiring can be set to be equal to or narrower than the width of the first flat reflective portion.

[0229] The pixel electrode can be arranged at a predetermined distance from the first reflective portion in a direction parallel to the upper surface of the substrate.

[0230] The display device may further include: data wiring extending in a direction perpendicular to the upper surface of the substrate; and gate wiring and reference wiring extending in a direction parallel to the upper surface of the substrate, wherein the wiring may include: a first wiring extending from the thin-film transistor in a direction perpendicular to the upper surface of the substrate and partially overlapping the light-emitting region and the first non-light-emitting region; and a second wiring extending in a direction parallel to the upper surface of the substrate and connected to the data wiring.

[0231] The reference wiring and the second wiring may be located in the upper process margin region. The width of the first wiring may be set to be narrower than the width of the first non-light-emitting region, and the width of the second wiring may be set to be smaller than the width of the upper process margin region.

[0232] The width of the first wiring can be set to be narrower than the width of the second wiring.

[0233] The first wiring may partially overlap with the pixel electrode, while the second wiring may not overlap with the pixel electrode.

[0234] The pixel electrode can be configured in a closed loop or in a horseshoe shape with an opening on one side.

[0235] The end of the first wiring may be disposed in the upper process margin area, wherein the second wiring may be connected to the end of the first wiring that protrudes into the upper process margin area.

[0236] The display device may further include: data wiring extending in a direction perpendicular to the upper surface of the substrate; and gate wiring and reference wiring extending in a direction parallel to the upper surface of the substrate, wherein the wiring may include: a first wiring extending from the thin-film transistor in a direction perpendicular to the upper surface of the substrate, and an end of the first wiring disposed in a first non-light-emitting region; and a second wiring connected to the end of the first wiring in the first non-light-emitting region, and extending in a direction parallel to the upper surface of the substrate to connect to the data wiring.

[0237] The reference wiring may be located in the upper process margin area, wherein the second wiring may not be located in the upper process margin area.

[0238] The first wiring may partially overlap with the pixel electrode, and the second wiring may partially overlap with the pixel electrode.

[0239] The first wiring may not overlap with the pixel electrode, while the second wiring may partially overlap with the pixel electrode.

[0240] The pixel electrode can be configured in a closed loop or in a horseshoe shape with an opening on one side.

[0241] The pixel electrode may be configured to extend to a portion of the upper process margin region.

[0242] The wiring may overlap with the first flat reflective portion.

[0243] In another aspect, a display device may include: a substrate including a plurality of pixels having a plurality of sub-pixels, the substrate including a light-emitting region disposed in each of the plurality of sub-pixels; and wiring partially overlapping the light-emitting region, wherein the substrate may further include a second non-light-emitting region located on the outer side of each of the plurality of sub-pixels, wherein the second non-light-emitting region may include: a first planarization layer disposed on the substrate; a second planarization layer disposed on the first planarization layer; a second patterned portion recessed on the second planarization layer; and a second reflective portion disposed on the second patterned portion.

[0244] The display device may further include a thin-film transistor for driving each of the plurality of sub-pixels, wherein the wiring may be branch wiring connected to the thin-film transistor, wherein the branch wiring may include data branch wiring.

[0245] The first planarization layer may have a different refractive index than the second planarization layer.

[0246] The second reflective portion may be disposed between the pixel electrodes included in each of the plurality of sub-pixels that emit light of different colors.

[0247] Each of the plurality of sub-pixels may include a pixel electrode arranged at a distance from the second reflective portion.

[0248] The second reflective portion may be partially arranged closer to the substrate than the pixel electrode.

[0249] The second reflective portion may include: a second flat reflective portion arranged parallel to the upper surface of the substrate; and a second oblique reflective portion connected to the second flat reflective portion, wherein data wiring that partially overlaps with the second flat reflective portion may be provided on the substrate, wherein the data wiring may be connected to the wiring.

[0250] The substrate may further include a first non-light-emitting area located inside the light-emitting area, and the wiring may partially overlap with the first non-light-emitting area.

[0251] The first non-light-emitting area may include: a first patterned portion recessed on the second planarization layer; and a first reflective portion disposed on the first patterned portion.

[0252] Each of the plurality of sub-pixels may include a pixel electrode arranged at a distance from the first reflective portion.

[0253] The first reflective portion may be partially arranged closer to the substrate than the pixel electrode.

[0254] The first reflective portion may include: a first flat reflective portion arranged parallel to the upper surface of the substrate; and a first tilted reflective portion connected to the first flat reflective portion, wherein the wiring may overlap with the first flat reflective portion.

[0255] The width of the wiring may be equal to or narrower than the width of the first flat reflective portion.

[0256] Each of the plurality of sub-pixels may include a pixel electrode disposed in the light-emitting area, wherein the pixel electrode may include: a first pixel electrode, the first pixel electrode being arranged at a distance from one side of the first reflective portion; a second pixel electrode, the second pixel electrode being arranged at a distance from the other side of the first reflective portion; a third pixel electrode, the third pixel electrode connecting one side of the first pixel electrode and one side of the second pixel electrode; and a fourth pixel electrode, the fourth pixel electrode connecting the other side of the first pixel electrode and the other side of the second pixel electrode, wherein the wiring may overlap with two or more portions of the first pixel electrode, the second pixel electrode, the third pixel electrode and the fourth pixel electrode.

[0257] The wiring may include: a first wiring disposed between the first pixel electrode and the second pixel electrode; and a second wiring connected to the first wiring and disposed in a different direction from the first wiring, wherein the first wiring may partially overlap with the fourth pixel electrode and the second wiring may partially overlap with the second pixel electrode.

[0258] The plurality of sub-pixels may further include data wiring arranged along a first direction between adjacent sub-pixels, and the second wiring may partially overlap with the data wiring.

[0259] The plurality of sub-pixels may further include a dam that covers the edges on both sides of the pixel electrode in the first direction, wherein the dam may not be arranged between the first sub-pixel and the second sub-pixel or between the second sub-pixel and the third sub-pixel.

[0260] Each of the plurality of sub-pixels may further include: a circuit region disposed on one side of the light-emitting region and including a thin-film transistor; a gate wiring disposed between the light-emitting region and the circuit region along the second direction; and a pixel power wiring disposed parallel to the data wiring and interspersed therebetween the light-emitting region, the gate wiring being partially overlapping each of the pixel power wiring and the data wiring.

[0261] Embodiments of the invention have been described in more detail with reference to the accompanying drawings; however, the invention is not limited to these embodiments and can be practiced in various modifications without departing from the inventive concept. Therefore, the embodiments disclosed herein are intended to illustrate, not limit, the inventive concept, and the scope of the inventive concept is not limited by these embodiments. Thus, the above embodiments are exemplary in all respects and should be understood as non-limiting. All inventive concepts within the scope of protection of this invention should be interpreted as included within the scope of the claims of this invention.

[0262] The display device according to the invention is configured such that the wiring for driving each of the plurality of sub-pixels partially overlaps with a non-light-emitting area (or a first non-light-emitting area) disposed on the inner side of each of the plurality of sub-pixels, thereby allowing an increase in the size (or area) of the light-emitting area.

[0263] Due to the increased size (or area) of the light-emitting area, the display device according to the present invention can have an improved service life.

[0264] The display device according to the present invention is provided with a reflective portion (or a first reflective portion) (which is arranged in a non-light-emitting area (or a first non-light-emitting area) located inside each of the plurality of sub-pixels), thereby improving the light extraction efficiency of light emitted from the light-emitting element layer.

[0265] The display device according to the present invention is provided with a reflective portion (or a second reflective portion) (which is arranged in a non-light-emitting area (or a second non-light-emitting area) located on the outside of each of a plurality of sub-pixels), so that the reflective portion (or the second reflective portion) can reflect light guided toward adjacent sub-pixels, thereby maximizing the light extraction efficiency.

[0266] Since the display device according to the present invention can extract light even in the non-light-emitting area by means of reflective portions (or first reflective portions and second reflective portions) provided on the inner and outer sides of each of the multiple sub-pixels, the display device can have the same luminous efficiency or even improved luminous efficiency with lower power compared to a display device that does not have reflective portions on the inner and outer sides of each of the multiple sub-pixels, thereby reducing the total power consumption.

[0267] The effects obtained from this invention are not limited to those described above, and other effects not mentioned will be obvious to those skilled in the art based on the description.

Claims

1. A display device, comprising: A substrate, the substrate including a display area and a non-display area surrounding the display area, wherein a plurality of sub-pixels are arranged in the display area, and the display area includes a first non-light-emitting area and a light-emitting area; Wiring disposed on the substrate; and The first reflective portion disposed on the substrate The wiring partially overlaps with the first non-light-emitting area and the light-emitting area, and the first reflective portion is located in the first non-light-emitting area.

2. The display device according to claim 1, wherein the first non-light-emitting area is disposed on the inner side of each of the plurality of sub-pixels. The display area further includes a second non-light-emitting area disposed on the outer side of each of the plurality of sub-pixels.

3. The display device according to claim 2, wherein the first reflective portion comprises: A first flat reflective portion arranged parallel to the upper surface of the substrate; as well as A first tilted reflector connected to the first flat reflector.

4. The display device according to claim 3, further comprising: A first planarization layer is disposed on the wiring; A second planarization layer disposed on the first planarization layer; as well as The first pattern portion is disposed on the second planarization layer. The first reflective part is disposed on the first pattern part. The first patterned portion is located in the first non-light-emitting area.

5. The display device according to claim 4, further comprising: Pixel electrodes disposed on the second planarization layer, Each of the plurality of sub-pixels includes a thin-film transistor. The pixel electrode is connected to the drain or source of the thin-film transistor through a contact hole passing through the first planarization layer.

6. The display device according to claim 4, wherein the first reflective portion is formed along the contour of the first pattern portion recessed in the first non-light-emitting area.

7. The display device according to claim 4, wherein the width of the first patterned portion is formed to decrease in the direction from the first reflective portion toward the substrate.

8. The display device according to claim 4, further comprising: The second pattern portion is recessed on the second planarization layer; as well as The second reflective portion is provided on the second pattern portion. The second patterned portion and the second reflective portion are located in the second non-light-emitting area.

9. The display device of claim 4, wherein the first planarization layer is configured to have a different refractive index than the second planarization layer.

10. The display device of claim 5, wherein the first flat reflective portion and a portion of the first tilted reflective portion are positioned closer to the substrate than the pixel electrode.

11. The display device according to claim 3, wherein the width of the wiring is set to be equal to or narrower than the width of the first flat reflective portion.

12. The display device according to claim 5, wherein the pixel electrode is arranged at a predetermined distance from the first reflective portion in a direction parallel to the upper surface of the substrate.

13. The display device according to claim 5, further comprising: Data wiring extending in a direction perpendicular to the upper surface of the substrate; as well as Gate wiring and reference wiring extending in a direction parallel to the upper surface of the substrate. The wiring includes: A first wiring extends from the thin-film transistor in a direction perpendicular to the upper surface of the substrate and partially overlaps with the light-emitting area and the first non-light-emitting area; as well as The second wiring extends in a direction parallel to the upper surface of the substrate and is connected to the data wiring.

14. The display device of claim 13, wherein the reference wiring and the second wiring are located in the upper process margin region. The width of the first wiring is set to be narrower than the width of the first non-light-emitting area. The width of the second wiring is set to be smaller than the width of the upper process margin area.

15. The display device of claim 14, wherein the width of the first wiring is set to be narrower than the width of the second wiring.

16. The display device of claim 13, wherein the first wiring partially overlaps with the pixel electrode. The second wiring does not overlap with the pixel electrode.

17. The display device of claim 13, wherein the pixel electrode is arranged in a closed loop or is configured as a horseshoe shape with an opening on one side.

18. The display device according to claim 14, wherein the end of the first wiring is disposed in the upper process margin region. The second wiring is connected to the end of the first wiring that protrudes into the upper process margin region.

19. The display device according to claim 5, further comprising: Data wiring extending in a direction perpendicular to the upper surface of the substrate; as well as Gate wiring and reference wiring extending in a direction parallel to the upper surface of the substrate. The wiring includes: A first wiring extends from the thin-film transistor in a direction perpendicular to the upper surface of the substrate, and the end of the first wiring is disposed in the first non-light-emitting area. as well as The second wiring is connected to the end of the first wiring in the first non-light-emitting area and extends in a direction parallel to the upper surface of the substrate to connect to the data wiring.

20. The display device of claim 19, wherein the reference wiring is located in the upper process margin region. The second wiring is not located in the upper process margin area.

21. The display device of claim 19, wherein the first wiring partially overlaps with the pixel electrode. The second wiring partially overlaps with the pixel electrode.

22. The display device of claim 19, wherein the first wiring does not overlap with the pixel electrode. The second wiring partially overlaps with the pixel electrode.

23. The display device of claim 19, wherein the pixel electrode is arranged in a closed loop or is configured as a horseshoe shape with an opening on one side.

24. The display device of claim 20, wherein the pixel electrode is provided with a dimension extending into a portion of the upper process margin region.

25. The display device according to claim 3, wherein the wiring overlaps with the first flat reflective portion.

26. A display device, comprising: A substrate, the substrate comprising a plurality of pixels having a plurality of sub-pixels, the substrate comprising a light-emitting region disposed in each of the plurality of sub-pixels; as well as The wiring partially overlaps with the light-emitting area. The substrate further includes a second non-light-emitting region located on the outer side of each of the plurality of sub-pixels. The second non-light-emitting region includes: A first planarization layer disposed on the substrate; A second planarization layer disposed on the first planarization layer; The second patterned portion is recessed and formed on the second planarization layer; and A second reflective portion disposed on the second pattern portion.

27. The display device of claim 26, further comprising a thin-film transistor for driving each of the plurality of sub-pixels. The wiring described therein is a branch wiring connected to the thin-film transistor. The branch cabling mentioned therein includes data branch cabling.

28. The display device of claim 26, wherein the first planarization layer has a different refractive index than the second planarization layer.

29. The display device of claim 26, wherein the second reflective portion is disposed between pixel electrodes included in each of the plurality of sub-pixels that emit light of different colors.

30. The display device of claim 26, wherein each of the plurality of sub-pixels includes a pixel electrode arranged at a distance from the second reflective portion.

31. The display device of claim 30, wherein the second reflective portion is partially arranged closer to the substrate than the pixel electrode.

32. The display device according to claim 26, wherein the second reflective portion comprises: The second flat reflective portion is arranged parallel to the upper surface of the substrate; as well as The second tilted reflector is connected to the second flat reflector. The substrate has data wiring that partially overlaps with the second flat reflective portion. The data cabling is connected to the cabling.

33. The display device of claim 26, wherein the substrate further includes a first non-light-emitting region located inside the light-emitting region, and the wiring partially overlaps with the first non-light-emitting region.

34. The display device according to claim 33, wherein the first non-light-emitting area comprises: A first patterned portion is recessed on the second planarization layer; as well as A first reflective portion disposed on the first pattern portion.

35. The display device of claim 34, wherein each of the plurality of sub-pixels includes a pixel electrode arranged at a distance from the first reflective portion.

36. The display device of claim 35, wherein the first reflective portion is partially arranged closer to the substrate than the pixel electrode.

37. The display device according to claim 34, wherein the first reflective portion comprises: A first flat reflective portion is arranged parallel to the upper surface of the substrate; as well as A first tilted reflective portion, which is connected to the first flat reflective portion. The wiring overlaps with the first flat reflective portion.

38. The display device of claim 37, wherein the width of the wiring is equal to or narrower than the width of the first flat reflective portion.

39. The display device of claim 34, wherein each of the plurality of sub-pixels includes a pixel electrode disposed in the light-emitting area. The pixel electrode includes: The first pixel electrode is arranged at a distance from one side of the first reflective portion; The second pixel electrode is arranged at a distance from the other side of the first reflective portion; A third pixel electrode, wherein the third pixel electrode is connected to one side of the first pixel electrode and one side of the second pixel electrode; and The fourth pixel electrode is connected to the other side of the first pixel electrode and the other side of the second pixel electrode. The wiring overlaps with two or more portions of the first pixel electrode, the second pixel electrode, the third pixel electrode, and the fourth pixel electrode.

40. The display device according to claim 39, wherein the wiring comprises: A first wiring is provided, wherein the first wiring is disposed between the first pixel electrode and the second pixel electrode; as well as A second wiring is connected to the first wiring and is arranged in a different direction than the first wiring. The first wiring partially overlaps with the fourth pixel electrode, and the second wiring partially overlaps with the second pixel electrode.

41. The display device of claim 40, wherein the plurality of sub-pixels further includes data wiring arranged between adjacent sub-pixels along a first direction, and the second wiring partially overlaps with the data wiring.

42. The display device of claim 41, wherein the plurality of sub-pixels further comprises a dam covering an edge located on both sides of the pixel electrode in the first direction. The embankment is not located between the first sub-pixel and the second sub-pixel, nor between the second sub-pixel and the third sub-pixel.

43. The display device of claim 42, wherein each of the plurality of sub-pixels further comprises: A circuit region is disposed on one side of the light-emitting region and includes a thin-film transistor; A gate wiring, wherein the gate wiring is arranged along the second direction between the light-emitting region and the circuit region; The pixel power wiring is arranged parallel to the data wiring and the light-emitting area is interspersed therebetween. The gate wiring partially overlaps with each of the pixel power wiring and the data wiring.

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