Display panel and display device

Abstract

This application relates to a display panel and a display device. The display panel includes a substrate, a pad, a protective layer, and side traces. The substrate includes a first surface and a second surface disposed opposite to each other. The pad is located on the first surface and includes a test area, a middle area, and an overlap area connected sequentially along a first direction, which is parallel to the first surface. The protective layer is located on the side of the pad away from the substrate and covers a portion of the pad. The protective layer has a first opening and a second opening. The first opening exposes at least a portion of the surface of the test area, and the second opening exposes at least a portion of the surface of the overlap area. The side traces are located on the side of the pad and the protective layer away from the substrate and extend to cover the side of the substrate and the second surface. The side traces expose the first opening and at least cover the overlap area exposed by the second opening and the protective layer around the second opening. This application reduces the probability of side trace peeling, which helps to improve the yield and stability of the display panel.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a display panel and display device. Background Technology

[0002] Micro-LED (Micro Light Emitting Diode Display) technology boasts advantages such as high brightness, wide color gamut, and high reliability. It easily achieves flexible, transparent, freely spliced, and sensor-integrated effects, making it widely used in micro-displays, consumer electronics, and large-screen displays. It is widely recognized by the industry as the next-generation display technology. In the development of Micro-LED display technology, "infinite splicing" is considered an important industrialization goal, and side-mounted wiring is a key technology for achieving this effect.

[0003] However, in the actual manufacturing process, the side wiring is complex, which to some extent affects the yield and stability of the display panel. Summary of the Invention

[0004] Therefore, it is necessary to provide a display panel and display device to reduce the probability of side traces peeling off, thereby helping to improve the yield and stability of the display panel.

[0005] In a first aspect, this application provides a display panel, including:

[0006] The substrate includes a first surface and a second surface disposed opposite to each other;

[0007] A pad, located on the first surface, includes a test area, an intermediate area, and an overlap area connected sequentially along a first direction, the first direction being parallel to the first surface;

[0008] A protective layer is located on the side of the pad away from the substrate and covers a portion of the pad. The protective layer is provided with a first opening and a second opening, the first opening exposing at least a portion of the surface of the test area and the second opening exposing at least a portion of the surface of the overlap area.

[0009] Side routing is located on the side of the padding and the protective layer away from the substrate, and extends to cover the side of the substrate and the second surface. The side routing exposes the first opening and at least covers the overlap area exposed by the second opening and the protective layer around the second opening.

[0010] This application provides a pad comprising a test area, a middle area, and an overlap area on the first surface of the substrate, and provides a protective layer covering the pad and the first surface to protect the pad and the substrate. By exposing at least a portion of the overlap area through a second opening of the protective layer, and by ensuring that the side traces completely cover the overlap area and the protective layer around the second opening, the adhesion between the side traces and the pad is enhanced, reducing the probability of the side traces peeling off and exposing the overlap area. At the same time, the first opening of the protective layer exposes at least a portion of the test area, and the side traces do not cover the test area exposed by the first opening, so that the test area can be used to perform open circuit and short circuit tests on the display panel, reducing the difficulty of testing.

[0011] In one embodiment, an electrostatic discharge (ESD) protection device is disposed within the substrate, and the ESD protection device is connected to the test area of ​​the pad via a first interconnect.

[0012] This application, by setting an electrostatic discharge (ESD) protection device connected to the test area of ​​the pad, helps to absorb the charge accumulated in the test area, thereby reducing the probability of ESD damage to the display panel.

[0013] In one embodiment, a plurality of thin-film transistors are further disposed within the substrate, the plurality of thin-film transistors being spaced apart on the side of the electrostatic discharge protection device away from the pad, the thin-film transistors being connected to the electrostatic discharge protection device via a second interconnect line, and the first interconnect line and the second interconnect line being separate from each other.

[0014] This application connects the thin-film transistor and the pad to an electrostatic discharge (ESD) protection device, which effectively eliminates the charge accumulated in the thin-film transistor and the pad, while avoiding the probability of charge accumulated in the test area being transferred to the thin-film transistor due to the connection of the first interconnect and the second interconnect, thereby reducing the probability of the thin-film transistor being damaged by ESD.

[0015] In one embodiment, along the first direction, the width of the intermediate area is smaller than the width of the test area and the width of the overlap area, respectively.

[0016] This application helps to increase the distance between the middle areas of two adjacent pads by setting a width smaller than that of the test area and the overlap area, thereby helping to avoid short circuit abnormalities that may be caused by the small spacing between the two adjacent side traces.

[0017] In one embodiment, the width of the middle area is greater than the minimum design width, and the width of the middle area is less than or equal to 80% of the width of the overlap area.

[0018] This application increases the distance between the middle zones of two adjacent gaskets while ensuring the quality of the gasket process by controlling the width of the middle zone to between the minimum design width and 80% of the overlap zone width, thereby helping to further reduce the risk of short circuits between adjacent gaskets.

[0019] In one embodiment, the width of the overlap area is smaller than the width of the test area.

[0020] This application increases the area ratio of the test area within the pad by setting a relatively large test area, which is wider than the width of the middle area and the overlap area. This reduces the area ratio of the overlap area within the pad, thereby reducing the area of ​​the side traces to be wrapped. This helps to improve the accuracy of subsequent electrical tests using the test area, reduces the difficulty of aligning the pins in the test area during electrical testing, and also helps to reduce the probability of the overlap area peeling off from the side traces. In this way, it effectively improves the efficiency and accuracy of electrical testing of the display panel, and improves the yield and stability of the display panel.

[0021] In one embodiment, the width of the intermediate region is in the range of 50μm to 120μm.

[0022] This application increases the distance between the intermediate zones of two adjacent pads by controlling the width of the intermediate zone, thereby helping to further reduce the risk of short circuits between adjacent pads.

[0023] In one embodiment, the material of the pad and the side trace includes a conductive material, which includes at least one of metallic copper and metallic aluminum.

[0024] This application ensures the conductivity of the pads and side traces by setting the materials used for the pads and side traces, thereby helping to ensure the normal functioning of the display panel.

[0025] In one embodiment, the material of the protective layer includes an inorganic insulating material, which includes at least one of ceramics, mica, and glass.

[0026] This application reduces or avoids the risk of short circuits between different conductive structures in the display panel by setting a protective layer made of inorganic insulating material, while also helping to protect other structures in the display panel from damage.

[0027] Secondly, this application also provides a display device, which includes the display panel described above.

[0028] In summary, this application provides a display panel and a display device. The display panel includes a substrate, a pad, a protective layer, and side traces. The substrate includes a first surface and a second surface disposed opposite to each other. The pad is located on the first surface and includes a test area, a middle area, and an overlap area connected sequentially along a first direction, the first direction being parallel to the first surface. The protective layer is located on the side of the pad away from the substrate and covers a portion of the pad. The protective layer has a first opening and a second opening. The first opening exposes at least a portion of the surface of the test area, and the second opening exposes at least a portion of the surface of the overlap area. The side traces are located on the side of the pad and the protective layer away from the substrate and extend to cover the side of the substrate and the second surface. The side traces expose the first opening and at least cover the overlap area exposed by the second opening and the protective layer around the second opening. This application reduces the probability of side trace peeling, which helps to improve the yield and stability of the display panel. Attached Figure Description

[0029] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0030] Figure 1 This is a schematic diagram of the cross-sectional structure of a display substrate in a related technology.

[0031] Figure 2 This is a schematic diagram of the structure of the upper surface of a display substrate in a related technology.

[0032] Figure 3 This is a schematic diagram of the structure of pads and side traces on the upper surface of a display substrate in a related technology.

[0033] Figure 4 This is a cross-sectional structural diagram of a display panel provided in one embodiment of this application.

[0034] Figure 5 This is a top view of the first surface of a display panel provided in one embodiment of this application.

[0035] Figure 6 This is a schematic diagram of the structure of the pad and side wiring in the first surface of a display panel provided in one embodiment of this application.

[0036] Figure 7 This is a schematic diagram of the structure of a display device provided in one embodiment of this application.

[0037] The reference numerals in the figures include: 100-substrate; 101-upper surface; 102-lower surface; 110-pad; 120-insulating layer; 121-opening; 130-side trace; 200-base; 201-first surface; 202-second surface; 210-pad; 211-test area; 211a-via connection area; 212-intermediate area; 213-overlap area; 220-protective layer; 221-first opening; 222-second opening; 230-side trace; 240-electrostatic discharge protection device; 241-first interconnect; 250-thin film transistor; 251-second interconnect; 260-light-emitting chip structure; 300-display device; 310-display panel. Detailed Implementation

[0038] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0039] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0040] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this application, the first element, part, region, layer, doping type, or portion discussed below may be referred to as a second element, part, region, layer, or portion.

[0041] Spatial relation terms such as “below,” “under,” “below,” “below,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, an element or feature described as “below,” “below,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0042] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term “and / or” includes any and all combinations of the associated listed items.

[0043] Micro-LED (Micro Light Emitting Diode Display) technology boasts advantages such as high brightness, wide color gamut, and high reliability. It easily achieves flexible, transparent, freely spliced, and sensor-integrated effects, making it widely used in micro-displays, consumer electronics, and large-screen displays. It is widely recognized by the industry as the next-generation display technology. In the development of Micro-LED display technology, "infinite splicing" is considered an important industrialization goal, and side-mounted wiring is a key technology for achieving this effect.

[0044] Figure 1 This is a schematic cross-sectional view of a display substrate in a related technology. Figure 2 for Figure 1 The diagram shows a top view of the upper surface of the display substrate. Figure 1 Corresponding to Figure 2 Cross-sectional structure along the PQ direction.

[0045] See Figure 1 and Figure 2Generally, the display substrate includes a substrate 100, pads 110, an insulating layer 120, and side traces 130. The substrate 100 includes an upper surface 101 and a lower surface 102 disposed opposite to each other. The pads 110 are located on the upper surface 101. The insulating layer 120 is located on the side of the pads 110 away from the substrate 100, and an opening 121 is provided within the insulating layer 120 to expose the pads 110. The side traces 130 are located on the side of the insulating layer 120 away from the pads 110, and extend to cover the side edge and lower surface 102 of the substrate 100. The side traces 130 extend into the opening 121 and cover a portion of the surface of the pads 110. Optionally, the materials of the pads 110 and the side traces 130 respectively include conductive materials, such as at least one of metallic copper and metallic aluminum. Optionally, the material of the insulating layer 120 may include an inorganic insulating material, such as one of silicon oxide, silicon nitride, or silicon oxynitride.

[0046] It should be noted that, for reference Figure 2 and Figure 3 While the side trace 130 covers part of the surface of the pad 110, part of the surface of the pad 110 is still not covered by the side trace 130, so that the test probe can be stuck on the exposed surface of the pad 110 during the open-short test (OS) of the display substrate, thereby ensuring the smooth progress of the open-short test of the display substrate.

[0047] For example, see Figure 3 The area enclosed by the dashed rectangle represents the portion of pad 110 covered by the side trace 130. It can be seen that in typical display substrates, the side trace 130 does not cover the entire surface of pad 110; therefore, the overlap area between the side trace 130 and pad 110 is not a full-coverage design. For example, during the manufacturing process of the side trace 130, a temporary protective film (not shown in the figure) is typically applied to both the upper surface 101 and lower surface 102 of the substrate 100. This temporary protective film exposes the areas on the upper surface 101 and lower surface 102 where the side trace 130 will be formed. Subsequently, the side trace 130 is formed on the exposed surfaces of the upper surface 101 and lower surface 102 as described above. The temporary protective film is then removed after the side trace 130 is formed.

[0048] In the display substrate described above, since the overlap area between the side trace 130 and the pad 110 is not a full-coverage design, part of the pad 110 is retained for electrical testing of the side trace 130. However, when the edge of the side trace 130 is in direct contact with the pad 110 it overlaps with, the adhesion between the pad 110 and the side trace 130 is weak, making it very easy to become a weak point for peeling, causing the overlap edge area of ​​the side trace 130 to become a peeling-prone area.

[0049] Based on this, in the manufacturing process described above, since a temporary protective plate is first covered on the surface of the substrate 100 and then the side trace 130 is formed, if the edge of the side trace 130 is adhered to or overlapped with the temporary protective film during the subsequent removal of the temporary protective film, it is very easy for the part of the side trace 130 close to the temporary protective film (i.e. the part of the side trace 130 that overlaps with the pad 110) to be peeled off together.

[0050] For example, see Figure 2 In the area circled by the dashed line in the figure, the side trace 130 has been stripped, causing at least part of the overlap area between the side trace 130 and the pad 110 to be exposed, which affects the connection quality between the side trace 130 and the pad 110. In severe cases, it may even affect the yield and stability of the display panel.

[0051] Generally, reducing the area of ​​the pads can reduce the overlap area, which helps improve the separation between the pads and side traces. However, reducing the pad area increases the difficulty of probe testing during electrical testing (such as OS testing), significantly increasing the probability of test probes hitting blank areas and causing false tests, which seriously affects testing efficiency and the accuracy of test results.

[0052] Therefore, it is necessary to provide a display panel and display device to reduce the probability of side traces peeling off, thereby helping to improve the yield and stability of the display panel.

[0053] Figure 4 This is a cross-sectional structural diagram of a display panel provided in one embodiment of this application. Figure 5 for Figure 4 The diagram shows a top view of the first surface of the display panel. Figure 4 for Figure 5 A schematic diagram of the cross-sectional structure along the MN direction.

[0054] See Figure 4 and Figure 5One embodiment of this application provides a display panel including a substrate 200, a pad 210, a protective layer 220, and side traces 230; wherein, the substrate 200 includes a first surface 201 and a second surface 202 disposed opposite to each other; the pad 210 is located on the first surface 201 and includes a test area 211, a middle area 212, and an overlap area 213 sequentially connected along a first direction (i.e., direction A), the first direction being parallel to the first surface 201; the protective layer 220 is located on the side of the pad 210 away from the substrate 200 and covers a portion of the pad 210. The protective layer 220 is provided with a first opening 221 and a second opening 222. The first opening 221 exposes at least a portion of the surface of the test area 211, and the second opening 222 exposes at least a portion of the surface of the overlap area 213. The side wiring 230 is located on the side of the pad 210 and the protective layer 220 away from the substrate 200, and extends to cover the side of the substrate 200 and the second surface 202. The side wiring 230 exposes the first opening 221 and at least covers the overlap area 213 exposed by the second opening 222 and the protective layer 220 around the second opening 222.

[0055] This application provides a pad comprising a test area, a middle area, and an overlap area on the first surface of the substrate, and provides a protective layer covering the pad and the first surface to protect the pad and the substrate. By exposing at least a portion of the overlap area through a second opening of the protective layer, and by ensuring that the side traces completely cover the overlap area and the protective layer around the second opening, the adhesion between the side traces and the pad is enhanced, reducing the probability of the side traces peeling off and exposing the overlap area. At the same time, the first opening of the protective layer exposes at least a portion of the test area, and the side traces do not cover the test area exposed by the first opening, so that the test area can be used to perform open circuit and short circuit tests on the display panel, reducing the difficulty of testing.

[0056] Continue reading Figure 4 and Figure 5 In one embodiment, the substrate 200 includes a first region X1 and a second region X2 disposed adjacent to each other. The first region X1 is an edge region of the substrate 200 near one side and includes a pad 210 and a side trace 230. The second region X2 is a region of the substrate 200 on the side away from the side trace 230. Accordingly, the first direction (i.e., direction A) is the direction away from the second region X2.

[0057] See Figure 4In one embodiment, an electrostatic discharge (ESD) protection device 240 is provided in the substrate 200, and the ESD protection device 240 is connected to the test area 211 of the pad 210 through a first interconnect 241, so as to absorb the charge accumulated in the test area 211 by utilizing the ESD protection device 240, thereby reducing the probability of electrostatic damage in the display panel.

[0058] In one embodiment, the material of the first interconnect 241 includes a conductive material, and the conductive material includes at least one of metallic copper and metallic aluminum. In other embodiments of this application, the material of the first interconnect can also be replaced with other commonly used conductive materials (including metallic conductive materials and alloy conductive materials) as needed, and this application does not impose any restrictions on this.

[0059] See Figure 4 and Figure 6 In one embodiment, the test area 211 further includes a via connection area 211a for connection to the first interconnect 241, ensuring that the test area 211 can be connected to the electrostatic discharge protection device 240 via the first interconnect 241. Optionally, a protective layer 220 covers the via connection area 211a, and a first opening 221 in the protective layer 220 exposes the remaining area of ​​the test area 211 other than the via connection area 211a, thereby helping to improve the yield of the display panel.

[0060] See Figure 4 and Figure 5 In one embodiment, a plurality of thin film transistors (TFTs) are also disposed within the substrate 200. The TFTs are spaced apart on the side of the electrostatic discharge protection device 240 away from the pad 210, and the TFTs are connected to the electrostatic discharge protection device 240 through a second interconnect 251. The first interconnect 241 and the second interconnect 251 are separated from each other.

[0061] Continue reading Figure 4 In one embodiment, the thin-film transistor 250 is located in the second region X2, and the second region X2 also includes a light-emitting chip structure 260, one end of which is connected to one end of the thin-film transistor 250 to realize the display function of the display panel.

[0062] In one embodiment, the material of the second interconnecting line 251 includes a conductive material, and the conductive material includes at least one of metallic copper and metallic aluminum. Optionally, the material of the first interconnecting line 241 may be the same as or different from the material of the second interconnecting line 251. In other embodiments of the present application, the material of the second interconnecting line may also be replaced with other commonly used conductive materials (including metallic conductive materials and alloy conductive materials) according to actual needs, and the present application does not limit this.

[0063] It should be noted that by connecting the thin film transistor 250 and the gasket 210 to the electrostatic protection device 240 respectively, while effectively eliminating the charges accumulated in the thin film transistor 250 and the gasket 210, the probability that the charges accumulated in the test area 211 caused by the connection of the first interconnecting line 241 and the second interconnecting line 251 is transferred to the thin film transistor 250 is avoided, thereby reducing the risk of the thin film transistor 250 being damaged by static electricity, and further contributing to improving the yield and stability of the display panel.

[0064] Furthermore, it should be noted that the specific components of the substrate, the thin film transistor and the electrostatic protection device located in the substrate, and the light-emitting chip structure located on the first surface of the substrate as described above are well-known common knowledge to those skilled in the art, and the present application will not expand on this again. At the same time, Figure 4 and Figure 6 the positional relationship between the various devices and structures in is only an example, and those skilled in the art can adjust it according to the actual performance requirements and process requirements of the display panel, and the present application does not limit this.

[0065] Referring to Figure 6 , in one embodiment, along the first direction (i.e., the A direction), the width a of the intermediate area 212 is respectively smaller than the width b of the test area 211 and the width c of the overlapping area 213, that is, a < b and a < c. It should be noted that by setting the width relationship between the test area 211, the overlapping area 213 and the intermediate area 212, it helps to increase the distance between the intermediate areas 212 of two adjacent gaskets 210, thereby helping to avoid short-circuit abnormalities that may be caused by too small spacing between the side-walking lines of two adjacent sides.

[0066] Continuing to refer to Figure 6 , in one embodiment, the width c of the overlapping area 213 is smaller than the width a of the test area 211, that is, a > c. It should be noted that by setting the test area 211 with a relatively large width, so that the width b of the test area 211 is greater than the width a of the intermediate area 212 and the width c of the overlapping area 213, the area ratio of the test area 211 in the gasket 210 is increased, thereby helping to improve the test accuracy of the subsequent electrical test using the test area 211, reduce the alignment difficulty of piercing the needle into the test area 211 during the electrical test process, and further effectively improve the efficiency and accuracy of the electrical test of the display panel.

[0067] Further, see Figure 3 and Figure 6 Since the side trace 230 completely covers the overlap area 213 and the protective layer 220 around the second opening 222, in one embodiment of this application, the overlap area 213 between the side trace 230 and the pad 210 is a fully enclosed design. In this case, because the width c of the overlap area 213 is smaller than the width b of the test area 211, the area ratio of the overlap area 213 in the pad 210 is reduced, thus correspondingly reducing the area of ​​the side trace 230. This helps to reduce the probability of peeling between the overlap area 213 and the side trace 230, effectively improving the yield and stability of the display panel.

[0068] contrast Figure 1 and Figure 4 , Figure 2 and Figure 5 As can be seen, in a typical display substrate, the insulating layer 120 does not cover the pad 110, and the side trace 130 covers part of the surface of the pad 110 through the opening 121 in the insulating layer 120, thus achieving a non-full-coverage connection between the side trace 130 and the pad 110. However, in the display panel described in this application, the protective layer 220 covers part of the surface of the pad 210 and provides a second opening 222 that exposes the overlap area 213, so that the side trace 230 can be connected to the overlap area 213 of the pad 210 through the second opening 222. At the same time, the side trace 230 covers the overlap area 213 and the protective layer 220 around the second opening 222, thus achieving a full-coverage design between the side trace 230 and the overlap area 213 of the pad 210.

[0069] It should be noted that, since the adhesion between the side trace 230 and the pad 210 is less than the adhesion between the side trace 230 and the protective layer 220 (correspondingly, the adhesion between the side trace 130 and the pad 110 is less than the adhesion between the side trace 130 and the insulating layer 120), this application enhances the adhesion of the side trace 230 to the overlap area 213 and the protective layer 220 around it by providing a protective layer 220 covering part of the surface of the pad 210, thereby reducing the probability of the side trace 230 peeling off.

[0070] Furthermore, in one embodiment, during the manufacturing process of the side trace 230, a temporary protective film (not shown in the figure) needs to be applied to both the first surface 201 and the second surface 202 of the substrate 200. At this time, the area where the side trace 230 will be formed is predetermined in the first surface 201 and the second surface 202 of the temporary protective film (the predetermined area includes at least the overlapping area 213 and part of the protective layer 220 around the second opening 222). Subsequently, the side trace 230 as described above is formed on the exposed surfaces of the first surface 201 and the second surface 202. After the side trace 230 is formed, the temporary protective film is removed.

[0071] In the manufacturing process of the side trace 230 as described above, the protective layer 220 can enhance the adhesion between the temporary protective film and the substrate 200, reducing or avoiding blistering due to insufficient adhesion between the temporary protective film and the substrate 200. This reduces or avoids the possibility of internal plating abnormalities caused by blistering of the temporary protective film during the coating process of the side trace 230. Simultaneously, the temporary protective film and the protective layer 220 can form a double-layer protective structure, protecting the structure in the pad 210 and the substrate 200 from damage during the preparation of the side trace 230. Furthermore, after the side trace 230 is formed and during the removal of the temporary protective film, because the adhesion between the side trace 230 and the protective layer 220 is relatively strong, the portion of the side trace 230 near the temporary protective film (i.e., the portion of the side trace 230 overlapping the pad 210 and covering part of the protective layer 220) is not easily peeled off during the removal of the temporary protective film, thereby reducing or avoiding the probability of the side trace 230's edges lifting, curling, or peeling.

[0072] Continue reading Figure 6 In one embodiment, the width 'a' of the intermediate region 212 is greater than the minimum design width of the conductive lines in the display panel to ensure the reliability and stability of the display panel, and the width of the intermediate region 212 is less than or equal to 80% of the width of the overlap region 213, i.e. .

[0073] It should be noted that by controlling the width 'a' of the middle area 212 to be between the minimum design width of the display panel and 80% of the overlap area width, the distance between the middle areas 212 of two adjacent pads 210 is increased while ensuring the process quality of the pads 210, thereby helping to further reduce the risk of short circuits between adjacent pads 210.

[0074] It should be noted that the "minimum design width" mentioned above refers to the minimum width that satisfies both the conditions of "allowing the middle area to achieve electrical connection between the test area and the overlap area" and "being manufacturable in actual manufacturing processes." If the actual width of the middle area is less than the minimum design width, it may lead to problems such as the middle area being too small to manufacture, or the resistance increasing due to the middle area being too small, thereby affecting the electrical connection between the test area and the overlap area. In addition, the actual value of the minimum design width is related to factors such as the size of the display panel, the parameters of each component in the display panel, and the process requirements in the manufacturing process of the display panel. Those skilled in the art can determine the actual value of the minimum design width of the display panel by combining the above factors and actual conditions, and this application does not impose any restrictions on this.

[0075] See Figure 6 In one embodiment, the width 'a' of the intermediate region 212 is in the range of 50 μm to 120 μm, i.e. This increases the distance between the intermediate zone 212 of two adjacent pads 210, thereby helping to further reduce the risk of short circuits between adjacent pads 210.

[0076] It should be noted that since the resistance in the conductive structure is inversely related to the cross-sectional area of ​​the conductive structure, the width 'a' of the intermediate region 212 can be taken to the maximum value within the width range described above, so as to increase the cross-sectional area of ​​the intermediate region 212 along the direction perpendicular to the first direction, thereby helping to reduce the resistance of the intermediate region 212.

[0077] In other embodiments of this application, the width relationship between the test area, the middle area and the overlap area in the pad can be adjusted according to actual needs. For example, the specific width of different areas in the pad can be reasonably adjusted in combination with relevant parameters such as the alignment deviation value and the number of side wirings to meet the different needs of the display panel. This application does not impose any restrictions on this.

[0078] See Figure 4 and Figure 5 In one embodiment, both the pad 210 and the side trace 230 are made of conductive materials, including at least one of copper and aluminum, to ensure the conductivity of the pad 210 and the side trace 230, thereby helping to ensure the normal functioning of the display panel.

[0079] It should be noted that, in one embodiment, the material of the pad 210 and the material of the side trace 230 may be the same or different. In other embodiments of this application, the conductive material may also be replaced with other commonly used metal conductive materials or alloy conductive materials. Those skilled in the art can select appropriate conductive materials according to actual needs, and this application does not impose any restrictions on this.

[0080] Continue reading Figure 4 and Figure 5 In one embodiment, the protective layer 220 is made of an inorganic insulating material, including at least one of ceramic, mica, and glass. This protective layer 220 provides electrical isolation between different conductive structures in the display panel (e.g., pads 210, side traces 230, connection terminals of the light-emitting chip structure 260, etc.), reducing or avoiding the risk of short circuits between these structures. Furthermore, the protective layer 220 can also protect other structures in the display panel from damage. In other embodiments of this application, those skilled in the art can select suitable inorganic insulating materials as the material for the protective layer according to actual needs; this application does not impose any limitations on this.

[0081] Figure 7 This is a schematic diagram of the structure of a display device provided in one embodiment of this application. (See attached diagram.) Figure 7 One embodiment of this application also provides a display device 300, which includes a display panel 310 as described above, and the specific structure of the display panel 310 can be found in [reference needed]. Figures 4 to 6 This application reduces the probability of stripping due to side traces of the display panel in the display device by providing a display device including the display panel as described above, thereby helping to improve the yield and stability of the display device.

[0082] In summary, this application provides a display panel and a display device. The display panel includes a substrate, a pad, a protective layer, and side traces. The substrate includes a first surface and a second surface disposed opposite to each other. The pad is located on the first surface and includes a test area, a middle area, and an overlap area connected sequentially along a first direction, the first direction being parallel to the first surface. The protective layer is located on the side of the pad away from the substrate and covers a portion of the pad. The protective layer has a first opening and a second opening. The first opening exposes at least a portion of the surface of the test area, and the second opening exposes at least a portion of the surface of the overlap area. The side traces are located on the side of the pad and the protective layer away from the substrate and extend to cover the side of the substrate and the second surface. The side traces expose the first opening and at least cover the overlap area exposed by the second opening and the protective layer around the second opening. This application reduces the probability of side trace peeling, which helps to improve the yield and stability of the display panel.

[0083] In the description of this specification, the references to terms such as "some embodiments," "other embodiments," "ideal embodiments," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example that are included in at least one embodiment or example of this application. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0084] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0085] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A display panel, characterized in that, include: The substrate includes a first surface and a second surface disposed opposite to each other; A pad, located on the first surface, includes a test area, an intermediate area, and an overlap area connected sequentially along a first direction, the first direction being parallel to the first surface; A protective layer is located on the side of the pad away from the substrate and covers a portion of the pad. The protective layer is provided with a first opening and a second opening, the first opening exposing at least a portion of the surface of the test area and the second opening exposing at least a portion of the surface of the overlap area. Side routing is located on the side of the padding and the protective layer away from the substrate, and extends to cover the side of the substrate and the second surface. The side routing exposes the first opening and at least covers the overlap area exposed by the second opening and the protective layer around the second opening.

2. The display panel according to claim 1, characterized in that, An electrostatic discharge (ESD) protection device is disposed within the substrate, and the ESD protection device is connected to the test area of ​​the pad via a first interconnection line.

3. The display panel according to claim 2, characterized in that, The substrate also contains a plurality of thin-film transistors, which are spaced apart on the side of the electrostatic discharge protection device away from the pad. The thin-film transistors are connected to the electrostatic discharge protection device through a second interconnect line, and the first interconnect line and the second interconnect line are separate from each other.

4. The display panel according to claim 1, characterized in that, Along the first direction, the width of the middle area is smaller than the width of the test area and the width of the overlap area, respectively.

5. The display panel according to claim 4, characterized in that, The width of the middle area is greater than the minimum design width, and the width of the middle area is less than or equal to 80% of the width of the overlap area.

6. The display panel according to claim 4, characterized in that, The width of the overlap area is smaller than the width of the test area.

7. The display panel according to claim 4, characterized in that, The width of the intermediate region is in the range of 50μm to 120μm.

8. The display panel according to claim 1, characterized in that, The material of the pad and the side wiring includes a conductive material, which includes at least one of metallic copper and metallic aluminum.

9. The display panel according to claim 1, characterized in that, The protective layer is made of inorganic insulating material, which includes at least one of ceramics, mica, and glass.

10. A display device, characterized in that, The display panel includes any one of claims 1 to 9.

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