Ddr buffer device equalization for self-training mode

Abstract

This document describes a method and system for performing the following operations: configuring Device Equalization Self-Training Mode (DESTM) control using in-band signaling, the DESTM control including at least setting a minimum duration; enabling DESTM control using a host; triggering a buffer to execute the self-training mode; transmitting a Linear Feedback Shift Register (LFSR) code pattern to the buffer within the minimum duration; and waiting for the minimum completion time to end before disabling DESTM. The minimum duration indicates the time during which the self-training mode is active and is predefined. The buffer executes the self-training mode within the predefined minimum duration.

Description

Technical Field

[0001] The examples in this disclosure generally relate to using buffer-balanced self-training during task modes when accessing sideband signals is infeasible or undesirable. Background Technology

[0002] As the number of cores in modern processors increases, higher memory bandwidth is needed to unleash the computing power of the central processing unit (CPU). Increasing memory bandwidth is a major driving force behind the development of DDR5 (fifth generation Double Data Rate (DDR) technology). Compared to DDR4, DDR5 doubles the data transfer rate while supporting greater memory density. Several different techniques are used to achieve these higher transfer rates. One of these techniques is a equalization technique called Decision Feedback Equalization (DFE). DFE is an equalization technique that enables DDR5 to support higher input / output (I / O) speeds. While DFE is a reliable solution for achieving higher data rates, its coefficients can be recalibrated over time. Furthermore, buffer device equalization, such as DFE, has been proposed for buffer self-training modes. However, such buffer self-training modes are implemented using only sideband signals, thus limiting the capabilities of the host system or system-on-a-chip (SoC). Summary of the Invention

[0003] One embodiment described herein is an apparatus including a host processor that: configures Device Equalization Self-Training Mode (DESTM) control using in-band signaling, the DESTM control including at least setting a minimum duration; enabling the DESTM control; triggering a data buffer to execute a self-training mode; transmitting a linear feedback shift register (LFSR) pattern to the data buffer during the minimum duration; and waiting for the minimum completion time to end before disabling the DESTM.

[0004] One embodiment described herein is a memory including a data buffer having interface logic and data path logic. The data buffer: uses in-band signaling to configure Device Equalization Self-Training Mode (DESTM) control, which includes at least setting a minimum duration; enabling the DESTM control; triggering the data buffer to execute the self-training mode; transmitting a Linear Feedback Shift Register (LFSR) code pattern to the data buffer within the minimum duration; and waiting for the minimum completion time to end before disabling the DESTM.

[0005] One embodiment described herein is a system comprising: a memory; and a host processor communicating with the memory, the host processor: configuring Device Equalization Self-Training Mode (DESTM) control using in-band signaling, the DESTM control including at least setting a minimum duration; enabling the DESTM control; triggering a data buffer in the memory to execute a self-training mode; transmitting a Linear Feedback Shift Register (LFSR) code pattern to the data buffer during the minimum duration; and waiting for the minimum completion time to end before disabling the DESTM. Attached Figure Description

[0006] To gain a more detailed understanding of the features described above, a more specific description of the brief summary can be obtained by referring to the exemplary embodiments, some of which are illustrated in the accompanying drawings. However, it should be noted that the drawings illustrate only typical exemplary embodiments and should not be considered as limiting their scope.

[0007] Figure 1 A flowchart illustrating a process for performing equalization self-training of a double data rate (DDR) buffer device using in-band signals is provided.

[0008] Figure 2 A timing diagram of a band waveform for performing DDR buffer device equalization self-training using in-band signals, based on an example, is shown.

[0009] Figure 3 An example is provided for a method to perform DDR buffer device equalization self-training using in-band signals.

[0010] Figure 4 An example is illustrated of a method for performing buffer device equalization self-training on a buffer of a dual in-line memory module (DIMM) using in-band signals.

[0011] Figure 5 An example is illustrated of a system for performing buffer device equalization self-training on a buffer of a dual in-line memory module (DIMM) using in-band signals.

[0012] For ease of understanding, the same reference numerals are used where possible to denote common elements in the figures. It is conceivable that elements of one example can be advantageously incorporated into other examples. Detailed Implementation

[0013] Various features are described below with reference to the accompanying drawings. It should be noted that the drawings may be drawn to scale or not, and elements with similar structures or functions are indicated by the same reference numerals in all drawings. It should be noted that the drawings are intended only to facilitate the description of features. They are not intended to provide an exhaustive description of the embodiments herein, nor are they intended to limit the scope of the claims. Furthermore, the illustrated examples do not necessarily possess all the aspects or advantages shown. Aspects or advantages described in connection with a particular example are not necessarily limited to that example and may be practiced in any other example even if not so illustrated or so explicitly described.

[0014] In-band signaling involves transmitting control information within the same frequency band or channel used for data. This contrasts with out-of-band signaling, which transmits over different channels or even separate networks. Each system transmits both data and control signals. Data signals are the fundamental reason for transmission, while control signals start, stop, and manage the session. When data and control signals are transmitted within the same channel or frequency, signaling is called "in-band" signaling. When control signals reside in a separate channel from data, they are called "out-of-band" signaling.

[0015] Sidebands typically carry information transmitted at a lower speed than in-band signals. Sidebands require other components to perform this control information transmission. Therefore, additional synchronization is needed between the components that perform sideband control information transmission and the components that perform in-band data transmission.

[0016] The Joint Electronic Device Engineering Committee (JEDEC) Solid State Technology Association is an independent semiconductor engineering trade organization and standardization body. JEDEC was established to provide recognized technical standards for a wide range of applications, from how to handle electronic packages and define package outlines to methods for characterizing performance. JEDEC's goal is to create common standards that can be used by both manufacturers and consumers. Having common technical standards reduces the chances of consumers being misled and confused when choosing products and promotes product interchangeability.

[0017] Semiconductor memory plays a vital role in the development of countless electronic devices, ranging from computers and game consoles to televisions and telecommunications products. JEDEC standards practically cover every key standard for semiconductor memory in today's market.

[0018] Regarding DDR5, JEDEC released the JESD79-5 DDR5 SDRAM standard in July 2020, and a second update, JESD79-5B, in August 2022. This standard meets the demands driven by dense cloud and enterprise data center applications, providing developers with twice the performance and significantly improved power efficiency.

[0019] Regarding DDR4, JEDEC released the standard in September 2012 and recently updated it in January 2020. The JEDEC DDR4 standard has been defined as providing higher performance, improved reliability, and reduced power consumption, thus representing a significant achievement compared to previous dynamic random access memory (DRAM) technologies.

[0020] High-speed serial links, such as those used in DDR4 and DDR5, are susceptible to various signal degradation challenges. Insertion loss, frequency-dependent attenuation, and inter-symbol interference (ISI) are among the most common sources of signal degradation. When a rectangular pulse is transmitted, it suffers distortion, which becomes noticeable when it reaches the receiver. This rectangular pulse may widen due to group delay dispersion, as different frequency components of the signal propagate at different speeds along the signal path. Furthermore, impedance mismatch can cause reflections that propagate back and forth in the channel.

[0021] Typically, these signal losses can be compensated for using any of several equalization techniques. Commonly used equalization techniques are feedforward equalization (FFE), continuous-time linear equalization (CTLE), and decision feedback equalization (DFE).

[0022] A Discrete Equalizer (DFE) is a nonlinear equalizer that quantizes a signal and feeds back discrete symbols. DDR5 specifies the use of a DFE. A DFE is used instead of an FFE or a Crosstalk Equalizer (CTLE) because a DFE provides equalization without increasing the signal noise level. FFE and CTLE boost the high-frequency response of the channel to compensate for the channel's frequency-dependent attenuation. This boost is a result of an analog filtering process. This leads to an increase in noise-like effects such as noise and crosstalk. The limiter stage in a DFE quantizes the signal while ignoring noise voltage and does not propagate noise to the equalizer's output. Therefore, a DFE provides a high-frequency boost without noise.

[0023] In DDR5 and buffers, multi-tap decision feedback equalization (DFE) is specified to mitigate loss and reflection without amplifying noise. Equalization aims to manipulate the signal to compensate for channel loss and dispersion. DFE helps mitigate the effects of ISI. ISI is the effect of a given symbol's response to subsequent symbols observed at the receiver. ISI can be caused by incorrect termination, large capacitive loads in the channel, or dispersion effects where different frequencies attenuate by varying amounts (typically, higher frequencies attenuate more than lower frequencies, causing the channel to behave like a low-pass filter) and reflected signals.

[0024] It has been suggested to add a buffer device equalization self-training mode to DDR technology, where such a mode can only be started using sideband signals, which would be useful during startup. However, such a self-training mode cannot be implemented during task mode because sideband signals are slow, and the self-training process requires additional interaction between higher-level firmware and the memory subsystem. Furthermore, sideband signals may not be accessible during task mode.

[0025] Accordingly, the example implementation proposes a system and method that does not limit buffer-based equalization in self-training mode to sideband signals. Instead, buffer-based equalization in self-training mode can be extended to in-band signals. Using in-band signals allows buffer-based equalization to be implemented during task mode (i.e., during runtime). Using in-band signals further allows the elimination of unnecessary interactions between the memory subsystem and higher-level firmware. This extension to in-band signaling for buffer-based equalization in self-training mode is not limited to register clock drivers (RCDs) but can also be scaled to DDR data buffers (DBs). Therefore, the exemplary implementation can be applied to both the buffer components RCD and DB.

[0026] RCD is a component of a Dual In-line Memory Module (DIMM). A DIMM consists of a series of dynamic random access memory (RAM) components on a small circuit board with pins for connecting it to the computer motherboard. A DIMM stores each bit of data in a separate memory cell. One type of DIMM is the register-type DIMM (RDIMM), which is configured to meet the stringent requirements of compute-intensive operations, such as those used in continuously running server systems. RCD is also a component of an RDIMM, and LRDIM / MRDIMM includes both RCD and DB components.

[0027] In operation, the RCD first receives instructions or commands from the CPU and then transmits them to the memory module. The RCD acts as an "intermediary" between the CPU and DRAM; that is, the CA and CS signals are buffered by the RCD and then passed from the RCD to the DRAM on the rising edge of the next clock signal. This results in an increase in instruction execution time, but buffering reduces the pressure on the CPU's memory controller and helps minimize the impact on signal integrity. The primary purpose of the RCD and DB is to maintain the same memory speed even during heavy workloads. The DB, or DDR DB, transfers n bits of data per clock cycle between the SoC and DRAM. The DB is a memory storage element used to temporarily store data as it moves between the SoC and DRAM.

[0028] Therefore, a DIMM or LRDIMM / MRDIMM has two buffer components, namely RCD and DB. The DIMM is inserted into the motherboard to communicate with, for example, a System-on-a-Chip (SoC). The SoC can also be referred to as the host. The SoC can put the RCD or buffer component into a self-training mode. This self-training mode focuses on equalization, such as the DFE used for DDR5 technology. After self-training is completed, a more accurate equalization value is obtained because the equalization value can change over time when operating, for example, at high frequencies.

[0029] Based on the recommendation to add a buffer device equalization self-training mode that can be initiated using sideband signals, the host or SoC will program settings such as those related to various configurations. The SoC will drive, for example, a linear feedback shift register (LFSR) pattern. The SoC will then program such bits using only sideband signals. However, communication devices use more than just sideband signals. Communication devices also use in-band signals. For example, the sideband bus may not communicate with SoC pins. The proposed method instructs registers within the buffer component to be programmed via the sideband bus rather than via the DDR interface. Therefore, in-band signaling is incompatible with the currently proposed method for adding a buffer device equalization self-training mode.

[0030] The example implementation extends the capabilities of the equalization self-training mode to in-band signaling. In other words, the initialization of the equalization self-training mode can also be performed via in-band signaling, not just via the sideband bus. Therefore, the equalization self-training mode is not limited to startup time but can be extended to be applied during task mode (i.e., when the system or SoC boots up and is running (during runtime)). The equalization self-training mode is implemented using in-band signals by changing the equalization value in the register when the buffer has fully completed the self-training mode within a predefined minimum duration, which indicates the duration for which the self-training mode is active. This minimum duration is a new feature added to the registers of the DIMM, enabling operation using in-band signaling.

[0031] Figure 1 A flowchart 100 is illustrated, based on an example, for performing equalization self-training of a double data rate (DDR) buffer device using in-band signals.

[0032] Flowchart 100 enables all configurations to be executed using in-band signaling and to be executed during task mode (i.e., during runtime).

[0033] Buffer device equalization in self-training mode is a process in memory systems used to automatically adjust and optimize signal integrity between the memory controller and memory modules. This process is beneficial for ensuring reliable and high-performance data transmission, especially in high-speed memory systems such as DDR4 and DDR5. Buffer devices (such as data buffers or register buffers) are used in memory modules (e.g., register-type DIMMs or load-reducing DIMMs) to buffer data signals and improve signal integrity. Buffer devices help reduce the electrical load on the memory controller and ensure stable communication over the high-speed memory bus. Equalization refers to the process of adjusting the electrical characteristics of a signal (such as amplitude, timing, and impedance) to compensate for signal degradation caused by factors such as long transmit lines, noise, and interference. The goal is to achieve a clean, stable signal that can be reliably interpreted by the receiving device. In self-training mode, the buffer device performs adjustments autonomously without manual intervention or extensive control from the memory controller. Self-training mode involves the buffer device measuring signal quality and making real-time adjustments to optimize performance.

[0034] At box 102, in task mode, the buffer is idle. It has the ability to communicate directly with the DIMM. Therefore, features can be added to the DIMM's registers (RCD and DB) to enable in-band signaling capabilities. Configuring device equalization in self-training mode using in-band signaling involves setting up a system where the memory controller and memory devices communicate and adjust signal parameters via the data path itself, rather than using out-of-band signals or a separate control path.

[0035] At box 104, the host or SoC configures peripherals using in-band signaling. DFE equalization technology is employed, and DFE taps are handled. A tap is a point on a delay line corresponding to a certain delay. Additionally, a minimum duration (tck) feature is provided. The minimum duration (tck) is set by the user based on the desired application or is predefined or predetermined. For example, a buffer vendor or manufacturer may determine or set this variable. Once the buffer vendor or manufacturer has determined the appropriate value for such a variable, it can be programmed in the DIMM's RCD and / or DB.

[0036] At box 106, the host or SoC programs the register (RW). The SoC can provide enable, for example, using a control register. In another example, enable can be provided via a new command. In practice, as long as a trigger mechanism exists, the buffer (e.g., RCD or DB) understands this as the start of the shortest DESTM start time.

[0037] At box 108, the host or SoC waits for the start of the shortest DESTM start time. Simultaneously, at box 120, the buffer (e.g., RCD or DB) enters self-training mode. The SoC's wait time can also be set, predefined, or predetermined. The SoC's wait time can be synchronized with the start of the current shortest DESTM start time.

[0038] At box 120, the buffer is ready to enter self-training mode. In other words, the buffer begins self-training.

[0039] At box 122, the buffer receives the LFSR pattern and performs self-training using an LFSR checker. Using the first rising edge as an alignment or indication, the buffer completes self-training within a programmed preset minimum duration (minimum DESTM duration). DESTM stands for Device Equalization Self-Training Mode.

[0040] At box 110, once the tDESTM_START wait time has ended, the host or SoC drives the LFSR pattern for at least the programmed minimum duration (minimum DESTM duration). During this time, the buffer uses the agreed-upon first rising edge to detect the first rising edge and uses this first rising edge as the first alignment or first indication. Therefore, no bits are needed to notify the buffer to restart the self-training mode. The buffer can detect when to start the self-training mode by using the first rising edge of the agreed-upon time (i.e., the wait time and the minimum duration, both of which are preset). Furthermore, subsequent patterns can be easily computed based on shift registers. Therefore, alignment can be achieved by using the detection of the first rising edge from the buffer itself. In other words, the duration of the transmitted LFSR pattern depends on the minimum duration, and box 110 represents the length of the time frame from when the LFSR pattern is transmitted until the buffer completes the self-training mode (by using those LFSR patterns).

[0041] At box 112, the host or SoC waits for the shortest completion time (shortest DESTM completion time) to end. Once this time limit is reached, the process can proceed to box 124.

[0042] At box 124, determine whether the self-training mode has been fully completed. If yes, proceed to box 126. If no, proceed to box 128.

[0043] At box 126, if the self-training mode is fully completed, the buffer applies the trained result and programs that result into a register (RW). In other words, the modified, updated, or new equalizer value is moved or placed into the register. Since the self-training mode is fully completed, the equalizer value is changed.

[0044] At box 127, upon completion, the buffer programs information indicating the level of abstraction for training quality into a read-only control word register. This provides the SoC with a reference for comparing different training results.

[0045] At box 128, if the self-training mode is not yet fully complete, the buffer saves the trained results to a temporary RW or temporary register for use in the next self-training sequence. The buffer also restores the original values. In other words, the original or initial equalization values ​​are maintained in the register.

[0046] Furthermore, if the self-training mode is time-reused, then several iterations of the self-training mode can be performed.

[0047] Therefore, this method determines whether the self-training mode is fully completed, and based on this determination, changes the equalization value or maintains the original equalization value in the register.

[0048] Once the self-training mode ends, the process proceeds to box 114.

[0049] At box 114, the host or SoC programs the register (RW) to disable DESTM. The system periodically exits and enters self-training mode. When the system re-enters self-training mode, the buffer can either start the self-training mode from its interruption (if the self-training mode has not yet fully completed) or restart the self-training mode (if the self-training mode has fully completed).

[0050] This process can be described as a self-contained process within the buffer because the host or SoC does not need to manage this self-training state. Alternatively, such self-training state is managed by the buffer itself.

[0051] Therefore, in summary, an agreement was reached regarding the runtime and the alignment (using the first rising edge). Additionally, an agreement was reached regarding the characteristics of the buffer: the buffer will be self-contained and will manage its own state to push the correct equalizer value back to the register. The equalizer value can be a fully trained value or a partially trained value; the computed partially trained value is stored (and not used), so that the initial or original value is maintained in the register. Therefore, it is possible to put the buffer into self-training mode using in-band signals, thereby enabling self-training in task mode. It is envisioned that the buffer receiving the updated or new equalizer value is either an RCD buffer or a DB buffer.

[0052] Configuring device equalization in self-training mode using in-band signaling involves setting up a system in which the memory controller and memory devices communicate and adjust signal parameters via the data path itself, rather than using out-of-band signals or a separate control path.

[0053] From the host's perspective, the host or host processor initiates self-training mode by transmitting a specific command or sequence via the data path. This specific command or sequence signals the start of the training process. If necessary, the host can use pre-encoded patterns within normal data transmissions to transmit initial training parameters, such as timing and voltage levels.

[0054] During execution, the host continuously monitors feedback from the memory device. This feedback is typically encoded within normal data responses from the memory device. Based on the received feedback, the host iteratively adjusts signal parameters. This may include voltage swings, timing adjustments, and changes to impedance settings. Upon completion, the host ensures signal integrity and timing parameters remain within acceptable limits by performing a series of read / write tests. Once the optimal settings are determined, the host can lock these settings to ensure stable operation.

[0055] From the memory's perspective, upon receiving an in-band signal to begin training, the memory device enters self-training mode. The memory device measures current signal quality parameters, such as voltage level, noise, and timing margin. During execution, the memory device uses in-band signaling to transmit feedback to the memory controller. This feedback can be encoded within the normal data response or using a reserved data pattern. Based on commands received from the host processor and internal measurements, the memory device adjusts its equalization settings. This may involve changing impedance, modifying signal timing, or adjusting voltage levels. After completion, and after finding optimal parameters, the memory device stabilizes these settings and exits self-training mode. The memory device resumes normal operation once the newly optimized settings take effect.

[0056] From a system perspective, the system firmware can initiate training sequences during system startup or specific maintenance cycles. The system ensures sufficient resources and time are allocated to the training process. This may involve temporarily reducing memory traffic from other components. Regarding monitoring and logging, the system continuously monitors the training process to ensure its successful completion. This includes monitoring the status register and error log. The system records training data, including initial and final settings, any errors encountered, and the overall success of the process. This data is useful for diagnostics and future optimization. Regarding error handling, if the training process fails or suboptimal settings are found, the system can retry the process using adjusted parameters.

[0057] according to Figure 1The benefits of using a self-training mode in the process include: automation, eliminating the need for manual tuning and intervention, saving time and reducing complexity; adaptability, continuously adapting to changing conditions to ensure optimal performance over time; reliability, enhancing signal integrity for more reliable and error-free data transfer; and performance optimization, optimizing signal parameters for higher data transfer rates and better overall memory performance. Therefore, buffer device equalization in a self-training mode is an advanced feature for enhancing the reliability and performance of data transfer in modern memory systems. By autonomously adjusting signal parameters, buffer devices ensure efficient communication between the memory controller and memory modules, even under varying conditions. This self-optimization process is beneficial for maintaining high-speed and stable operation in modern computing environments.

[0058] Figure 2 A timing diagram 200 illustrating a band waveform for performing DDR buffer device equalization self-training using in-band signals, based on an example, is shown.

[0059] Waveform 202 represents the in-band signal, waveform 204 represents the in-band chip select signal, and waveform 206 represents the command bus signal.

[0060] During interval 210, the host waits for tDESTM_START. The wait time is predefined.

[0061] During interval 212, the host drives the LFSR pattern for at least the programmed duration (minimum DESTM duration). The host is selected based on which channel or bus has been trained to drive the LFSR pattern. For example, this channel or bus could be the CS pin, the CA pin, or a data pin. The data pin is a data buffer.

[0062] During the interval 214, the host waits until the DESTM time ends. In other words, the host waits until...<tDESTM_COMPLETE> The buffer pushes the result (the new equalization value) back into the register, and the host disables DESTM. Any operations that occur between code comparisons, as well as the management of the registers being trained and applied, are handled by the buffer component itself.

[0063] DESTM enable 220 occurs before the start of the shortest duration, and DESTM disable 222 occurs after the end of the shortest duration. LFSR pattern 225 is driven by the host or SoC during the shortest duration, causing the LFSR pattern to synchronize with the first rising edge. In the top diagram, when LFSR pattern 225 is sent to the DCS_n pin, it is synchronized with the first rising edge. In the middle diagram, when LFSR pattern 225 is sent to the DCA / DPAR pin, it is synchronized with the first rising edge. In the top diagram, when LFSR pattern 225 is sent to the DQ pin, it is synchronized with the first rising edge.

[0064] The top two charts relate to RCD, while the bottom chart relates to DB 230.

[0065] Figure 3 An example is provided for a method to perform DDR buffer device equalization self-training using in-band signals.

[0066] At box 302, in-band signaling is used to configure Device Equalization Self-Training Mode (DESTM) control, which includes at least setting a minimum duration. The DESTM control may also include determining the DFE tap, performing LFSR selection, and performing channel selection. The minimum duration indicates the time the self-training mode is active. This minimum duration is, for example, predefined by the buffer vendor or manufacturer.

[0067] At box 304, a host or processor host is used to enable DESTM control. This host can be, for example, a system-on-a-chip (SoC) or other type of memory subsystem.

[0068] At box 306, a trigger buffer is used to execute a self-training mode. This buffer can be, for example, a register-type clock driver (RCD) and / or a DDR data buffer (DB). The buffer can be integrated into, for example, a dual in-line memory module (DIMM) or a register-type DIMM (RDIMM). The DIMM is connected to the computer's motherboard via double-sided pin connections, enabling native 64-bit data path throughput.

[0069] At box 308, a Linear Feedback Shift Register (LFSR) pattern is passed to the buffer during the shortest duration. An LFSR is a shift register whose input bits are a linear function of its previous state. In other words, an LFSR includes both a shift register and feedback functionality. An LFSR is used to generate randomly occurring bit sequences.

[0070] At box 310, the system waits for the shortest duration to end before disabling DESTM. When the shortest duration ends, it determines whether the buffer's self-training is complete. If the buffer's self-training is complete, the buffer applies the trained result and programs the registers using that result. In other words, a new equalization value is provided to the registers. If the buffer's self-training is not complete, the buffer stores the trained result in a temporary buffer. The original equalization value is then provided to the registers. Therefore, the registers are not updated using the trained result computed during the shortest duration. However, when the buffer re-enters self-training mode, it can resume the self-training process from where it left off at a later time.

[0071] Figure 4 An example is illustrated of a method for performing buffer device equalization self-training on a buffer of a dual in-line memory module (DIMM) using in-band signals.

[0072] At box 402, communication between the SoC and the DIMM is enabled, where the DIMM includes multiple buffers. The DIMM includes at least two types of buffer components. The buffer components of the DIMM are register-type clock drivers (RCDs) and / or DDR data buffers (DBs). The RCD communicates with the SoC via a command bus and clock. The DDR DB communicates with the SoC via data strobe signals. The DIMM is inserted into the motherboard to communicate with the SoC. This allows the SoC to communicate directly with the buffer components of the DIMM.

[0073] At box 404, DESTM is enabled for multiple buffers of the DIMM. DESTM is a feature proposed to be added to memory devices.

[0074] At box 406, a predefined minimum duration is configured for the self-training mode using in-band signaling. The buffer self-training feature is not intended to adapt to in-band signaling. Instead, the buffer self-training feature is only intended to be compatible with sideband signals of the sideband bus. Sideband signals are useful during startup mode. However, sideband signals are too slow to be used during task mode and are also inaccessible to the user during task mode. Therefore, the example implementation envisions using the proposed buffer self-training feature utilizing in-band signaling such that the buffer self-training feature is available in task mode (i.e., during runtime).

[0075] At box 408, the host is permitted to enable a predefined minimum duration. The SoC can provide enablement, for example, using a control register. In another example, enablement can be provided via a new command. In practice, as long as a trigger mechanism exists, the buffer (e.g., RCD) understands this as the start of the minimum duration.

[0076] At box 410, at least one of the multiple buffers is triggered to execute a self-training mode. In self-training mode, the buffer automatically performs adjustments without manual intervention or extensive control from the memory controller.

[0077] At box 412, the LFSR pattern is transmitted to at least one of a plurality of buffers during a predefined minimum duration. An LFSR is a shift register whose input bits are a linear function of its previous state. In other words, an LFSR includes a shift register and a feedback function. An LFSR is used to generate randomly occurring bit sequences.

[0078] At box 414, the system waits for a predefined minimum duration to end before disabling self-training mode. When the minimum duration ends, it determines whether the buffer's self-training is complete. If the buffer's self-training is complete, the buffer applies the trained result and programs the registers using that result. In other words, a new equalization value is provided to the registers. If the buffer's self-training is not complete, the buffer stores the trained result in a temporary buffer. The original equalization value is then provided to the registers. Therefore, the registers are not updated using the trained result computed during the minimum duration. However, when the buffer re-enters self-training mode, it can resume the self-training process from where it left off at a later time.

[0079] Therefore, according to Figure 1 , Figure 3 and Figure 4 Performing buffer device equalization in self-training mode can involve different perspectives, namely, from the perspective of the host or host processor, memory and overall system.

[0080] From the host's perspective, buffer device equalization in self-training mode primarily concerns initiating and managing the process to ensure optimal signal integrity and performance. From the host's perspective, the host sends commands to begin the self-training process. This may involve setting specific registers in the memory controller or issuing special instructions. The host can configure parameters that define successful training, such as training mode, voltage levels, timing parameters, and thresholds. The host typically monitors the progress of the training process via status registers or interrupts. The host ensures that the process completes within acceptable timing constraints. Based on feedback, the host can iteratively adjust settings to optimize performance. This may involve fine-tuning voltage levels, timing margins, or other relevant parameters. The host verifies the results of the training process to ensure that signal quality and timing are within acceptable limits for reliable operation.

[0081] From a memory perspective, self-training involves the memory module (DRAM) and buffer devices working together to achieve optimal signal levels and timing. From the memory's perspective, the memory module initializes its internal training routine upon receiving a command from the host. The DRAM chip and buffer devices measure various signal parameters, such as voltage levels, timing margins, and noise levels. Based on these measurements, the buffer devices adjust their equalization settings. This may involve fine-tuning impedance levels, adjusting phase relationships, or modifying signal amplitude. The DRAM and buffer devices can establish a feedback loop with the host to report their status and any adjustments made. This ensures that the host can make further adjustments if necessary. Once the optimal settings are found, the memory module stabilizes its configuration and is ready for normal operation.

[0082] From a system perspective, self-training for buffer device equalization involves coordination among all system components to ensure reliable and efficient memory operation. The system firmware can initiate the training process during a startup sequence or during specific maintenance cycles. The system monitors the overall health and performance of the memory subsystem. This includes not only individual measurements but also system-wide metrics such as temperature, power consumption, and overall system stability. During training, system resources can be allocated to ensure the process does not interfere with other operations. This may involve temporarily halting certain operations or prioritizing memory access for training purposes. The system implements robust error handling and rollback mechanisms. If training fails or produces suboptimal results, the system can retry the process, use default settings, or alert the user / administrator. The system logs the training process, including parameters, results, and any anomalies encountered. This log can be used for diagnosis, future optimization, or troubleshooting.

[0083] Figure 5 An example of a system 500 is provided for performing buffer device equalization self-training on a buffer of a dual in-line memory module (DIMM) using in-band signals.

[0084] In system 500, SoC 510 communicates with DIMM 520. DIMM 520 includes multiple buffers 530. The multiple buffers 530 may include RCD buffer component 532 and / or DB buffer component 534. In one example, SoC 510 may also be referred to as a host or processor host. SoC 510 may put RCD buffer component 532 into self-training mode 535. Self-training mode 535 focuses on equalization, such as DFE for DDR5 technology. After self-training is completed, a more accurate equalization value is obtained because the equalization value can change over time when operating, for example, at high frequencies.

[0085] In one example, multiple buffers 530 can be data buffers. Data buffers can be DDR buffers. DDR data buffers manage data transfer between the memory controller and memory modules. DDR data buffers can include various components such as data storage units, control logic, data path logic, interface logic, clock management circuitry, and register interfaces. Data path logic can include multiplexers / demultiplexers and data bus drivers / receivers. Interface logic can include command interfaces and data interfaces. The command interface handles commands from the memory controller, and the data interface manages the actual data transfer to and from DRAM (e.g., to the host processor).

[0086] In addition, refer to Figure 5 System 500 uses in-band signaling to configure Device Equalization Self-Training Mode (DESTM) control 512, wherein DESTM control 512 includes at least setting a minimum duration. DESTM control 512 may also include determining DFE taps, performing LFSR selection, and performing channel selection. The minimum duration indicates the time during which self-training mode 535 is active. This minimum duration is, for example, predefined by a buffer vendor or manufacturer.

[0087] In summary, the device equalization self-training mode can be configured using in-band signaling to handle DFE taps, LFSR selection, channel selection, and minimum DESTM duration (tck). The minimum DESTM duration is a new feature added to the register. The host then enables DESTM by programming the register (RW). The host waits...<tDESTN_START> The buffer enters self-training mode. Simultaneously, the host drives the LFSR pattern. The buffer begins self-training and uses the first rising edge to determine alignment. The host drives the LFSR for at least the minimum duration (minimum DESTM time). The host waits.<tDESTN_COMPLETE> That is, it waits for the preset minimum duration to end. The buffer completes self-training and notifies the host that the buffer has completed training. The buffer then pushes the result (i.e., the new or updated equalization value) back to the register. The host then disables DESTM by programming the register. Thus, the buffer equalization self-training mode can be used during in-band signaling, which allows for use during task mode when no access to sideband signaling is provided. This advantageously allows for faster processing and advantageously eliminates any unnecessary interaction between the memory subsystem and the highest level firmware. Furthermore, such a solution is not limited to RCD buffers but can be extended to DB buffers.

[0088] Reference has been made to the embodiments presented in this disclosure. However, the scope of this disclosure is not limited to the specifically described embodiments. Rather, any combination of the described features and elements (whether or not it relates to different embodiments) is contemplated as an implementation and practice of the contemplated embodiments. Furthermore, while the embodiments disclosed herein may achieve advantages over other possible solutions or over the prior art, whether a particular advantage is achieved through a given embodiment does not limit the scope of this disclosure. Therefore, the foregoing aspects, features, embodiments, and advantages are merely illustrative and should not be considered as elements or limitations of the appended claims unless expressly stated in the claims.

[0089] As those skilled in the art will understand, the embodiments disclosed herein may be embodied as systems, methods, or computer program products. Therefore, aspects may take the form of entirely hardware implementations, entirely software implementations (including firmware, resident software, microcode, etc.), or implementations combining software and hardware aspects, all of which may generally be referred to herein as “circuit,” “module,” or “system.” Furthermore, aspects may take the form of computer program products embodied in one or more computer-readable media having computer-readable program code embodied thereon.

[0090] Any combination of one or more computer-readable media may be used. A computer-readable medium can be a computer-readable signal medium or a computer-readable storage medium. A computer-readable storage medium can be (e.g., but not limited to) an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples (not an exhaustive list) of computer-readable storage media will include: electrical connections having one or more wires, portable computer floppy disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disc read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing. In the context of this document, a computer-readable storage medium is any tangible medium that can contain or store programs for use by or in connection with an instruction execution system, apparatus, or device.

[0091] Computer-readable signal media may include propagated data signals having computer-readable program code embodied therein (e.g., in baseband or as part of a carrier wave). Such propagated signals may take any of a variety of forms, including, but not limited to, electromagnetic, optical, or any suitable combination thereof. Computer-readable signal media may be any computer-readable medium that is not a computer-readable storage medium and can convey, propagate, or transmit a program for use by or in connection with an instruction execution system, apparatus, or device.

[0092] Program code embodied on a computer-readable medium may be transmitted using any suitable medium, including but not limited to wireless, wired, fiber optic cable, radio frequency (RF) or any suitable combination of the foregoing.

[0093] Computer program code used to perform operations relating to the aspects of this disclosure may be written in any combination of one or more programming languages, including object-oriented programming languages ​​(such as Java, Smalltalk, C++, etc.) and conventional procedural programming languages ​​(such as the "C" programming language or similar programming languages). The program code may be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter case, the remote computer may be connected to the user's computer via any type of network (including a local area network (LAN) or a wide area network (WAN)) or may be connected to an external computer (e.g., via the Internet through an Internet service provider).

[0094] Various aspects of this disclosure are described below with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments presented in this disclosure. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, executable via the processor of the computer or other programmable data processing apparatus, create components for implementing the functions / actions specified in one or more blocks of the flowchart illustrations and / or block diagrams.

[0095] These computer program instructions may also be stored in a computer-readable medium that can instruct a computer, other programmable data processing apparatus or other device to function in a particular manner, such that the instructions stored in the computer-readable medium produce an article of writing including instructions that implement the functions / actions specified in one or more boxes of a flowchart and / or block diagram.

[0096] Computer program instructions may also be loaded onto a computer, other programmable data processing apparatus or other equipment to cause a series of operational steps to be performed on the computer, other programmable apparatus or other equipment to produce a computer-implemented method, such that the instructions, which execute on the computer or other programmable apparatus, provide a process for implementing the function / action specified in one or more boxes of a flowchart and / or block diagram.

[0097] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible embodiments of systems, methods, and computer program products according to various examples of specific implementations of this disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of instructions comprising one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions indicated in the blocks may not occur in the order shown in the figures. For example, depending on the functionality involved, two blocks shown consecutively may actually be executed substantially simultaneously, or these blocks may sometimes be executed in reverse order. It will also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented by a dedicated hardware-based system that performs the specified function or action or executes a combination of dedicated hardware and computer instructions.

[0098] The techniques disclosed above may also be described in the following non-limiting embodiments.

[0099] Example 1. An apparatus comprising: a host processor configured to: In-band signaling is used to configure Device Equalization Self-Training Mode (DESTM) control, which includes at least setting a minimum duration; enabling the DESTM control; triggering a data buffer to execute self-training mode; transmitting a Linear Feedback Shift Register (LFSR) code pattern to the data buffer during the minimum duration; and waiting for the minimum completion time to end before disabling the DESTM.

[0100] Example 2. The apparatus according to Example 1, wherein the shortest duration indicates the time during which the self-training mode is active.

[0101] Example 3. The apparatus according to Example 1, wherein the minimum duration is predefined.

[0102] Example 4. The apparatus according to Example 1, wherein the host processor enables the DESTM control by programming the control register.

[0103] Example 5. The apparatus according to Example 1, wherein the DESTM control further includes determining the decision feedback equalizer (DFE) tap, performing LFSR selection, and performing channel selection.

[0104] Example 6. The apparatus according to Example 1, wherein the data buffer uses a first rising edge as a first alignment point.

[0105] Example 7. The apparatus according to Example 1, wherein the data buffer executes the self-training mode during the shortest duration.

[0106] Example 8. The apparatus according to Example 7, wherein the host processor determines whether the self-training mode has been fully completed within the shortest duration.

[0107] Example 9. The apparatus according to Example 8, wherein if the self-training mode has been fully completed within the shortest duration, a new equalization value is provided to the data buffer.

[0108] Example 10. The apparatus according to Example 8, wherein if the self-training mode has not been fully completed within the shortest duration, the data buffer restores its original equalization value.

[0109] Example 11. The apparatus according to Example 10, wherein when the data buffer re-enters the self-training mode at a subsequent time, the data buffer continues the self-training mode from its interruption point.

[0110] Example 12. The apparatus according to Example 1, wherein the data buffer performs the self-training mode during task mode without accessing sideband signals.

[0111] Example 13. The apparatus according to Example 1, wherein the data buffer is at least one of a register-type clock driver and a double data rate (DDR) data buffer.

[0112] Example 14. A memory comprising: a data buffer including interface logic and data path logic, the data buffer being configured to: configure Device Equalization Self-Training Mode (DESTM) control using in-band signaling, the DESTM control including at least setting a minimum duration; enabling the DESTM control; triggering the data buffer to execute a self-training mode; transmitting a Linear Feedback Shift Register (LFSR) code pattern to the data buffer during the minimum duration; and waiting for the minimum completion time to end before disabling the DESTM.

[0113] Example 15. The memory according to Example 14, wherein the DESTM control further includes determining the decision feedback equalization (DFE) tap, performing LFSR selection, and performing channel selection.

[0114] Example 16. The memory according to Example 14, wherein the data buffer uses a first rising edge as a first alignment point.

[0115] Example 17. The memory according to Example 14, wherein the data buffer executes the self-training mode during the shortest duration.

[0116] Example 18. The memory according to Example 17, wherein if the self-training mode has been fully completed within the shortest duration, a new equalization value is provided to the data buffer.

[0117] Example 19. The memory according to Example 17, wherein if the self-training mode has not been fully completed within the shortest duration, the data buffer restores its original equalization value.

[0118] Example 20. A system comprising: a memory; and a host processor communicating with the memory, the host processor being configured to: configure Device Equalization Self-Training Mode (DESTM) control using in-band signaling, the DESTM control including at least setting a minimum duration; enabling the DESTM control; triggering a data buffer in the memory to execute a self-training mode; transmitting a Linear Feedback Shift Register (LFSR) code pattern to the data buffer during the minimum duration; and waiting for the minimum completion time to end before disabling the DESTM.

[0119] While the foregoing is directed to specific examples, other and additional examples may be devised without departing from the basic scope of the invention, the scope of which is defined by the appended claims.

Claims

1. An apparatus, the apparatus comprising: The host processor is configured to: In-band signaling is used to configure Device Equalization Self-Training Mode (DESTM) control, which includes at least setting a minimum duration. Enable the DESTM control; Trigger the data buffer to execute self-training mode; During the shortest possible duration, transmit the linear feedback shift register (LFSR) code pattern to the data buffer; and Before disabling the DESTM, wait for the shortest completion time to end.

2. The apparatus of claim 1, wherein the shortest duration indicates the time during which the self-training mode is active.

3. The apparatus of claim 1, wherein the minimum duration is predefined.

4. The apparatus of claim 1, wherein the host processor enables the DESTM control by programming the control register.

5. The apparatus of claim 1, wherein the DESTM control further includes determining the decision feedback equalizer (DFE) tap, performing LFSR selection, and performing channel selection.

6. The apparatus of claim 1, wherein the data buffer uses a first rising edge as a first alignment point.

7. The apparatus of claim 1, wherein the data buffer executes the self-training mode during the shortest possible duration.

8. The apparatus of claim 7, wherein the host processor determines whether the self-training mode has been fully completed within the shortest duration.

9. The apparatus of claim 1, wherein the data buffer performs the self-training mode during task mode without accessing sideband signals.

10. The apparatus of claim 1, wherein the data buffer is at least one of a register-type clock driver and a double data rate (DDR) data buffer.

11. A memory, the memory comprising: A data buffer, comprising interface logic and data path logic, is configured as follows: In-band signaling is used to configure Device Equalization Self-Training Mode (DESTM) control, which includes at least setting a minimum duration. Enable the DESTM control; The data buffer is triggered to execute the self-training mode; During the shortest possible duration, transmit the linear feedback shift register (LFSR) code pattern to the data buffer; and Before disabling the DESTM, wait for the shortest completion time to end.

12. The memory of claim 11, wherein the DESTM control further includes determining a decision feedback equalization (DFE) tap, performing LFSR selection, and performing channel selection.

13. The memory of claim 11, wherein the data buffer: Use the first rising edge as the first alignment point; and / or The self-training mode is executed within the shortest possible duration.

14. The apparatus of claim 8 or the memory of claim 13, wherein, If the self-training mode has been fully completed within the shortest duration, a new equalization value is provided to the data buffer.

15. The apparatus of claim 8 or the memory of claim 13, wherein, If the self-training mode has not been fully completed within the shortest duration, the data buffer restores its original equalization value.

16. A system comprising: Memory; and A host processor, which communicates with the memory, is configured to: In-band signaling is used to configure Device Equalization Self-Training Mode (DESTM) control, which includes at least setting a minimum duration. Enable the DESTM control; Trigger the data buffer in the memory to execute the self-training mode; During the shortest possible duration, transmit the linear feedback shift register (LFSR) code pattern to the data buffer; and Before disabling the DESTM, wait for the shortest completion time to end.

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