Method for providing supplemental dielectric material and related circuitry

Abstract

This document provides integrated circuits and related methods. An integrated circuit can be formed on a die and includes several components. These components include a first electrode, a dielectric layer disposed on the first electrode, an active layer positioned on top of the dielectric layer, and a supplementary layer located near the active layer. Methods may include forming the dielectric layer, forming the active layer on the dielectric layer, and / or forming a supplementary dielectric layer on the dielectric layer.

Description

Technical Field

[0001] This disclosure relates to transistors. Specifically, this disclosure relates to transistor devices and manufacturing methods using a supplementary dielectric layer. Background Technology

[0002] A field-effect transistor (“FET”) is a transistor that uses an electric field to control or modify the current flowing between the source and drain terminals. The electric field is generated by a voltage applied to the gate terminal of the FET. The FET uses electrons and / or holes as charge carriers to achieve this effect. FETs can be primarily majority-carrier devices or minority-carrier devices. The voltage applied to the gate of the FET creates an active channel through which charge carriers flow from the source terminal to the drain terminal. The nonlinear impedance through this channel can be changed by applying different voltages relative to the source and / or drain terminals to the gate terminal. However, these characteristics are transient, as the FET quickly returns to its original resting state once the voltage is no longer applied.

[0003] A ferroelectric field-effect transistor (“FeFET”) is a FET that incorporates ferroelectric materials. Ferroelectric materials are materials with electric polarization (or polarization density). The electric field polarization of ferroelectric materials can be used to create active channels within the FeFET. By utilizing this property of ferroelectric materials, the electric field polarization in the ferroelectric material can be used to maintain the state of the FeFET without any electrical bias. In other words, the FeFET can retain information within the ferroelectric material without any external power being applied to it. This feature makes FeFETs suitable for non-volatile memory applications involving discrete or continuous values. Summary of the Invention

[0004] A method for manufacturing an integrated circuit device involves forming a dielectric layer, creating an active layer on top of the dielectric layer, and then forming a supplementary dielectric layer on the dielectric layer. In one embodiment of the method, the supplementary dielectric layer may deposit a dielectric material without substantially depositing an active layer. In another embodiment of the method, electrodes are formed prior to forming the dielectric layer. In one embodiment of the method, the electrodes used may be gate electrodes. Furthermore, the method may also involve forming a proximity dielectric material adjacent to the electrodes. In one embodiment of the method, forming the active layer involves etching away portions of the active layer.

[0005] In another embodiment, the method further involves applying an active mask to etch away non-active layer portions, thereby forming an active layer, and using the active mask to deposit a supplementary dielectric layer on the dielectric layer. In one embodiment of the method, an active mask is applied to deposit the active layer, followed by applying a supplementary dielectric mask to deposit a supplementary dielectric layer on the dielectric layer. In another embodiment of the method, an opposite-active mask is used to deposit a supplementary dielectric layer on the dielectric layer. In one embodiment, the method involves forming an integrated circuit on a back-end process. Furthermore, in another embodiment, the active layer of the method may be made of a ferroelectric material.

[0006] On the other hand, an integrated circuit comprising several layers is disclosed. The integrated circuit includes a first electrode, a dielectric layer disposed on top of the first electrode, an active layer on the dielectric layer, and a supplementary layer adjacent to the active layer. Optionally, the integrated circuit may also have a metal connector, wherein the first electrode is located on the metal connector. In one embodiment of the integrated circuit, there is an adjacent dielectric material disposed near the metal connector, and another supplementary layer disposed on top of the adjacent dielectric material. Furthermore, the integrated circuit may have a second electrode disposed on a first portion of the active layer and a third electrode disposed on a second portion of the active layer. In one embodiment, the integrated circuit has a first electrode as a gate electrode and a second electrode as a drain electrode. Furthermore, as an optional feature, the integrated circuit may also include a first metal connector coupled to the first electrode, a second metal connector coupled to the second electrode, and a third metal connector coupled to the third electrode. As described in one embodiment, the integrated circuit also includes an adjacent dielectric disposed near the first electrode. The integrated circuit includes a first electrode for providing a gate, a dielectric layer disposed on the first electrode for insulation, an active layer disposed on the dielectric layer for ferroelectric effect, and a supplementary layer for additional insulation. In addition, the integrated circuit may optionally include: a second electrode for providing a drain, the second electrode being disposed on a first portion of the active layer; and a third electrode for providing a source, the third electrode being disposed on a second portion of the active layer. Attached Figure Description

[0007] These and other aspects will become more apparent from the following detailed description of various embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0008] Figure 1 A block diagram of an artificial intelligence accelerator utilizing FeFET memory according to an embodiment of the present disclosure is shown;

[0009] Figure 2 A diagram of a memory cell utilizing a FeFET transistor according to an embodiment of the present disclosure is shown;

[0010] Figure 3 The illustration shows an embodiment of the present disclosure. Figure 2 When FeFET is used to store binary state, Figure 2 The operating characteristics of FeFET;

[0011] Figure 4 The illustration shows an embodiment of the present disclosure. Figure 2 When FeFETs are used to store continuous values ​​(such as the weights of neuromorphic units), Figure 2 The operating characteristics of FeFET;

[0012] Figure 5 A memory array utilizing FeFET transistors according to an embodiment of the present disclosure is shown; and

[0013] Figures 6A to 6D Several diagrams of transistors (such as FeFETs) are shown to illustrate a fabrication method utilizing a supplementary dielectric layer according to an embodiment of the present disclosure. Detailed Implementation

[0014] Figure 1 A block diagram of an artificial intelligence (“AI”) accelerator 100 utilizing FeFET memory 112 according to one embodiment of the present disclosure is shown. The AI ​​accelerator 100 can be implemented on a semiconductor device, a custom integrated circuit, an application-specific integrated circuit (“ASIC”), a graphics processing unit (“GPU”), a field-programmable gate array (“FPGA”), any device known to those skilled in the art, or a combination thereof. The AI ​​accelerator 100 includes an array 102 of processing elements (“PE”) that performs the majority of the AI ​​computations. The PE array 102 uses multiple processing elements 110 to perform the AI ​​computations. These processing elements 110 can form a multi-core processor, wherein each processing element 110 performs AI computations in parallel with other processing elements 110. Additionally or alternatively, the processing elements 110 may include arithmetic logic units, neuromorphic computing elements, processors, multi-core processors, many-core processors, reduced instruction set computer (“RISC”) processors, and / or other computing devices known to those skilled in the art.

[0015] Processing element 110 may each be a portion of a neuromorphic circuit; for example, in some embodiments, processing element 110 may each form a portion of an artificial neural network, wherein each accompanying memory 112 is an analog memory configured to act as parameters (e.g., weights) of an artificial neuron. In still other embodiments, each processing element 110 and its corresponding memory 112 may form an in-memory processing architecture, for example, to achieve efficient and parallel execution of multiply-accumulate operations.

[0016] The memory 112 is implemented using a FeFET, which is described in further detail below. In some embodiments, the memory 112 may store binary data and / or analog data. Additionally or alternatively, in some embodiments, the memory 112 may store a combination of binary and analog data.

[0017] AI accelerator 100 may also include shared memory 108. The computation results calculated by PE array 102 may be stored and / or indicated by information stored in shared memory 104 inside the AI ​​accelerator and / or in shared memory 108 outside the AI ​​accelerator 100. Shared memory 104 and / or shared memory 108 may utilize FeFET memory cells as described herein. AI accelerator 100 also includes an on-chip network 106 for communicating with other devices, for example, via TCP / IP, Ethernet, Wi-Fi, etc.

[0018] Figure 2 A diagram is shown of a memory cell 200 utilizing a FeFET 202 according to an embodiment of the present disclosure. The memory cell 200 also includes a program signal circuit 206 and a sensing circuit 204. The program signal circuit 206 can apply one or more positive or negative voltage pulse signals to program the FeFET 202. The FeFET 202 includes a drain 210, a source 212, and a gate 208. However, due to the symmetry of the FeFET 202, the operation of the drain 210 and the source 212 can be reversed.

[0019] FeFET 202 can be powered by a Vread voltage relative to voltage SL. The Vread voltage can be ground, a fixed voltage, a programmable voltage, a variable voltage, or can be coupled to ground or a voltage source via another transistor (not shown), etc. Similarly, the SL reference can be ground, a fixed voltage, a programmable voltage, a variable voltage, or can be coupled to ground or a voltage source via another transistor (not shown), etc. For example, voltages Vread and SL can be predetermined values ​​to achieve, for example, a fixed voltage between drain 210 and source 212 intermittently or continuously. In other embodiments, voltages Vread and SL can be set to achieve, for example, a constant current from drain 210 to source 212 intermittently or continuously.

[0020] The voltage applied to the gate 208 of the FeFET 202 by the program signal circuit 206 can cause polarization to form in the ferroelectric material of the FeFET 202. If the voltage has sufficient amplitude and duration to change the state of the ferroelectric material, the ferroelectric polarization can be maintained (or substantially maintained) for a long time after the voltage applied to the gate 208 of the FeFET 202 is removed. This is a result of stable polarization in the ferroelectric material. Ferroelectric materials are insulators, where the polarization induced by the applied electric field generated by the voltage applied to the gate 208 is maintained after the voltage is removed.

[0021] A positive voltage bias (or pulse) applied to the gate 208 of FeFET 202 from the program signal circuit 206 causes the threshold voltage of FeFET 202 to decrease, and causes the channel of FeFET 202 to enter accumulation mode. Conversely, a negative voltage bias (or pulse) applied to the gate 208 of FeFET 202 from the program signal circuit 206 causes the threshold voltage of FeFET 202 to increase, and causes the channel of FeFET 202 to enter depletion mode. The first state can correspond to a value of 0 and the second state can correspond to a value of 1, or vice versa.

[0022] refer to Figures 2 to 3 : Figure 3 Figure 300 illustrates an embodiment according to the present disclosure. Figure 2 When the FeFET202 is used to store binary state, Figure 2 The operating characteristics of the FeFET 202 are shown in Figure 300. Figure 300 illustrates axis 302, which represents the current Ids, i.e., the current from drain 210 through the FeFET 202 and through source 212 to ground. The current Ids is carried through the channel of the FeFET 202, which has polarization characteristics based on the ferroelectric material. Figure 300 also includes axis 304, which shows... Figure 2 The voltage at gate 208. The Vg value applied to gate 208 can be within the voltage range to determine the state of the FeFET without significantly interfering with the polarization of the ferroelectric material.

[0023] Figure 3The diagram illustrates the relationship between Ids and Vg for the states of a FeFET 202 according to one embodiment of the present disclosure. A first curve 306 shows the FeFET 202 in a first state, as it has a first threshold voltage 308. A second curve 308 shows the FeFET 202 in a second state, as it has a second threshold voltage 312. The states of the FeFET 202 can be programmed by a programmable signal circuit 206 to change the polarization of the ferroelectric material in the FeFET 202. These states can be detected by a sensing circuit 302. In some embodiments, it is not necessary to apply a Vg voltage to the FeFET 202 to determine the state; however, in other embodiments, a sufficient voltage needs to be applied to the gate 208 to determine the state of the FeFET, but the FeFET 202 is not programmed.

[0024] refer to Figure 2 and Figure 4 : Figure 4 Figure 400 illustrates an embodiment of the present disclosure where the FeFET 202 is used to store continuous values ​​(such as weights of neuromorphic units). Figure 2 The operating characteristics of FeFET 202.

[0025] Figure 400 illustrates axis 402 for the current Ids. Ids is the current from drain 210 through FeFET 202 and through source 212 to ground. The current Ids is carried through the channel of FeFET 202, where the channel has polarization characteristics based on the ferroelectric material. Figure 400 also includes axis 404, which shows... Figure 2 The voltage at gate 208. The Vg value applied to gate 208 can be within the voltage range to determine the state of the FeFET without significantly interfering with the polarization of the ferroelectric material.

[0026] Figure 4 The diagram illustrates the relationship between Ids and Vg for polarization based on a FeFET 202 according to an embodiment of the present disclosure. As the polarization changes, the characteristic curve shifts as shown by arrow 408. These shifted curves cause a shift in the threshold voltage 406. These values ​​can be mapped to weights in an artificial neural network. For example, an arithmetic logic unit can read these values ​​to... Figure 1In-memory computation is performed within the processing element. In some embodiments, memory is used for in-memory computation, and together with other analog circuitry, computations of the artificial neural network can be performed based on mapping values ​​corresponding to the weights of neural network units (e.g., neurons). During the neural network training phase, the AI ​​accelerator 100 can use program signal circuitry 206 to change the polarization of the ferroelectric material in the FeFET 202 to correspond to the neuron weights. These threshold voltages 406 can be detected by sensing circuitry 204. In some embodiments, a Vg voltage is not required to be applied to the FeFET 202 to determine its state; however, in other embodiments, the voltage is applied to the gate 208.

[0027] Figure 5 A memory array 500 utilizing FeFET transistors 514 according to one embodiment of the present disclosure is shown. Each FeFET transistor 514 has a polarization state. Interface circuitry (not shown) can select one of word lines 502, 504, or 506 to activate a column of FeFET transistors 514. These activated FeFETs 514, coupled to an activated word line (e.g., 504), cause each bit line of bit lines 508, 510, 512 to output a state (or value) corresponding to the ferroelectric polarization in each of the respective FeFETs 514. Those skilled in the art will understand that the array of FeFETs 514 can be increased to achieve a target memory size. Furthermore, those skilled in the art will understand that programming circuitry can be added to the memory array 500.

[0028] The FeFET transistor 512 can be powered by a voltage relative to voltage SL from bit lines 502, 504, and 506. The SL reference can be ground, a fixed voltage, a programmable voltage, a variable voltage, or can be coupled to ground or a voltage source via another transistor (not shown), etc.

[0029] Figures 6A to 6D Several diagrams of transistors such as FeFETs are shown to illustrate a fabrication method utilizing a supplementary dielectric layer according to an embodiment of the present disclosure.

[0030] Transistor 600 may be a MOSFET and / or FeFET. Transistor 600 may be formed on a back-end process (BEOL) to enhance on-chip memory footprint and enable improved data transfer and computing capabilities. Transistor 600 includes a conductive interconnect 602, which may be linked to a lower layer and connected to a gate electrode 622. Gate electrode 622 may have a gate width of less than 100 nm and may utilize a patterned back-gate and / or dual-gate BEOL FET or FeFET device architecture. Surrounding the conductive interconnect 604 is a dielectric layer 604 providing insulation. Furthermore, another dielectric layer 606 may be applied to further enhance insulation properties. Gate electrode 622 is encapsulated by another dielectric layer 608, while a dielectric layer 610 covers gate electrode 622. An active layer 612 may be disposed on dielectric layer 610. Active layer 612 may be made of a ferroelectric material.

[0031] Because there is always a short circuit risk between the source electrode 616 or drain electrode 617 and the gate electrode 622, therefore, in forming such Figure 6A Following the active layer shown, additional steps can be taken. Therefore, in order to effectively increase... Figure 6A The dielectric layer 610 has a thickness in a specific region (i.e., above the back gate and below the source / drain contacts outside the active region), and more dielectric material can be added.

[0032] The supplementary dielectric layer 614 mitigates the reduction in dielectric thickness in MOSFET and FeFET devices within the BEOL caused by any etching steps performed after the application of the active layer 612. By increasing the thickness of the dielectric layer above the back gate and below the source / drain contacts outside the active region, the proposed approach helps prevent potential short-circuit and reliability issues. Furthermore, it efficiently utilizes existing masks, reusing active masks whenever possible, and minimizes the need for additional masks unless alignment issues arise.

[0033] Once the active layer is such Figure 6A As shown, the dielectric layer 610 has been patterned, and subsequent processes (i.e., etching processes) may unintentionally reduce its thickness. Therefore, this can result in a thin dielectric layer primarily outside the active region 612. Thus, as... Figure 6B As shown, a supplementary dielectric layer 614 can be added. The same mask can be used to add the supplementary dielectric layer 614, provided that the "active mask" was initially created to define the active region and expose the remaining surface for subsequent etching steps. This allows for full coverage of the active region and provides a favorable environment for depositing the additional dielectric layer.

[0034] In other embodiments, for example, if there are concerns about peripheral misalignment, or if the primary purpose of the active mask is simply to create an open active region for channel layer deposition, two additional embodiments of the method can be employed: A first method can use “opposite active” lithography, which serves as a viable option for depositing the supplementary dielectric layer 614. This technique can facilitate alignment with the active region, effectively mitigating misalignment concerns that may arise during the process. Another embodiment involves generating a completely new mask specifically designed for this particular step. This can reduce the risk of misalignment issues and the complications related to the active region that may occur during later stages of the process. After successfully depositing the supplementary dielectric layer 614 in the designated region, the remaining steps of a standard BEOL FET process can be followed, for example.

[0035] After that, as Figure 6C As shown, the source electrode 616 and the drain electrode 617 are positioned on top of the active layer 612 and the supplementary dielectric layer 614. Figure 6D As shown, the source electrode 616 and the drain electrode 617 are then surrounded by a dielectric layer 618, which also separates the source electrode 616 from the drain electrode 617. A conductive connector 620 is linked to the source electrode 616 and a separate conductive connector 621 is coupled to the drain electrode 617, allowing additional circuitry to be placed in a layer above the transistor 600.

[0036] Various alternatives and modifications can be devised by those skilled in the art without departing from this disclosure. Therefore, this disclosure is intended to cover all such alternatives, modifications, and variations. Furthermore, while several embodiments of this disclosure have been shown in the accompanying drawings and / or discussed herein, this is not intended to limit the disclosure thereto, as the scope of this disclosure is intended to be as broad as permitted in the art, and the specification should be read in this manner. Therefore, the above description should not be construed as limiting, but merely as illustrative of particular embodiments. Moreover, those skilled in the art will anticipate other modifications within the scope and spirit of the appended claims. Other elements, steps, methods, and techniques that are substantially different from those described above and / or in the appended claims are also intended to be within the scope of this disclosure.

[0037] The embodiments shown in the accompanying drawings are presented only to illustrate certain examples of this disclosure. Furthermore, the described drawings are merely illustrative and not restrictive. In the drawings, the dimensions of some elements may be exaggerated and not drawn to scale for illustrative purposes. Additionally, depending on the context, elements shown in the drawings with the same reference numerals may be the same elements or may be similar elements.

[0038] When the term "comprising" is used in this specification and claims, it does not exclude other elements or steps. When referring to a singular noun (e.g., "a," "an," or "the"), the use of an indefinite or definite article includes the plural form of that noun unless otherwise specified. Therefore, the term "comprising" should not be construed as limited to the items listed thereafter; it does not exclude other elements or steps, and thus the expression "device comprising items A and B" should not be limited to a device that includes only components A and B. This expression means that, relative to this disclosure, the only relevant components of the device are A and B.

[0039] Furthermore, the terms “first,” “second,” “third,” etc., used in the specification or claims are provided to distinguish similar elements and are not necessarily used to describe sequences or chronological order. It should be understood that such terms may be used interchangeably where appropriate (unless expressly stated otherwise), and the embodiments of this disclosure described herein can operate with other sequences and / or arrangements than those described or shown herein.

Claims

1. A method for manufacturing an integrated circuit device, the method comprising: Forming a dielectric layer; An active layer is formed on the dielectric layer; as well as A supplementary dielectric layer is formed on the dielectric layer.

2. The method of claim 1, wherein the supplementary dielectric layer is deposited with dielectric material, while the active layer is substantially not deposited.

3. The method according to claim 1, further comprising: Electrodes are formed before the dielectric layer is formed.

4. The method of claim 3, wherein the electrode is a gate electrode.

5. The method according to claim 3, further comprising: A proximity dielectric material is formed near the electrode.

6. The method of claim 1, wherein the act of forming the active layer comprises: A portion of the active layer is etched away.

7. The method according to claim 1, further comprising: An active mask is applied to etch away the non-active layer portion, thereby forming the active layer; as well as The active mask is applied to deposit the supplementary dielectric layer on the dielectric layer.

8. The method according to claim 1, further comprising: An active mask is applied to deposit the active layer; as well as Apply a supplementary dielectric mask to deposit the supplementary dielectric layer on the dielectric layer.

9. The method according to claim 1, further comprising: An opposite active mask is applied to deposit the supplementary dielectric layer on the dielectric layer.

10. The method of claim 1, wherein the integrated circuit is formed on a back-end process.

11. The method according to claim 1, wherein the active layer is a ferroelectric material.

12. An integrated circuit, comprising: First electrode; A dielectric layer is disposed on the first electrode; An active layer is disposed on the dielectric layer; as well as A supplementary layer is configured to be adjacent to the active layer.

13. The integrated circuit of claim 12, further comprising a metal connector, wherein the first electrode is disposed on the metal connector.

14. The integrated circuit of claim 13, further comprising: Adjacent dielectric material, wherein the adjacent dielectric material is disposed adjacent to the metal connector; as well as Another supplementary layer is disposed on the adjacent dielectric material.

15. The integrated circuit of claim 12, further comprising: The second electrode is disposed on the first portion of the active layer; as well as The third electrode is disposed on the second portion of the active layer.

16. The integrated circuit of claim 15, wherein the first electrode is a gate electrode and the second electrode is a drain electrode.

17. The integrated circuit according to claim 15, further comprising: A first metal connector is coupled to the first electrode; A second metal connector is coupled to the second electrode; as well as A third metal connector is coupled to the third electrode.

18. The integrated circuit of claim 12, further comprising a proximity dielectric, the proximity dielectric being configured to be adjacent to the first electrode.

19. An integrated circuit, comprising: A first electrode device, the first electrode device being used to provide a gate; A dielectric layer device for providing insulation, the dielectric device being disposed on the first electrode device; An active layer device for providing ferroelectric effect, the active layer being disposed on the dielectric layer device; and A supplementary layer device for providing supplementary insulation.

20. The integrated circuit of claim 19, further comprising: A second electrode device is used to provide a drain electrode, and the second electrode device is disposed on a first portion of the active layer device. as well as A third electrode device is provided to provide a source electrode and is disposed on the second part of the active layer device.

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