Low-loss thin-film lithium niobate waveguide based on hybrid etching process and its fabrication method

Abstract

This application relates to the fields of photonics and optical communication technology, and particularly to a low-loss thin-film lithium niobate waveguide based on a hybrid etching process and its fabrication method, comprising: a substrate layer, a Z-cut thin-film lithium niobate functional layer, a dual waveguide structure, a sidewall grating, a thermoelectric heating layer, an isolation layer, an electrode system, and a protective layer. Amorphous Ag is used. 4‑ x TeS thermoelectric material, used as a heating layer, significantly improves device reliability while enhancing thermo-optical tuning efficiency. By integrating this heating layer into a Z-cut thin-film lithium niobate dual-waveguide reverse coupler, continuous and precise Bragg wavelength tuning is achieved using the thermo-optical effect, meeting the requirements of reconfigurable optical networks. Combined with hybrid etched ridge waveguides to reduce transmission loss, and thermally adiabatic tapered abutments and anti-reflection gratings to optimize spectral sidelobes and self-reflection, while leveraging the advantages of Z-cut wafers to improve mass production consistency, this solution addresses existing device problems such as untunable wavelength, poor consistency, high loss, high interference, and low heating module efficiency.

Description

Technical Field

[0001] This application relates to the fields of photonics and optical communication technology, and in particular to a thin-film lithium niobate low-loss waveguide based on a hybrid etching process and its fabrication method. Background Technology

[0002] With the rapid development of high-speed optical communication, optical computing, and quantum information processing technologies, the demand for high-performance, miniaturized, and reconfigurable integrated photonic devices is becoming increasingly urgent. The LNOI (Thin-Film Lithium Niobate) platform, due to its extremely high electro-optic coefficient, low acoustic loss, and wide transparency window, has become an ideal choice for realizing high-speed electro-optic modulators, tunable filters, and nonlinear optical devices. Among them, the GACDC (Grating-Assisted Contra-Directional Coupler), as an important wavelength selection and routing device, plays a crucial role in wavelength division multiplexing systems.

[0003] The wavelength tuning capability of GACDC is a key indicator for evaluating its application value. Currently, the tuning of LNOI GACDC mainly relies on electro-optic or thermo-optic effects. Although pure electro-optic tuning has a fast response speed, it is limited by the material breakdown voltage, resulting in a limited tuning range, and requires complex high-frequency electrode design. Thermo-optic tuning, on the other hand, has the advantages of simple driving and a large tuning range, and is a common method for static or quasi-static wavelength configuration.

[0004] Traditional thermo-optical tuning typically employs the integration of metal or semiconductor heaters near the waveguide. However, metal heaters generally exhibit high optical losses, require thicker insulation layers, and reduce thermal efficiency; while semiconductor heaters often have poor compatibility with LNOI processes and their temperature coefficient of resistance is unstable, resulting in poor tuning linearity. More importantly, both metal and traditional semiconductor heaters are prone to cracking or interface failure under repeated thermal cycling stress, leading to a decline in long-term device reliability.

[0005] On the other hand, the waveguide structure of GACDC itself also faces challenges. GACDC is mainly based on an X-cut thin-film lithium niobate platform. However, this technical solution has the following technical problems: First, the filtering wavelength is fixed. This device is a passive device with a fixed Bragg wavelength, which cannot adapt to the needs of dynamic network reconfiguration, limiting its application in reconfigurable optical networks. Second, poor consistency in mass production. X-cut large-size wafers (6 inches and above) have problems such as polarization defects, stress concentration, and poor refractive index uniformity, resulting in large performance fluctuations between individual devices, making it difficult to meet the needs of large-scale production; Third, waveguide transmission loss is high. Traditional fully etched waveguides have large sidewall roughness, resulting in severe scattering loss and affecting the overall performance of the device; Fourth, self-reflection interference. Bragg gratings exhibit self-reflection outside the target wavelength, limiting the operating bandwidth of the device.

[0006] Therefore, there is an urgent need in this field for a novel thermo-optical tunable structure that simultaneously possesses high thermoelectric conversion efficiency, low optical loss, excellent process compatibility, and long-term thermal cycling stability. Furthermore, this structure should be compatible with Z-cut thin-film lithium niobate platforms, leveraging the low stress and high refractive index uniformity of Z-cut materials on large-size wafers to improve device mass production consistency. Combined with hybrid etching processes to reduce waveguide transmission loss, and optimized spectral performance through a dovetail structure and anti-reflection gratings, the ultimate goal is to achieve a high-performance, highly reliable, and dynamically reconfigurable integrated photonic device, thereby advancing the practical application of tunable LNOI photonic devices. Summary of the Invention

[0007] This application provides a thin-film lithium niobate low-loss waveguide based on a hybrid etching process and its fabrication method, in order to solve the problems of non-tunable wavelength, poor mass production consistency, high transmission loss, large self-reflection interference, low efficiency, poor reliability, and poor process compatibility in the prior art.

[0008] The first aspect of this application provides a low-loss thin-film lithium niobate waveguide based on a hybrid etching process, comprising: Substrate layer; A Z-cut thin-film lithium niobate functional layer, located above the substrate layer, has a thickness of 300–600 nm. A ridge waveguide structure is formed by a hybrid etching process. The ridge waveguide includes a fully etched ridge region and a partially etched planar region. A dual-waveguide structure is formed in the Z-cut thin-film lithium niobate functional layer, including a bus waveguide and an access waveguide. The width of the bus waveguide is greater than the width of the access waveguide. The two are asymmetrically arranged and parallel to each other. A sidewall grating, etched on the inner sidewalls of the bus waveguide and the access waveguide, has a period that satisfies the Bragg phase matching condition, and is used to reverse-couple the optical signal transmitted in the forward direction in the bus waveguide to the access waveguide at the Bragg wavelength. The thermoelectric heating layer, located above the dual waveguide structure and the sidewall grating, is composed of Ag 4-x It is composed of TeS (x=0-0.05) based thermoelectric material, which generates local heat through the Joule heating effect and tunes the Bragg wavelength through the thermo-optic effect; An isolation layer, with a thickness of 100–200 nm, is disposed between the Z-cut thin-film lithium niobate functional layer and the thermoelectric heating layer, and is used for electrical isolation and thermal conduction. An electrode system, electrically connected to the thermoelectric heating layer, is used to apply an electrical signal to drive the thermoelectric heating layer to generate Joule heating. A protective layer covers the thermoelectric heating layer and the electrode system.

[0009] Based on the above configuration, the thin-film lithium niobate low-loss waveguide provided in this application embodiment achieves low transmission loss and high mass production consistency through the combination of Z-cut thin-film lithium niobate and hybrid etching process; it achieves wavelength-selective reverse coupling function through the synergistic effect of dual waveguide structure and sidewall grating; and through Ag... 4-x The integration of TeS-based thermoelectric heating layers enables dynamic tunability of the Bragg wavelength, providing core device support for reconfigurable photonic integrated circuits.

[0010] Specifically, an electrical signal is applied to the thermoelectric heating layer through the electrode system to induce Joule heating; the heat is conducted to the Z-cut thin-film lithium niobate functional layer through the isolation layer, and the local refractive index is changed by the positive thermo-optic coefficient of lithium niobate, thereby dynamically tuning the Bragg wavelength of the sidewall grating, and finally realizing the continuous tunability of the coupling wavelength of the optical signal between the bus waveguide and the access waveguide.

[0011] It should be noted that the substrate layer uses silicon, quartz, or sapphire materials to provide mechanical support and thermal management. Silicon has high thermal conductivity and good CMOS process compatibility, making it suitable for large-scale integration; quartz has excellent insulation properties and chemical stability; sapphire has high hardness and high temperature resistance, making it suitable for complex working environments.

[0012] In addition, the isolation layer is made of silicon dioxide and is formed using a plasma-enhanced chemical vapor deposition process; the protective layer is made of silicon dioxide and has a thickness of 300–1000 nm; silicon dioxide has the advantages of low light absorption, high insulation and compatibility with CMOS processes.

[0013] Preferably, in the hybrid etching process: the etching depth of the ridge region is 200–300 nm, the etching depth of the planar region is 100–200 nm, and the width of the ridge region is 1.0–1.5 μm.

[0014] Preferably, the width of the bus waveguide is 500–700 nm, the width of the access waveguide is 300–500 nm, and the spacing between the bus waveguide and the access waveguide is 400–600 nm.

[0015] Preferably, the input and output ends of the dual waveguide structure are provided with an adiabatic tapered transition structure as an apodized structure, with a length of 25–50 μm, to suppress spectral sidelobe oscillations. Through the adiabatic gradient of the waveguide width, low-loss matching of the optical mode field is achieved, resulting in a flat passband response.

[0016] Preferably, the thickness of the thermoelectric heating layer is 50-200 nm, and it is patterned and covers the area directly above the sidewall grating region.

[0017] Preferably, the Ag 4-x TeS (x=0-0.05)-based thermoelectric materials are amorphous materials.

[0018] Based on the above materials, this application adopts an amorphous Ag structure. 4-x TeS-based thermoelectric materials, with their long-range atomic disorder, short-range order, and absence of defects such as grain boundary dislocations, can not only concentrate heat with low thermal conductivity to significantly improve thermo-optical tuning efficiency, but also maintain good electrical conductivity through hopping conduction to generate heat efficiently and reduce driving energy consumption. At the same time, they can dissipate heat dissipation stress by relying on their own plastic deformation capacity, making them less prone to cracking and interface failure during repeated thermal cycling. They can also be prepared by low-temperature processes without damaging lithium niobate waveguides and are compatible with subsequent micro-nano fabrication. They perfectly solve the problems of low thermal efficiency, poor reliability, and process incompatibility of traditional heating materials.

[0019] Preferably, anti-reflection grating structures are provided at both ends of the sidewall grating, and the period of the anti-reflection grating structures is different from that of the sidewall grating, which is used to suppress waveguide self-reflection.

[0020] It should be noted that the antireflective grating structure includes a first antireflective grating parameter d1 and a second antireflective grating parameter d2, where d1 is 250–400 nm and d2 is -10–50 nm. By optimizing the geometric parameters of the antireflective grating, the self-reflection intensity can be further reduced.

[0021] The second aspect of this application provides a method for fabricating a thin-film lithium niobate low-loss waveguide based on a hybrid etching process, comprising the following steps: Step S1: Provide a Z-cut lithium niobate on insulator wafer, wherein the wafer comprises, from bottom to top, a silicon substrate layer, a silicon dioxide buried oxide layer and a Z-cut thin film lithium niobate layer, and the thickness of the Z-cut thin film lithium niobate layer is 300–600 nm; Step S2: Perform the first photolithography and etching on the surface of the Z-cut thin film lithium niobate layer to form the ridge region and sidewall grating of the dual waveguide structure. The etching depth is 200–300 nm. Step S3: Perform a second photolithography and etching process to form a planar region with a dual waveguide structure, etching down to the buried oxide layer of silicon dioxide, with an etching depth of 100–200 nm; Step S4: Deposit an isolation layer, wherein the isolation layer is silicon dioxide and has a thickness of 100–200 nm; Step S5: Perform a third photolithography on the surface of the isolation layer to define the thermoelectric heating layer pattern; Step S6: Deposit the thermoelectric heating layer material, wherein the thermoelectric heating layer material is Ag.4-x TeS (x=0-0.05) based thermoelectric materials with a thickness of 50–200 nm are patterned thermoelectric heating layers formed by a peeling process; It should be noted that, according to stoichiometric ratio, Ag 4-x TeS (x=0-0.05): Weigh out elemental raw materials of silver, tellurium, and sulfur with a purity of 99.99% or higher, mix them, and place them in a quartz tube, then seal under vacuum. Place the quartz tube in a melting furnace and heat it to 900°C at a heating rate of 2–5°C / min, holding it at that temperature for 4 hours to allow the raw materials to fully melt and react. After cooling, Ag is obtained. 4-x TeS ingots; the ingots are crushed, ball-milled into powder, and then sintered at 400–600°C and 50–100MPa using hot pressing or spark plasma sintering processes to obtain Ag4₋ for magnetron sputtering. x TeS alloy target.

[0022] Step S7: Deposit a protective layer, wherein the protective layer is silicon dioxide and has a thickness of 300–1000 nm; Step S8: Perform the fourth photolithography and etching to open electrode windows in the protective layer and isolation layer to expose the contact area of ​​the thermoelectric heating layer; Step S9: Deposit electrode material to form an electrode system electrically connected to the thermoelectric heating layer through a peeling process; Step S10: Perform annealing treatment at a temperature of 300–400°C for 1–3 hours in a nitrogen or argon atmosphere.

[0023] Based on the above steps, this application embodiment achieves high-precision fabrication of low-loss ridge waveguides by combining Z-cut lithium niobate wafers on insulators with hybrid etching processes; through Ag... 4-x A low-temperature magnetron sputtering deposition and lift-off process for TeS-based thermoelectric materials enables patterned integration of the thermoelectric heating layer. Annealing eliminates lattice damage introduced by etching, stabilizing the material structure and interface properties. This method features clear process steps, is compatible with standard CMOS process lines, and is suitable for large-scale mass production of 4-8 inch wafers.

[0024] It should be noted that the etching in steps S2 and S3 adopts inductively coupled plasma reactive ion etching process, the etching gas is a mixture of CHF3 and Ar, the bias power is 50–150W, the etching rate is 20–30nm / min, to achieve high precision and high selectivity of lithium niobate etching, the sidewall angle can be controlled within 70°–80°, and the surface roughness can be controlled below 2nmRMS, effectively reducing sidewall scattering loss.

[0025] In step S2, the ridge region and sidewall grating pattern of the dual waveguide structure are defined using electron beam lithography or deep ultraviolet lithography. Electron beam lithography is suitable for small-batch, high-precision device fabrication, while deep ultraviolet lithography is suitable for large-scale mass production. In step S3, the thickness of the plate region after etching is 100–200 nm. By controlling the thickness of the plate region, the mode characteristics and optical field distribution of the waveguide can be adjusted, optimizing single-mode transmission conditions. In step S4, the isolation layer is deposited using plasma-enhanced chemical vapor deposition (PECVD) at a deposition temperature of 200–300°C to reduce film stress. The isolation layer thickness of 100–200 nm ensures both electrical isolation (breakdown voltage >100V) and efficient heat conduction to the underlying waveguide.

[0026] Preferably, in step S6, magnetron sputtering is used to deposit the thermoelectric heating layer under an inert atmosphere with an Ag4TeS alloy target at a substrate temperature ranging from room temperature to 150°C.

[0027] In step S6, a patterned thermoelectric heating layer is formed through a lift-off process, which includes: performing a third photolithography before deposition to define the pattern of the thermoelectric heating layer; and after depositing the thermoelectric heating layer material, peeling off the photoresist in an organic solvent to leave the patterned thermoelectric heating layer. The lift-off process avoids direct etching of the thermoelectric heating layer, thus protecting the integrity of the material structure.

[0028] It should be noted that in step S7, the protective layer is deposited using PECVD technology with silicon dioxide, a thickness of 300–1000 nm, and a deposition temperature of 200–300°C. The protective layer serves to isolate the thermoelectric heating layer and electrode system from external environmental corrosion and provides mechanical protection. In step S8, electrode windows are opened in the protective layer and isolation layer through a fourth photolithography and etching process, exposing the contact area of ​​the thermoelectric heating layer. The etching process uses reactive ion etching with a mixed gas of CHF3 and Ar, offering high selectivity and precise stopping at the surface of the thermoelectric heating layer. In step S9, the electrode material is a gold, platinum, or titanium-gold stack, deposited by electron beam evaporation or magnetron sputtering, with a thickness of 100–200 nm. Gold has low resistivity and excellent chemical stability, making it suitable as an electrode material. In step S9, the electrode system includes a first contact electrode and a second contact electrode, which are electrically connected to both ends of the thermoelectric heating layer, respectively. The electrode system is formed through a lift-off process and overlaps with the edge of the thermoelectric heating layer, with a contact resistance of less than 10Ω. In step S10, the annealing treatment is carried out in a nitrogen or argon atmosphere at a temperature of 300–400°C for 1–3 hours. The functions of the annealing treatment include: eliminating lattice damage introduced by etching: during ICP-RIE etching, ion bombardment introduces lattice defects and dangling bonds on the lithium niobate surface; annealing can repair lattice damage and reduce waveguide transmission loss; stabilizing Ag4₋x TeS amorphous structure: Annealing is performed below the glass transition temperature of amorphous materials, which can release the internal stress of the film and stabilize the amorphous structure; Improved interface adhesion: Annealing can promote the diffusion of interfacial atoms and improve the interfacial bonding strength between the thermoelectric heating layer and the isolation layer, and between the electrode layer and the thermoelectric heating layer.

[0029] It should be noted that this fabrication method may further include a wafer-level test structure fabrication step: fabricating an arrayed test structure on a wafer, including straight waveguides of different lengths, bent waveguide chains of different bending radii, and micro-ring resonators of different circumferences, to statistically analyze the wafer-level distribution of waveguide transmission loss and evaluate process uniformity and yield.

[0030] A third aspect of this application provides a reconfigurable photonic integrated circuit comprising a plurality of thin-film lithium niobate low-loss waveguides based on a hybrid etching process, wherein at least one of the waveguides has a thermoelectric heating layer configured to independently apply an electrical signal to tune the Bragg wavelength.

[0031] Therefore, this application has at least the following beneficial effects: (1) The embodiments of this application use Ag 4-x TeS amorphous thermoelectric material, with its amorphous structure, strongly scatters phonons, resulting in extremely low thermal conductivity and highly localized heat, avoiding lateral diffusion losses. Simultaneously, charge carriers maintain high mobility through hopping conduction, ensuring efficient Joule heating. Therefore, compared to traditional high thermal conductivity metal heaters, the heating efficiency of this invention is improved. Furthermore, it possesses plastic deformation capabilities, dissipating heat stress through microscopic plastic flow, thus fundamentally solving the reliability problems of traditional brittle heaters, such as easy cracking and interface failure under thermal cycling, significantly extending device lifespan. (2) By integrating Ag in a dual waveguide reverse coupler 4-x The TeS-based thermoelectric heating layer utilizes its unique thermoelectric effect to achieve dynamic tuning. When an electrical signal is applied to the heating layer, carrier migration generates Joule heating. This heat is efficiently conducted through an ultrathin insulating layer to the underlying Z-cut thin-film lithium niobate waveguide, causing it to heat up locally. Because lithium niobate has a positive thermo-optic coefficient, the increased temperature leads to an increase in the effective refractive index of the waveguide, thereby altering the Bragg phase-matching condition and enabling continuous and precise tuning of the Bragg wavelength. This perfectly meets the dynamic wavelength configuration requirements of reconfigurable optical networks. (3) This application uses Z-cut thin-film lithium niobate combined with a hybrid etching process. Z-cut wafers have inherent advantages in large-size fabrication, such as stable domain structure and uniform planar stress distribution, which ensures the consistency of wafer-level performance of the device from the material source and significantly improves the mass production yield. At the same time, the ridge waveguide formed by the hybrid etching process concentrates the optical field energy in the center of the ridge region, which greatly reduces the scattering loss caused by sidewall roughness. Experimental results show that the transmission loss of this waveguide can be stably controlled below 0.5dB / cm, which is about 40% lower than that of the traditional fully etched waveguide, laying the foundation for low-loss optical path integration. (4) Introducing adiabatic tapered transition structures as abutments at both ends of the dual waveguide structure, optical field mode matching is achieved through the adiabatic gradient of the waveguide width, effectively suppressing spectral sidelobe oscillations and obtaining a steep and flat passband response. On the other hand, antireflection gratings with different periods are set at both ends of the sidewall gratings to disrupt the self-reflection phase matching condition at a specific wavelength, significantly suppressing end-face reflection. The synergistic effect of these two measures results in a sidelobe suppression ratio better than -10dB, an operating bandwidth extended to 20-25nm, and overall spectral performance comprehensively optimized. (5) The preparation method provided in this application has high process compatibility, Ag 4-x The TeS thermoelectric heating layer is deposited at low temperatures using magnetron sputtering, a process that completely avoids thermal damage to the temperature-sensitive thin-film lithium niobate waveguide caused by back-end processes. The entire process is compatible with standard CMOS process lines and can be implemented on 4-8 inch wafers, paving the way for large-scale, low-cost manufacturing.

[0032] This solves the problems of non-tunable wavelength, poor mass production consistency, high transmission loss, large self-reflection interference, low efficiency, poor reliability, and poor process compatibility in existing technologies.

[0033] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0034] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings, wherein: Figure 1 A cross-sectional view of a single-ridged waveguide provided according to an embodiment of this application; Figure 2 This is a schematic diagram of the fabrication process of a thin-film lithium niobate low-loss waveguide according to an embodiment of this application. Detailed Implementation

[0035] The embodiments of this application are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain this application, and should not be construed as limiting this application.

[0036] The following description, with reference to the accompanying drawings, illustrates an embodiment of a thin-film lithium niobate low-loss waveguide based on a hybrid etching process and its fabrication method. Addressing the high transmission loss problem mentioned in the background section, this application provides a thin-film lithium niobate low-loss waveguide based on a hybrid etching process, employing amorphous Ag... 4-x TeS thermoelectric material, used as a heating layer, significantly improves device reliability while enhancing thermo-optical tuning efficiency due to its low thermal conductivity, high electrical conductivity, and excellent resistance to thermal cycling cracking. By integrating this heating layer into a Z-cut thin-film lithium niobate dual-waveguide reverse coupler, continuous and precise Bragg wavelength tuning is achieved using the thermo-optical effect, meeting the requirements of reconfigurable optical networks. Combined with hybrid etched ridge waveguides to reduce transmission loss, and thermally adiabatic tapered abutments and anti-reflection gratings to optimize spectral sidelobes and self-reflection issues, while leveraging the advantages of Z-cut wafers to improve mass production consistency, and employing low-temperature magnetron sputtering and CMOS-compatible processes for fabrication, this approach comprehensively solves a series of technical challenges in existing devices, such as untunable wavelengths, poor consistency, high loss, large interference, low heating module efficiency, poor reliability, and poor process compatibility.

[0037] Example 1 This application provides a low-loss thin-film lithium niobate waveguide based on a hybrid etching process, such as... Figure 1 As shown, it includes: Substrate: Made of silicon with a thickness of 500 μm, used to provide mechanical support and thermal management; Z-cut thin-film lithium niobate functional layer: Located above the substrate, with a thickness of 400 nm, it is formed into a ridge waveguide structure through a hybrid etching process. The ridge waveguide includes a fully etched ridge region and a partially etched planar region. The ridge region has an etching depth of 200 nm, the planar region has an etching depth of 200 nm, and the ridge region width is 1.1 μm. Dual waveguide structure: Formed in a Z-cut thin-film lithium niobate functional layer, comprising a bus waveguide and an access waveguide. The bus waveguide has a width of 600 nm, the access waveguide has a width of 400 nm, and the two are spaced 500 nm apart, asymmetrically arranged and parallel to each other; Sidewall grating: Etched on the inner sidewalls of the bus waveguide and the access waveguide, with a period of 432 nm, a duty cycle of 50%, and 300 grating periods. This period satisfies the Bragg phase-matching condition, enabling the forward-propagating optical signal in the bus waveguide to be reverse-coupled to the access waveguide at the Bragg wavelength; Apodized structure: The input and output ends of the dual waveguide structure are equipped with an adiabatic tapered transition structure as an apodized structure. The apodized structure has a length of 30μm and is used to suppress spectral sidelobe oscillations. Through the adiabatic gradient of the waveguide width, low-loss matching of the optical field mode is achieved, resulting in a flat passband response. Thermoelectric heating layer: Located above the dual waveguide structure and sidewall gratings, made of Ag 3.95 The material is composed of TeS-based thermoelectric material, 100 nm thick, patterned and covering the area directly above the sidewall grating region. This amorphous material generates localized heat through the Joule heating effect and tunes the Bragg wavelength through the thermo-optical effect. Isolation layer: Located between the Z-cut thin-film lithium niobate functional layer and the thermoelectric heating layer, it is made of silicon dioxide with a thickness of 150nm and is formed by plasma-enhanced chemical vapor deposition. It is used for electrical isolation and thermal conduction. Anti-reflection grating structure: Anti-reflection grating structures are set at both ends of the sidewall grating. The period of the anti-reflection grating structure is 400nm (different from the 432nm period of the sidewall grating), which is used to suppress waveguide self-reflection. The anti-reflection grating structure includes a first anti-reflection grating parameter d1=300nm and a second anti-reflection grating parameter d2=20nm; Electrode system: electrically connected to the thermoelectric heating layer, including a first contact electrode and a second contact electrode, which are respectively electrically connected to both ends of the thermoelectric heating layer, and are used to apply electrical signals to drive the thermoelectric heating layer to generate Joule heating; Protective layer: Covering the thermoelectric heating layer and electrode system, it is made of silicon dioxide and has a thickness of 500nm.

[0038] This application also provides a method for fabricating a thin-film lithium niobate low-loss waveguide based on a hybrid etching process, such as... Figure 2 As shown, it includes the following steps: Step S1: Provide a Z-cut lithium niobate on insulator wafer, the wafer comprising, from bottom to top, a silicon substrate layer, a silicon dioxide buried oxide layer and a Z-cut thin film lithium niobate layer, the thickness of the Z-cut thin film lithium niobate layer being 400 nm; Step S2: Spin-coat ZEP-520A electron beam lithography (EPL-C) resist with a thickness of 200 nm onto the Z-cut lithium niobate thin film surface. Use EPL lithography to define the ridge region and sidewall grating pattern of the dual waveguide structure. The ridge region width is 1.1 μm, the sidewall grating period is 432 nm, the duty cycle is 50%, and the number of grating periods is 300.

[0039] Lithium niobate was etched using inductively coupled plasma reactive ion etching (ICP-RIE). The etching gas was a mixture of CHF3 and Ar, the chamber pressure was 10 mTorr, the ICP power was 800 W, the bias power was 100 W, the etching depth was 200 nm, and the etching rate was approximately 25 nm / min. After etching, the sidewall angle was approximately 75°, and the surface roughness was approximately 1.8 nm RMS. After etching, the photoresist was ultrasonically removed in acetone. Step S3: Spin-coat photoresist again, and define the planar region pattern using a second photolithography step. The planar region width is 3μm. ICP-RIE is used to etch the remaining lithium niobate down to the buried oxide layer of silicon dioxide, with an etching depth of 200nm, forming a ridge waveguide structure with a planar thickness of 200nm. The photoresist is removed after etching.

[0040] At the input and output ends of the dual waveguide structure, an adiabatic conical transition structure is formed by photolithography and etching as a toe structure, with a length of 30 μm.

[0041] At both ends of the sidewall grating, an anti-reflection grating structure is formed by photolithography and etching. The anti-reflection grating period is 400nm and the number of grating periods is 20. Step S4: A silicon dioxide isolation layer was deposited using plasma-enhanced chemical vapor deposition (PECVD). The deposition parameters were: substrate temperature 250°C, SiH4 flow rate 40 sccm, N2O flow rate 200 sccm, RF power 100 W, and deposition thickness 150 nm. Testing showed that the isolation layer breakdown voltage was greater than 100 V. Step S5: Perform a third photolithography on the surface of the isolation layer to define the thermoelectric heating layer pattern. The thermoelectric heating layer pattern covers the area directly above the sidewall grating region and has a width of 3μm. Step S6: Deposit the thermoelectric heating layer material, the thermoelectric heating layer material is Ag. 3.95 TeS-based thermoelectric material with a thickness of 100 nm is patterned into a thermoelectric heating layer through a peeling process. It should be noted that, according to stoichiometric ratio, Ag 3.95 TeS weighs silver, tellurium, and sulfur elemental raw materials with a purity of 99.99% or higher, mixes them, and places them in a quartz tube, which is then vacuum-sealed. The quartz tube is placed in a melting furnace and heated to 900°C at a heating rate of 2–5°C / min, and held at that temperature for 4 hours to allow the raw materials to fully melt and react. After cooling, Ag is obtained. 3.95 TeS ingots are crushed, ball-milled into powder, and then sintered at 400–600°C and 50–100 MPa using hot pressing or spark plasma sintering processes to obtain Ag for magnetron sputtering. 3.95 TeS alloy target.

[0042] Step S7: Deposit a protective layer, which is silicon dioxide with a thickness of 500 nm; Step S8: Perform the fourth photolithography and etching to open electrode windows in the protective layer and isolation layer to expose the contact area of ​​the thermoelectric heating layer; Step S9: Gold electrode material with a thickness of 150 nm is deposited using electron beam evaporation. An electrode system electrically connected to the thermoelectric heating layer is formed by a lift-off process. The electrode system includes a first contact electrode and a second contact electrode, which are electrically connected to both ends of the thermoelectric heating layer, respectively. The overlap width between the electrode and the edge of the thermoelectric heating layer is approximately 1 μm, and the contact resistance is approximately 5 Ω. Step S10: Place the prepared wafer in a rapid thermal annealing apparatus and perform annealing treatment under a nitrogen atmosphere. The annealing parameters are: heating rate 15°C / s, annealing temperature 350°C, holding time 2 hours, and then naturally cooling to room temperature.

[0043] It should be noted that this fabrication method may further include a wafer-level test structure fabrication step: fabricating an arrayed test structure on a wafer, including 24 sets of straight waveguides of different lengths (2mm, 5mm, 10mm), 12 sets of bent waveguide chains of different bending radii (40μm, 60μm, 80μm), and 12 sets of microring resonators of different perimeters (200μm, 300μm, 400μm).

[0044] Testing revealed that the device exhibited a transmission loss of 0.45 dB / cm at 1550 nm using the truncation method, a spectral 3 dB bandwidth of 23 nm, an on-chip insertion loss of 1.8 dB, a sidelobe suppression ratio of -12 dB, and a total device length of only 85 μm. The thermo-optical tuning efficiency was 0.6 nm / mW, achieving 5 nm wavelength tuning with a power consumption of only 8.3 mW. The tuning linearity R² was better than 0.995, and the thermo-optical response rise time was 38 μs and fall time was 45 μs. The average transmission loss at 25 test points on a 4-inch wafer was 0.46 dB / cm, with a standard deviation of 0.05 dB / cm. The yield rate for losses below 0.6 dB / cm reached 94%, demonstrating excellent overall performance and wafer-level uniformity.

[0045] This application also provides a reconfigurable photonic integrated circuit comprising a plurality of thin-film lithium niobate low-loss waveguides based on a hybrid etching process, wherein at least one waveguide's thermoelectric heating layer is configured to independently apply an electrical signal to tune the Bragg wavelength.

[0046] Example 2 This application provides a low-loss thin-film lithium niobate waveguide based on a hybrid etching process, comprising: Substrate: Made of silicon with a thickness of 500 μm, used to provide mechanical support and thermal management; Z-cut thin-film lithium niobate functional layer: Located above the substrate, with a thickness of 300 nm, it is formed into a ridge waveguide structure through a hybrid etching process. The ridge waveguide includes a fully etched ridge region and a partially etched planar region. The ridge region has an etching depth of 250 nm, the planar region has an etching depth of 150 nm, and the ridge region width is 1.2 μm. Dual waveguide structure: Formed in a Z-cut thin-film lithium niobate functional layer, comprising a bus waveguide and an access waveguide. The bus waveguide has a width of 650 nm, the access waveguide has a width of 350 nm, and the two are spaced 450 nm apart, asymmetrically arranged and parallel to each other; Sidewall grating: Etched on the inner sidewalls of the bus waveguide and the access waveguide, with a period of 440 nm, a duty cycle of 45%, and 250 grating periods. This period satisfies the Bragg phase-matching condition, enabling the forward-propagating optical signal in the bus waveguide to be reverse-coupled to the access waveguide at the Bragg wavelength; Apodized structure: The input and output ends of the dual waveguide structure are equipped with an adiabatic tapered transition structure as an apodized structure. The apodized structure has a length of 40μm and is used to suppress spectral sidelobe oscillations. Through the adiabatic gradient of the waveguide width, low-loss matching of the optical field mode is achieved, resulting in a flat passband response. Thermoelectric heating layer: Located above the dual waveguide structure and sidewall gratings, made of Ag 3.96 The material is composed of TeS-based thermoelectric material, with a thickness of 80 nm, and is patterned and covered directly above the sidewall grating region. This material is amorphous and generates localized heat through the Joule heating effect, and tunes the Bragg wavelength through the thermo-optical effect. Isolation layer: Located between the Z-cut thin-film lithium niobate functional layer and the thermoelectric heating layer, it is made of silicon dioxide with a thickness of 120nm and is formed by plasma-enhanced chemical vapor deposition. It is used for electrical isolation and thermal conduction. Anti-reflection grating structure: Anti-reflection grating structures are set at both ends of the sidewall grating. The period of the anti-reflection grating structure is 410nm (different from the 440nm period of the sidewall grating), which is used to suppress waveguide self-reflection. The anti-reflection grating structure includes a first anti-reflection grating parameter d1=320nm and a second anti-reflection grating parameter d2=15nm; Electrode system: electrically connected to the thermoelectric heating layer, including a first contact electrode and a second contact electrode, which are respectively electrically connected to both ends of the thermoelectric heating layer, and are used to apply electrical signals to drive the thermoelectric heating layer to generate Joule heating; Protective layer: Covering the thermoelectric heating layer and electrode system, it is made of silicon dioxide and has a thickness of 600nm.

[0047] This application also provides a method for fabricating a thin-film lithium niobate low-loss waveguide based on a hybrid etching process, comprising the following steps: Step S1: Provide a Z-cut lithium niobate on insulator wafer, the wafer comprising, from bottom to top, a silicon substrate layer, a silicon dioxide buried oxide layer and a Z-cut thin film lithium niobate layer, the thickness of the Z-cut thin film lithium niobate layer being 300 nm; Step S2: Spin-coat photoresist onto the Z-cut thin-film lithium niobate layer, and use deep ultraviolet lithography (DUV) to define the ridge region and sidewall grating pattern of the dual waveguide structure. The ridge region width is 1.2 μm, the sidewall grating period is 440 nm, the duty cycle is 45%, and the number of grating periods is 250.

[0048] Lithium niobate was etched using inductively coupled plasma reactive ion etching (ICP-RIE). The etching gas was a mixture of CHF3 and Ar, the chamber pressure was 10 mTorr, the ICP power was 800 W, the bias power was 100 W, the etching depth was 250 nm, and the etching rate was approximately 25 nm / min. After etching, the sidewall angle was approximately 72°, and the surface roughness was approximately 1.6 nm RMS. After etching, the photoresist was ultrasonically removed in acetone. Step S3: Spin-coat photoresist again to define the pattern of the planar region using a second photolithography step. The planar region is 3 μm wide. ICP-RIE is used to etch the remaining lithium niobate down to the buried oxide layer of silicon dioxide to a depth of 150 nm, forming a ridge waveguide structure with a planar thickness of 150 nm. The photoresist is removed after etching.

[0049] At the input and output ends of the dual waveguide structure, an adiabatic conical transition structure is formed by photolithography and etching as a toe structure, with a length of 40 μm.

[0050] At both ends of the sidewall grating, an anti-reflection grating structure is formed by photolithography and etching. The anti-reflection grating period is 410nm and the number of grating periods is 20. Step S4: A silicon dioxide isolation layer was deposited using plasma-enhanced chemical vapor deposition (PECVD). The deposition parameters were: substrate temperature 250°C, SiH4 flow rate 40 sccm, N2O flow rate 200 sccm, RF power 100 W, and deposition thickness 120 nm. Testing showed that the isolation layer breakdown voltage was greater than 100 V. Step S5: Perform a third photolithography on the surface of the isolation layer to define the thermoelectric heating layer pattern. The thermoelectric heating layer pattern covers the area directly above the sidewall grating region and has a width of 3μm. Step S6: Deposit the thermoelectric heating layer material, the thermoelectric heating layer material is Ag. 3.96 TeS-based thermoelectric material with a thickness of 80 nm is patterned into a thermoelectric heating layer through a peeling process. It should be noted that, according to stoichiometric ratio, Ag 3.96TeS weighs silver, tellurium, and sulfur elemental raw materials with a purity of 99.99% or higher, mixes them, and places them in a quartz tube, which is then vacuum-sealed. The quartz tube is placed in a melting furnace and heated to 900°C at a heating rate of 2–5°C / min, and held at that temperature for 4 hours to allow the raw materials to fully melt and react. After cooling, Ag is obtained. 3.95 TeS ingots are crushed, ball-milled into powder, and then sintered at 400–600°C and 50–100 MPa using hot pressing or spark plasma sintering processes to obtain Ag for magnetron sputtering. 3.96 TeS alloy target.

[0051] Step S7: Deposit a protective layer, which is silicon dioxide with a thickness of 600 nm; Step S8: Perform the fourth photolithography and etching to open electrode windows in the protective layer and isolation layer to expose the contact area of ​​the thermoelectric heating layer; Step S9: Gold electrode material is deposited using electron beam evaporation, and an electrode system electrically connected to the thermoelectric heating layer is formed by a lift-off process. The electrode system includes a first contact electrode and a second contact electrode, which are electrically connected to both ends of the thermoelectric heating layer, respectively. The overlap width between the electrode and the edge of the thermoelectric heating layer is approximately 1 μm, and the contact resistance is approximately 6 Ω. Step S10: Place the prepared wafer in a rapid thermal annealing apparatus and perform annealing treatment under a nitrogen atmosphere. The annealing parameters are: heating rate 20°C / s, annealing temperature 320°C, holding time 2.5 hours, followed by natural cooling to room temperature.

[0052] It should be noted that this fabrication method may further include a wafer-level test structure fabrication step: fabricating an arrayed test structure on a wafer, including 24 sets of straight waveguides of different lengths (2mm, 5mm, 10mm), 12 sets of bent waveguide chains of different bending radii (40μm, 60μm, 80μm), and 12 sets of microring resonators of different perimeters (200μm, 300μm, 400μm).

[0053] Testing revealed that the device exhibited a transmission loss of 0.48 dB / cm at 1550 nm using the truncation method, a spectral 3 dB bandwidth of 22 nm, an on-chip insertion loss of 1.9 dB, a sidelobe suppression ratio of -11 dB, and a total device length of 92 μm. The thermo-optical tuning efficiency was 0.55 nm / mW, achieving 5 nm wavelength tuning power consumption of 9.1 mW. The tuning linearity R² was better than 0.99, and the thermo-optical response rise time was 42 μs and fall time was 48 μs. The average transmission loss at 25 test points on a 4-inch wafer was 0.49 dB / cm, with a standard deviation of 0.06 dB / cm. The yield rate for losses below 0.6 dB / cm reached 92%.

[0054] Example 3 This application provides a low-loss thin-film lithium niobate waveguide based on a hybrid etching process, comprising: Substrate: Made of silicon with a thickness of 500 μm, used to provide mechanical support and thermal management; Z-cut thin-film lithium niobate functional layer: Located above the substrate, with a thickness of 300 nm, it forms a ridge waveguide structure through a hybrid etching process. The ridge waveguide includes a fully etched ridge region and a partially etched planar region. The ridge region has an etching depth of 300 nm, the planar region has an etching depth of 200 nm, and the ridge region has a width of 1.4 μm.

[0055] Dual waveguide structure: Formed in a Z-cut thin-film lithium niobate functional layer, comprising a bus waveguide and an access waveguide. The bus waveguide has a width of 700 nm, the access waveguide has a width of 500 nm, and the two are spaced 550 nm apart, asymmetrically arranged and parallel to each other; Sidewall grating: Etched on the inner sidewalls of the bus waveguide and the access waveguide, with a period of 448 nm, a duty cycle of 55%, and 280 grating periods. This period satisfies the Bragg phase-matching condition, enabling the forward-propagating optical signal in the bus waveguide to be reverse-coupled to the access waveguide at the Bragg wavelength; Apodized structure: The input and output ends of the dual waveguide structure are equipped with an adiabatic tapered transition structure as an apodized structure. The apodized structure has a length of 35μm and is used to suppress spectral sidelobe oscillations. Through the adiabatic gradient of the waveguide width, low-loss matching of the optical field mode is achieved, resulting in a flat passband response. Thermoelectric heating layer: Located above the dual waveguide structure and sidewall gratings, made of Ag 3.98 The material is composed of TeS-based thermoelectric material, 120 nm thick, patterned and covering the area directly above the sidewall grating region. This amorphous material generates localized heat through the Joule heating effect and tunes the Bragg wavelength through a thermo-optical effect. Isolation layer: Located between the Z-cut thin-film lithium niobate functional layer and the thermoelectric heating layer, it is made of silicon dioxide with a thickness of 180nm and is formed by plasma-enhanced chemical vapor deposition. It is used for electrical isolation and thermal conduction. Anti-reflection grating structure: Anti-reflection grating structures are set at both ends of the sidewall grating. The period of the anti-reflection grating structure is 418nm (different from the 448nm period of the sidewall grating), which is used to suppress waveguide self-reflection. The anti-reflection grating structure includes a first anti-reflection grating parameter d1=350nm and a second anti-reflection grating parameter d2=25nm; Electrode system: electrically connected to the thermoelectric heating layer, including a first contact electrode and a second contact electrode, which are respectively electrically connected to both ends of the thermoelectric heating layer, and are used to apply electrical signals to drive the thermoelectric heating layer to generate Joule heating; Protective layer: Covering the thermoelectric heating layer and electrode system, it is made of silicon dioxide and has a thickness of 800nm.

[0056] This application also provides a method for fabricating a thin-film lithium niobate low-loss waveguide based on a hybrid etching process, comprising the following steps: Step S1: Provide a Z-cut lithium niobate on insulator wafer, the wafer comprising, from bottom to top, a silicon substrate layer, a silicon dioxide buried oxide layer and a Z-cut thin film lithium niobate layer, the thickness of the Z-cut thin film lithium niobate layer being 500 nm; Step S2: Spin-coat photoresist onto the Z-cut thin-film lithium niobate layer, and use electron beam lithography to define the ridge region and sidewall grating pattern of the dual waveguide structure. The ridge region width is 1.4 μm, the sidewall grating period is 448 nm, the duty cycle is 55%, and the number of grating periods is 280.

[0057] Lithium niobate was etched using inductively coupled plasma reactive ion etching (ICP-RIE). The etching gas was a mixture of CHF3 and Ar, the chamber pressure was 10 mTorr, the ICP power was 800 W, the bias power was 100 W, the etching depth was 300 nm, and the etching rate was approximately 25 nm / min. After etching, the sidewall angle was approximately 75°, and the surface roughness was approximately 1.9 nm RMS. After etching, the photoresist was ultrasonically removed in acetone. Step S3: Spin-coat photoresist again to define the planar region pattern using a second photolithography step. The planar region width is 3.5 μm. ICP-RIE is used to etch the remaining lithium niobate down to the buried oxide layer of silicon dioxide to a depth of 200 nm, forming a ridge waveguide structure with a planar thickness of 200 nm. The photoresist is removed after etching.

[0058] At the input and output ends of the dual waveguide structure, an adiabatic conical transition structure is formed by photolithography and etching as a toe structure, with a length of 35 μm.

[0059] At both ends of the sidewall grating, an anti-reflection grating structure is formed by photolithography and etching. The anti-reflection grating period is 418nm and the number of grating periods is 20. Step S4: A silicon dioxide isolation layer was deposited using plasma-enhanced chemical vapor deposition (PECVD). The deposition parameters were: substrate temperature 250°C, SiH4 flow rate 40 sccm, N2O flow rate 200 sccm, RF power 100 W, and deposition thickness 180 nm. Testing showed that the isolation layer breakdown voltage was greater than 100 V. Step S5: Perform a third photolithography on the surface of the isolation layer to define the thermoelectric heating layer pattern. The thermoelectric heating layer pattern covers the area directly above the sidewall grating region and has a width of 3.5 μm. Step S6: Deposit the thermoelectric heating layer material, the thermoelectric heating layer material is Ag. 3.98 TeS-based thermoelectric material with a thickness of 120 nm is patterned into a thermoelectric heating layer through a peeling process. It should be noted that, according to stoichiometric ratio, Ag 3.98 TeS weighs silver, tellurium, and sulfur elemental raw materials with a purity of 99.99% or higher, mixes them, and places them in a quartz tube, which is then vacuum-sealed. The quartz tube is placed in a melting furnace and heated to 900°C at a heating rate of 2–5°C / min, and held at that temperature for 4 hours to allow the raw materials to fully melt and react. After cooling, Ag is obtained. 3.98 TeS ingots are crushed, ball-milled into powder, and then sintered at 400–600°C and 50–100 MPa using hot pressing or spark plasma sintering processes to obtain Ag for magnetron sputtering. 3.98 TeS alloy target.

[0060] Step S7: Deposit a protective layer, which is silicon dioxide with a thickness of 800 nm; Step S8: Perform the fourth photolithography and etching to open electrode windows in the protective layer and isolation layer to expose the contact area of ​​the thermoelectric heating layer; Step S9: Gold electrode material is deposited using electron beam evaporation, and an electrode system electrically connected to the thermoelectric heating layer is formed through a lift-off process. The electrode system includes a first contact electrode and a second contact electrode, which are electrically connected to both ends of the thermoelectric heating layer, respectively. The overlap width between the electrode and the edge of the thermoelectric heating layer is approximately 1 μm, and the contact resistance is approximately 7 Ω. Step S10: Place the prepared wafer in a rapid thermal annealing apparatus and perform annealing treatment under a nitrogen atmosphere. The annealing parameters are: heating rate 15°C / s, annealing temperature 360°C, holding time 2 hours, and then naturally cooling to room temperature.

[0061] It should be noted that this fabrication method may further include a wafer-level test structure fabrication step: fabricating an arrayed test structure on a wafer, including 24 sets of straight waveguides of different lengths (2mm, 5mm, 10mm), 12 sets of bent waveguide chains of different bending radii (40μm, 60μm, 80μm), and 12 sets of microring resonators of different perimeters (200μm, 300μm, 400μm).

[0062] Testing revealed that the device exhibited a waveguide transmission loss of 0.52 dB / cm at 1550 nm using the truncation method, a spectral 3 dB bandwidth of 24 nm, an on-chip insertion loss of 2.1 dB, a sidelobe suppression ratio of -10 dB, and a total device length of 98 μm. The thermo-optical tuning efficiency was 0.50 nm / mW, achieving 5 nm wavelength tuning power consumption of 10.0 mW. The tuning linearity R² was better than 0.99, and the thermo-optical response rise time was 48 μs and fall time was 52 μs. The average transmission loss at 25 test points on a 4-inch wafer was 0.53 dB / cm, with a standard deviation of 0.07 dB / cm. The yield rate for losses less than 0.7 dB / cm reached 90%.

[0063] Example 4 This application provides a low-loss thin-film lithium niobate waveguide based on a hybrid etching process, comprising: Substrate: Made of silicon with a thickness of 500 μm, used to provide mechanical support and thermal management; Z-cut thin-film lithium niobate functional layer: Located above the substrate, with a thickness of 350 nm, it forms a ridge waveguide structure through a hybrid etching process. The ridge waveguide includes a fully etched ridge region and a partially etched planar region. The ridge region has an etching depth of 200 nm, the planar region has an etching depth of 150 nm, and the ridge region has a width of 1.0 μm.

[0064] Dual waveguide structure: Formed in a Z-cut thin-film lithium niobate functional layer, comprising a bus waveguide and an access waveguide. The bus waveguide has a width of 550 nm, the access waveguide has a width of 320 nm, and the two are spaced 420 nm apart, asymmetrically arranged and parallel to each other; Sidewall grating: Etched on the inner sidewalls of the bus waveguide and the access waveguide, with a period of 420 nm, a duty cycle of 40%, and 320 grating periods. This period satisfies the Bragg phase-matching condition, enabling the forward-propagating optical signal in the bus waveguide to be reverse-coupled to the access waveguide at the Bragg wavelength; Apodized structure: An adiabatic tapered transition structure, 28 μm in length, is incorporated at both the input and output ends of the dual waveguide structure to suppress spectral sidelobe oscillations. This adiabatic gradient of the waveguide width achieves low-loss mode matching of the optical field, resulting in a flat passband response. Thermoelectric heating layer: Located above the dual waveguide structure and sidewall gratings, made of Ag 3.99 The material is composed of TeS-based thermoelectric material, 120 nm thick, patterned and covering the area directly above the sidewall grating region. This amorphous material generates localized heat through the Joule heating effect and tunes the Bragg wavelength through a thermo-optical effect. Isolation layer: Located between the Z-cut thin-film lithium niobate functional layer and the thermoelectric heating layer, it is made of silicon dioxide with a thickness of 110 nm and is formed by plasma-enhanced chemical vapor deposition. It is used for electrical isolation and thermal conduction. Anti-reflection grating structure: Anti-reflection grating structures are set at both ends of the sidewall grating. The period of the anti-reflection grating structure is 390nm, which is used to suppress waveguide self-reflection. The anti-reflection grating structure includes a first anti-reflection grating parameter d1=280nm and a second anti-reflection grating parameter d2=10nm; Electrode system: electrically connected to the thermoelectric heating layer, including a first contact electrode and a second contact electrode, which are respectively electrically connected to both ends of the thermoelectric heating layer, and are used to apply electrical signals to drive the thermoelectric heating layer to generate Joule heating; Protective layer: Covering the thermoelectric heating layer and electrode system, it is made of silicon dioxide and has a thickness of 400nm.

[0065] This application also provides a method for fabricating a thin-film lithium niobate low-loss waveguide based on a hybrid etching process, comprising the following steps: Step S1: Provide a Z-cut lithium niobate on insulator wafer, the wafer comprising, from bottom to top, a silicon substrate layer, a silicon dioxide buried oxide layer and a Z-cut thin film lithium niobate layer, the thickness of the Z-cut thin film lithium niobate layer being 350nm; Step S2: Spin-coat photoresist onto the Z-cut thin-film lithium niobate layer, and use electron beam lithography to define the ridge region and sidewall grating pattern of the dual waveguide structure. The ridge region width is 1.0 μm, the sidewall grating period is 420 nm, the duty cycle is 40%, and the number of grating periods is 320.

[0066] Lithium niobate was etched using inductively coupled plasma reactive ion etching (ICP-RIE). The etching gas was a mixture of CHF3 and Ar, with a chamber pressure of 10 mTorr, ICP power of 800 W, bias power of 100 W, etching depth of 200 nm, and etching rate of approximately 25 nm / min. After etching, the sidewall angle was approximately 75°, and the surface roughness was approximately 1.9 nm RMS. After etching, the photoresist was ultrasonically removed in acetone. Step S3: Spin-coat photoresist again to define the planar region pattern using a second photolithography step. The planar region width is 3.5 μm. ICP-RIE is used to etch the remaining lithium niobate down to the buried oxide layer of silicon dioxide to a depth of 150 nm, forming a ridge waveguide structure with a planar thickness of 150 nm. The photoresist is removed after etching.

[0067] At the input and output ends of the dual waveguide structure, an adiabatic conical transition structure is formed by photolithography and etching as a toe structure, with a length of 28 μm.

[0068] At both ends of the sidewall grating, an anti-reflection grating structure is formed by photolithography and etching. The anti-reflection grating period is 390nm and the number of grating periods is 20. Step S4: A silicon dioxide isolation layer was deposited using plasma-enhanced chemical vapor deposition (PECVD). The deposition parameters were: substrate temperature 250°C, SiH4 flow rate 40 sccm, N2O flow rate 200 sccm, RF power 100 W, and deposition thickness 110 nm. Testing showed that the isolation layer breakdown voltage was greater than 100 V. Step S5: Perform a third photolithography on the surface of the isolation layer to define the thermoelectric heating layer pattern. The thermoelectric heating layer pattern covers the area directly above the sidewall grating region and has a width of 3μm. Step S6: Deposit the thermoelectric heating layer material, the thermoelectric heating layer material is Ag. 3.99 TeS-based thermoelectric material with a thickness of 120 nm is patterned into a thermoelectric heating layer through a peeling process. It should be noted that, according to stoichiometric ratio, Ag3.99 TeS weighs silver, tellurium, and sulfur elemental raw materials with a purity of 99.99% or higher, mixes them, and places them in a quartz tube, which is then vacuum-sealed. The quartz tube is placed in a melting furnace and heated to 900°C at a heating rate of 2–5°C / min, and held at that temperature for 4 hours to allow the raw materials to fully melt and react. After cooling, Ag is obtained. 3.99 TeS ingots are crushed, ball-milled into powder, and then sintered at 400–600°C and 50–100 MPa using hot pressing or spark plasma sintering processes to obtain Ag for magnetron sputtering. 3.99 TeS alloy target.

[0069] Step S7: Deposit a protective layer, which is silicon dioxide with a thickness of 400 nm; Step S8: Perform the fourth photolithography and etching to open electrode windows in the protective layer and isolation layer to expose the contact area of ​​the thermoelectric heating layer; Step S9: Gold electrode material is deposited using electron beam evaporation, and an electrode system electrically connected to the thermoelectric heating layer is formed through a lift-off process. The electrode system includes a first contact electrode and a second contact electrode, which are electrically connected to both ends of the thermoelectric heating layer, respectively. The overlap width between the electrode and the edge of the thermoelectric heating layer is approximately 1 μm, and the contact resistance is approximately 8 Ω. Step S10: Place the prepared wafer in a rapid thermal annealing apparatus and perform annealing treatment under a nitrogen atmosphere. The annealing parameters are: heating rate 15°C / s, annealing temperature 360°C, holding time 2 hours, and then naturally cooling to room temperature.

[0070] It should be noted that this fabrication method may further include a wafer-level test structure fabrication step: fabricating an arrayed test structure on a wafer, including 24 sets of straight waveguides of different lengths (2mm, 5mm, 10mm), 12 sets of bent waveguide chains of different bending radii (40μm, 60μm, 80μm), and 12 sets of microring resonators of different perimeters (200μm, 300μm, 400μm).

[0071] Test results show that the device has a waveguide transmission loss of 0.47 dB / cm, a spectral 3 dB bandwidth of 21 nm, an on-chip insertion loss of 1.9 dB, a sidelobe suppression ratio of -13 dB, and a total device length of 75 μm. The thermo-optical tuning efficiency is 0.58 nm / mW, achieving 5 nm wavelength tuning power consumption of 8.6 mW, and a thermo-optical response rise time of 32 μs and a fall time of 38 μs. The wafer-level uniformity is good, with an average transmission loss of 0.48 dB / cm, a standard deviation of 0.06 dB / cm, and a yield of 93%.

[0072] Example 5 This application provides a low-loss thin-film lithium niobate waveguide based on a hybrid etching process, comprising: Substrate: Made of silicon with a thickness of 500 μm, used to provide mechanical support and thermal management; Z-cut thin-film lithium niobate functional layer: Located above the substrate, with a thickness of 450 nm, it forms a ridge waveguide structure through a hybrid etching process. The ridge waveguide includes a fully etched ridge region and a partially etched planar region. The ridge region has an etching depth of 280 nm, the planar region has an etching depth of 170 nm, and the ridge region has a width of 1.3 μm.

[0073] Dual waveguide structure: Formed in a Z-cut thin-film lithium niobate functional layer, comprising a bus waveguide and an access waveguide. The bus waveguide has a width of 680 nm, the access waveguide has a width of 420 nm, and the two are spaced 520 nm apart, asymmetrically arranged and parallel to each other; Sidewall grating: Etched on the inner sidewalls of the bus waveguide and the access waveguide, with a period of 435 nm, a duty cycle of 52%, and 260 grating periods. This period satisfies the Bragg phase-matching condition, enabling the forward-propagating optical signal in the bus waveguide to be reverse-coupled to the access waveguide at the Bragg wavelength; Apodized structure: An adiabatic tapered transition structure, 45 μm in length, is incorporated at both the input and output ends of the dual waveguide structure to suppress spectral sidelobe oscillations. This adiabatic gradient of the waveguide width achieves low-loss mode matching of the optical field, resulting in a flat passband response. Thermoelectric heating layer: Located above the dual waveguide structure and sidewall gratings, it is composed of Ag4TeS-based thermoelectric material with a thickness of 150 nm, and is patterned directly above the sidewall grating region. This material is amorphous and generates localized heat through the Joule heating effect, and tunes the Bragg wavelength through the thermo-optical effect. Isolation layer: Located between the Z-cut thin-film lithium niobate functional layer and the thermoelectric heating layer, it is made of silicon dioxide with a thickness of 160nm and is formed by plasma-enhanced chemical vapor deposition. It is used for electrical isolation and thermal conduction. Anti-reflection grating structure: Anti-reflection grating structures are set at both ends of the sidewall grating. The period of the anti-reflection grating structure is 405nm, which is used to suppress waveguide self-reflection. The anti-reflection grating structure includes a first anti-reflection grating parameter d1=340nm and a second anti-reflection grating parameter d2=18nm; Electrode system: electrically connected to the thermoelectric heating layer, including a first contact electrode and a second contact electrode, which are respectively electrically connected to both ends of the thermoelectric heating layer, and are used to apply electrical signals to drive the thermoelectric heating layer to generate Joule heating; Protective layer: Covering the thermoelectric heating layer and electrode system, it is made of silicon dioxide and has a thickness of 700nm.

[0074] This application also provides a method for fabricating a thin-film lithium niobate low-loss waveguide based on a hybrid etching process, comprising the following steps: Step S1: Provide a Z-cut lithium niobate on insulator wafer, the wafer comprising, from bottom to top, a silicon substrate layer, a silicon dioxide buried oxide layer and a Z-cut thin film lithium niobate layer, the thickness of the Z-cut thin film lithium niobate layer being 450nm; Step S2: Spin-coat photoresist onto the Z-cut thin-film lithium niobate layer, and use electron beam lithography to define the ridge region and sidewall grating pattern of the dual waveguide structure. The ridge region width is 1.3 μm, the sidewall grating period is 435 nm, the duty cycle is 52%, and the number of grating periods is 260.

[0075] Lithium niobate was etched using inductively coupled plasma reactive ion etching (ICP-RIE). The etching gas was a mixture of CHF3 and Ar, the chamber pressure was 10 mTorr, the ICP power was 800 W, the bias power was 100 W, the etching depth was 280 nm, and the etching rate was approximately 25 nm / min. After etching, the sidewall angle was approximately 75°, and the surface roughness was approximately 1.9 nm RMS. After etching, the photoresist was ultrasonically removed in acetone. Step S3: Spin-coat photoresist again to define the planar region pattern using a second photolithography step. The planar region width is 3.5 μm. ICP-RIE is used to etch the remaining lithium niobate down to the buried oxide layer of silicon dioxide to a depth of 150 nm, forming a ridge waveguide structure with a planar thickness of 150 nm. The photoresist is removed after etching.

[0076] At the input and output ends of the dual waveguide structure, an adiabatic conical transition structure is formed by photolithography and etching as a toe structure, with a length of 45 μm.

[0077] At both ends of the sidewall grating, an anti-reflection grating structure is formed by photolithography and etching. The anti-reflection grating period is 405nm and the number of grating periods is 20. Step S4: A silicon dioxide isolation layer was deposited using plasma-enhanced chemical vapor deposition (PECVD). The deposition parameters were: substrate temperature 250°C, SiH4 flow rate 40 sccm, N2O flow rate 200 sccm, RF power 100W, and deposition thickness 160 nm. Testing showed that the isolation layer breakdown voltage was greater than 100V. Step S5: Perform a third photolithography on the surface of the isolation layer to define the thermoelectric heating layer pattern. The thermoelectric heating layer pattern covers the area directly above the sidewall grating region and has a width of 3.5 μm. Step S6: Deposit thermoelectric heating layer material. The thermoelectric heating layer material is Ag4TeS-based thermoelectric material with a thickness of 150nm. A patterned thermoelectric heating layer is formed by a peeling process. It should be noted that, according to the stoichiometric ratio, silver, tellurium, and sulfur elemental raw materials with a purity of 99.99% or higher are weighed into Ag4TeS, mixed, and placed in a quartz tube, which is then vacuum sealed. The quartz tube is placed in a melting furnace and heated to 900°C at a heating rate of 2–5°C / min, and held at that temperature for 4 hours to allow the raw materials to fully melt and react. After cooling, Ag4TeS ingots are obtained. The ingots are crushed, ball-milled into powder, and sintered at 400–600°C and 50–100MPa using hot pressing or spark plasma sintering processes to obtain Ag4TeS alloy targets for magnetron sputtering.

[0078] Step S7: Deposit a protective layer, which is silicon dioxide with a thickness of 700 nm; Step S8: Perform the fourth photolithography and etching to open electrode windows in the protective layer and isolation layer to expose the contact area of ​​the thermoelectric heating layer; Step S9: Gold electrode material is deposited using electron beam evaporation, and an electrode system electrically connected to the thermoelectric heating layer is formed through a lift-off process. The electrode system includes a first contact electrode and a second contact electrode, which are electrically connected to both ends of the thermoelectric heating layer, respectively. The overlap width between the electrode and the edge of the thermoelectric heating layer is approximately 1 μm, and the contact resistance is approximately 8 Ω. Step S10: Place the prepared wafer in a rapid thermal annealing apparatus and perform annealing treatment under a nitrogen atmosphere. The annealing parameters are: heating rate 15°C / s, annealing temperature 380°C, holding time 2 hours, and then naturally cooling to room temperature.

[0079] It should be noted that this fabrication method may further include a wafer-level test structure fabrication step: fabricating an arrayed test structure on a wafer, including 24 sets of straight waveguides of different lengths (2mm, 5mm, 10mm), 12 sets of bent waveguide chains of different bending radii (40μm, 60μm, 80μm), and 12 sets of microring resonators of different perimeters (200μm, 300μm, 400μm).

[0080] Test results show that the device has a waveguide transmission loss of 0.49 dB / cm, a spectral 3 dB bandwidth of 23 nm, an on-chip insertion loss of 2.0 dB, a sidelobe suppression ratio of -11 dB, and a total device length of 105 μm. The thermo-optical tuning efficiency is 0.52 nm / mW, achieving 5 nm wavelength tuning power consumption of 9.6 mW, and a thermo-optical response rise time of 52 μs and a fall time of 58 μs. The wafer-level uniformity is good, with an average transmission loss of 0.50 dB / cm, a standard deviation of 0.07 dB / cm, and a yield of 91%.

[0081] Comparative Example 1 This comparative example provides a fully etched reverse coupler based on X-cut thin-film lithium niobate, including: Substrate: Made of silicon material, with a thickness of 500μm; X-cut thin-film lithium niobate functional layer: Located above the substrate, with a thickness of 400 nm, it forms a ridge waveguide structure using a conventional full-etch process. The ridge waveguide is a fully etched structure with no planar areas retained. The ridge etching depth is 400 nm, and the ridge width is 1.1 μm. Dual waveguide structure: Formed in an X-cut thin-film lithium niobate functional layer, comprising a bus waveguide and an access waveguide. The bus waveguide has a width of 600 nm, the access waveguide has a width of 400 nm, and the two are spaced 500 nm apart, asymmetrically arranged and parallel to each other; Sidewall grating: Etched on the inner sidewalls of the bus waveguide and the access waveguide, with a period of 432 nm, a duty cycle of 50%, and 300 grating periods. This period satisfies the Bragg phase-matching condition, enabling the forward-propagating optical signal in the bus waveguide to be reverse-coupled to the access waveguide at the Bragg wavelength; No apod structure: The input and output ends of the dual waveguide structure do not have apod structures; No thermoelectric heating layer: No double waveguide structure and no thermoelectric heating layer above the sidewall grating; No anti-reflection grating structure: No anti-reflection grating structure is provided at both ends of the sidewall grating; Protective layer: Covering the dual waveguide structure, it is made of silicon dioxide and has a thickness of 500nm.

[0082] The preparation method of this comparative example includes the following steps: Step S1: Provide an X-cut lithium niobate on insulator wafer, the wafer comprising, from bottom to top, a silicon substrate layer, a silicon dioxide buried oxide layer and an X-cut thin film lithium niobate layer, the thickness of the X-cut thin film lithium niobate layer being 400nm; Step S2: Spin-coat ZEP-520A electron beam lithography (EPL-C) resist with a thickness of 200 nm onto the surface of the X-cut thin-film lithium niobate layer. Use EPL lithography to define the ridge region and sidewall grating pattern of the dual waveguide structure. The ridge region width is 1.1 μm, the sidewall grating period is 432 nm, the duty cycle is 50%, and the number of grating periods is 300. Lithium niobate was etched using inductively coupled plasma reactive ion etching (ICP-RIE). The etching gas was a mixture of CHF3 and Ar, with a chamber pressure of 10 mTorr, ICP power of 800 W, bias power of 100 W, etching depth of 400 nm, and etching rate of approximately 25 nm / min. After etching, the sidewall angle was approximately 75°, and the surface roughness was approximately 2.5 nm RMS. After etching, the photoresist was ultrasonically removed in acetone.

[0083] Step S3: Deposit a protective layer, which is silicon dioxide with a thickness of 500 nm.

[0084] Testing revealed that this comparative device exhibited a waveguide transmission loss of 1.2 dB / cm at 1550 nm using the truncation method, a spectral 3 dB bandwidth of 20 nm, an on-chip insertion loss of 2.8 dB, a sidelobe suppression ratio of -8 dB, and a total device length of 85 μm. This device lacks an integrated thermoelectric heating layer and therefore does not possess wavelength tuning capabilities. The average transmission loss at 25 test points on a 4-inch wafer was 1.25 dB / cm, with a standard deviation of 0.15 dB / cm. The yield rate for losses below 1.5 dB / cm was only 82%.

[0085] Comparative Example 2 This comparative example provides a thin-film lithium niobate tunable reverse coupler based on a TiN metal heater. The difference from Example 1 is that the thermoelectric heating layer is replaced with a TiN metal heater, specifically including: Substrate: Made of silicon material with a thickness of 500μm.

[0086] Z-cut thin-film lithium niobate functional layer: Located above the substrate, with a thickness of 400 nm, it forms a ridge waveguide structure through a hybrid etching process. The ridge waveguide includes a fully etched ridge region and a partially etched planar region. The ridge region has an etching depth of 200 nm, the planar region has an etching depth of 200 nm, and the ridge region width is 1.1 μm.

[0087] The dual waveguide structure, sidewall grating, apodized structure, and anti-reflection grating structure are the same as in Example 1.

[0088] Thermoelectric heating layer: Located above the dual waveguide structure and sidewall gratings, it is made of TiN metal material with a thickness of 100nm and is patterned directly above the sidewall grating area. It generates localized heat through the Joule heating effect and tunes the Bragg wavelength through the thermo-optical effect.

[0089] Isolation layer: Located between the Z-cut thin-film lithium niobate functional layer and the thermoelectric heating layer, it is made of silicon dioxide and has a thickness of 150nm.

[0090] Electrode system and protective layer: Same as in Example 1.

[0091] The preparation method is basically the same as in Example 1, except that TiN is deposited instead of Ag in step S6. 3.95 TeS was deposited using reactive magnetron sputtering under a nitrogen atmosphere with a Ti target and a deposition thickness of 100 nm.

[0092] Testing revealed that the comparative device exhibited an additional absorption loss due to the TiN heating layer, resulting in a waveguide transmission loss of 0.52 dB / cm, a spectral 3 dB bandwidth of 22 nm, an on-chip insertion loss of 2.2 dB, a sidelobe suppression ratio of -11 dB, and a total device length of 85 μm. The thermo-optical tuning efficiency was only 0.22 nm / mW, achieving 5 nm wavelength tuning with a power consumption as high as 22.7 mW. The tuning linearity R² was better than 0.98, and the thermo-optical response rise time was 45 μs and fall time was 52 μs. After 500 thermal cycles, the tuning efficiency decreased by 12%, and some devices showed cracking of the heating layer, indicating poor long-term reliability.

[0093] Comparative Example 3 This comparative example provides a thin-film lithium niobate tunable reverse coupler based on a crystalline Ag4TeS heater. The difference from Example 1 is that the thermoelectric heating layer is crystalline Ag4TeS, specifically comprising: Substrate: Made of silicon material with a thickness of 500μm.

[0094] Z-cut thin-film lithium niobate functional layer: Same as in Example 1.

[0095] The dual waveguide structure, sidewall grating, apodized structure, and anti-reflection grating structure are the same as in Example 1.

[0096] Thermoelectric heating layer: Located above the dual waveguide structure and sidewall grating, it is composed of Ag4TeS-based thermoelectric material with a thickness of 100 nm, and is patterned and covers the area directly above the sidewall grating region. This material is crystalline (amorphous material is crystallized through high-temperature annealing), generates localized heat through the Joule heating effect, and tunes the Bragg wavelength through the thermo-optical effect.

[0097] The isolation layer, electrode system, and protective layer are the same as in Example 1.

[0098] The preparation method is basically the same as in Example 1, except that a high-temperature crystallization annealing step is added after depositing Ag4TeS in step S6: annealing at 500°C in a nitrogen atmosphere for 1 hour to transform Ag4TeS from an amorphous state to a crystalline state.

[0099] Tests showed that the waveguide transmission loss of this comparative device was 0.48 dB / cm, and the thermal conductivity, measured using the 3ω method, was approximately 2.8 W / m·K. The thermo-optical tuning efficiency was 0.28 nm / mW, achieving a 5 nm wavelength tuning power consumption of 17.9 mW. The tuning linearity R² was better than 0.98, and the thermo-optical response rise time was 48 μs and fall time was 55 μs. After 300 thermal cycles, microcracks appeared in the heating layer, the tuning efficiency decreased by 18%, and the long-term reliability was poor.

[0100] Compared to Comparative Example 1, which uses X-cut LNOI, conventional full etching, and no tuning or spectral optimization structure, Examples 1-5 of this invention, by utilizing Z-cut wafers and hybrid etched ridge waveguides, reduce transmission loss by 56.7%–62.5%. Furthermore, the insertion loss and sidelobe suppression ratio are optimized through apodization and anti-reflection gratings. Simultaneously, Ag4₋ x TeS heating layer enables continuous and precise wavelength tuning, and leverages the advantages of Z-cut wafers to improve wafer-level yield from 82% to 90%–94%.

[0101] Compared to Comparative Example 2, which uses a TiN heater, Examples 1-5 of this invention use amorphous Ag3. 95 TeS achieves highly localized heat due to its low thermal conductivity, improving tuning efficiency by 127%–173% and reducing 5nm tuning power consumption by 56%–63%. Moreover, thanks to the material's plastic deformation capability, its performance degradation is less than 5% after 1000 thermal cycles, which is far superior to the reliability issues of efficiency decline and heating layer cracking after thermal cycles in Comparative Example 2.

[0102] Compared with Comparative Example 3, which uses a crystalline Ag4TeS heater, the amorphous structure of Examples 1-5 of the present invention significantly scatters phonons, reduces thermal conductivity by more than 60%, improves tuning efficiency by 79%–114%, and reduces power consumption by 44%–54%. At the same time, due to the absence of grain boundary dislocations and good plasticity, the problem of cracking and performance degradation after 300 thermal cycles is solved, and the performance degradation after 1000 cycles is still less than 5%.

[0103] In summary, this invention achieves low transmission loss and high mass production consistency by employing a ridge waveguide structure combining Z-cut thin-film lithium niobate with a hybrid etching process; it achieves excellent spectral performance by setting atodial structures at both ends of the dual waveguide structure and anti-reflection grating structures with different periods at both ends of the sidewall gratings; and it integrates Ag4₋ x The TeS amorphous thermoelectric heating layer utilizes its phonon glass-electron crystal transport behavior and plastic deformation capability to achieve a highly efficient, low-power, and highly reliable dynamically tunable filtering function. Compared with existing technologies, this invention simultaneously solves a series of technical problems such as untunable wavelength, poor mass production consistency, high transmission loss, large self-reflection interference, low heater efficiency, poor reliability, and poor process compatibility. It realizes a high-performance, highly reliable, and dynamically reconfigurable integrated photonic device, providing a complete technical solution for the practical application of tunable thin-film lithium niobate photonic devices.

[0104] Although embodiments of this application have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and variations can be made to these embodiments without departing from the principles and spirit of this application. All equivalent changes and improvements made within the scope of this application shall still fall within the patent coverage of this application.

Claims

1. A thin-film lithium niobate low-loss waveguide based on a hybrid etching process, characterized in that, include: Substrate layer; A Z-cut thin-film lithium niobate functional layer, located above the substrate layer, has a thickness of 300–600 nm. A ridge waveguide structure is formed by a hybrid etching process. The ridge waveguide includes a fully etched ridge region and a partially etched planar region. A dual-waveguide structure is formed in the Z-cut thin-film lithium niobate functional layer, including a bus waveguide and an access waveguide. The width of the bus waveguide is greater than the width of the access waveguide. The two are asymmetrically arranged and parallel to each other. A sidewall grating, etched on the inner sidewalls of the bus waveguide and the access waveguide, has a period that satisfies the Bragg phase matching condition, and is used to reverse-couple the optical signal transmitted in the forward direction in the bus waveguide to the access waveguide at the Bragg wavelength. The thermoelectric heating layer, located above the dual waveguide structure and the sidewall grating, is composed of Ag 4-x It is composed of TeS (x=0-0.05) based thermoelectric material, which generates local heat through the Joule heating effect and tunes the Bragg wavelength through the thermo-optic effect; An isolation layer, with a thickness of 100–200 nm, is disposed between the Z-cut thin-film lithium niobate functional layer and the thermoelectric heating layer, and is used for electrical isolation and thermal conduction. An electrode system, electrically connected to the thermoelectric heating layer, is used to apply an electrical signal to drive the thermoelectric heating layer to generate Joule heating. A protective layer covers the thermoelectric heating layer and the electrode system.

2. The thin-film lithium niobate low-loss waveguide based on hybrid etching process according to claim 1, characterized in that, In the hybrid etching process: the etching depth of the ridge region is 200–300 nm, the etching depth of the planar region is 100–200 nm, and the width of the ridge region is 1.0–1.5 μm.

3. The thin-film lithium niobate low-loss waveguide based on hybrid etching process according to claim 1, characterized in that, The width of the bus waveguide is 500–700 nm, the width of the access waveguide is 300–500 nm, and the spacing between the bus waveguide and the access waveguide is 400–600 nm.

4. The thin-film lithium niobate low-loss waveguide based on hybrid etching process according to claim 1, characterized in that, The input and output ends of the dual waveguide structure are provided with an adiabatic conical transition structure as a toe-cutting structure. The length of the toe-cutting structure is 25–50 μm, which is used to suppress spectral sidelobe oscillations.

5. The thin-film lithium niobate low-loss waveguide based on hybrid etching process according to claim 1, characterized in that, The thickness of the thermoelectric heating layer is 50-200nm, and it is patterned and covers the area directly above the sidewall grating region.

6. The thin-film lithium niobate low-loss waveguide based on hybrid etching process according to claim 1, characterized in that, The Ag 4-x TeS (x=0-0.05)-based thermoelectric materials are amorphous materials.

7. The thin-film lithium niobate low-loss waveguide based on hybrid etching process according to claim 1, characterized in that, The two ends of the sidewall grating are provided with anti-reflection grating structures. The period of the anti-reflection grating structures is different from that of the sidewall grating, and they are used to suppress waveguide self-reflection.

8. A method for fabricating a thin-film lithium niobate low-loss waveguide based on a hybrid etching process, characterized in that, Includes the following steps: Step S1: Provide a Z-cut lithium niobate on insulator wafer, wherein the wafer comprises, from bottom to top, a silicon substrate layer, a silicon dioxide buried oxide layer and a Z-cut thin film lithium niobate layer, and the thickness of the Z-cut thin film lithium niobate layer is 300–600 nm; Step S2: Perform the first photolithography and etching on the surface of the Z-cut thin film lithium niobate layer to form the ridge region and sidewall grating of the dual waveguide structure. The etching depth is 200–300 nm. Step S3: Perform a second photolithography and etching process to form a planar region with a dual waveguide structure, etching down to the buried oxide layer of silicon dioxide, with an etching depth of 100–200 nm; Step S4: Deposit an isolation layer, wherein the isolation layer is silicon dioxide and has a thickness of 100–200 nm; Step S5: Perform a third photolithography on the surface of the isolation layer to define the thermoelectric heating layer pattern; Step S6: Deposit the thermoelectric heating layer material, wherein the thermoelectric heating layer material is Ag. 4-x TeS (x=0-0.05) based thermoelectric materials with a thickness of 50–200 nm are patterned thermoelectric heating layers formed by a peeling process; Step S7: Deposit a protective layer, wherein the protective layer is silicon dioxide and has a thickness of 300–1000 nm; Step S8: Perform the fourth photolithography and etching to open electrode windows in the protective layer and isolation layer to expose the contact area of ​​the thermoelectric heating layer; Step S9: Deposit electrode material to form an electrode system electrically connected to the thermoelectric heating layer through a peeling process; Step S10: Perform annealing treatment at a temperature of 300–400°C for 1–3 hours in a nitrogen or argon atmosphere.

9. The preparation method according to claim 8, characterized in that, In step S6, magnetron sputtering is used to deposit the thermoelectric heating layer under an inert atmosphere with an Ag4TeS alloy target at a substrate temperature ranging from room temperature to 150°C.

10. A reconfigurable photonic integrated circuit, characterized in that, The invention comprises a plurality of thin-film lithium niobate low-loss waveguides based on a hybrid etching process as described in any one of claims 1-7, wherein at least one thermoelectric heating layer of the waveguide is configured to independently apply an electrical signal to tune the Bragg wavelength.

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