Dynamic voltage frequency scaling method, device, system, chip and electronic equipment based on multiple power domains

Abstract

This disclosure relates to the field of integrated circuit design technology, specifically to a method, apparatus, system, chip, and electronic device for dynamic voltage and frequency regulation based on multiple power domains. For deterministic services, the system determines the target voltage-frequency combination and regulation method based on the specified functional modules and frequency range, combined with a preset frequency regulation strategy and a frequency-voltage correspondence table. For uncertain services, a timer triggers a periodic interrupt. The low-power management module identifies functional modules whose application scenarios and performance levels do not match based on the performance status parameters and voltage information of functional modules in each power domain. It determines the target voltage-frequency combination and regulation method according to a preset DVFS strategy table, and adjusts the target voltage through the PMIC and the target frequency through the clock reset module according to the corresponding adjustment sequence. This achieves independent, precise, and on-demand dynamic regulation of voltage and frequency under multiple power domains, effectively improving energy efficiency and performance adaptability.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit design technology, and specifically to a method, apparatus, system, chip, and electronic device for dynamic voltage and frequency regulation based on multiple power supply domains. Background Technology

[0002] With the rapid development of microcontroller-based products such as IoT devices, power data acquisition terminals, and personal terminal devices, chip power consumption has become increasingly prominent, severely impacting device battery life and heat dissipation performance. Against this backdrop, DVFS (Dynamic Voltage and Frequency Scaling) technology has emerged. This technology reduces power consumption by adjusting the chip's voltage and frequency in real time, thereby improving device battery life and alleviating some of the problems caused by chip power consumption. However, simple DVFS technology still has many limitations in practical applications and cannot meet the diverse power management needs of different scenarios.

[0003] Traditional chips typically employ fixed voltage and frequency to address varying power demands. This approach lacks flexibility, failing to respond quickly to changes in power requirements, resulting in slow response times. This is particularly problematic in high-performance chip applications, such as high-performance computing chips or AI accelerator chips, where, despite their inherently high power consumption, they require lower power consumption in specific scenarios. The inflexibility of traditional methods severely limits system performance, preventing the full realization of chip capabilities.

[0004] Meanwhile, in multi-processor or multi-core chip applications, the rational allocation of resources and the voltage and frequency adjustment of each processor or core become critical issues. Existing DVFS methods are difficult to effectively solve this problem, as they cannot rationally allocate resources according to the actual working conditions of each processor or core. This results in some processors or cores being overloaded while others are idle, thus limiting system performance and failing to achieve overall performance optimization.

[0005] Furthermore, current power management methods lack adaptability to different application scenarios during voltage and frequency regulation. Different application scenarios have significantly different requirements for power consumption and performance, and existing technologies cannot flexibly adjust to the optimal balance between power consumption and performance, thus failing to meet diverse application needs.

[0006] Therefore, overcoming the problem that existing DVFS technology cannot achieve a dynamic balance between global optimal power consumption and performance in diverse application scenarios due to its rigid adjustment mechanism, lack of multi-core collaboration and scenario adaptability has become an urgent technical challenge. Summary of the Invention

[0007] To address the problems in related technologies, embodiments of this disclosure provide a method, apparatus, system, chip, and electronic device for dynamic voltage and frequency regulation based on multiple power supply domains.

[0008] In a first aspect, this disclosure provides a dynamic voltage and frequency regulation system based on multiple power domains. The dynamic voltage and frequency regulation system includes: a system-on-a-chip (SoC) and a power management chip (PMIC). The SoC includes: a timer, a low-power management module, a clock reset module, and multiple power domains. Each power domain includes a performance monitoring unit, a voltage sensor, and at least one functional module. The functional module in each power domain is connected to a corresponding independently adjustable voltage output interface of the PMIC and a corresponding independently adjustable frequency output interface of the clock reset module to receive independent voltage and clock signals. Each functional module includes a processor or controller. The timer is connected to the low-power management module, wherein:

[0009] The timer is configured to: generate a first interrupt signal for triggering a dynamic voltage frequency adjustment task based on a preset first trigger period, and send the first interrupt signal to the low power management module. The low-power management module is configured to: respond to a service scheduling event and determine a corresponding voltage and frequency adjustment strategy based on the type of the service to be run, including: when the type of the service is a deterministic service, obtaining the specified functional module executing the service and the specified frequency range of the specified functional module when executing the service, determining whether the current frequency of the specified functional module is within the specified frequency range, and if not, determining the target voltage and frequency combination and the corresponding voltage and frequency adjustment method of the specified functional module based on a preset frequency adjustment strategy, a preset frequency-voltage correspondence table, the specified frequency range, and the current frequency of the specified functional module; wherein, the target voltage and frequency combination includes a target voltage and a target frequency; When the type of the service is an uncertain service, in response to the first interrupt signal, the performance status parameters of the functional modules in the corresponding power domain are obtained based on the performance monitoring unit in each power domain; the current voltage of the functional modules in the corresponding power domain is obtained based on the voltage sensor in each power domain; according to the performance status parameters of the functional modules in the power domain and the corresponding preset discrimination conditions, it is determined whether the application scenario and performance level of the functional modules in the power domain are matched; the functional modules whose application scenario and performance level are not matched are taken as functional modules to be adjusted, and the target voltage-frequency combination and the corresponding voltage-frequency adjustment method of the functional modules to be adjusted are determined according to the application scenario, current frequency, current voltage and preset DVFS strategy table of the functional modules to be adjusted. According to the adjustment sequence indicated by the corresponding voltage and frequency adjustment method, the current voltage of the target functional module is adjusted to the target voltage through the PMIC, and the current frequency of the target functional module is adjusted to the target frequency through the clock reset module; wherein, the target functional module includes: the designated functional module or the functional module to be adjusted.

[0010] Secondly, this disclosure provides a dynamic voltage and frequency adjustment method based on multiple power domains. The dynamic voltage and frequency adjustment method is applied to a System-on-a-Chip (SoC), which includes a timer, a clock reset module, and multiple power domains. Each power domain includes a performance monitoring unit, a voltage sensor, and at least one functional module. Each functional module in each power domain is connected to a corresponding independently adjustable voltage output interface of the PMIC and a corresponding independently adjustable frequency output interface of the clock reset module to receive independent voltage and clock signals. Each functional module includes a processor or controller. The dynamic voltage and frequency adjustment method is used to respond to a service scheduling event and determine a corresponding voltage and frequency adjustment strategy based on the type of service to be run, including: When the service type is a deterministic service, the specified functional module executing the service and the specified frequency range of the specified functional module when executing the service are obtained. It is determined whether the current frequency of the specified functional module is within the specified frequency range. If not, the target voltage-frequency combination and the corresponding voltage-frequency adjustment method of the specified functional module are determined according to the preset frequency adjustment strategy, the preset frequency-voltage correspondence table, the specified frequency range and the current frequency of the specified functional module. The target voltage-frequency combination includes the target voltage and the target frequency. When the type of the service is uncertain, in response to the first interrupt signal, the performance status parameters of the functional modules in the corresponding power domain are obtained based on the performance monitoring unit in each power domain; the current voltage of the functional modules in the corresponding power domain is obtained based on the voltage sensor in each power domain; according to the performance status parameters of the functional modules in the power domain and the corresponding preset discrimination conditions, it is determined whether the application scenario and performance level of the functional modules in the power domain are matched; the functional modules whose application scenario and performance level are not matched are identified as functional modules to be adjusted, and the target voltage-frequency combination and corresponding voltage-frequency adjustment method of the functional modules to be adjusted are determined according to the application scenario, current frequency, current voltage and preset DVFS strategy table; wherein, the first interrupt signal is used to trigger the dynamic voltage-frequency adjustment task, and the first interrupt signal is generated by the timer based on the preset first trigger cycle; According to the adjustment sequence indicated by the corresponding voltage and frequency adjustment method, the current voltage of the target functional module is adjusted to the target voltage through the PMIC, and the current frequency of the target functional module is adjusted to the target frequency through the clock reset module; wherein, the target functional module includes: the designated functional module or the functional module to be adjusted.

[0011] Thirdly, this disclosure provides a dynamic voltage and frequency adjustment device based on multiple power domains. The dynamic voltage and frequency adjustment device is disposed on a System-on-a-Chip (SoC). The SoC includes a timer, a clock reset module, and multiple power domains. Each power domain includes a performance monitoring unit, a voltage sensor, and at least one functional module. The functional module in each power domain is connected to a corresponding independent adjustable voltage output interface of the PMIC and a corresponding independent adjustable frequency output interface of the clock reset module to receive independent voltage and clock signals. Each functional module includes a processor or controller. The dynamic voltage and frequency adjustment device is used to respond to service scheduling events and determine a corresponding voltage and frequency adjustment strategy based on the type of service to be run, including: A deterministic service processing module is configured to: when the service type is deterministic service, obtain the specified functional module executing the service and the specified frequency range of the specified functional module when executing the service, determine whether the current frequency of the specified functional module is within the specified frequency range, and if not, determine the target voltage-frequency combination and the corresponding voltage-frequency adjustment method of the specified functional module according to a preset frequency adjustment strategy, a preset frequency-voltage correspondence table, the specified frequency range and the current frequency of the specified functional module; wherein, the target voltage-frequency combination includes target voltage and target frequency; An uncertain service processing module is configured to: when the service type is uncertain, respond to a first interrupt signal, acquire performance status parameters of the functional modules in the corresponding power domain based on the performance monitoring unit in each power domain; acquire the current voltage of the functional modules in the corresponding power domain based on the voltage sensor in each power domain; determine whether the application scenario and performance level of the functional modules in the power domain match based on the performance status parameters of the functional modules in the power domain and the corresponding preset discrimination conditions; designate functional modules whose application scenario and performance level do not match as functional modules to be adjusted, and determine the target voltage-frequency combination and corresponding voltage-frequency adjustment method of the functional modules to be adjusted based on the application scenario, current frequency, current voltage and preset DVFS strategy table of the functional modules to be adjusted; wherein, the first interrupt signal is used to trigger the dynamic voltage-frequency adjustment task, and the first interrupt signal is generated by the timer based on a preset first trigger cycle; The voltage and frequency adjustment module is configured to: adjust the current voltage of the target functional module to the target voltage through the PMIC according to the adjustment sequence indicated by the corresponding voltage and frequency adjustment method, and adjust the current frequency of the target functional module to the target frequency through the clock reset module; wherein the target functional module includes: the designated functional module or the functional module to be adjusted.

[0012] Fourthly, this disclosure provides a chip including a memory and a processor; the memory is used to store computer instructions, wherein the computer instructions are executed by the processor to implement the dynamic voltage frequency adjustment method as described in the second aspect.

[0013] Fifthly, this disclosure provides an electronic device including the dynamic voltage frequency adjustment system described in the first aspect.

[0014] In a sixth aspect, this disclosure provides a computer-readable storage medium storing computer instructions that, when executed by a processor, implement the dynamic voltage frequency adjustment method described in the second aspect.

[0015] In a seventh aspect, this disclosure provides a computer program product including computer instructions that, when executed by a processor, implement the dynamic voltage frequency adjustment method described in the second aspect.

[0016] According to the technical solution provided in the embodiments of this disclosure, a hierarchical and classified Dynamic Voltage and Frequency Scaling (DVFS) mechanism is proposed for complex SoC systems with heterogeneous multi-core and multi-power domains. The traditional single and reactive DVFS strategy is upgraded into a high-efficiency, intelligent and reliable hybrid intelligent adjustment system that integrates "pre-configuration" and "dynamic perception". Under the premise of meeting the performance requirements of various services in complex SoCs, it realizes independent, accurate and on-demand dynamic adjustment of voltage and frequency under multiple power domains, effectively improving energy efficiency and performance adaptability. It overcomes the problem that existing DVFS technology lacks multi-core collaboration and scenario adaptability due to rigid adjustment mechanism, and achieves a global optimal power consumption and dynamic performance balance in diverse application scenarios.

[0017] On the one hand, this disclosure uses a dual-mode triggering and differentiated DVFS strategy based on service type identification to divide the services to be processed by the SoC into "deterministic services" and "uncertain services," and designs two independent adjustment triggering and decision-making mechanisms for them. For deterministic services, such as encoding and decoding with fixed computational load, the system adopts an event-triggered pre-configuration mode; for uncertain services, such as user interaction and network load, a dynamic monitoring and feedback mode with timer periodic triggering and multi-domain independent monitoring and scenario matching mechanism is adopted. This realizes the intelligence and precision of energy efficiency management strategy, avoids the limitations of a single strategy, ensures the execution efficiency and low latency of predictable tasks, and can flexibly adapt to dynamically changing loads, thereby achieving the optimal energy efficiency balance in complex system scenarios.

[0018] For deterministic services, based on the pre-configured adjustment mechanism, the core of the adjustment logic is to determine whether the current frequency of the specified functional module running the deterministic service is within the corresponding specified frequency range. If not, the adjustment is performed at a fixed point according to the preset frequency adjustment strategy, the preset frequency-voltage correspondence table, the specified frequency range and the current frequency of the specified functional module. This greatly improves the adjustment efficiency and accuracy of known loads, bypasses the complex real-time performance monitoring and analysis process, realizes fast and low-overhead adjustment, effectively eliminates unnecessary performance redundancy reserved for deterministic tasks, and directly reduces static and dynamic power consumption. On the other hand, this disclosure is based on an independent performance monitoring and scenario-based matching diagnosis mechanism for multiple power domains. It integrates a performance monitoring unit and a voltage sensor within each power domain and periodically collects the performance status parameters and voltage data of each power domain through a timer. The system maps real-time performance parameters to specific application scenarios according to preset discrimination conditions and independently judges whether the current performance level of each power domain matches the scenario. This realizes fine-grained, real-time and scenario-based perception of the load status of different functional modules (such as CPU, GPU, etc.) within the chip, solves the problem of coarse management of traditional global DVFS strategy, and provides a reliable data foundation for subsequent differentiated and precise adjustment.

[0019] Furthermore, the physical basis of this disclosed technical solution lies in the SoC's adoption of a multi-power domain design, where each functional module has an independent power rail and clock domain, and is directly connected to the independent voltage output interface of the PMIC and the independent frequency output interface of the clock module, respectively. This provides hardware execution capability for the software strategy in this disclosed solution, ensuring that voltage and frequency adjustment of a certain power domain will not interfere with the normal operation of other domains. This achieves true parallel and fine-grained power management, breaking through the energy efficiency bottleneck caused by traditional single or few power domains, and is the underlying architectural guarantee for achieving optimal chip-level energy efficiency.

[0020] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0021] Other features, objects, and advantages of this disclosure will become more apparent from the following detailed description of non-limiting embodiments, taken in conjunction with the accompanying drawings. In the drawings: Figure 1 A schematic diagram of a dynamic voltage and frequency regulation system based on multiple power supply domains according to an embodiment of the present disclosure is shown. Figure 2 This diagram shows a structural block diagram of a clock reset module according to an embodiment of the present disclosure; Figure 3 This diagram shows a structural block diagram of a frequency modulation control module according to an embodiment of the present disclosure; Figure 4 This diagram shows a structural block diagram of another frequency modulation control module according to an embodiment of the present disclosure; Figure 5 A frequency division diagram of a 2N equal duty cycle frequency division circuit according to an embodiment of the present disclosure is shown; Figure 6 A schematic diagram of a pulse frequency divider circuit according to an embodiment of the present disclosure is shown; Figure 7 This diagram shows a structural connection of a dynamic glitch-free switching selection circuit according to an embodiment of the present disclosure. Figure 8 A flowchart illustrating a method for dynamic voltage frequency regulation based on multiple power supply domains according to an embodiment of the present disclosure is shown. Figure 9 A structural block diagram of a dynamic voltage and frequency regulation device based on multiple power supply domains according to an embodiment of the present disclosure is shown. Figure 10 A structural block diagram of a chip according to an embodiment of the present disclosure is shown. Detailed Implementation

[0022] In the following, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings to enable those skilled in the art to readily implement them. Furthermore, for clarity, portions unrelated to the description of exemplary embodiments have been omitted from the drawings.

[0023] In this disclosure, it should be understood that terms such as “comprising” or “having” are intended to indicate the presence of features, figures, steps, behaviors, components, parts or combinations thereof disclosed in this specification, and are not intended to exclude the possibility of the presence or addition of one or more other features, figures, steps, behaviors, components, parts or combinations thereof.

[0024] It should also be noted that, unless otherwise specified, the embodiments and features described in this disclosure can be combined with each other. This disclosure will now be described in detail with reference to the accompanying drawings and embodiments.

[0025] In this disclosure, any operation involving the acquisition of user information or user data, or the display of user information or user data to others, is an operation authorized or confirmed by the user, or actively selected by the user.

[0026] As mentioned earlier, existing DVFS technology is unable to achieve a dynamic balance between global optimal power consumption and performance in diverse application scenarios due to its rigid adjustment mechanism, lack of multi-core collaboration, and scenario adaptability.

[0027] To overcome the limitations of existing DVFS technology and achieve a globally optimal dynamic balance between power consumption and performance in diverse application scenarios, this disclosure constructs a closed-loop dynamic voltage and frequency regulation system based on "sensing-diagnosis-strategy-execution" and applies it to the energy efficiency management of multi-power domain SoCs. "Sensing" is achieved through performance monitoring units, voltage sensors, and temperature sensors to realize fine-grained state perception at the domain level; "diagnosis" is achieved through intelligent diagnosis of regulation nodes by classifying services and matching application scenarios; "strategy" is achieved by querying preset strategy tables and corresponding tables to form customized voltage and frequency adjustment strategies for each domain; and "execution" is achieved through independently controlled hardware channels to independently execute adjustments in each power domain requiring adjustment. This enables independent, precise, and on-demand dynamic adjustment of voltage and frequency across multiple power domains, effectively improving energy efficiency and performance adaptability. It overcomes the problems of existing DVFS technology, which lacks multi-core collaboration and scenario adaptability due to rigid regulation mechanisms, and achieves a globally optimal dynamic balance between power consumption and performance in diverse application scenarios.

[0028] The dynamic voltage and frequency adjustment system provided in this disclosure includes: a System-on-Chip (SoC) and a Power Management Chip (PMIC); the SoC includes: a timer, a low-power management module, a clock reset module, and multiple power domains. Each power domain includes a performance monitoring unit, a voltage sensor, and at least one functional module. The PMIC is an external power supply chip of the SoC and is the execution unit for dynamic voltage adjustment. The clock reset module outputs the clock for each functional module and is the execution unit for dynamic clock frequency adjustment. The voltage sensor monitors the supply voltage of the functional module in the corresponding power domain, providing real-time feedback for fine voltage adjustment and ensuring the accuracy and safety of dynamic voltage adjustment. Each functional module in each power domain is connected to the corresponding independent adjustable voltage output interface of the PMIC and the corresponding independent adjustable frequency output interface of the clock reset module to receive independent voltage and clock signals. Each functional module includes a processor or controller. The timer is connected to the low-power management module. The low-power management module and the clock reset module communicate via a system bus, as do the low-power management module, the clock reset module, and each power domain. The low-power management module communicates with the PMIC via the system bus and an I2C interface.

[0029] In one implementation of this disclosure, the dynamic voltage and frequency adjustment system further includes: an external memory, such as a DDR chip; the power domain further includes a temperature sensor for monitoring the temperature of the functional modules in the corresponding power domain to prevent data transmission errors or performance degradation due to overheating.

[0030] Figure 1 A schematic diagram of a dynamic voltage and frequency regulation system based on multiple power supply domains according to an embodiment of the present disclosure is shown. Figure 1As shown, the multiple power domains include: a first power domain, a second power domain, a third power domain, and a fourth power domain; the first power domain includes a double data rate DDR controller, and the performance monitoring unit in the first power domain includes a first bandwidth monitoring unit, used to monitor the data read / write bandwidth between the DDR controller and external memory (DDR chips), which is a key indicator for evaluating the load and performance bottlenecks of the storage subsystem; the second power domain includes a central processing unit (CPU), and the performance monitoring unit in the second power domain includes a second bandwidth monitoring unit and a load monitoring unit, wherein the second bandwidth monitoring unit is used to monitor the bandwidth of the CPU accessing memory or other peripherals, and the load monitoring unit is used to monitor the CPU core utilization and instruction throughput. Indicators such as throughput and active cycle percentage are core criteria for judging CPU application scenarios; the third power domain includes the Neural Processing Unit (NPU), and the performance monitoring units in the third power domain include a third bandwidth monitoring unit and a MAC utilization monitoring unit. The third bandwidth monitoring unit monitors the bandwidth of the NPU for reading weights and input data and writing results, while the MAC utilization monitoring unit monitors the actual utilization of the NPU's internal multiply-accumulator array. This is the most direct and effective indicator for evaluating the NPU's computational load, accurately distinguishing different stages of model inference, such as busy computation and data transfer; the fourth power domain includes the Graphics Processing Unit (GPU) and the Data Processing Unit (DPU), or the Data Processing Unit (DPU)... Figure 1 (Taking GPU and DPU as examples for description), the performance monitoring unit in the fourth power domain includes a fourth bandwidth monitoring unit. This fourth bandwidth monitoring unit monitors the data bandwidth shared by the DPU or GPU with the DPU, or externally (e.g., display interfaces, other memory), reflecting the overall data pressure of the rendering pipeline and display processing stages. The external memory is connected to the DDR controller in the first power domain.

[0031] This disclosure equips each power domain with a dedicated voltage sensor, enabling real-time monitoring of the precise voltage values ​​actually obtained by the functional modules within that domain, rather than relying solely on the theoretical output voltage of the power management chip. Due to the impedance of the internal power supply network of the chip, the actual voltage will drop due to changes in current load. Monitoring voltage by power domain ensures that the voltage requirements for circuit operation are always met during dynamic voltage regulation, fundamentally avoiding timing errors or system failures caused by insufficient voltage, and significantly improving the safety and reliability of dynamic regulation. Another key function of the dedicated voltage sensor is to support adaptive voltage regulation. It can compensate for electrical characteristic deviations caused by minor differences in manufacturing processes in different areas within the same chip, allowing the system to independently find and maintain the lowest stable operating voltage for each power domain. This adaptive regulation tailored to the characteristics of the silicon wafer itself can break through the fixed range of a preset voltmeter, achieving additional power consumption optimization while ensuring correct functionality, making energy efficiency management more refined and intelligent.

[0032] This disclosure equips each power domain with a dedicated temperature sensor, enabling precise monitoring and location of localized hotspots on the chip. In modern complex SoCs, different processing units generate significantly different amounts of heat, and uniform temperature measurement across the entire domain cannot reflect the true heat distribution. Local temperature data allows the system to accurately identify overheated areas and implement thermal protection measures such as frequency and voltage reduction only for that specific power domain, while other domains with normal temperatures can continue to operate at high performance, thereby maximizing the preservation of overall computing power while ensuring system safety. The dedicated temperature sensor also provides key environmental parameters for dynamic adjustment decisions. Transistor characteristics are extremely sensitive to temperature, and circuit performance changes at high temperatures. Incorporating real-time temperature data into the DVFS strategy decision allows the system to select operating point combinations with better temperature adaptability. For example, it can use more conservative voltage and frequency settings at high temperatures to ensure stability, or prioritize operating modes with lower heat generation when performance requirements are met, achieving intelligent energy efficiency management based on temperature sensing.

[0033] This disclosure also configures dedicated performance monitoring units for each power domain, enabling direct capture of key indicators that best reflect the core operating status of that domain. For example, it monitors instruction throughput and utilization for the CPU, and the actual operating efficiency of the multiply-accumulator array for the NPU. This customized monitoring avoids misjudgments that may occur when using general or indirect indicators, providing high signal-to-noise ratio first-hand data for scenario identification and load assessment, making energy efficiency decisions more accurate and timely. The dedicated performance monitoring units are typically implemented in hardware, enabling continuous data acquisition with extremely low power consumption, without frequent interruptions to the main processor or the consumption of large computing resources for software analysis. This efficient data acquisition method significantly reduces the operating overhead of the dynamic adjustment system itself, allowing for refined energy efficiency management to be carried out in real time and without interruption, thereby ensuring the overall efficiency of the system in pursuing high performance and low power consumption goals.

[0034] When a SoC includes both a GPU and a DPU, this disclosure places them in the same power domain for coordinated voltage and frequency regulation, based on the inherent continuity of display processing operations. Since the GPU (responsible for graphics rendering) and the DPU (responsible for display post-processing and output) are strongly dependent and execute sequentially in the display pipeline, their loads are typically linearly coupled or highly correlated; that is, when the GPU's rendering task is heavy, the DPU's subsequent data processing volume is also large, and vice versa. Placing them in the same power domain allows the system to treat them as a single "display processing unit" for overall control. When display performance needs to be improved, the voltage and frequency of both are increased simultaneously; when the load decreases, the voltage and frequency of both are decreased simultaneously. This avoids the efficiency imbalance and energy waste that can occur with independent domain regulation, such as "the GPU is upclocked and ready, but the DPU is still running at a low frequency causing data congestion" or "the GPU is downclocked to save energy, but the DPU is still idling at a high frequency," thus achieving optimal energy efficiency for the entire display pipeline. Meanwhile, a shared power domain means that the GPU and DPU can share the same set of voltage regulators (an interface from the PMIC) and clock generation / distribution network, which simplifies the design of the power grid and clock tree inside the chip, reduces the number of independent output channels required by the power management chip, thereby reducing chip design complexity, saving silicon area, and reducing overall system cost.

[0035] In addition, to independently adjust the voltage frequency of functional modules in each power domain, the PMIC in this disclosure provides a dedicated, independently adjustable voltage output interface for each power domain, such as... Figure 1 As shown, the PMIC outputs power_ddr, power_apcpu, power_npu, and power_gpu voltage signals to the first, second, third, and fourth power domains respectively through corresponding independent adjustable voltage output interfaces. This means that the supply voltage of each power domain is physically separated and can be adjusted independently. For example, when the NPU requires high voltage to perform high-load AI inference, the PMIC can increase the output of power_npu individually, while the CPU may be in an idle state, and the PMIC can reduce its power_apcpu voltage to a minimum to save energy. This architecture completely solves the energy waste problem of "one core boosting, all cores boosting" in traditional shared power rails, providing a hardware foundation for the most precise energy consumption control.

[0036] Meanwhile, the clock reset module provides a dedicated, independently adjustable clock output interface for each power domain. For example... Figure 1As shown, the clock reset module outputs ddr_clk, apcpu_clk, npu_clk, and gpu_clk clock signals to the first, second, third, and fourth power domains respectively through corresponding independent adjustable frequency output interfaces. This means that the operating frequency of each power domain can be set and dynamically adjusted independently. For example, when a high screen refresh rate is required, the system can increase the frequency of gpu_clk to enhance GPU rendering capabilities, while the NPU's npu_clk frequency can be kept at a lower level. The clock tree of each domain is independent, and adjusting the frequency of one domain will not affect the timing stability of other domains, achieving true parallel performance scheduling.

[0037] The following is a detailed description of each module in the dynamic voltage and frequency regulation system disclosed herein.

[0038] According to an embodiment of this disclosure, the timer is configured to: generate a first interrupt signal for triggering a dynamic voltage frequency adjustment task based on a preset first trigger period, and send the first interrupt signal to the low power management module; generate a second interrupt signal for triggering a dynamic voltage frequency adjustment task based on a preset second trigger period, and send the second interrupt signal to the low power management module.

[0039] The first and second trigger cycles can be flexibly set according to the specific implementation. For example, the first trigger cycle can be set to 500ms, then an interrupt will be generated every 500ms, thereby activating the corresponding DVFS task.

[0040] The low-power management module is configured to: in response to a service scheduling event, determine the corresponding voltage and frequency adjustment strategy based on the type of service to be run.

[0041] A service scheduling event is a system event triggered by software or hardware, signifying that a new computing task is about to begin consuming processor resources. It does not refer to the entire execution process of a task, but specifically to the critical moment when task execution rights switch. The trigger source can be software-initiated, i.e., an application starts a new task or explicitly requests a task switch through system calls (such as fork, exec, or specific performance mode setting APIs). It can also be triggered by hardware interrupts, i.e., timer interrupts (time slice exhaustion), external I / O interrupts (data arrival), etc., causing the scheduler to be invoked, which may trigger a task switch. The service scheduling event is the "trigger" that initiates the decision-making process of the low-power management module, indicating that the system's workload characteristics may be about to change, thus requiring a re-evaluation and setting of the voltage and frequency strategy to meet the needs of the new task. At the moment the "service scheduling event" occurs, the low-power management module analyzes the new task and customizes a corresponding voltage and frequency adjustment scheme for it.

[0042] This disclosure defines two types of tasks: deterministic tasks and non-deterministic tasks. Deterministic tasks refer to those whose performance requirements (computational load, deadline) are predictable before execution or specified by the software. For example, decoding a video stream at a specific bitrate or completing a periodic real-time control calculation allows the software to know in advance the required Fmin (the minimum frequency to guarantee correctness) and Fmax (the maximum or optimal frequency allowed). Non-deterministic tasks refer to complex tasks whose performance requirements cannot be predicted in advance and change dynamically with user interaction or external events. Examples include web browsing, graphical interface operation, and general computing tasks. During the discrimination process, the scheduler or the task itself can pass a deterministic tag and Fmin / Fmax values ​​to the low-power management module through specific registers or APIs, or infer based on the task's origin (such as whether it is triggered by a periodic timer) or historical behavior patterns.

[0043] Specifically, determining the corresponding voltage frequency adjustment strategy based on the type of service to be operated includes: When the type of the service is a deterministic service, the specified functional module that executes the service and the specified frequency range of the specified functional module when executing the service are obtained. It is determined whether the current frequency of the specified functional module is within the specified frequency range. If not, the target voltage-frequency combination and the corresponding voltage-frequency adjustment method of the specified functional module are determined according to the preset frequency adjustment strategy, the preset frequency-voltage correspondence table, the specified frequency range and the current frequency of the specified functional module. The target voltage-frequency combination includes the target voltage and the target frequency.

[0044] In this disclosure, for deterministic tasks, a preset target range control strategy is adopted, namely: the goal of voltage frequency adjustment is to ensure that the operating frequency of the functional module performing the service is always kept within the specified range of [Fmin, Fmax]. If the current operating frequency is not within this range, the corresponding adjustment operation is performed.

[0045] According to embodiments of this disclosure, the preset frequency-voltage correspondence table includes multiple frequency-voltage pairs, each frequency-voltage pair containing a frequency and a voltage corresponding to that frequency. The preset frequency adjustment strategy includes a first preset frequency adjustment strategy and a second preset frequency adjustment strategy. Determining the target voltage-frequency combination and corresponding voltage-frequency adjustment method for the specified functional module based on the preset frequency adjustment strategy, the preset frequency-voltage correspondence table, the specified frequency range, and the current frequency of the specified functional module includes: If the current frequency of the specified functional module is less than the lowest specified frequency in the specified frequency range, and the voltage frequency adjustment method corresponding to the specified functional module is a boost frequency adjustment method, then: the target frequency of the specified functional module is obtained according to the first preset frequency adjustment strategy and the current frequency of the specified functional module; the target voltage of the specified functional module is obtained according to the target frequency of the specified functional module and the preset frequency-voltage correspondence table.

[0046] If the current frequency of the specified functional module is greater than the highest specified frequency in the specified frequency range, and the voltage frequency adjustment method corresponding to the specified functional module is a frequency reduction and voltage reduction adjustment method, then: the target frequency of the specified functional module is obtained according to the second preset frequency adjustment strategy and the current frequency of the specified functional module; the target voltage of the specified functional module is obtained according to the target frequency of the specified functional module and the preset frequency-voltage correspondence table.

[0047] The core design principle of the preset frequency-voltage correspondence table in this disclosure is to pre-calibrate a minimum voltage that ensures stable operation of the chip at each available operating frequency. The first preset frequency adjustment strategy guides how to increase the frequency, for example, by adding an increase step size (e.g., 200MHz) to the current frequency, then comparing it with the lowest specified frequency, and taking the larger of the two as the target frequency. The second preset frequency adjustment strategy guides how to decrease the frequency, for example, by subtracting a decrease step size (e.g., 300MHz) from the current frequency, then comparing it with the highest specified frequency, and taking the smaller of the two as the target frequency. After determining the target frequency, the target voltage corresponding to that target frequency can be obtained based on the preset frequency-voltage correspondence table.

[0048] When the type of the service is an uncertain service, in response to the first interrupt signal, the performance status parameters of the functional modules in the corresponding power domain are obtained based on the performance monitoring unit in each power domain; the current voltage of the functional modules in the corresponding power domain is obtained based on the voltage sensor in each power domain; according to the performance status parameters of the functional modules in the power domain and the corresponding preset discrimination conditions, it is determined whether the application scenario and performance level of the functional modules in the power domain are matched; the functional modules whose application scenario and performance level are not matched are taken as functional modules to be adjusted, and the target voltage-frequency combination and the corresponding voltage-frequency adjustment method of the functional modules to be adjusted are determined according to the application scenario, current frequency, current voltage and preset DVFS strategy table of the functional modules to be adjusted.

[0049] Specifically, the application scenarios include, but are not limited to, low-load and high-load scenarios. Low-load scenarios refer to situations where the actual performance requirements of functional modules (such as DDR controllers, CPUs, NPUs, etc.) are far lower than the maximum capacity provided by their current configuration. The system exhibits significant performance redundancy. In this state, the dynamic power consumption of functional modules (proportional to the square of voltage and frequency) consumes unnecessary energy, while the proportion of static power consumption increases relatively, resulting in a very low overall energy efficiency. High-load scenarios refer to situations where the actual performance requirements of functional modules are close to or have reached the performance limit provided by their current configuration. The system performance experiences bottlenecks or faces pressure. In this state, functional modules may experience task processing delays, frame rate drops, and slower response times due to insufficient performance. Simultaneously, the chip temperature will rise rapidly due to continuous operation under high load.

[0050] According to embodiments of this disclosure, determining whether the application scenario and performance level of the functional module in the power domain match based on the performance status parameters of the functional module in the power domain and the corresponding preset discrimination conditions includes: For example Figure 1 Taking the system architecture shown as an example, for the DDR controller, the performance status parameters include the bandwidth parameters of the DDR controller obtained through the first bandwidth monitoring unit. If the bandwidth parameters of the DDR controller are all lower than the first preset low bandwidth threshold within a preset time period, it indicates that the data throughput demand is very low, and the current high voltage and high frequency configuration is wasted. In this case, it is determined that the application scenario and performance level of the DDR controller are mismatched, and the DDR controller is currently in a low load scenario. If the bandwidth parameters are all higher than the first preset high bandwidth threshold within a preset time period, it indicates that the data throughput demand is huge, and the current performance configuration may become a bottleneck, causing task delays. In this case, it is determined that the application scenario and performance level of the DDR controller are mismatched, and the DDR controller is currently in a high load scenario.

[0051] For the CPU, the performance status parameters include the CPU bandwidth parameters obtained through the second bandwidth monitoring unit and the CPU utilization rate obtained through the load monitoring unit. If the CPU utilization rate is lower than a preset low CPU utilization threshold (e.g., 20%) for a preset period of time, it indicates that the computing task is very light and there is no need to maintain the current high performance state. In this case, it is determined that the application scenario and performance level of the CPU are mismatched, and the CPU is currently in a low load scenario. If the CPU utilization rate is higher than a preset high CPU utilization threshold (e.g., 80%) for a preset period of time, or the CPU bandwidth parameters are higher than a second preset high bandwidth threshold for a preset period of time, it indicates that the computing or data access requirements are extremely high, and the current frequency / voltage configuration may not be able to guarantee the timely completion of the task. In this case, it is determined that the application scenario and performance level of the CPU are mismatched, and the CPU is currently in a high load scenario.

[0052] For the NPU, the performance status parameters include the bandwidth parameters of the NPU obtained by the third bandwidth monitoring unit and the MAC utilization of the NPU obtained by the MAC utilization monitoring unit. If the MAC utilization is lower than a preset low threshold for a preset period of time, it indicates that the neural network computing unit is in a lightly used or idle state, and it is determined that the application scenario and performance level of the NPU are mismatched, and the NPU is currently in a low-load scenario. If the MAC utilization is higher than a preset high threshold for a preset period of time, or the bandwidth parameters are higher than a third preset high threshold for a preset period of time, it indicates that the neural network computing or data transfer demand is saturated, and it is determined that the application scenario and performance level of the NPU are mismatched, and the NPU is currently in a high-load scenario.

[0053] For the DPU or the DPU and the GPU, the performance status parameters include the bandwidth parameters of the DPU or the DPU and the GPU obtained by the fourth bandwidth monitoring unit. If the bandwidth parameters of the DPU or the DPU and the GPU are all lower than the fourth preset low bandwidth threshold within a preset time period, it is determined that the application scenario and performance level of the DPU or the DPU and the GPU are currently in a low-load scenario. If the bandwidth parameters of the DPU or the DPU and the GPU are all higher than the fourth preset high bandwidth threshold within a preset time period, it is determined that the application scenario and performance level of the DPU or the DPU and the GPU are currently in a high-load scenario.

[0054] Specifically, the preset DVFS strategy table is used to describe multiple performance level voltage-frequency pairs. Each performance level voltage-frequency pair contains a performance level and a corresponding voltage and frequency. The step of determining the target voltage-frequency combination and corresponding voltage-frequency adjustment method for the functional module to be adjusted based on the current application scenario, current frequency, current voltage, and the preset DVFS strategy table includes: The current performance level of the functional module to be adjusted is determined based on its current frequency and current voltage, as well as the preset DVFS strategy table.

[0055] If the functional module to be adjusted is currently in a low-load scenario, and the voltage and frequency adjustment method corresponding to the functional module to be adjusted is a frequency reduction and voltage reduction adjustment method, then: from the preset DVFS strategy table, select the voltage and frequency corresponding to the performance level that is one or more levels lower than the current performance level, as the target voltage and the target frequency.

[0056] If the functional module to be adjusted is currently in a high-load scenario, and the voltage and frequency adjustment method corresponding to the functional module to be adjusted is a boost and frequency adjustment method, then: select the voltage and frequency corresponding to the performance level that is one or more levels higher than the current performance level from the preset DVFS strategy table, as the target voltage and the target frequency.

[0057] In practice, the CPU utilization level can be dynamically adjusted based on the load level. For example, when the CPU utilization is below 10%, the CPU utilization level can be reduced by 2 levels, and when it is between 10% and 20%, the CPU utilization level can be reduced by 1 level.

[0058] The pre-defined DVFS strategy table predefines several discrete performance levels for each functional module, with each performance level specifying its operating frequency and corresponding core voltage. Due to significant differences in circuit structure, process characteristics, and power consumption models among different functional modules, a voltage-frequency point optimized for the CPU may be in an inefficient region for the GPU (too high a voltage or too low a frequency), resulting in energy waste or performance loss. Therefore, this disclosure accepts and utilizes the physical and functional asymmetry of heterogeneous computing units within the chip, defining an independent pre-defined frequency-voltage correspondence table and DVFS strategy table for each functional module. Compared to a scheme where all functional modules share the same set of tables, this allows each module to operate on its own optimal energy efficiency curve, thereby significantly improving the overall energy efficiency ratio at the system level, extending device battery life, and achieving refined module-level energy efficiency management.

[0059] Table 1 shows a preset DVFS strategy table corresponding to the CPU functional module in one implementation of this disclosure.

[0060] Table 1 Preset DVFS Strategy Table

[0061] As shown in Table 1, the high-performance mode is for scenarios that require the maximum computing power; the balanced mode achieves a balance between performance and power consumption and is suitable for daily tasks; the energy-saving mode and the low-power mode are used for background, light load, or scenarios with high battery life requirements.

[0062] In addition to providing the above-described scheme for dynamic voltage and frequency adjustment based on service type, this disclosure also introduces an emergency temperature control mechanism into the DVFS system. It runs in parallel with the conventional service type-based DVFS and uses interrupt triggering to quickly intervene in overheated or overcooled functional modules.

[0063] According to an embodiment of this disclosure, in response to the second interrupt signal, the current temperature of the functional module in the corresponding power domain is obtained based on the temperature sensor in each power domain; based on the current temperature of the functional module in each power domain and a preset normal temperature range, it is determined whether the current temperature of the functional module in each power domain is within the preset normal temperature range; functional modules whose current temperature is not within the preset normal temperature range are identified as functional modules to be adjusted; and based on a preset temperature control strategy, a preset temperature-frequency-voltage correspondence table, and the current temperature of the functional module to be adjusted, the target voltage-frequency combination and the corresponding voltage-frequency adjustment method of the functional module to be adjusted are determined.

[0064] The preset normal temperature range is a safe operating range that is wider than the emergency threshold but more conservative than the module's absolute maximum rating. If the current temperature is within the preset normal temperature range, the temperature is normal and no dynamic voltage frequency adjustment is performed.

[0065] According to embodiments of this disclosure, a preset temperature-frequency-voltage correspondence table contains multiple temperature-voltage-frequency pairs, each containing a temperature value and a corresponding voltage and frequency. The step of determining the target voltage-frequency combination and corresponding voltage-frequency adjustment method for the functional module to be adjusted based on a preset temperature control strategy, the preset temperature-frequency-voltage correspondence table, and the current temperature of the functional module to be adjusted includes: If the current temperature of the functional module to be adjusted is greater than the highest temperature value of the preset normal temperature range, and the voltage frequency adjustment method corresponding to the functional module to be adjusted is the frequency reduction and voltage reduction adjustment method, then: from the preset temperature frequency voltage correspondence table, select the voltage and frequency corresponding to the temperature value that is one or more levels lower than the current temperature, as the target voltage and the target frequency. If the current temperature of the functional module to be adjusted is less than the lowest temperature value of the preset normal temperature range, and the voltage and frequency adjustment method corresponding to the functional module to be adjusted is the boost and frequency adjustment method, then: from the preset temperature-frequency-voltage correspondence table, select the voltage and frequency corresponding to the temperature value that is one or more levels higher than the current temperature, as the target voltage and the target frequency.

[0066] This disclosure, based on the aforementioned emergency temperature control mechanism, achieves millisecond-level real-time monitoring and response to chip overheating risks. It effectively prevents device performance degradation, accelerated circuit aging, and even permanent damage caused by instantaneous heat accumulation, thereby significantly improving system reliability and long-term operational stability. Simultaneously, this mechanism uses a preset temperature-frequency-voltage correspondence table for precise control, intelligently balancing frequency reduction and performance maintenance while meeting stringent thermal constraints. This avoids the abrupt, one-size-fits-all frequency reduction or system shutdown common in traditional temperature control solutions, ensuring a continuous user experience and the device's ability to operate continuously in high-temperature environments.

[0067] After obtaining the target voltage-frequency combination and corresponding voltage-frequency adjustment method of the functional module to be adjusted based on the above scheme, the current voltage of the target functional module is adjusted to the target voltage through the PMIC according to the adjustment sequence indicated by the corresponding voltage-frequency adjustment method, and the current frequency of the target functional module is adjusted to the target frequency through the clock reset module; wherein, the target functional module includes: the designated functional module or the functional module to be adjusted.

[0068] The voltage and frequency adjustment methods include: a boost and frequency adjustment method or a frequency and voltage reduction adjustment method. The adjustment sequence indicated by the boost and frequency adjustment method includes: dynamic voltage and frequency adjustment in the order of first increasing the voltage and then increasing the frequency. The adjustment sequence indicated by the frequency and voltage reduction adjustment method includes: dynamic voltage and frequency adjustment in the order of first decreasing the frequency and then decreasing the voltage.

[0069] When performing dynamic voltage and frequency regulation, this disclosure follows strict hardware timing. According to embodiments of this disclosure, adjusting the current voltage of the target functional module to the target voltage via the PMIC and adjusting the current frequency of the target functional module to the target frequency via the clock reset module, according to the adjustment sequence indicated by the corresponding voltage and frequency regulation method, includes: When the voltage and frequency adjustment method is a boost and boost adjustment method, the current voltage of the target functional module is first adjusted to the target voltage through the PMIC, and then the current frequency of the target functional module is adjusted to the target frequency through the clock reset module; when the voltage and frequency adjustment method is a down-frequency and down-voltage adjustment method, the current frequency of the target functional module is first adjusted to the target frequency through the clock reset module, and then the current voltage of the target functional module is adjusted to the target voltage through the PMIC.

[0070] Dynamic voltage adjustment is achieved through a PMIC. According to embodiments of this disclosure, adjusting the current voltage of the target functional module to the target voltage via the PMIC includes: The low-power management module sends the target voltage of the target functional module to the PMIC via the system bus and I2C interface. The PMIC adjusts the voltage signal output to the target functional module through the corresponding independent adjustable voltage output interface based on the target voltage of the target functional module and a preset voltage adjustment step size. The PMIC writes the intermediate voltage value calculated based on the preset voltage adjustment step size to the corresponding independent adjustable voltage output interface register. When the low-power management module determines that the intermediate voltage value in the independent adjustable voltage output interface register is consistent with the target voltage, it obtains the current voltage of the target functional module through the voltage sensor in the power domain corresponding to the target functional module. If the obtained current voltage of the target functional module is consistent with the target voltage, the voltage adjustment is determined to be complete.

[0071] The dynamic voltage adjustment scheme provided in this disclosure breaks the simple open-loop mode of "sending the target voltage command is considered as completion" in the traditional DVFS. Its core inventive concept is to construct a four-level closed-loop control process of "command sending - step execution - digital verification - physical verification", and realize the controllability and reliability of the voltage adjustment process through software and hardware collaboration.

[0072] In one implementation of this disclosure, when executing the instruction transmission, the low-power management module encapsulates the power rail identifier (e.g., VDD_CPU) of the target functional module and the target voltage value into a command data packet conforming to the PMIC register read / write format. This data packet is then transmitted to the SoC's I2C controller via the system bus. The I2C controller, acting as the master device, initiates communication with the PMIC. According to the I2C protocol, the PMIC device address is sent first, followed by the PMIC internal register address corresponding to the target voltage and the target voltage value. During step voltage regulation, the PMIC internally predefines a safe voltage regulation step size for each adjustable power rail, avoiding voltage abrupt changes and reducing inrush current. After completing one step adjustment, the current register value is written back to its status register for the host to read. Simultaneously with the PMIC's step voltage regulation, the low-power management module polls the PMIC's status register via I2C, reads the written-back voltage value from the register, and compares it with the initially sent target voltage value, until the current voltage of the target functional module is gradually adjusted to the target voltage value. Finally, after the voltage boost is complete, the voltage collected by the voltage sensor is read again to determine if it is the same as the target voltage. A reverse redundancy correction is then performed to make the DVFS process more reliable and stable. If the voltage collected by the voltage sensor differs from the target voltage, it may be due to other anomalies, requiring reporting and handling of the anomaly.

[0073] In the above-disclosed scheme, the PMIC does not directly jump to the target voltage, but gradually approaches it according to a preset safety step size. It actively decouples a drastic voltage jump into a series of smooth micro-steps, avoiding excessive current changes caused by instantaneous large voltage jumps. This effectively prevents hardware damage risks such as circuit latch-up, timing violations, or even device breakdown caused by power rail collapse or overshoot.

[0074] Dynamic frequency adjustment is achieved through a clock reset module. Adjusting the current frequency of the target functional module to the target frequency via the clock reset module includes: The low-power management module generates corresponding frequency adjustment parameters based on the target frequency of the target functional module, and sends the frequency adjustment parameters to the clock reset module through the system bus. The clock reset module generates a clock signal corresponding to the target frequency according to the frequency adjustment parameters, and outputs the generated clock signal to the target functional module through the corresponding independent adjustable frequency output interface.

[0075] This disclosure provides two specific dynamic frequency adjustment schemes: Scheme 1 and Scheme 2, wherein: In Scheme 1, the low-power management module generates corresponding frequency adjustment parameters based on the target frequency of the target functional module, including: acquiring historical frequency switching records of the target functional module, the historical frequency switching records including at least one actual switching duration and stable load rate after switching from the current frequency of the target functional module to a specified frequency; calculating a predicted optimized switching path based on the historical frequency switching records, the current frequency of the target functional module, the target frequency, and a preset frequency switching model, the optimized switching path indicating one or more intermediate frequencies from the current frequency of the target functional module to the target frequency and the expected dwell time of each intermediate frequency; converting the optimized switching path into the frequency adjustment parameters, the frequency adjustment parameters being used to instruct the clock reset module to adjust the clock signal output to the target functional module step by step according to the optimized switching path.

[0076] The clock reset module includes multiple frequency modulation control modules, which are connected to the multiple power domains through corresponding independent adjustable frequency output interfaces. Each frequency modulation control module is used to control the clock signal output to the functional module in the corresponding power domain.

[0077] Figure 2 A structural block diagram of a clock reset module according to an embodiment of the present disclosure is shown. Figure 2 As shown, the clock reset module includes: a DDR frequency modulation control module, a CPU frequency modulation control module, an NPU frequency modulation control module, and a GPU frequency modulation control module. The DDR frequency modulation control module is connected to the DDR controller in the first power domain through a corresponding independent adjustable frequency output interface. The CPU frequency modulation control module is connected to the CPU in the second power domain through a corresponding independent adjustable frequency output interface. The NPU frequency modulation control module is connected to the NPU in the third power domain through a corresponding independent adjustable frequency output interface. The GPU frequency modulation control module is connected to the GPU and DPU in the fourth power domain through a corresponding independent adjustable frequency output interface.

[0078] Figure 3 A structural block diagram of a frequency modulation control module according to an embodiment of the present disclosure is shown. Figure 3 As shown, in Scheme 1, the frequency modulation control module includes: a path execution controller, a timing control module, and a clock signal generation module.

[0079] The path execution controller is configured to: receive frequency adjustment parameters of the target functional module from the low-power management module, decode the frequency adjustment parameters, and obtain multiple matching pairs containing intermediate frequencies and expected dwell times, as well as the execution order of each matching pair.

[0080] The timing control module is configured to: send the intermediate frequency of the current matching pair to the clock signal generation module according to the execution order of each matching pair; after the expected dwell time of the current matching pair is reached, send the intermediate frequency of the next matching pair to the clock signal generation module, until the intermediate frequency of each matching pair is sent to the clock signal generation module.

[0081] The clock signal generation module is configured to generate a corresponding clock signal based on the received intermediate frequency and send it to the target functional module through a corresponding independent adjustable frequency output interface.

[0082] In Scheme 1, the frequency adjustment parameter is transformed from a single target frequency value to an "optimized switching path" that includes multiple intermediate frequencies and dwell times. Its core beneficial technical effects are as follows: by introducing a progressive frequency adjustment trajectory generated based on historical switching performance data prediction, it can effectively smooth out the instantaneous current surges and power supply noise caused by frequency step switching, thereby significantly improving the stability and signal integrity of the chip power supply network and reducing the risk of timing violations. At the same time, this path planning allows the clock generation module and voltage regulator to work more finely together, reducing energy loss during the switching transient process, and can adaptively optimize the switching speed according to the load response characteristics. While ensuring rapid response to user operation and task requirements, it achieves further improvement in the overall energy efficiency and thermal stability of the system.

[0083] In Scheme 2, the frequency adjustment parameters include: a first frequency division coefficient, a second frequency division coefficient, and clock switching parameters; furthermore, the structure of the frequency modulation control module is completely different from that in Scheme 2. Figure 4 A structural block diagram of another frequency modulation control module according to an embodiment of the present disclosure is shown. Figure 4 As shown, unlike Scheme 1, the frequency modulation control module includes two frequency modulation control sub-modules and a dynamic glitch-free switching selection circuit. The output terminal of each frequency modulation control sub-module is connected to the corresponding input terminal of the dynamic glitch-free switching selection circuit. The frequency modulation control sub-module includes a PLL circuit, a 2N duty cycle frequency division circuit, and a pulse frequency division circuit connected in sequence. The PLL circuits of the two frequency modulation control sub-modules are mutually ping-pong; when one PLL circuit is in the working state, the other PLL circuit is in the standby state, and when one PLL circuit is in the standby state, the other PLL circuit is in the working state.

[0084] like Figure 4As shown, the two frequency modulation control submodules include a first frequency modulation control submodule and a second frequency modulation control submodule, wherein the PLL circuit in the first frequency modulation control submodule is a first PLL circuit, and the PLL circuit in the second frequency modulation control submodule is a second PLL circuit.

[0085] According to embodiments of this disclosure, the low-power management module generates corresponding frequency adjustment parameters based on the target frequency of the target functional module, including: Obtain the identifier of the source PLL circuit of the current operating clock of the target functional module; the source PLL circuit refers to the PLL circuit that is currently in operation. Based on the target frequency, the identifier of the source PLL circuit, and a preset PLL frequency configuration table, a preferred PLL configuration scheme for generating the target frequency is determined. The preset PLL frequency configuration table includes a first PLL frequency configuration pair and a second PLL frequency configuration pair. The first PLL frequency configuration pair includes the identifier of the first PLL circuit and the PLL frequency configuration parameters corresponding to the first PLL circuit. The second PLL frequency configuration pair includes the identifier of the second PLL circuit and the PLL frequency configuration parameters corresponding to the second PLL circuit. The preferred PLL configuration scheme includes the identifier of the target PLL circuit and the first and second division coefficients calculated based on the target frequency and the current output frequency of the target PLL circuit. The target PLL circuit is the identifier of the source PLL circuit or another PLL circuit.

[0086] Based on the identifier of the target PLL circuit, the clock switching parameters are generated. The clock switching parameters are used to select the signal output by the frequency modulation control submodule corresponding to the target PLL circuit. If the target PLL circuit is the first PLL circuit, the clock switching parameters are configured as the first clock switching parameters; if the target PLL circuit is the second PLL circuit, the clock switching parameters are configured as the second clock switching parameters. The first frequency division coefficient, the second frequency division coefficient, and the clock switching parameter are encapsulated into the frequency adjustment parameter.

[0087] According to an embodiment of this disclosure, the clock reset module generates a clock signal corresponding to the target frequency based on the frequency adjustment parameters, including: The frequency modulation control submodule corresponding to the target PLL circuit generates a corresponding second-level frequency division signal according to the frequency adjustment parameters, including: generating a corresponding output clock signal based on a reference clock and PLL frequency configuration parameters corresponding to the target PLL circuit; dividing the output clock signal by a power of 2 according to the first division coefficient using a 2N equal duty cycle frequency division circuit in the frequency modulation control submodule corresponding to the target PLL circuit to generate a first-level frequency division signal with equal duty cycle; receiving a preset number of the first-level frequency division signals using a pulse frequency division circuit in the frequency modulation control submodule corresponding to the target PLL circuit, and selecting one or more consecutive first-level frequency division signals as second-level frequency division signals to output to the dynamic glitch-free switching selection circuit according to the second division coefficient.

[0088] In a specific example, N is an integer not greater than 4, and the preset number can be set to 16. Thus, the 2N equal duty cycle frequency divider circuit can achieve equal duty cycles of 1 / 2, 1 / 4, 1 / 8, and 1 / 16, while the pulse frequency divider circuit can achieve frequency divisions from 1 / 16, 2 / 16, 3 / 16 to 16 / 16. Therefore, the clock signal output from the PLL circuit, after being divided by the 2N equal duty cycle frequency divider circuit and the pulse frequency divider circuit, can achieve a maximum division factor of 1 / 256.

[0089] The dynamic glitch-free switching selection circuit, based on the clock switching parameters, uses the second-level frequency division signal output by the pulse frequency division circuit in the frequency modulation control submodule corresponding to the target PLL circuit as the clock signal corresponding to the target frequency. This includes: if the clock switching parameters are the first clock switching parameters, then the second-level frequency division signal output by the first frequency modulation control submodule is output as the clock signal corresponding to the target frequency; if the clock switching parameters are the second clock switching parameters, then the second-level frequency division signal output by the second frequency modulation control submodule is output as the clock signal corresponding to the target frequency.

[0090] In one specific implementation, if the clock switching parameter is the first clock switching parameter and the source PLL circuit is the first PLL circuit, or if the clock switching parameter is the second clock switching parameter and the source PLL circuit is the second PLL circuit, that is, the target PLL circuit is the source PLL circuit, then the current output path remains unchanged, and the second-order frequency division signal output by the frequency modulation control submodule corresponding to the source PLL circuit is output as the clock signal corresponding to the target frequency; if the clock switching parameter is the first clock switching parameter and the source PLL circuit is the second PLL circuit, or if the clock switching parameter is the second clock switching parameter and the source PLL circuit is the first PLL circuit, that is, the target PLL circuit is not the source PLL circuit but another PLL circuit, then the output path is switched from the frequency modulation control submodule corresponding to the source PLL circuit to the frequency modulation control submodule corresponding to the target PLL circuit, and the second-order frequency division signal received after the switch is output as the clock signal corresponding to the target frequency.

[0091] In one implementation of this disclosure, the 2N equal duty cycle frequency division circuit is a fixed frequency division ratio circuit group with multiple-select output, and its core structure consists of the following two parts: 1. Basic Frequency Divider Chain. This chain consists of three cascaded D flip-flops (D-FF). The first-stage D-FF forms a divider by two, with its D input connected to its own inverting output (~Q), triggering a flip on each rising edge of the input clock PLL_OUT. The second-stage D-FF uses the output (Q1) of the first-stage D-FF as its clock input, also connecting its D input to its own ~Q, forming another divider by two. Since the frequency of Q1 is already half of clk, the output (Q2) of this stage has a frequency of 1 / 4 of clk. The third-stage D-FF uses the output (Q2) of the second-stage D-FF as its clock input, connecting its D input to its own ~Q, and its output (Q3) has a frequency of 1 / 8 of clk.

[0092] At this point, the circuit has generated three divided clocks: DIV2_OUT(Q1), DIV4_OUT(Q2), and DIV8_OUT(Q3). Since each D flip-flop toggles once per cycle of its clock, all these divided signals have the same duty cycle (50%).

[0093] 2. Clock Selector (Glitch-Free Switching Circuit). This is a 4-to-1 multiplexer (MUX), but its internal implementation uses glitch-free switching logic instead of a simple digital selector to ensure the continuity of the output clock during switching. The clock selector receives four clock signals: the original input clock PLL_OUT, the divide-by-2 clock DIV2_OUT, the divide-by-4 clock DIV4_OUT, and the divide-by-8 clock DIV8_OUT. The clock selector receives the first division factor at the control terminal to select one of the four inputs as the first-level divided signal output.

[0094] The 2N equal duty cycle frequency divider circuit in this disclosure generates a fixed number of power-of-2 frequency dividers through a hard-wired D flip-flop chain. Then, a multiplexer controlled by the first division factor and equipped with glitch-free switching capability dynamically selects one of them as the output. This achieves coarse-grained but high-quality (equal duty cycle, glitch-free) frequency adjustment of the input clock by dividing it by 1, 2, 4, or 8, providing a stable reference clock for the subsequent pulse frequency divider circuit.

[0095] Figure 5 A frequency division diagram of a 2N equal duty cycle frequency division circuit according to an embodiment of the present disclosure is shown.

[0096] Table 2 shows the correspondence between the first frequency division coefficient and the clock frequency division control.

[0097] Table 2. Correspondence between the first frequency division coefficient and clock frequency division control.

[0098] In one implementation of this disclosure, the pulse frequency divider circuit is a pulse selective output circuit based on a periodic mask, and its core structure consists of the following four main parts: 1. Modulo-16 Counter. This is a 4-bit binary synchronous counter, composed of four D flip-flops and corresponding combinational logic. The modulo-16 counter receives the first-stage divider signal from the previous stage (a 2N duty cycle divider circuit). On the rising edge of each input clock cycle, the counter value cyclically increments from 0 to 15, then returns to 0, repeating the cycle. Its output indicates the current position within a 16-clock-cycle window.

[0099] 2. Frequency divider decoder and clock gating signal generator. This is a combinational logic circuit that receives the current count value from a modulo-16 counter and then generates 16 corresponding clock gating signals in parallel based on each possible count value (1 to 16).

[0100] 3. 16-to-1 Clock Gated Multiplexer. This is a combination of a comparator circuit and a gating circuit. The modulo-16 counter is less than or equal to the second frequency divider (if the second frequency divider is 0, i.e., 4'h0, it passes directly without frequency division), obtaining the gating signal switch. This gating signal switch is logically ANDed with the input original clock to obtain a gated clock signal. This signal is the same as the original clock only in the first N cycles within 16 clock cycles, and remains low in the last (16-N) cycles. The second frequency divider N represents the number of pulses to be output within a 16-cycle window, meaning that within each 16-cycle time window, N complete original clock pulses are allowed to pass, while the remaining (16-N) pulses are blocked.

[0101] 4. Output Selector. This is a glitch-free clock multiplexer. It receives the output from a 16-to-1 clock-gated multiplexer, buffers and shapes it, and outputs a second-order frequency-divided signal. The waveform of the output second-order frequency-divided signal is no longer a constant duty cycle, but a periodic signal composed of N consecutive original clock pulses and (16-N) clock cycles of low-level signals. Its highest frequency component is still F_in, but the duty cycle becomes N / 16. When the second division factor changes, the output selector ensures that the current output clock has been safely turned off before the new mask template is applied to the output, and is turned on after the new template is ready, thus avoiding partial pulses or glitches at the switching point.

[0102] The pulse divider circuit in this disclosure uses a programmable periodic pulse masking mechanism to change the average frequency of the output clock by selectively passing or blocking pulses without altering the original clock period. It provides high-resolution (1 / 16-step) frequency fine-tuning capability, and when combined with the preceding 2N equal duty cycle divider circuit (providing coarse adjustments of 1, 1 / 2, 1 / 4, and 1 / 8), it achieves a wide range of flexible frequency synthesis across multiple levels.

[0103] Figure 6 A schematic diagram of a pulse frequency divider circuit according to an embodiment of the present disclosure is shown.

[0104] Table 3 shows the correspondence between the second frequency division coefficient and the clock frequency division control.

[0105] Table 3. Correspondence between the second frequency division coefficient and the clock frequency division control.

[0106] In one implementation of this disclosure, the dynamic glitch-free switching selection circuit is a synchronous glitch-free clock multiplexer based on a handshake mechanism, which ensures that no glitches are generated in the output when switching clock sources through carefully designed timing logic.

[0107] Figure 7 A structural connection diagram of a dynamic glitch-free switching selection circuit according to an embodiment of the present disclosure is shown. Figure 7 As shown, the core inputs of the circuit are two clock signals that need to be switched: pulse-divided outputs DIVP_OUT1 and DIVP_OUT2 from the two frequency modulation control submodules. The control terminal is the clock switching parameter sel_cfg from the low-power management module. The circuit mainly consists of four functional units. First, there are two clock gating units, each containing an AND gate controlled by enable signals en1 and en2, used to turn the corresponding input clock on or off. Second, there is a crucial synchronization unit, composed of two independent two-stage flip-flop chains, using DIVP_OUT1 and DIVP_OUT2 as clocks respectively, with the sel_cfg signal and its inverted signal as inputs. This unit is responsible for synchronizing the asynchronous switching control signals to their respective clock domains. Third, there is an enable generation and interlocking logic unit, which receives the outputs from the two synchronization chains and generates mutually exclusive enable signals en1 and en2, ensuring that at most one clock is allowed to pass at any given time. Finally, there is an output logic unit, usually an OR gate, which combines the two gated clock signals to generate the final output clock CLK_OUT.

[0108] The dynamic glitch-free switching selection circuit disclosed herein implements glitch-free switching based on a strict timing principle of "safe shutdown first, then synchronous startup." When the system decides to switch from the current clock DIVP_OUT1 to the target clock DIVP_OUT2, the switching parameter sel_cfg changes. This change does not take effect immediately; instead, it first enters the synchronization process. Specifically, the inverted signal of sel_cfg is sent to the synchronization chain with DIVP_OUT2 as the clock. After a delay of two stages of flip-flops, its output acts on the enable generation logic, ultimately pulling the enable signal en1 of the current clock path low. This pull-down action is synchronized with the clock edge of DIVP_OUT2, ensuring that its path is reliably shut off before the next expected pulse of DIVP_OUT1 arrives, thus entering a low-level state after outputting the last complete clock pulse.

[0109] While closing the current path, the original signal of sel_cfg is fed into another synchronization chain clocked by DIVP_OUT1. After a corresponding delay, its output is used to pull the enable signal en2 of the target clock path high. This design introduces a deterministic time window between en1 becoming 0 and en2 becoming 1. Within this window, the AND gate outputs of both clocks are low, resulting in a stable low-level "dead zone" for the final output CLK_OUT. This dead zone completely isolates the direct connection between the two clock sources, which is crucial to avoid any partial pulses or race conditions.

[0110] Finally, once en2 is safely pulled high, the path to the target clock DIVP_OUT2 is opened, and the complete DIVP_OUT2 clock begins to appear at the output. The entire switching process ensures that the control signal edge is aligned with the clock edge through the delay of the synchronization chain, and forces the insertion of a dead time without clock output through interlocking logic, thereby achieving a clean, reliable, and glitch-free clock switching that is transparent to subsequent circuits.

[0111] After completing an adjustment, the system waits for the next trigger cycle to arrive, and then repeats the entire process to achieve dynamic, closed-loop feedback control.

[0112] This embodiment of the disclosure achieves significant performance improvement by employing a dual PLL ping-pong architecture and a dynamic, glitch-free switching mechanism. The specific beneficial effects are as follows: 1. The frequency adjustment range has been expanded, enabling a wider voltage frequency operating range.

[0113] By configuring different PLL frequency configuration parameters for the first and second frequency modulation control submodules based on actual needs, the first and second PLL circuits can operate at different output frequency points. For example, the first PLL circuit can be configured to output a high-frequency clock (e.g., 1.6GHz-2.0GHz), and the second PLL circuit can be configured to output a mid-to-low-frequency clock (e.g., 800MHz-1.2GHz). Through this differentiated configuration, the two PLL circuits can cover complementary frequency ranges, significantly expanding the frequency range supported by the system and avoiding the problem that a single PLL cannot handle both extremely low and extremely high frequencies due to the range limitation of the voltage-controlled oscillator.

[0114] 2. Enables rapid and seamless frequency switching, reducing service latency.

[0115] During dynamic voltage and frequency adjustment, when the target frequency exceeds the available range of the currently operating PLL, or when switching between significantly different frequency ranges is required, the system does not need to wait for the current PLL to relock. Through this mechanism, the low-power management module can generate corresponding clock switching parameters (first or second clock switching parameters) based on the target PLL circuit identifier. The dynamic glitch-free switching selection circuit then completes the switch from the source PLL to the target PLL instantaneously at the clock cycle boundary. This ping-pong operation allows one PLL to be operating while the other can lock to the target frequency in advance, thereby reducing the frequency switching time from microsecond-level PLL relocking time to nanosecond-level clock cycle switching time, significantly reducing the impact of frequency adjustment on service continuity.

[0116] 3. Supports multiple frequency combinations to achieve refined power consumption management.

[0117] The dual PLL architecture, combined with its respective subsequent 2N duty cycle frequency divider and pulse frequency divider circuits, can generate a rich variety of intermediate frequencies. For example, the output of each PLL, after passing through the first-stage 2N frequency divider, can generate multiple coarse frequency tuning points, and then through the second-stage pulse frequency divider circuit, it can achieve fine-grained frequency stepping. This multi-stage frequency divider structure enables the system to provide a variety of fine-grained frequency selections over a wide frequency range. Combined with the intelligent decision-making mechanism based on service type and application scenario in this embodiment, it can provide more accurate voltage-frequency combinations for deterministic and uncertain services, achieving refined power consumption management on demand, and minimizing system power consumption while ensuring performance.

[0118] 4. Improve system stability under high dynamic loads.

[0119] In uncertain business scenarios, the load on functional modules may fluctuate drastically. Through a dual PLL ping-pong switching mechanism, the system can quickly respond to changes in performance status parameters reported by the performance monitoring unit. When a power domain requires a sharp performance boost, it can immediately switch to a pre-locked high-frequency backup PLL; conversely, when the load decreases and rapid frequency reduction is needed for energy saving, it can switch to a low-frequency PLL. This rapid response capability ensures that the system maintains an instantaneous match between performance and power consumption in various application scenarios, avoiding performance bottlenecks or energy waste caused by slow frequency adjustments.

[0120] In summary, the technical solution defined in this disclosure, through the collaborative work of a dual PLL ping-pong architecture and a dynamic glitch-free switching circuit, not only broadens the frequency adjustment range and achieves fast and seamless switching, but also supports fine-grained frequency combinations. Thus, while ensuring high-performance computing requirements, it significantly improves the dynamic power management efficiency and response speed of the system.

[0121] Figure 8 The diagram illustrates a method for dynamic voltage and frequency adjustment based on multiple power domains according to an embodiment of this disclosure. The dynamic voltage and frequency adjustment method is applied to a System-on-Chip (SoC), which includes a timer, a clock reset module, and multiple power domains. Each power domain includes a performance monitoring unit, a voltage sensor, and at least one functional module. Each functional module in each power domain is connected to a corresponding independently adjustable voltage output interface of the PMIC and a corresponding independently adjustable frequency output interface of the clock reset module to receive independent voltage and clock signals. Each functional module includes a processor or controller. The dynamic voltage and frequency adjustment method is used to determine a corresponding voltage and frequency adjustment strategy based on the type of service to be run in response to a service scheduling event, including the following steps S810-S880: In step S810, in response to the service scheduling event, the type of service to be run is determined.

[0122] When the type of the service is deterministic, step S820 is executed; when the type of the service is uncertain, step S850 is executed.

[0123] In step S820, the specified functional module for executing the service and the specified frequency range of the specified functional module when executing the service are obtained.

[0124] In step S830, it is determined whether the current frequency of the specified functional module is within the specified frequency range.

[0125] If not, proceed to step S840.

[0126] In step S840, the target voltage-frequency combination and the corresponding voltage-frequency adjustment method of the specified functional module are determined according to the preset frequency adjustment strategy, the preset frequency-voltage correspondence table, the specified frequency range and the current frequency of the specified functional module; wherein, the target voltage-frequency combination includes the target voltage and the target frequency.

[0127] In step S850, in response to the first interrupt signal, the performance status parameters of the functional modules in the corresponding power domain are obtained based on the performance monitoring unit in each power domain; and the current voltage of the functional modules in the corresponding power domain is obtained based on the voltage sensor in each power domain.

[0128] In step S860, based on the performance status parameters of the functional modules in the power domain and the corresponding preset discrimination conditions, it is determined whether the application scenario and performance level of the functional modules in the power domain are currently matched, and functional modules whose application scenario and performance level are not currently matched are identified as functional modules to be adjusted.

[0129] In step S870, the target voltage-frequency combination and the corresponding voltage-frequency adjustment method of the functional module to be adjusted are determined according to the current application scenario, current frequency, current voltage and preset DVFS strategy table of the functional module to be adjusted; wherein, the first interrupt signal is used to trigger the dynamic voltage-frequency adjustment task, and the first interrupt signal is generated by the timer based on the preset first trigger period.

[0130] In step S880, according to the adjustment sequence indicated by the corresponding voltage frequency adjustment method, the current voltage of the target functional module is adjusted to the target voltage through the PMIC, and the current frequency of the target functional module is adjusted to the target frequency through the clock reset module; wherein, the target functional module includes: the designated functional module or the functional module to be adjusted.

[0131] According to embodiments of this disclosure, the power domain further includes a temperature sensor; the dynamic voltage frequency adjustment method further includes the following steps: In response to the second interrupt signal, the current temperature of the functional module in the corresponding power domain is obtained based on the temperature sensor in each power domain; according to the current temperature of the functional module in each power domain and the preset normal temperature range, it is determined whether the current temperature of the functional module in each power domain is within the preset normal temperature range; functional modules whose current temperature is not within the preset normal temperature range are identified as functional modules to be adjusted; according to the preset temperature control strategy, the preset temperature-frequency-voltage correspondence table, and the current temperature of the functional module to be adjusted, the target voltage-frequency combination and the corresponding voltage-frequency adjustment method of the functional module to be adjusted are determined; wherein, the second interrupt signal is generated by the timer based on the preset second trigger cycle.

[0132] The above steps can be executed in parallel with steps S810~S880.

[0133] According to the technical solution provided in the embodiments of this disclosure, a hierarchical and classified Dynamic Voltage and Frequency Scaling (DVFS) mechanism is proposed for complex SoC systems with heterogeneous multi-core and multi-power domains. The traditional single and reactive DVFS strategy is upgraded into a high-efficiency, intelligent and reliable hybrid intelligent adjustment system that integrates "pre-configuration" and "dynamic perception". Under the premise of meeting the performance requirements of various services in complex SoCs, it realizes independent, accurate and on-demand dynamic adjustment of voltage and frequency under multiple power domains, effectively improving energy efficiency and performance adaptability. It overcomes the problem that existing DVFS technology lacks multi-core collaboration and scenario adaptability due to rigid adjustment mechanism, and achieves a global optimal power consumption and dynamic performance balance in diverse application scenarios.

[0134] Figure 9This diagram illustrates a structural block diagram of a dynamic voltage and frequency adjustment device based on multiple power domains according to an embodiment of the present disclosure. The dynamic voltage and frequency adjustment device 900 is disposed on a System-on-Chip (SoC), which includes a timer, a clock reset module, and multiple power domains. Each power domain includes a performance monitoring unit, a voltage sensor, and at least one functional module. Each functional module in each power domain is connected to a corresponding independently adjustable voltage output interface of the PMIC and a corresponding independently adjustable frequency output interface of the clock reset module to receive independent voltage and clock signals. Each functional module includes a processor or controller. The dynamic voltage and frequency adjustment device is used to determine a corresponding voltage and frequency adjustment strategy based on the type of service to be run in response to a service scheduling event. The dynamic voltage and frequency adjustment device 900 includes: a deterministic service processing module, configured to: when the service type is a deterministic service, acquire a specified functional module executing the service and a specified frequency range of the specified functional module when executing the service, determine whether the current frequency of the specified functional module is within the specified frequency range, and if not, determine the target voltage and frequency combination and the corresponding voltage and frequency adjustment method of the specified functional module according to a preset frequency adjustment strategy, a preset frequency-voltage correspondence table, the specified frequency range and the current frequency of the specified functional module; wherein, the target voltage and frequency combination includes a target voltage and a target frequency; and an uncertain service processing module, configured to: when the service type is an uncertain service, respond to a first interrupt signal, acquire the performance status parameters of the functional modules in the corresponding power domain based on the performance monitoring units in each power domain; acquire the current voltage of the functional modules in the corresponding power domain based on the voltage sensors in each power domain; and determine the target voltage and frequency adjustment method of the functional modules in the power domain based on the performance monitoring units in each power domain. The system uses the performance status parameters of the block and the corresponding preset discrimination conditions to determine whether the application scenario and performance level of the functional module in the power domain match. Functional modules whose application scenario and performance level do not match are designated as functional modules to be adjusted. Based on the application scenario, current frequency, current voltage, and preset DVFS strategy table of the functional module to be adjusted, the system determines the target voltage-frequency combination and the corresponding voltage-frequency adjustment method for the functional module to be adjusted. The first interrupt signal is used to trigger the dynamic voltage-frequency adjustment task, and the first interrupt signal is generated by the timer based on a preset first trigger cycle. The voltage-frequency adjustment module is configured to: adjust the current voltage of the target functional module to the target voltage through the PMIC according to the adjustment sequence indicated by the corresponding voltage-frequency adjustment method, and adjust the current frequency of the target functional module to the target frequency through the clock reset module. The target functional module includes either the specified functional module or the functional module to be adjusted.

[0135] According to embodiments of this disclosure, the power domain further includes a temperature sensor; the dynamic voltage frequency adjustment device further includes a temperature adaptation module, configured to: in response to a second interrupt signal, acquire the current temperature of the functional module in the corresponding power domain based on the temperature sensor in each power domain; determine whether the current temperature of the functional module in each power domain is within the preset normal temperature range based on the current temperature of the functional module in each power domain and a preset normal temperature range; designate functional modules whose current temperature is not within the preset normal temperature range as functional modules to be adjusted; and determine the target voltage frequency combination and corresponding voltage frequency adjustment method of the functional module to be adjusted based on a preset temperature control strategy, a preset temperature frequency voltage correspondence table, and the current temperature of the functional module to be adjusted; wherein, the second interrupt signal is generated by the timer based on a preset second trigger cycle.

[0136] This disclosure also provides a chip, Figure 10 A structural block diagram of a chip according to an embodiment of the present disclosure is shown, such as... Figure 10 As shown, it includes a memory and a processor; wherein the memory is used to store one or more computer instructions, wherein the one or more computer instructions are executed by the processor to implement the dynamic voltage frequency adjustment method as described in any of the above method embodiments.

[0137] This disclosure also provides an electronic device including the dynamic voltage frequency regulation system described in any of the above system embodiments.

[0138] This disclosure also provides a computer-readable storage medium, which may be a computer-readable storage medium included in the electronic device or computer system described in the above embodiments; or it may be a standalone computer-readable storage medium not assembled into a device. The computer-readable storage medium stores one or more programs, which are used by one or more processors to execute the dynamic voltage frequency regulation method described in this disclosure.

[0139] This disclosure also provides a computer program product, including a computer program that, when executed by a processor, implements the dynamic voltage frequency regulation method described in any one of the present disclosures.

[0140] The above description is merely a preferred embodiment of this disclosure and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of the invention involved in this disclosure is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the inventive concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features disclosed in this disclosure that have similar functions.

Claims

1. A dynamic voltage and frequency regulation system based on multiple power supply domains, characterized in that, The dynamic voltage and frequency adjustment system includes: a System-on-Chip (SoC) and a Power Management Chip (PMIC). The SoC includes: a timer, a low-power management module, a clock reset module, and multiple power domains. Each power domain includes a performance monitoring unit, a voltage sensor, and at least one functional module. Each functional module in the power domain is connected to a corresponding independently adjustable voltage output interface of the PMIC and a corresponding independently adjustable frequency output interface of the clock reset module to receive independent voltage and clock signals. Each functional module includes a processor or controller. The timer is connected to the low-power management module. The timer is configured to: generate a first interrupt signal for triggering a dynamic voltage frequency adjustment task based on a preset first trigger period, and send the first interrupt signal to the low power management module. The low-power management module is configured to: respond to a service scheduling event and determine a corresponding voltage and frequency adjustment strategy based on the type of the service to be run, including: when the type of the service is a deterministic service, obtaining the specified functional module executing the service and the specified frequency range of the specified functional module when executing the service, determining whether the current frequency of the specified functional module is within the specified frequency range, and if not, determining the target voltage and frequency combination and the corresponding voltage and frequency adjustment method of the specified functional module based on a preset frequency adjustment strategy, a preset frequency-voltage correspondence table, the specified frequency range, and the current frequency of the specified functional module; wherein, the target voltage and frequency combination includes a target voltage and a target frequency; When the type of the service is an uncertain service, in response to the first interrupt signal, the performance status parameters of the functional modules in the corresponding power domain are obtained based on the performance monitoring unit in each power domain; the current voltage of the functional modules in the corresponding power domain is obtained based on the voltage sensor in each power domain; according to the performance status parameters of the functional modules in the power domain and the corresponding preset discrimination conditions, it is determined whether the application scenario and performance level of the functional modules in the power domain are matched; the functional modules whose application scenario and performance level are not matched are taken as functional modules to be adjusted, and the target voltage-frequency combination and the corresponding voltage-frequency adjustment method of the functional modules to be adjusted are determined according to the application scenario, current frequency, current voltage and preset DVFS strategy table of the functional modules to be adjusted. According to the adjustment sequence indicated by the corresponding voltage and frequency adjustment method, the current voltage of the target functional module is adjusted to the target voltage through the PMIC, and the current frequency of the target functional module is adjusted to the target frequency through the clock reset module; wherein, the target functional module includes: the designated functional module or the functional module to be adjusted.

2. The dynamic voltage and frequency regulation system according to claim 1, characterized in that, The power domain also includes a temperature sensor; The timer is also configured to: generate a second interrupt signal for triggering a dynamic voltage frequency adjustment task based on a preset second trigger period, and send the second interrupt signal to the low power management module; The low-power management module is further configured to: respond to the second interrupt signal, acquire the current temperature of the functional module in the corresponding power domain based on the temperature sensor in each power domain; determine whether the current temperature of the functional module in each power domain is within the preset normal temperature range based on the current temperature of the functional module in each power domain and the preset normal temperature range; identify functional modules whose current temperature is not within the preset normal temperature range as functional modules to be adjusted; and determine the target voltage-frequency combination and corresponding voltage-frequency adjustment method of the functional module to be adjusted based on the preset temperature control strategy, the preset temperature-frequency-voltage correspondence table, and the current temperature of the functional module to be adjusted.

3. The dynamic voltage and frequency regulation system according to claim 1, characterized in that, The dynamic voltage and frequency adjustment system further includes: an external memory; the plurality of power domains include: a first power domain, a second power domain, a third power domain, and a fourth power domain; the first power domain includes a double data rate (DDR) controller, and the performance monitoring unit in the first power domain includes a first bandwidth monitoring unit; the second power domain includes a central processing unit (CPU), and the performance monitoring unit in the second power domain includes a second bandwidth monitoring unit and a load monitoring unit; the third power domain includes a neural network processor (NPU), and the performance monitoring unit in the third power domain includes a third bandwidth monitoring unit and a MAC utilization monitoring unit; the fourth power domain includes a graphics processing unit (GPU) and a data processing unit (DPU), or a DPU, and the performance monitoring unit in the fourth power domain includes a fourth bandwidth monitoring unit; wherein, the external memory is connected to the DDR controller in the first power domain.

4. The dynamic voltage and frequency regulation system according to claim 3, characterized in that, The application scenarios include: low-load scenarios and high-load scenarios; the step of determining whether the application scenario and performance level of the functional module in the power domain match based on the performance status parameters of the functional module in the power domain and the corresponding preset discrimination conditions includes: For the DDR controller, the performance status parameters include the bandwidth parameters of the DDR controller obtained by the first bandwidth monitoring unit. If the bandwidth parameters of the DDR controller are all lower than a first preset low bandwidth threshold within a preset time period, it is determined that the application scenario and performance level of the DDR controller are currently mismatched, and the DDR controller is currently in a low load scenario. If the bandwidth parameters are all higher than the first preset high bandwidth threshold within a preset time period, it is determined that the application scenario and performance level of the DDR controller are currently mismatched, and the DDR controller is currently in a high load scenario. For the CPU, the performance status parameters include the CPU bandwidth parameters obtained by the second bandwidth monitoring unit and the CPU utilization rate obtained by the load monitoring unit. If the CPU utilization rate is lower than a preset low CPU utilization threshold for a preset period of time, it is determined that the application scenario and performance level of the CPU are not matched, and the CPU is currently in a low load scenario. If the CPU utilization rate is higher than a preset high CPU utilization threshold for a preset period of time, or the CPU bandwidth parameters are higher than a second preset high bandwidth threshold for a preset period of time, it is determined that the application scenario and performance level of the CPU are not matched, and the CPU is currently in a high load scenario. For the NPU, the performance status parameters include the bandwidth parameters of the NPU obtained by the third bandwidth monitoring unit and the MAC utilization of the NPU obtained by the MAC utilization monitoring unit. If the MAC utilization is lower than a preset low threshold for a preset period of time, it is determined that the application scenario and performance level of the NPU are mismatched, and the NPU is currently in a low-load scenario. If the MAC utilization is higher than a preset high threshold for a preset period of time, or the bandwidth parameters are higher than a third preset high threshold for a preset period of time, it is determined that the application scenario and performance level of the NPU are mismatched, and the NPU is currently in a high-load scenario. For the DPU or the DPU and the GPU, the performance status parameters include the bandwidth parameters of the DPU or the DPU and the GPU obtained by the fourth bandwidth monitoring unit. If the bandwidth parameters of the DPU or the DPU and the GPU are all lower than the fourth preset low bandwidth threshold within a preset time period, it is determined that the application scenario and performance level of the DPU or the DPU and the GPU are currently in a low-load scenario. If the bandwidth parameters of the DPU or the DPU and the GPU are all higher than the fourth preset high bandwidth threshold within a preset time period, it is determined that the application scenario and performance level of the DPU or the DPU and the GPU are currently in a high-load scenario.

5. The dynamic voltage and frequency regulation system according to claim 1, characterized in that, The preset frequency-voltage correspondence table contains multiple frequency-voltage pairs, each containing a frequency and a voltage corresponding to that frequency. The preset frequency adjustment strategy includes a first preset frequency adjustment strategy and a second preset frequency adjustment strategy. Determining the target voltage-frequency combination and corresponding voltage-frequency adjustment method for the specified functional module based on the preset frequency adjustment strategy, the preset frequency-voltage correspondence table, the specified frequency range, and the current frequency of the specified functional module includes: If the current frequency of the specified functional module is less than the lowest specified frequency in the specified frequency range, and the voltage frequency adjustment method corresponding to the specified functional module is a boost frequency adjustment method, then: the target frequency of the specified functional module is obtained according to the first preset frequency adjustment strategy and the current frequency of the specified functional module; the target voltage of the specified functional module is obtained according to the target frequency of the specified functional module and the preset frequency-voltage correspondence table. If the current frequency of the specified functional module is greater than the highest specified frequency in the specified frequency range, and the voltage frequency adjustment method corresponding to the specified functional module is a frequency reduction and voltage reduction adjustment method, then: the target frequency of the specified functional module is obtained according to the second preset frequency adjustment strategy and the current frequency of the specified functional module; the target voltage of the specified functional module is obtained according to the target frequency of the specified functional module and the preset frequency-voltage correspondence table.

6. The dynamic voltage and frequency regulation system according to claim 1, characterized in that, The preset DVFS strategy table is used to describe multiple performance level voltage-frequency pairs. Each performance level voltage-frequency pair contains a performance level and a corresponding voltage and frequency. The step of determining the target voltage-frequency combination and corresponding voltage-frequency adjustment method for the functional module to be adjusted based on the current application scenario, current frequency, current voltage, and the preset DVFS strategy table includes: The current performance level of the functional module to be adjusted is determined based on the current frequency and current voltage of the functional module to be adjusted and the preset DVFS strategy table; If the functional module to be adjusted is currently in a low-load scenario and the voltage and frequency adjustment method corresponding to the functional module to be adjusted is a frequency reduction and voltage reduction adjustment method, then: from the preset DVFS strategy table, select the voltage and frequency corresponding to the performance level that is one or more levels lower than the current performance level as the target voltage and the target frequency. If the functional module to be adjusted is currently in a high-load scenario, and the voltage and frequency adjustment method corresponding to the functional module to be adjusted is a boost and frequency adjustment method, then: select the voltage and frequency corresponding to the performance level that is one or more levels higher than the current performance level from the preset DVFS strategy table, as the target voltage and the target frequency.

7. The dynamic voltage and frequency regulation system according to claim 1, characterized in that, The voltage and frequency adjustment methods include: a boost and frequency adjustment method or a frequency and voltage reduction adjustment method. The adjustment sequence indicated by the boost and frequency adjustment method includes: dynamic voltage and frequency adjustment in the order of first increasing the voltage and then increasing the frequency. The adjustment sequence indicated by the frequency and voltage reduction adjustment method includes: dynamic voltage and frequency adjustment in the order of first decreasing the frequency and then decreasing the voltage. The step of adjusting the current voltage of the target functional module to the target voltage via the PMIC and adjusting the current frequency of the target functional module to the target frequency via the clock reset module, according to the adjustment sequence indicated by the corresponding voltage frequency adjustment method, includes: When the voltage and frequency adjustment method is a boost and frequency adjustment method, the current voltage of the target functional module is first adjusted to the target voltage through the PMIC, and then the current frequency of the target functional module is adjusted to the target frequency through the clock reset module. When the voltage frequency adjustment method is a frequency reduction and voltage reduction adjustment method, the current frequency of the target functional module is first adjusted to the target frequency through the clock reset module, and then the current voltage of the target functional module is adjusted to the target voltage through the PMIC.

8. The dynamic voltage and frequency regulation system according to claim 1, characterized in that, The low-power management module communicates with the PMIC via the system bus and I2C interface; The step of adjusting the current voltage of the target functional module to the target voltage via the PMIC includes: The low-power management module sends the target voltage of the target functional module to the PMIC via the system bus and I2C interface. The PMIC adjusts the voltage signal output to the target functional module through the corresponding independent adjustable voltage output interface based on the target voltage of the target functional module and a preset voltage adjustment step size. The PMIC writes the intermediate voltage value calculated based on the preset voltage adjustment step size to the corresponding independent adjustable voltage output interface register. When the low-power management module determines that the intermediate voltage value in the independent adjustable voltage output interface register is consistent with the target voltage, it obtains the current voltage of the target functional module through the voltage sensor in the power domain corresponding to the target functional module. If the obtained current voltage of the target functional module is consistent with the target voltage, the voltage adjustment is determined to be complete.

9. The dynamic voltage and frequency regulation system according to claim 1, characterized in that, The step of adjusting the current frequency of the target functional module to the target frequency through the clock reset module includes: The low-power management module generates corresponding frequency adjustment parameters based on the target frequency of the target functional module, and sends the frequency adjustment parameters to the clock reset module through the system bus. The clock reset module generates a clock signal corresponding to the target frequency according to the frequency adjustment parameters, and outputs the generated clock signal to the target functional module through the corresponding independent adjustable frequency output interface.

10. The dynamic voltage and frequency regulation system according to claim 9, characterized in that, The low-power management module generates corresponding frequency adjustment parameters based on the target frequency of the target functional module, including: Obtain the historical frequency switching records of the target functional module, which include the actual switching time and the stable load rate after the switching is completed at least once when the target functional module switches from its current frequency to a specified frequency. Based on the historical frequency switching records, the current frequency of the target functional module, the target frequency, and the preset frequency switching model, a predicted optimized switching path is calculated. The optimized switching path indicates the switching from the current frequency of the target functional module to one or more intermediate frequencies of the target frequency and the expected dwell time of each intermediate frequency. The optimized switching path is converted into the frequency adjustment parameters, which are used to instruct the clock reset module to adjust the clock signal output to the target functional module step by step according to the optimized switching path.

11. The dynamic voltage and frequency regulation system according to claim 10, characterized in that, The clock reset module includes: multiple frequency modulation control modules, which are connected to the multiple power domains through corresponding independent adjustable frequency output interfaces. Each frequency modulation control module is used to control the clock signal output to the functional module in the corresponding power domain. The frequency modulation control module includes: a path execution controller, a timing control module, and a clock signal generation module. The path execution controller is configured to: receive frequency adjustment parameters of the target functional module from the low-power management module, parse the frequency adjustment parameters, and obtain multiple matching pairs containing intermediate frequencies and expected dwell times, as well as the execution order of each matching pair; The timing control module is configured to: send the intermediate frequency of the current matching pair to the clock signal generation module according to the execution order of each matching pair; after the expected dwell time of the current matching pair is reached, send the intermediate frequency of the next matching pair to the clock signal generation module, until the intermediate frequency of each matching pair is sent to the clock signal generation module. The clock signal generation module is configured to generate a corresponding clock signal based on the received intermediate frequency and send it to the target functional module through a corresponding independent adjustable frequency output interface.

12. The dynamic voltage and frequency regulation system according to claim 9, characterized in that, The frequency adjustment parameters include: a first frequency division coefficient, a second frequency division coefficient, and clock switching parameters; the clock reset module includes: multiple frequency modulation control modules, which are connected to the multiple power domains through corresponding independent adjustable frequency output interfaces. Each frequency modulation control module is used to control the clock signal output to the functional module in the corresponding power domain; each frequency modulation control module includes two frequency modulation control sub-modules and a dynamic glitch-free switching selection circuit. The output terminal of each frequency modulation control sub-module is connected to the corresponding input terminal of the dynamic glitch-free switching selection circuit. Each frequency modulation control sub-module includes a PLL circuit, a 2N duty cycle frequency division circuit, and a pulse frequency division circuit connected in sequence; the PLL circuits of the two frequency modulation control sub-modules are mutually ping-pong, when one PLL circuit is in the working state, the other PLL circuit is in the standby state, and when one PLL circuit is in the standby state, the other PLL circuit is in the working state. The two frequency modulation control submodules include: a first frequency modulation control submodule and a second frequency modulation control submodule, wherein the PLL circuit in the first frequency modulation control submodule is a first PLL circuit, and the PLL circuit in the second frequency modulation control submodule is a second PLL circuit. The low-power management module generates corresponding frequency adjustment parameters based on the target frequency of the target functional module, including: Obtain the identifier of the source PLL circuit of the current operating clock of the target functional module; the source PLL circuit refers to the PLL circuit that is currently in operation. Based on the target frequency, the identifier of the source PLL circuit, and a preset PLL frequency configuration table, a preferred PLL configuration scheme for generating the target frequency is determined. The preset PLL frequency configuration table includes a first PLL frequency configuration pair and a second PLL frequency configuration pair. The first PLL frequency configuration pair includes the identifier of the first PLL circuit and PLL frequency configuration parameters corresponding to the first PLL circuit. The second PLL frequency configuration pair includes the identifier of the second PLL circuit and PLL frequency configuration parameters corresponding to the second PLL circuit. The preferred PLL configuration scheme includes the identifier of the target PLL circuit and a first division coefficient and a second division coefficient calculated based on the target frequency and the current output frequency of the target PLL circuit. The target PLL circuit is either the source PLL circuit or the identifier of another PLL circuit. Based on the identifier of the target PLL circuit, the clock switching parameters are generated. The clock switching parameters are used to select the signal output by the frequency modulation control submodule corresponding to the target PLL circuit. If the target PLL circuit is the first PLL circuit, the clock switching parameters are configured as the first clock switching parameters; if the target PLL circuit is the second PLL circuit, the clock switching parameters are configured as the second clock switching parameters. The first frequency division coefficient, the second frequency division coefficient, and the clock switching parameter are encapsulated into the frequency adjustment parameter.

13. The dynamic voltage and frequency regulation system according to claim 12, characterized in that, The clock reset module generates a clock signal corresponding to the target frequency according to the frequency adjustment parameters, including: The frequency modulation control submodule corresponding to the target PLL circuit generates a corresponding second-level frequency division signal according to the frequency adjustment parameters, including: generating a corresponding output clock signal based on a reference clock and PLL frequency configuration parameters corresponding to the target PLL circuit; dividing the output clock signal by a power of 2 according to the first division coefficient using a 2N equal duty cycle frequency division circuit in the frequency modulation control submodule corresponding to the target PLL circuit to generate a first-level frequency division signal with equal duty cycle; receiving a preset number of the first-level frequency division signals using a pulse frequency division circuit in the frequency modulation control submodule corresponding to the target PLL circuit, and selecting one or more consecutive first-level frequency division signals according to the second division coefficient as the second-level frequency division signal to be output to the dynamic glitch-free switching selection circuit; The dynamic glitch-free switching selection circuit, based on the clock switching parameters, uses the second-level frequency division signal output by the pulse frequency division circuit in the frequency modulation control submodule corresponding to the target PLL circuit as the clock signal corresponding to the target frequency. This includes: if the clock switching parameters are the first clock switching parameters, then the second-level frequency division signal output by the first frequency modulation control submodule is output as the clock signal corresponding to the target frequency; if the clock switching parameters are the second clock switching parameters, then the second-level frequency division signal output by the second frequency modulation control submodule is output as the clock signal corresponding to the target frequency.

14. A dynamic voltage-frequency regulation method based on multiple power source domains, characterized in that, The dynamic voltage and frequency adjustment method is applied to a System-on-a-Chip (SoC), which includes a timer, a clock reset module, and multiple power domains. Each power domain includes a performance monitoring unit, a voltage sensor, and at least one functional module. Each functional module in the power domain is connected to a corresponding independently adjustable voltage output interface of the PMIC and a corresponding independently adjustable frequency output interface of the clock reset module to receive independent voltage and clock signals. Each functional module includes a processor or controller. The dynamic voltage and frequency adjustment method is used to respond to service scheduling events and determine a corresponding voltage and frequency adjustment strategy based on the type of service to be executed, including: When the service type is a deterministic service, the specified functional module executing the service and the specified frequency range of the specified functional module when executing the service are obtained. It is determined whether the current frequency of the specified functional module is within the specified frequency range. If not, the target voltage-frequency combination and the corresponding voltage-frequency adjustment method of the specified functional module are determined according to the preset frequency adjustment strategy, the preset frequency-voltage correspondence table, the specified frequency range and the current frequency of the specified functional module. The target voltage-frequency combination includes the target voltage and the target frequency. When the type of the service is uncertain, in response to the first interrupt signal, the performance status parameters of the functional modules in the corresponding power domain are obtained based on the performance monitoring unit in each power domain; the current voltage of the functional modules in the corresponding power domain is obtained based on the voltage sensor in each power domain; according to the performance status parameters of the functional modules in the power domain and the corresponding preset discrimination conditions, it is determined whether the application scenario and performance level of the functional modules in the power domain are matched; the functional modules whose application scenario and performance level are not matched are identified as functional modules to be adjusted, and the target voltage-frequency combination and corresponding voltage-frequency adjustment method of the functional modules to be adjusted are determined according to the application scenario, current frequency, current voltage and preset DVFS strategy table; wherein, the first interrupt signal is used to trigger the dynamic voltage-frequency adjustment task, and the first interrupt signal is generated by the timer based on the preset first trigger cycle; According to the adjustment sequence indicated by the corresponding voltage and frequency adjustment method, the current voltage of the target functional module is adjusted to the target voltage through the PMIC, and the current frequency of the target functional module is adjusted to the target frequency through the clock reset module; wherein, the target functional module includes: the designated functional module or the functional module to be adjusted.

15. The dynamic voltage frequency adjustment method according to claim 14, characterized in that, The power domain further includes a temperature sensor; the dynamic voltage frequency adjustment method further includes: In response to the second interrupt signal, the current temperature of the functional module in the corresponding power domain is obtained based on the temperature sensor in each power domain; according to the current temperature of the functional module in each power domain and the preset normal temperature range, it is determined whether the current temperature of the functional module in each power domain is within the preset normal temperature range; functional modules whose current temperature is not within the preset normal temperature range are identified as functional modules to be adjusted; according to the preset temperature control strategy, the preset temperature-frequency-voltage correspondence table, and the current temperature of the functional module to be adjusted, the target voltage-frequency combination and the corresponding voltage-frequency adjustment method of the functional module to be adjusted are determined; wherein, the second interrupt signal is generated by the timer based on the preset second trigger cycle.

16. A dynamic voltage and frequency regulation device based on multiple power supply domains, characterized in that, The dynamic voltage and frequency adjustment device is installed on a System-on-Chip (SoC). The SoC includes a timer, a clock reset module, and multiple power domains. Each power domain includes a performance monitoring unit, a voltage sensor, and at least one functional module. Each functional module in the power domain is connected to a corresponding independent adjustable voltage output interface of the PMIC and a corresponding independent adjustable frequency output interface of the clock reset module to receive independent voltage and clock signals. Each functional module includes a processor or controller. The dynamic voltage and frequency adjustment device is used to respond to service scheduling events and determine a corresponding voltage and frequency adjustment strategy based on the type of service to be executed, including: A deterministic service processing module is configured to: when the service type is deterministic service, obtain the specified functional module executing the service and the specified frequency range of the specified functional module when executing the service, determine whether the current frequency of the specified functional module is within the specified frequency range, and if not, determine the target voltage-frequency combination and the corresponding voltage-frequency adjustment method of the specified functional module according to a preset frequency adjustment strategy, a preset frequency-voltage correspondence table, the specified frequency range and the current frequency of the specified functional module; wherein, the target voltage-frequency combination includes target voltage and target frequency; An uncertain service processing module is configured to: when the service type is uncertain, respond to a first interrupt signal, acquire performance status parameters of the functional modules in the corresponding power domain based on the performance monitoring unit in each power domain; acquire the current voltage of the functional modules in the corresponding power domain based on the voltage sensor in each power domain; determine whether the application scenario and performance level of the functional modules in the power domain match based on the performance status parameters of the functional modules in the power domain and the corresponding preset discrimination conditions; designate functional modules whose application scenario and performance level do not match as functional modules to be adjusted, and determine the target voltage-frequency combination and corresponding voltage-frequency adjustment method of the functional modules to be adjusted based on the application scenario, current frequency, current voltage and preset DVFS strategy table of the functional modules to be adjusted; wherein, the first interrupt signal is used to trigger the dynamic voltage-frequency adjustment task, and the first interrupt signal is generated by the timer based on a preset first trigger cycle; The voltage and frequency adjustment module is configured to: adjust the current voltage of the target functional module to the target voltage through the PMIC according to the adjustment sequence indicated by the corresponding voltage and frequency adjustment method, and adjust the current frequency of the target functional module to the target frequency through the clock reset module; wherein the target functional module includes: the designated functional module or the functional module to be adjusted.

17. The dynamic voltage frequency adjustment device according to claim 16, characterized in that, The power domain further includes a temperature sensor; the dynamic voltage frequency adjustment device further includes: The temperature adaptation module is configured to: respond to a second interrupt signal, acquire the current temperature of the functional module in the corresponding power domain based on the temperature sensor in each power domain; determine whether the current temperature of the functional module in each power domain is within the preset normal temperature range based on the current temperature of the functional module in each power domain and the preset normal temperature range; identify functional modules whose current temperature is not within the preset normal temperature range as functional modules to be adjusted; and determine the target voltage-frequency combination and corresponding voltage-frequency adjustment method of the functional module to be adjusted based on a preset temperature control strategy, a preset temperature-frequency-voltage correspondence table, and the current temperature of the functional module to be adjusted; wherein the second interrupt signal is generated by the timer based on a preset second trigger cycle.

18. A chip, characterized in that, It includes a memory and a processor; the memory is used to store computer instructions, wherein the computer instructions are executed by the processor to implement the dynamic voltage frequency adjustment method as described in any one of claims 14 to 15.

19. An electronic device, characterized in that, Includes the dynamic voltage frequency regulation system as described in any one of claims 1 to 13.

20. A computer-readable storage medium storing computer instructions thereon, characterized in that, When the computer instructions are executed by the processor, they implement the dynamic voltage frequency adjustment method according to any one of claims 14-15.

21. A computer program product comprising computer instructions, characterized in that, When the computer instructions are executed by the processor, they implement the dynamic voltage frequency adjustment method according to any one of claims 14-15.

Images