Data storage device and method of scheduling operations thereof

Abstract

This invention provides a data storage device and its operation instruction scheduling method. The data storage device includes a controller and non-volatile memory. The controller includes a register, which includes a power consumption index list. The non-volatile memory is used to store multiple instructions. The controller executes the multiple instructions to implement the operation instruction scheduling method, which includes: determining that a first operation instruction to be executed is a power-consuming operation instruction; determining that a first field of the first part of the power consumption index list stores the first operation instruction such that a first valid bit corresponding to the first field is enabled; executing the first operation instruction on the non-volatile memory based on the first valid bit; and clearing the first field and the first valid bit when receiving an operation instruction completion signal for the first operation instruction.

Description

Technical Field

[0001] This invention relates to an operation instruction scheduling technology for a data storage device, and more particularly to a data storage device and its operation instruction scheduling method. Background Technology

[0002] With technological advancements, the capacity and read / write speeds of data storage devices such as flash memory have increased dramatically. Capacities now often reach several megabytes (TB), and read / write speeds exceed 2GB / sec. Power consumption has become a significant issue for such devices. This is especially true for portable solid-state drives (SSDs, pSSDs). On many mobile platforms such as laptops, phones, and tablets, the power provided by the connection ports is limited. For example, a MacBook can only provide less than 0.9A of current to a USB pSSD (power = 5V * 0.9A = 4.5W). Therefore, if the pSSD's power consumption exceeds this value, it can cause device malfunctions. This can range from temporary inoperability to serious problems with the flash translation layer (FTL), resulting in permanent data corruption. Summary of the Invention

[0003] This invention provides a data storage device and its operation instruction scheduling method, which can automatically adjust the execution sequence of operation instructions of the data storage device to avoid excessive concentration of power-consuming operation instructions, thereby achieving the effects of distributing power consumption, reducing temperature, and minimizing the impact on write and read performance.

[0004] The data storage device provided by the present invention includes a controller and non-volatile memory. The controller includes a register, the register includes a power consumption index list, and the non-volatile memory is used to store multiple instructions. The controller is used to execute multiple instructions to implement an operation instruction scheduling method, which includes: determining that the first operation instruction to be executed is a power-consuming operation instruction; determining that the first field of the first part of the power consumption index list stores the first operation instruction so that the first calibration bit corresponding to the first field is enabled; executing the first operation instruction on the non-volatile memory based on the first valid bit; and clearing the first field and the first valid bit when receiving the operation instruction completion signal of the first operation instruction.

[0005] The operation instruction scheduling method provided by this invention is applicable to a data storage device, wherein the data storage device includes a controller and a non-volatile memory, the controller includes a register, the register includes a power consumption index list, and the operation instruction scheduling method includes: determining that a first operation instruction to be executed is a power-consuming operation instruction; determining that a first field of the first part of the power consumption index list stores the first operation instruction such that a first valid bit corresponding to the first field is enabled; executing the first operation instruction on the non-volatile memory based on the first valid bit; and clearing the first field and the first valid bit when an operation instruction completion signal of the first operation instruction is received.

[0006] In one embodiment of the present invention, the operation instruction scheduling method further includes: determining that the second operation instruction to be executed is a non-power-consuming operation instruction; determining that the second field of the second part of the power consumption index list stores the second operation instruction so that the second valid bit corresponding to the second field can be enabled; executing the second operation instruction on the non-volatile memory based on the second valid bit; and clearing the second field and the second valid bit when receiving the operation instruction completion signal of the second operation instruction.

[0007] In one embodiment of the present invention, the operation instruction scheduling method further includes: determining that the first part of the power consumption index list cannot store the first operation instruction; waiting for the third column of the first part of the power consumption index list and the third valid bit corresponding to the third column to be cleared; determining that the third column of the first part of the power consumption index list stores the first operation instruction so that the third valid bit corresponding to the third column can be cleared; executing the first operation instruction on non-volatile memory based on the third valid bit; and clearing the third column and the third valid bit when receiving the operation instruction completion signal of the first operation instruction.

[0008] In one embodiment of the present invention, the operation instruction scheduling method further includes: determining that the second part of the power consumption index list cannot store the second operation instruction; waiting for the fourth column of the second part of the power consumption index list and the fourth valid bit corresponding to the fourth column to be cleared; determining that the fourth column of the second part of the power consumption index list stores the second operation instruction so that the fourth valid bit corresponding to the fourth column can be cleared; executing the second operation instruction on non-volatile memory based on the fourth valid bit; and clearing the fourth column and the fourth valid bit when receiving the operation instruction completion signal of the second operation instruction.

[0009] In one embodiment of the present invention, the power-consuming operation instructions include block erase instructions, page write instructions, and cache write instructions.

[0010] This invention uses a power consumption index list to adjust the execution sequence of operation instructions of the data storage device, thereby avoiding excessive concentration of power-consuming operation instructions, achieving the effects of distributing power consumption, reducing temperature, and minimizing the impact on write and read performance.

[0011] The above description is merely an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0012] Figure 1 This is a system block diagram of a data storage device provided in an embodiment of the present invention;

[0013] Figure 2 This is a system block diagram of a controller provided in an embodiment of the present invention;

[0014] Figure 3 This is a flowchart of an operation instruction scheduling method provided in an embodiment of the present invention. Detailed Implementation

[0015] This invention is described in particular by way of the following examples, which are merely illustrative. Various modifications and refinements can be made by those skilled in the art without departing from the spirit and scope of this disclosure. Therefore, the scope of protection of this disclosure is determined by the appended claims. Throughout this specification and the claims, unless explicitly stated otherwise, the words “a” and “described” include a description comprising “a or at least one” element or component. Furthermore, as used herein, the singular article also includes a description of multiple elements or components unless clearly excluded from the specific context. Moreover, when applied in this description and throughout the claims below, unless explicitly stated otherwise, “in which” may include both “in which” and “therein”. The terms used throughout this specification and the claims, unless otherwise specified, generally have their ordinary meaning in the art, in the disclosure, and in the specific context. Certain terms used to describe this invention will be discussed below or elsewhere in this specification to provide additional guidance to those skilled in the art in describing this invention. Examples found anywhere in this specification, including examples of any terms used in the discussion herein, are merely illustrative and do not limit the scope or meaning of the invention or any of the illustrative terms. Similarly, the invention is not limited to the various embodiments set forth in this specification.

[0016] The terms “substantially,” “around,” “about,” or “approximately” as used herein should generally mean within 20%, preferably within 10%, of a given value or range. Furthermore, quantities provided herein may be approximate, thus meaning that unless otherwise stated, they may be expressed using the terms “about,” “approximately,” or “approximately.” When a quantity, concentration, or other numerical value or parameter has a specified range, preferred range, or lists upper and lower ideal values, it should be considered as specifically disclosing all ranges consisting of pairs of numbers or ideal values ​​of any upper and lower limits, regardless of whether such ranges are separately disclosed. For example, if a range of length X cm to Y cm is disclosed, it should be considered as disclosing a length of H cm, where H can be any real number between X and Y.

[0017] Furthermore, the use of the terms "coupled" or "connected" herein includes any direct and indirect electrical connection. For example, if the text describes a first device as electrically coupled to a second device, it means that the first device can be directly connected to the second device, or indirectly connected to the second device through other devices or connection means. Additionally, regarding the description of the transmission or provision of electrical signals, those skilled in the art will understand that attenuation or other non-ideal variations may occur during the transmission of electrical signals. However, unless otherwise specified, the source and receiver of the transmitted or provided electrical signal should be considered as essentially the same signal. For example, if an electrical signal S is transmitted (or provided) from terminal A of an electronic circuit to terminal B of the same electronic circuit, a voltage drop may occur across the source and drain terminals of a transistor switch and / or possible stray capacitances. However, unless the purpose of this design is to intentionally utilize the attenuation or other non-ideal variations that occur during transmission (or provision) to achieve certain specific technical effects, the electrical signal S at terminals A and B of the electronic circuit should be considered as essentially the same signal.

[0018] It is understood that terms such as "comprising," "including," "having," "containing," and "involving," as used herein, are open-ended, meaning they include but are not limited to. Furthermore, no embodiment or claim of this invention is required to achieve all the objects, advantages, or features disclosed herein. In addition, the abstract and headings are merely for assisting in patent document searching and are not intended to limit the scope of the claims.

[0019] Please see Figure 1 and 2The figures shown are system block diagrams of a data storage device and a controller provided in an embodiment of the present invention. The data storage device 1 provided in this embodiment includes non-volatile memory 2 and a controller 3. The controller 3 includes a host interface 31, registers 32, read-only registers 33, a microprocessor 34, a memory interface 35, and static memory 37, and is coupled to each other via a bus 36. The controller 3 is coupled to a host 4 via the host interface 31 and to the non-volatile memory 2 via the memory interface 35. The registers 32 include a power consumption specification list as shown in Table 1. The read-only registers 33 include multiple instructions. The memory interface 35 includes an encoder 351 and a decoder 352. The static memory 37 is used as a cache for the microprocessor 34. The controller 3 executes multiple instructions to implement the operation instruction scheduling method of the data storage device 1 to adjust the execution sequence of the operation instructions of the data storage device 1. Furthermore, the data storage device 1 preferably uses a physical interface such as Peripheral Component Interconnect Express (PCI-E) or Serial Advanced Technology Attachment (SATA) for high-speed transmission.

[0020] Table 1 Power Consumption Indicators List

[0021] Operation instructions School Bit 0 D0h (Erase) 1 1 D0h (Erase) 1 ： NA 0 30 NA 0 31 10h (page write) 1 32 15h (Cache Write) 1 ： NA 0 63 NA 0

[0022] According to one embodiment of the present invention, the data storage device 1 can be a flash memory, which can adopt a Universal Serial Bus (USB), Serial Advanced Technology Attachment (SATA), Parallel Advanced Technology Attachment (PATA), Peripheral Component Interconnect (PCI) physical interface or a memory such as a memory card, USB flash device, solid-state drive (SSD), or embedded multimedia card (eMMC) communication protocol using USB, Non-Volatile Memory Express (NVME), Advanced Host Controller Interface (AHCI), or Small Computer System Interface (SCSI).

[0023] According to one embodiment of the present invention, the non-volatile memory 2 is, for example, but not limited to, NAND flash memory, and the type of NAND flash memory is, for example, but not limited to, single-level cell (SLC), multi-level cell (MLC), triple-level cell (TLC), quad-level cell (QLC), etc.

[0024] According to an embodiment of the present invention, the controller 3, such as but not limited to a processor, or including a microprocessor, is used to execute the writing, reading, erasing and programming of the non-volatile memory 2 according to the commands of the host terminal, such as the host 4, and to automatically execute multiple instructions to implement the operation instruction scheduling method of the data storage device 1 provided in the embodiment of the present invention.

[0025] Please see Figure 3 The diagram shown is a flowchart of an operation instruction scheduling method provided in an embodiment of the present invention. The operation instruction scheduling method of the data storage device 1 provided in this embodiment is executed by the controller 3 and includes the following steps.

[0026] Step S1: Determine whether the first operation instruction to be executed is a power-consuming operation instruction. If the determination is yes, proceed to step S3; if the determination is no, proceed to step S11.

[0027] Step S3: Determine whether one of the fields in the first part of the power consumption index list can store the first operation instruction so that the corresponding calibration bit of the field can be enabled. If the determination is yes, proceed to step S5; if the determination is no, proceed to step S9.

[0028] Step S5: Execute the first operation instruction on non-volatile memory 2 based on the effective bits.

[0029] Step S7: When the operation instruction completion signal of the first operation instruction is received is received, clear one of the fields and the valid bit of the corresponding field.

[0030] Step S9: Wait for one of the fields in the first part of the power consumption index list and the corresponding valid bits of that field to be cleared, and then proceed to step S3.

[0031] Step S11: Determine whether one of the fields in the second part of the power consumption index list can store a second operation instruction so that the corresponding valid bit of the field can be enabled. If the determination is yes, proceed to step S13; if the determination is no, proceed to step S17.

[0032] Step S13: Execute the second operation instruction on non-volatile memory 2 based on the effective bits.

[0033] Step S15: When the operation instruction completion signal of the second operation instruction is received, clear one of the fields and the valid bit corresponding to the one of the fields.

[0034] Step S17: Wait for one of the fields in the second part of the power consumption index list and the corresponding valid bits of that field to be cleared, and then proceed to step S11.

[0035] It is worth noting that in this invention, the power consumption index list is divided into a first part and a second part, each with 32 fields. For example, the first part includes fields 0-31, and the second part includes fields 32-63. The first part stores power-consuming operation instructions, including block erase instructions, page program instructions, and cache program instructions, while the second part stores non-power-consuming operation instructions. Furthermore, those skilled in the art can determine which operation instructions are power-consuming and which are non-power-consuming based on the power consumption threshold of the actual data storage device 1, and the number of fields in the first and second parts of the actual data storage device 1, according to the hardware design of the device.

[0036] In one example, after determining that each operation instruction of the data storage device 1 belongs to either a power-consuming or non-power-consuming operation instruction, the controller 3 will first read the power consumption index list to check if there are any empty fields before executing the operation instruction. For example, when the controller 3 expects to execute a power-consuming operation instruction, the controller 3 will first determine if there are any empty fields in the first step to store the operation instruction so as to enable the valid bit of this field to change from 0 to 1; if there are empty fields, the controller 3 stores the operation instruction and enables the corresponding valid bit to change from 0 to 1, and then the controller 3 executes the operation instruction on the non-volatile memory 2 based on this valid bit; if there are no empty fields, the controller 3 waits for the field in the first step to be cleared and stops executing this operation instruction. When the controller 3 is informed by the polling status signal that the operation instruction in the first step has been completed and that a field has been cleared and the corresponding valid bit has changed from 1 to 0, the controller 3 stores the operation instruction in the field and enables the corresponding valid bit to change from 0 to 1, and then the controller 3 executes the operation instruction on the non-volatile memory 2 based on this valid bit.

[0037] For example, when the controller 3 anticipates executing a non-power-consuming operation instruction, the controller 3 first determines whether there is an empty field in the second step to store the operation instruction so as to enable the valid bit of this field to change from 0 to 1. If there is an empty field, the controller 3 stores the operation instruction and enables the corresponding valid bit to change from 0 to 1, and then the controller 3 executes the operation instruction on the non-volatile memory 2 based on this valid bit. If there is no empty field, the controller 3 waits for a field in the second step to be cleared and stops executing this operation instruction. When the controller 3 is informed by polling the status signal that an operation instruction in the second step has been completed and a field has been cleared and the corresponding valid bit has changed from 1 to 0, the controller 3 stores the operation instruction in the field and enables the corresponding valid bit to change from 0 to 1, and then the controller 3 executes the operation instruction on the non-volatile memory 2 based on this valid bit.

[0038] In summary, the data storage device and its operation instruction scheduling method provided by the present invention, by using a power consumption index list to adjust the execution sequence of the operation instructions of the data storage device, can avoid excessive concentration of power-consuming operation instructions, thereby achieving the effects of distributing power consumption and reducing temperature, while minimizing the impact on write and read performance, and thus improving the stability of the data storage device.

[0039] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the methods and techniques disclosed above without departing from the scope of the present invention to create equivalent embodiments. Any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the scope of the present invention.

Claims

1. A method for scheduling operation instructions, characterized in that, Applicable to a data storage device, wherein the data storage device includes a controller and a non-volatile memory, the controller includes a register, the register including a power consumption index list, the operation instruction scheduling method including: The first operation instruction to be executed is determined to be a power-consuming operation instruction. The first column of a first part of the power consumption index list is determined to store the first operation instruction so that a first calibration bit corresponding to the first column is enabled. The first operation instruction is executed on the non-volatile memory based on the first valid bit; and When the operation instruction completion signal of the first operation instruction is received is received, the first field and the first valid bit are cleared.

2. The operation instruction scheduling method as described in claim 1, characterized in that, Including: Determine that the second operation instruction to be executed is a non-power-consuming operation instruction; The second operation instruction is stored in a second field of a second part of the power consumption index list so that a second valid bit corresponding to the second field is enabled; The second operation instruction is executed on the non-volatile memory based on the second valid bit; and When the operation instruction completion signal of the second operation instruction is received, the second field and the second valid bit are cleared.

3. The operation instruction scheduling method as described in claim 1, characterized in that, Including: It is determined that the first part of the power consumption index list cannot store the first operation instruction; Wait for a third column of the first part of the power consumption index list and a third valid bit corresponding to the third column to be cleared; The third column of the first part of the power consumption index list is determined to store the first operation instruction so that the third calibration bit corresponding to the third column is enabled. The first operation instruction is executed on the non-volatile memory based on the third valid bit; and When the operation instruction completion signal of the first operation instruction is received is cleared, the third field and the third valid bit are cleared.

4. The operation instruction scheduling method as described in claim 2, characterized in that, Including: It is determined that the second part of the power consumption index list cannot store the second operation instruction; Wait for a fourth column and a fourth valid bit corresponding to the fourth column of the second part of the power consumption index list to be cleared; The second part of the power consumption index list is determined to store the second operation instruction in the fourth column so that the fourth calibration bit corresponding to the fourth column is enabled; The second operation instruction is executed on the non-volatile memory based on the fourth valid bit; and When the operation instruction completion signal of the second operation instruction is received is cleared, the fourth field and the fourth valid bit are cleared.

5. The operation instruction scheduling method as described in claim 1, characterized in that, The power-consuming operation instructions include block erase instructions, page write instructions, and cache write instructions.

6. A data storage device, characterized in that, include: A non-volatile memory used to store multiple instructions; as well as A controller coupled to the non-volatile memory, wherein the controller includes a register including a list of power consumption metrics, and the controller is used to execute the plurality of instructions to implement an operation instruction scheduling method comprising: The first operation instruction to be executed is determined to be a power-consuming operation instruction. The first column of a first part of the power consumption index list is determined to store the first operation instruction so that a first calibration bit corresponding to the first column is enabled. The first operation instruction is executed on the non-volatile memory based on the first valid bit; and When the operation instruction completion signal of the first operation instruction is received is received, the first field and the first valid bit are cleared.

7. The data storage device as described in claim 6, characterized in that, The operation instruction scheduling method further includes: Determine that the second operation instruction to be executed is a non-power-consuming operation instruction; The second operation instruction is stored in a second field of a second part of the power consumption index list so that a second valid bit corresponding to the second field is enabled; The second operation instruction is executed on the non-volatile memory based on the second valid bit; and When the operation instruction completion signal of the second operation instruction is received, the second field and the second valid bit are cleared.

8. The data storage device as described in claim 6, characterized in that, The operation instruction scheduling method further includes: It is determined that the first part of the power consumption index list cannot store the first operation instruction; Wait for a third column of the first part of the power consumption index list and a third valid bit corresponding to the third column to be cleared; The third column of the first part of the power consumption index list is determined to store the first operation instruction so that the third calibration bit corresponding to the third column is enabled. The first operation instruction is executed on the non-volatile memory based on the third valid bit; and When the operation instruction completion signal of the first operation instruction is received is cleared, the third field and the third valid bit are cleared.

9. The data storage device as claimed in claim 7, characterized in that, The operation instruction scheduling method further includes: It is determined that the second part of the power consumption index list cannot store the second operation instruction; Wait for a fourth column and a fourth valid bit corresponding to the fourth column of the second part of the power consumption index list to be cleared; The second part of the power consumption index list is determined to store the second operation instruction in the fourth column so that the fourth calibration bit corresponding to the fourth column is enabled; The second operation instruction is executed on the non-volatile memory based on the fourth valid bit; and When the operation instruction completion signal of the second operation instruction is received is cleared, the fourth field and the fourth valid bit are cleared.

10. The data storage device as claimed in claim 6, characterized in that, The power-consuming operation instructions include block erase instructions, page write instructions, and cache write instructions.

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