Artificial intelligence chip and computing system

By implementing a hardware-based LL128 protocol data synchronization and retry mechanism, the problem of synchronization overhead in inter-GPU communication is solved, achieving efficient and low-latency data transmission and improving the scalability of the computing system.

CN122309182APending Publication Date: 2026-06-30SHANGHAI BIREN TECH CO LTD
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
SHANGHAI BIREN TECH CO LTD
Filing Date
2026-05-21
Publication Date
2026-06-30

AI Technical Summary

Technical Problem

The performance of modern inter-GPU communication is limited by the overhead of data synchronization. Especially in collective communication operations, software-level flag polling and memory barriers lead to wasted computing resources and latency. Although the LL128 protocol improves bandwidth utilization, the synchronization overhead is still relatively large.

Method used

The data synchronization and retry mechanism of the LL128 protocol is implemented in hardware. Flag detection and synchronization operations are achieved through a data synchronization device, including instruction parsing, memory access control, flag detection and comparison, and data writing unit. Hardware circuitry is used to achieve nanosecond-level response.

Benefits of technology

It frees up computing resources, improves communication efficiency, reduces latency, and enhances the scalability of computing systems in large-scale cluster environments.

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Abstract

Embodiments of the present disclosure relate to the field of processor hardware architecture, and provide an artificial intelligence chip and a computing system. The artificial intelligence chip comprises a first computing core, a shared memory device corresponding to the first computing core, and a data synchronization device. The first computing core is configured to issue a first data request instruction. The data synchronization device is configured to perform a read operation on first data, a flag detection operation, and a synchronization operation according to the first data request instruction. The first data is stored in a global memory device coupled to the artificial intelligence chip. The synchronization operation comprises sending the first data to the shared memory device. The shared memory device is configured to store the first data sent by the data synchronization device for reading by the first computing core. Embodiments of the present disclosure hardwareize data synchronization and retry, significantly reduce communication delay, and release core computing resources of the artificial intelligence chip.
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