A Radiation Resistance Method for FPGA Dynamic Adaptive Refresh Based on CPU Feedback Control
The FPGA dynamic adaptive refresh method controlled by CPU feedback periodically reads configuration data and dynamically adjusts the strategy, solving the single-event upset problem of FPGA in a radiation environment. It achieves high reliability and low resource overhead radiation resistance, ensuring system continuity.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- XIDIAN UNIV
- Filing Date
- 2026-03-20
- Publication Date
- 2026-06-30
AI Technical Summary
Existing technologies cannot guarantee high reliability while also ensuring system energy efficiency and task continuity. They also cannot achieve closed-loop feedback control based on the actual radiation environment and system operating status, which makes the FPGA configuration memory prone to single-event upsets, leading to abnormal logic functions or system crashes.
By using CPU feedback control, FPGA configuration data is periodically read, SEU error rate is analyzed, and refresh strategy is dynamically adjusted, including refresh cycle and range, forming a closed-loop control of perception, decision-making and execution to achieve adaptive radiation resistance management.
It achieves high reliability, low resource overhead, and context-aware radiation resistance, ensuring the continuous and stable operation of the FPGA in complex radiation environments.
Smart Images
Figure CN122309210A_ABST
Abstract
Description
Technical Field
[0001] The embodiments of this application relate to the field of integrated circuit technology, and in particular to an anti-radiation method for FPGA dynamic adaptive refresh based on CPU feedback control. Background Technology
[0002] Field-Programmable Gate Arrays (FPGAs) are widely used in high-reliability applications such as aerospace, high-altitude aircraft, and the nuclear industry due to their high reconfigurability and parallel processing capabilities. However, the configuration memory of mainstream SRAM-based FPGAs is extremely sensitive to high-energy particles such as cosmic rays, and is prone to single-event upsets (SEUs). This can lead to errors in the stored configuration bits, potentially causing logical malfunctions or even system crashes.
[0003] To address the SEU problem, existing technologies have proposed several solutions, such as fixed-period refresh, triple-mode redundancy, and hardware autonomous refresh. However, none of these existing solutions have achieved closed-loop feedback control based on the actual radiation environment and system operating status. They generally suffer from low resource efficiency, insufficient flexibility, and low intelligence, failing to ensure high reliability while simultaneously considering system energy efficiency and task continuity. Summary of the Invention
[0004] In view of this, embodiments of this application propose an FPGA dynamic adaptive refresh anti-radiation method based on CPU feedback control. By periodically reading FPGA configuration data, analyzing the SEU error rate, and dynamically adjusting the refresh strategy accordingly, a high reliability, low resource overhead, and context-aware anti-radiation capability can be achieved.
[0005] To achieve the above objectives, embodiments of this application propose a radiation-resistant method for FPGA dynamic adaptive refresh based on CPU feedback control, the method comprising the following steps: Step 1: Analyze the original configuration bitstream of the FPGA, calculate and store the benchmark verification information for comparison, and establish an access interface with the FPGA configuration memory. Step 2: Through the access interface, periodically read the current configuration data of the FPGA configuration memory according to the current refresh strategy; Step 3: Verify the current configuration data based on the benchmark verification information, locate the configuration frame where the error occurred, and calculate the single-particle flip error rate per unit time. Step 4: Based on the single-particle flip error rate, dynamically generate the refresh strategy for the next execution; wherein, the refresh strategy includes the refresh period and / or refresh range; Step 5: When an error is detected, extract the corresponding correct configuration data from the original configuration bitstream and write the correct configuration data to the corresponding location in the FPGA configuration memory through the access interface to correct the error; Step 6: Repeat steps 2 to 5 to form a closed-loop control of perception, decision-making and execution, thereby achieving adaptive radiation resistance management.
[0006] To achieve the above objectives, embodiments of this application also propose a radiation-resistant device based on CPU feedback control and FPGA dynamic adaptive refresh, the device comprising: The initialization module is used to analyze the raw configuration bitstream of the FPGA, calculate and store the benchmark verification information for comparison, and establish an access interface with the FPGA configuration memory. The sensing module is used to periodically read the current configuration data of the FPGA configuration memory according to the current refresh strategy through the access interface; The error detection and statistics module is used to verify the current configuration data based on the benchmark verification information, locate the configuration frame where the error occurs, and count the single particle flip error rate per unit time. The dynamic strategy module is used to dynamically generate the refresh strategy for the next execution based on the single-particle flip error rate; wherein, the refresh strategy includes the refresh period and / or refresh range; The local repair module is used to extract the corresponding correct configuration data from the original configuration bitstream when an error is detected, and write the correct configuration data to the corresponding location of the FPGA configuration memory through the access interface to repair the error; The closed-loop iteration module is used to repeatedly execute the perception module, error detection and statistics module, dynamic strategy module, and local repair module to form a closed-loop control of perception, decision-making, and execution, thereby achieving adaptive radiation resistance management.
[0007] To achieve the above objectives, embodiments of this application also propose an electronic device, including: a processor and a memory, wherein the memory stores instructions executable by the processor, and the processor is configured to execute the instructions such that the electronic device can implement the radiation-resistant method for FPGA dynamic adaptive refresh based on CPU feedback control as described above.
[0008] To achieve the above objectives, embodiments of this application also propose a computer-readable storage medium storing a computer program that, when executed by a processor, enables an anti-radiation method for FPGA dynamic adaptive refresh based on CPU feedback control as described above.
[0009] This application proposes a radiation-resistant method for FPGA dynamic adaptive refresh based on CPU feedback control. The method analyzes the original configuration bitstream of the FPGA, calculates and stores benchmark verification information for comparison, and establishes an access interface with the FPGA configuration memory. Then, through the access interface, it periodically reads the current configuration data from the FPGA configuration memory according to the current refresh strategy. Next, it verifies the current configuration data based on the benchmark verification information, locates the configuration frame with the error, and calculates the single-event upset (SEE) error rate per unit time. Then, based on the SEE error rate, it dynamically generates the refresh strategy for the next execution. When an error is detected, the corresponding correct configuration data is extracted from the original configuration bitstream and written to the corresponding location in the FPGA configuration memory through the access interface to correct the error. The above steps are repeated to form a closed-loop control of perception, decision-making, and execution, thereby achieving adaptive radiation-resistant management. This solution achieves high reliability, low resource overhead, and context-aware radiation resistance by periodically reading FPGA configuration data, analyzing the SEE error rate, and dynamically adjusting the refresh strategy accordingly.
[0010] Optionally, the original configuration bitstream of the FPGA is analyzed, benchmark verification information for comparison is calculated and stored, and an access interface with the FPGA configuration memory is established. This includes: logically dividing the original configuration bitstream according to the physical frame structure of the FPGA configuration memory, and calculating a verification feature value for each logical frame after division, so as to use it as benchmark verification information; storing the benchmark verification information and its mapping relationship with the logical frame address in the local memory of the external processor; initializing and configuring the configuration access port driver between the external processor and the FPGA; wherein the configuration access port is the internal configuration access port ICAP or SelectMAP interface.
[0011] Optionally, by accessing the interface and following the current refresh strategy, the current configuration data of the FPGA configuration memory is periodically read, including: calculating the current verification feature value in real time for each frame of current configuration data read; comparing the current verification feature value with the benchmark verification information of the corresponding logic frame indexed from the local memory; if the comparison result is inconsistent, it is determined that the logic frame has undergone a single event flip, its physical address is recorded and the error statistics are updated.
[0012] Optionally, based on the single-event upset error rate, a refresh strategy is dynamically generated for the next periodic sensing step, including: collecting the single-event upset error rate, system task criticality level, and system power consumption status at the current moment; comprehensively evaluating the collected multi-dimensional information based on adaptive decision rules to obtain evaluation results; and outputting the refresh cycle and refresh range for the next periodic sensing based on the evaluation results.
[0013] Optionally, the adaptive decision rule includes: shortening the refresh cycle and / or expanding the refresh range if a first condition is met; and extending the refresh cycle and / or narrowing the refresh range if the first condition is not met. The first condition is at least one of the following: a single-event flip error rate exceeding a first threshold, or a system task criticality level of high risk.
[0014] Optionally, when an error is detected, the corresponding correct configuration data is extracted from the original configuration bitstream, and the correct configuration data is written to the corresponding location in the FPGA configuration memory through the access interface to correct the error. This includes: querying the mapping relationship based on the physical address of the erroneous configuration frame, and extracting the corresponding standard configuration frame data from the original configuration bitstream; sequentially sending a sequence of instructions to the FPGA through the configuration access port to complete the overwrite of configuration data at the specified physical address; wherein the instruction sequence includes a synchronization word, a target address write instruction, a configuration data write instruction, standard configuration frame data, and a desynchronization word.
[0015] Optionally, after sending a sequence of instructions to the FPGA through the configured access port to overwrite the configuration data of the specified physical address, the method further includes: performing a single-frame readback and verification on the repaired physical address; if the verification passes, clearing the error flag and recording the repair log; if the verification fails, re-triggering step 5. Attached Figure Description
[0016] To more clearly illustrate the technical solutions in the embodiments or related technologies of this application, the accompanying drawings used in the description of the embodiments or related technologies of this application will be briefly introduced below. Obviously, the following drawings are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. The drawings described herein are only used to explain this application and are not intended to limit this application.
[0017] Figure 1 This is a flowchart of an FPGA dynamic adaptive refresh anti-radiation method based on CPU feedback control provided in one embodiment of this application; Figure 2 This is a radiation-resistant system architecture diagram of FPGA dynamic adaptive refresh based on CPU feedback control provided in one embodiment of this application; Figure 3 This is a schematic diagram of dynamic refresh interval adjustment provided in one embodiment of this application; Figure 4 This is a detailed flowchart of an FPGA dynamic adaptive refresh anti-radiation method based on CPU feedback control provided in one embodiment of this application; Figure 5 This is a schematic diagram of the structure of an FPGA dynamic adaptive refresh anti-radiation device based on CPU feedback control provided in another embodiment of this application; Figure 6 This is a schematic diagram of the structure of an electronic device provided in another embodiment of this application. Detailed Implementation
[0018] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the various embodiments of this application will be described in detail below with reference to the accompanying drawings. Those skilled in the art will understand that many technical details have been presented in the embodiments of this application to facilitate better understanding. However, the technical solutions claimed in this application can be implemented even without these technical details and various variations and modifications based on the following embodiments. The division of the following embodiments is for ease of description and should not constitute any limitation on the specific implementation of this application. The following embodiments can be combined with and referenced by each other without contradiction.
[0019] Field-Programmable Gate Arrays (FPGAs) are widely used in high-reliability applications such as aerospace, high-altitude aircraft, and the nuclear industry due to their high reconfigurability and parallel processing capabilities. However, the configuration memory of mainstream SRAM-based FPGAs is extremely sensitive to high-energy particles such as cosmic rays, and is prone to single-event upsets (SEUs). This can lead to errors in the stored configuration bits, potentially causing logical malfunctions or even system crashes.
[0020] To address the SEU problem, existing technologies have proposed several solutions, such as: First, fixed-period refresh: For example, using soft error mitigation (SEM) IP cores provided by vendors such as Xilinx, the entire FPGA's configuration memory is read and refreshed at fixed time intervals. The main drawback of this method is that its refresh strategy is static and indiscriminate. In low-radiation environments, frequent full-chip refreshes will result in ineffective waste of configuration bus bandwidth and system power consumption; while in the event of sudden high-radiation events, the fixed refresh interval may not be able to correct accumulated errors in time, leading to insufficient refresh and decreased reliability.
[0021] Second, triple modular redundancy: This method masks errors by making three copies of critical user logic circuits and using majority voting. Its drawbacks include huge resource overhead (typically requiring about three times the logic resources), and the fact that this method only protects user logic and cannot protect the FPGA's configuration memory from SEU interference.
[0022] Third, hardware-based autonomous refresh: This method relies on the FPGA's internal state machine to control the refresh process. It lacks coordination with upper-layer applications (such as CPU task scheduling and power management), has poor flexibility, and is difficult to optimize based on the actual operating state of the system.
[0023] However, existing technical solutions have failed to achieve closed-loop feedback control based on the actual radiation environment and system operating status. They generally suffer from problems such as low resource efficiency, insufficient flexibility, and low level of intelligence, and cannot ensure high reliability while taking into account the system's energy efficiency and task continuity.
[0024] In view of this, embodiments of this application propose an FPGA dynamic adaptive refresh anti-radiation method based on CPU feedback control. By periodically reading FPGA configuration data, analyzing the SEU error rate, and dynamically adjusting the refresh strategy accordingly, a high reliability, low resource overhead, and context-aware anti-radiation capability can be achieved.
[0025] One embodiment of this application proposes a radiation-resistant method for FPGA dynamic adaptive refresh based on CPU feedback control, applied to an electronic device, wherein the electronic device can be a terminal or a server. This embodiment and the following embodiments will use a server as an example for description. The implementation details of the radiation-resistant method for FPGA dynamic adaptive refresh based on CPU feedback control proposed in this embodiment are described in detail below. The following implementation details are provided for ease of understanding and are not necessary for implementing this solution.
[0026] The specific process of the radiation resistance method for FPGA dynamic adaptive refresh based on CPU feedback control proposed in this embodiment can be described as follows: Figure 1 As shown, it includes steps 1 to 6.
[0027] For example, such as Figure 2 As shown, Figure 2 This diagram illustrates a radiation-resistant system architecture based on CPU feedback control and FPGA dynamic adaptive refresh, representing a proposed application. It shows the connections between the CPU, memory for storing the bitstream, and the FPGA chip. Step 1 is the raw bitstream input; steps 2 and 3 can be the sensing phase; step 4 can be the decision-making phase; and step 5 can be the execution phase. For a detailed description of steps 1 to 6, please refer to the following embodiments.
[0028] Step 1: Analyze the original configuration bitstream of the FPGA, calculate and store the benchmark verification information for comparison, and establish an access interface with the FPGA configuration memory.
[0029] It is understandable that step 1 can establish a benchmark for subsequent verification and repair, and establish a hardware communication link.
[0030] In one possible embodiment, step 1 includes: logically dividing the original configuration bitstream according to the physical frame structure of the FPGA configuration memory, and calculating a verification feature value for each logical frame after division to use it as a reference verification information; storing the reference verification information and its mapping relationship with the logical frame address in the local memory of the external processor; and initializing and configuring the configuration access port driver between the external processor and the FPGA.
[0031] The configuration access port is either the internal configuration access port ICAP or the SelectMAP interface.
[0032] For example, upon system power-on, an external CPU, acting as the main control unit, performs initialization. The CPU reads the original configuration bitstream file used to configure the FPGA. Subsequently, the CPU logically divides the entire bitstream into multiple consecutive frames according to the physical frame structure of the FPGA chip's (e.g., Xilinx 7 series or UltraScale+ series FPGA) configuration memory. For each logical frame, the CPU calculates a unique checksum value using a predetermined check algorithm. For example, the predetermined checksum algorithm could be CRC32 cyclic redundancy check or ECC error correction code algorithm. The checksum values of all frames and their corresponding logical frame addresses (which can be mapped to the FPGA's physical frame addresses) are integrated to generate a baseline checksum mapping table, which is stored in local memory (such as DDR SDRAM) that the CPU can access at high speed. This mapping table will serve as the baseline for all subsequent configuration data integrity checks.
[0033] Simultaneously, the CPU initializes the physical connection and communication protocol with the FPGA by loading and running the corresponding driver. In this embodiment, the connection is preferably established through the FPGA's Internal Configuration Access Port (ICAP) or SelectMAP parallel configuration interface. The CPU configures the operating mode of this interface to ensure that it has bidirectional data transmission capability, that is, it supports readback operations on the FPGA configuration memory and dynamic local reconfiguration operations, thereby establishing the hardware foundation for the CPU to non-intrusively access and control the FPGA configuration memory.
[0034] Step 2: By accessing the interface, periodically read the current configuration data of the FPGA configuration memory according to the current refresh strategy.
[0035] In one possible embodiment, step 2 includes: calculating the current verification feature value in real time for each frame of current configuration data read this time; comparing the current verification feature value with the benchmark verification information of the corresponding logical frame indexed from the local memory; if the comparison result is inconsistent, determining that the logical frame has undergone a single-event flip, recording its physical address and updating the error statistics.
[0036] For example, once the system enters the running state, a periodic task controlled by the CPU's internal hardware timer is initiated. The interrupt period of this timer is determined by the refresh period parameter in the currently effective refresh policy. When the timer interrupt is triggered, the CPU can send a configuration frame read command to the FPGA through the established ICAP or SelectMAP interface. The range of data read is also determined by the refresh range parameter in the current refresh policy: specifically, in full-chip mode, the CPU sequentially reads the data from the entire configuration memory; in partial or critical region mode, the CPU only reads the configuration data from predefined critical logic regions (e.g., control paths, state machines, etc.).
[0037] It should be noted that this read operation is performed in the background of the FPGA and will not interrupt the user logic functions running in the front end of the FPGA, thus achieving non-intrusive status monitoring.
[0038] Step 3: Verify the current configuration data based on the benchmark verification information, locate the configuration frame where the error occurred, and calculate the single-particle flip error rate per unit time.
[0039] Understandably, this step is the error detection and data statistics stage, which then completes the transformation from raw data to decision information.
[0040] For example, for each frame of current configuration data read back in step 2 above, the CPU can use a verification algorithm (e.g., CRC32) to calculate its current verification feature value in real time. Subsequently, the CPU indexes the corresponding benchmark verification feature value from the benchmark verification mapping table stored in local memory according to the address of the frame and performs a comparison.
[0041] For example, if the currently calculated eigenvalue matches the baseline eigenvalue, the frame configuration data is determined to be correct and no SEU has occurred. If they do not match, a single-event upset (SEU) error has occurred in the frame. The CPU immediately records the physical address of the erroneous frame and sets the corresponding error flag in the system status register.
[0042] The system can maintain an error counter with a sliding time window (e.g., a sliding time window of 1 minute). Each time a SEU event is detected, the counter is incremented by 1. The CPU periodically calculates the total number of SEU events within this time window and converts it into a single-event flip error rate per unit time. This single-event flip error rate is one of the core input parameters for subsequent dynamic decision-making.
[0043] Step 4: Based on the single-particle flip error rate, dynamically generate the refresh strategy for the next execution.
[0044] The refresh strategy includes the refresh cycle and / or refresh range.
[0045] For example, the refresh strategy can be used to control the timed triggering and reading behavior of the next cycle in step 2.
[0046] The refresh cycle represents the time interval between two periodic configuration readbacks of the FPGA configuration memory initiated by the CPU. It can be dynamically adjusted based on the real-time monitored single-event fault rate (SETR) as the primary input. When the SETR increases (e.g., when the system enters a high-radiation region), the policy engine automatically shortens the refresh cycle and increases the frequency of readbacks and verifications to detect and correct errors more quickly, thereby improving the system's instantaneous reliability. When the SETR decreases (e.g., in a background radiation environment), the policy engine automatically lengthens the refresh cycle and reduces the frequency of readback operations to decrease configuration bus bandwidth usage and system power consumption, improving energy efficiency.
[0047] The refresh range can represent the area of the FPGA configuration memory covered by each periodic readback operation, such as a full-chip refresh or a partial refresh (or critical area refresh). A full-chip refresh refers to scanning and reading all configuration frame data of the entire FPGA chip. A partial (critical area) refresh refers to scanning and reading only a pre-defined core logic area that is critical to the system function.
[0048] In one possible embodiment, step 4 includes: collecting the single-event flip error rate, system task criticality level, and system power consumption status at the current moment; comprehensively evaluating the collected multi-dimensional information based on adaptive decision rules to obtain evaluation results; and outputting the refresh cycle and refresh range for the next periodic sensing based on the evaluation results.
[0049] In one possible embodiment, the adaptive decision rule includes: shortening the refresh cycle and / or expanding the refresh range if a first condition is met; and extending the refresh cycle and / or reducing the refresh range if the first condition is not met.
[0050] The first condition is that the single-event upset error rate is higher than a first threshold, or the system task is classified as high-risk. For example, For example, the policy generation engine can receive the single-event flip error rate and make decisions based on the system task criticality level and system power consumption status. The policy generation engine can be implemented using CPU software. The decision-making process follows preset adaptive decision rules, such as: When the single-event flip error rate is high, such as more than 1 time per minute, it indicates that the system may be entering a high-radiation environment and / or the system mission is at a high risk. For example, when executing flight control commands, the strategy generation engine will output a shorter refresh cycle and a more comprehensive refresh range, such as switching to full-screen mode, to improve protection strength and timeliness.
[0051] When the single-event upset error rate is low, such as less than or equal to 1 time per minute, it indicates that the system may be encountering a solar flare or entering a radiation anomaly zone. When the system task is in a non-critical state, such as when the system power consumption is sufficient, the policy generation engine can generate a longer refresh cycle and a smaller refresh range, such as scanning only the critical area, in order to reduce system power consumption and bus bandwidth usage.
[0052] like Figure 4 As shown, Figure 4 This is a schematic diagram of dynamic refresh interval adjustment provided in one embodiment of this application, where the horizontal axis is time and the vertical axis is refresh frequency, used to show the process of automatic frequency increase when the error rate increases. Figure 4 This describes how the system dynamically adjusts its configuration readback and refresh frequency based on the real-time monitored single-event upset (SET) error rate. At low refresh rates, when the SET error rate is low, the policy generation engine determines the radiation threat is small. To save system power consumption and configuration bus bandwidth, a longer refresh interval can be output, i.e., the refresh frequency is reduced. At high refresh rates, when the SET error rate is high, the refresh frequency also remains stable at a high level, ensuring the system can continue to operate at a pace matching the threat level, maximizing the timeliness of repairs, and preventing error accumulation from causing functional failure.
[0053] Step 5: When an error is detected, extract the corresponding correct configuration data from the original configuration bitstream and write the correct configuration data to the corresponding location in the FPGA configuration memory through the access interface to correct the error.
[0054] Understandably, this step is a partial reconfiguration and repair execution phase to achieve precise repair.
[0055] In one possible embodiment, step 5 includes: querying the mapping relationship based on the physical address of the erroneous configuration frame, and extracting the corresponding standard configuration frame data from the original configuration bitstream; and sequentially sending a sequence of instructions to the FPGA through the configuration access port to complete the overwrite of configuration data for the specified physical address.
[0056] The instruction sequence includes a synchronization word, a target address write instruction, a configuration data write instruction, standard configuration frame data, and a desynchronization word.
[0057] For example, this repair process is triggered when a single-event upset is detected and the physical address of a specific erroneous configuration frame is located. First, the CPU reverse-lookups the address mapping relationship based on the physical address of the erroneous frame and extracts the correct configuration frame data corresponding to that address from the locally stored original configuration bitstream file. Subsequently, the CPU sends a series of standard configuration write instruction sequences to the FPGA through the ICAP / SelectMAP interface to perform local reconfiguration.
[0058] For example, the instruction sequence includes: 1. Send a synchronization word (such as hexadecimal code 0xAA995566) to start the configuration session and inform the FPGA configuration controller to prepare to receive instructions.
[0059] 2. Write the target physical address of the erroneous frame into the FPGA's frame address register (FAR), pointing to the area to be repaired.
[0060] 3. Send the write configuration data command.
[0061] 4. Push the extracted correct configuration frame data stream into the interface. At this time, the FPGA's internal configuration engine will physically overwrite the original erroneous data with the correct data at the address specified by FAR.
[0062] 5. Send the synchronization word to end the configuration session and release control of the interface.
[0063] Understandably, upon receiving this sequence, the configuration controller inside the FPGA will precisely overwrite the data corrupted by the SEU with the correct data at the physical address specified by the FAR. This repair process only affects the single or a few erroneous configuration frames and is transparent and uninterrupted to the operation of the vast majority of other user logic on the FPGA.
[0064] In one possible embodiment, after the configuration access port is configured to send a sequence of instructions to the FPGA to complete the overwrite of configuration data for the specified physical address, the method provided by the embodiments of this application further includes: performing a single-frame readback and verification on the repaired physical address; if the verification passes, clearing the error flag and recording the repair log; if the verification fails, re-triggering step 5.
[0065] For example, after completing the overwrite of configuration data to the specified faulty physical address, i.e., the repair action, the system can perform a single-frame readback and verification to ensure that the repair operation itself is correct and effective.
[0066] If the verification passes, meaning the newly calculated eigenvalue matches the baseline value, this indicates that the repair write operation was successful, the single-event flip error has been correctly cleared, and the configuration frame has been restored to normal. The system will then clear the error flags and record the repair log.
[0067] If the verification fails, it means that the newly calculated feature value is still inconsistent with the baseline value. This indicates that the repair operation has failed to correct the error. The system will not clear the error flag, but will automatically re-trigger step 5 to extract the correct data from the original bit stream again and initiate a new round of overwrite and verification to the same physical address, forming an internal retry loop for a single repair until the verification is successful.
[0068] Step 6: Repeat steps 2 to 5 to form a closed-loop control of perception, decision-making and execution, thereby achieving adaptive radiation resistance management.
[0069] For example, after completing one loop, the system returns to step 2 and waits for the next periodic trigger determined by the new refresh strategy. Through such continuous closed-loop iteration, the system can continuously monitor the radiation environment, intelligently adjust its behavior, and repair SEU events, thereby achieving long-term, adaptive, and energy-efficient radiation protection for the FPGA configuration memory and ensuring the continuous and stable operation of highly reliable electronic systems in complex radiation environments.
[0070] For example, such as Figure 4 As shown, Figure 4 This is a detailed flowchart of a radiation-resistant method for FPGA dynamic adaptive refresh based on CPU feedback control, as described in this application. (Combined with...) Figure 1Step 1 can be the initialization phase, where the CPU calculates the verification value and stores the configuration FPGA interface; Step 2 can be the periodic configuration readback phase, where the CPU reads the FPGA configuration frame data at intervals; Step 3 can be the error detection and statistics phase, where the data is compared, error frames are identified, and the SEU error rate is accumulated; Step 4 can be the dynamic refresh strategy generation phase, where the refresh interval and refresh range are calculated based on the error rate, task, or power consumption; Step 5 can be the CPU-initiated partial refresh phase, where the correct data is extracted and written to the FPGA for repair through the interface; Step 6 can be the closed-loop iteration phase, where a loop of perception, decision-making, and execution is executed.
[0071] This application proposes a radiation-resistant method for FPGA dynamic adaptive refresh based on CPU feedback control. The method analyzes the original configuration bitstream of the FPGA, calculates and stores benchmark verification information for comparison, and establishes an access interface with the FPGA configuration memory. Then, through the access interface, it periodically reads the current configuration data from the FPGA configuration memory according to the current refresh strategy. Next, it verifies the current configuration data based on the benchmark verification information, locates the configuration frame with the error, and calculates the single-event upset (SEE) error rate per unit time. Then, based on the SEE error rate, it dynamically generates the refresh strategy for the next execution. When an error is detected, the corresponding correct configuration data is extracted from the original configuration bitstream and written to the corresponding location in the FPGA configuration memory through the access interface to correct the error. The above steps are repeated to form a closed-loop control of perception, decision-making, and execution, thereby achieving adaptive radiation-resistant management. This solution achieves high reliability, low resource overhead, and context-aware radiation resistance by periodically reading FPGA configuration data, analyzing the SEE error rate, and dynamically adjusting the refresh strategy accordingly.
[0072] The steps described above are for clarity only. In implementation, they can be combined into one step, or some steps can be broken down into multiple steps, as long as they involve the same logical relationship, they are all within the scope of protection of this application. Adding insignificant modifications or introducing insignificant designs to the algorithm or process, without changing the core design of the algorithm and process, are also within the scope of protection of this application.
[0073] Another embodiment of this application proposes a radiation-resistant device based on CPU feedback control and FPGA dynamic adaptive refresh. The details of this radiation-resistant device are described below. The following implementation details are provided for ease of understanding and are not essential for implementing this example. Figure 5 This is a schematic diagram of the structure of a radiation-resistant device based on CPU feedback control and FPGA dynamic adaptive refresh proposed in this embodiment, including: The initialization module 210 is used to analyze the original configuration bit stream of the FPGA, calculate and store the benchmark verification information for comparison, and establish an access interface with the FPGA configuration memory. The sensing module 220 is used to periodically read the current configuration data of the FPGA configuration memory according to the current refresh strategy through the access interface; The error detection and statistics module 230 is used to verify the current configuration data based on the benchmark verification information, locate the configuration frame where the error occurs, and count the single particle flip error rate per unit time. The dynamic strategy module 240 is used to dynamically generate the refresh strategy for the next execution based on the single-particle flip error rate; wherein, the refresh strategy includes the refresh period and / or refresh range; The local repair module 250 is used to extract the corresponding correct configuration data from the original configuration bit stream when an error is detected, and write the correct configuration data to the corresponding location of the FPGA configuration memory through the access interface to repair the error. The closed-loop iteration module 260 is used to repeatedly execute the perception module, error detection and statistics module, dynamic strategy module and local repair module to form a closed-loop control of perception, decision-making and execution, thereby realizing adaptive radiation resistance management.
[0074] It is not difficult to see that this embodiment is a device embodiment corresponding to the above method embodiments, and this embodiment can be implemented in conjunction with the above method embodiments. The relevant technical details and technical effects mentioned in the above method embodiments are still valid in this embodiment, and will not be repeated here to reduce repetition. Accordingly, the relevant technical details mentioned in this embodiment can also be applied to the above method embodiments.
[0075] It is worth mentioning that all modules and units involved in this embodiment are logical modules. In practical applications, a logical unit can be a physical unit, a part of a physical unit, or a combination of multiple physical units. Furthermore, to highlight the innovative aspects of this application, this embodiment does not introduce units that are not closely related to solving the technical problems proposed in this application; however, this does not mean that other units do not exist in this embodiment.
[0076] Another embodiment of this application provides an electronic device, such as Figure 6 As shown, it includes a processor 31 and a memory 32. The memory 32 stores instructions that the processor 31 can execute. When the processor 31 is configured to execute the instructions, the electronic device can implement an FPGA dynamic adaptive refresh anti-radiation method based on CPU feedback control as described in the above method embodiment.
[0077] The memory and processor are connected via a bus, which includes any number of interconnecting buses and bridges, connecting various circuits of one or more processors and the memory. The bus can also connect various other circuits such as peripheral devices, voltage regulators, and power management circuits, which are well known in the art and will not be described further herein. The bus interface provides an interface between the bus and the transceiver. The transceiver can be a single component or multiple components, such as multiple receivers and transmitters, providing a unit for communicating with various other devices over a transmission medium. Data processed by the processor is transmitted over the wireless medium via an antenna, which further receives data and transmits it to the processor.
[0078] The processor manages the bus and general processing, and also provides various functions, including timing, peripheral interfaces, voltage regulation, power management, and other control functions. Memory is used to store data used by the processor during operation.
[0079] Another embodiment of this application proposes a computer-readable storage medium storing a computer program that, when executed by a processor, can implement a radiation-resistant method for FPGA dynamic adaptive refresh based on CPU feedback control as described in the above method embodiments.
[0080] That is, those skilled in the art will understand that all or part of the steps in the above method embodiments can be implemented by a program instructing related hardware. The program is stored in a storage medium and includes several instructions to cause a device (such as a microcontroller, chip, etc.) or processor to execute all or part of the steps of the method described in the method embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory, random access memory, magnetic disks, or optical disks.
[0081] Those skilled in the art will understand that the above embodiments are specific implementations of this application, and in practical applications, various changes can be made in form and detail without departing from the spirit and scope of this application. For those skilled in the art, several improvements and modifications can be made without departing from the principles of this application, and these improvements and modifications are also considered to be within the scope of protection of this application.
Claims
1. A radiation-resistant method for FPGA dynamic adaptive refresh based on CPU feedback control, characterized in that, The method includes: Step 1: Analyze the original configuration bitstream of the FPGA, calculate and store the benchmark verification information for comparison, and establish an access interface with the FPGA configuration memory. Step 2: Through the access interface, periodically read the current configuration data of the FPGA configuration memory according to the current refresh strategy; Step 3: Verify the current configuration data based on the benchmark verification information, locate the configuration frame where the error occurred, and calculate the single-particle flip error rate per unit time. Step 4: Based on the single-particle flip error rate, dynamically generate the refresh strategy for the next execution; wherein, the refresh strategy includes the refresh period and / or refresh range; Step 5: When an error is detected, extract the corresponding correct configuration data from the original configuration bitstream and write the correct configuration data to the corresponding location in the FPGA configuration memory through the access interface to correct the error; Step 6: Repeat steps 2 to 5 to form a closed-loop control of perception, decision-making and execution, thereby achieving adaptive radiation resistance management.
2. The method according to claim 1, characterized in that, The process of analyzing the original configuration bitstream of the FPGA, calculating and storing benchmark verification information for comparison, and establishing an access interface with the FPGA configuration memory includes: According to the physical frame structure of the FPGA configuration memory, the original configuration bit stream is logically divided, and a verification feature value is calculated for each logical frame after division, which is used as the reference verification information. The benchmark verification information and its mapping relationship with the logical frame address are stored in the local memory of the external processor. Initialize and configure the configuration access port driver between the external processor and the FPGA; wherein, the configuration access port is the internal configuration access port ICAP or SelectMAP interface.
3. The method according to claim 2, characterized in that, The step of periodically reading the current configuration data of the FPGA configuration memory through the access interface according to the current refresh strategy includes: For each frame of current configuration data read this time, calculate the current verification feature value in real time; Compare the current verification feature value with the baseline verification information of the corresponding logical frame indexed from the local memory; If the comparison results are inconsistent, it is determined that a single-event flip has occurred in the logical frame, its physical address is recorded, and the error statistics are updated.
4. The method according to claim 1, characterized in that, The refresh strategy for the next execution, based on the single-particle flip error rate, includes: Collect the single-event flip error rate, system task criticality level, and system power consumption status at the current moment; Based on adaptive decision rules, the collected information from multiple dimensions is comprehensively evaluated to obtain the evaluation results; Based on the evaluation results, the refresh cycle and refresh range for the next periodic sensing are output.
5. The method according to claim 4, characterized in that, The adaptive decision rules include: If the first condition is met, shorten the refresh cycle and / or expand the refresh range; If the first condition is not met, the refresh cycle will be extended and / or the refresh range will be reduced. The first condition is that the single-event flip error rate is higher than the first threshold, or the system task is classified as high-risk.
6. The method according to claim 1, characterized in that, When an error is detected, the corresponding correct configuration data is extracted from the original configuration bitstream, and the correct configuration data is written to the corresponding location in the FPGA configuration memory through the access interface to correct the error, including: Based on the physical address of the misconfiguration frame, query the mapping relationship and extract the corresponding standard configuration frame data from the original configuration bitstream; The configuration access port is configured to send a sequence of instructions to the FPGA to overwrite the configuration data at the specified physical address. The instruction sequence includes a synchronization word, a target address write instruction, a configuration data write instruction, standard configuration frame data, and a desynchronization word.
7. The method according to claim 6, characterized in that, After the step of sequentially sending a sequence of instructions to the FPGA via the configured access port to overwrite the configuration data at the specified physical address, it also includes: Perform a single-frame readback and verification on the repaired physical address; If the verification passes, clear the error flag and record the repair log; If the verification fails, step 5 will be retried.
8. A radiation-resistant device based on CPU feedback control and FPGA dynamic adaptive refresh, characterized in that, The device includes: The initialization module is used to analyze the raw configuration bitstream of the FPGA, calculate and store the benchmark verification information for comparison, and establish an access interface with the FPGA configuration memory. The sensing module is used to periodically read the current configuration data of the FPGA configuration memory according to the current refresh strategy through the access interface; The error detection and statistics module is used to verify the current configuration data based on the benchmark verification information, locate the configuration frame where the error occurs, and count the single particle flip error rate per unit time. The dynamic strategy module is used to dynamically generate the refresh strategy for the next execution based on the single-particle flip error rate; wherein, the refresh strategy includes the refresh period and / or refresh range; The local repair module is used to extract the corresponding correct configuration data from the original configuration bitstream when an error is detected, and write the correct configuration data to the corresponding location of the FPGA configuration memory through the access interface to repair the error; The closed-loop iteration module is used to repeatedly execute the perception module, error detection and statistics module, dynamic strategy module, and local repair module to form a closed-loop control of perception, decision-making, and execution, thereby achieving adaptive radiation resistance management.
9. An electronic device, characterized in that, include: A processor and a memory, wherein the memory stores instructions executable by the processor, and the processor is configured to, when executing the instructions, enable the electronic device to implement a radiation-resistant method for FPGA dynamic adaptive refresh based on CPU feedback control as described in any one of claims 1 to 7.
10. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by the processor, it can implement the radiation resistance method for FPGA dynamic adaptive refresh based on CPU feedback control as described in any one of claims 1 to 7.