A verification system, a verification method, a device and related equipment
By configuring cache consistency to verify the main address area and mirror address area of the device, triggering mirroring operations and comparing data correctness, the problem of low verification efficiency of memory address mirroring function is solved, and efficient and complete verification effect is achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- 海光信息技术(成都)有限公司
- Filing Date
- 2026-03-31
- Publication Date
- 2026-06-30
AI Technical Summary
The current memory address mirroring function has low verification efficiency, making it difficult to accurately trigger and verify the mirroring logic in complex processes. Furthermore, it is difficult to fully cover boundary conditions in randomized test scenarios, resulting in incomplete verification and long debugging cycles.
A verification system is provided, which configures two cache consistency slave device verification units, each with a master address area and a mirror address area. When a mirror operation is triggered, the correctness of the mirror data is compared. The system manages memory using a memory management unit and constructs diverse access requests to simulate real-world scenarios, thereby achieving data synchronization and rapid verification.
It improves the verification efficiency of the memory address mirroring function, reduces verification overhead, enhances the completeness and reliability of verification, and can promptly detect problems such as data inconsistency and mirroring operation failure.
Smart Images
Figure CN122309263A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of computer technology, specifically to a verification system, verification method, apparatus, and related equipment. Background Technology
[0002] With the increasing demands for reliability and availability in computing systems, high-reliability design of memory subsystems in large-scale System-on-Chip (SoC) and Network-on-Chip (NoC) systems has become a key technical requirement in the chip industry, especially for server-grade processors. Against this backdrop, DRAM Address Mirroring technology, as an efficient hardware fault-tolerance method, is widely used for protecting core data.
[0003] However, the current verification efficiency of the memory address mirroring function still needs to be improved. Summary of the Invention
[0004] In view of this, embodiments of this application provide a verification system, verification method, apparatus and related equipment to improve the verification efficiency of memory address mirroring function.
[0005] To achieve the above objectives, the embodiments of this application provide the following technical solutions.
[0006] In a first aspect, embodiments of this application provide a verification system, including: Two cache consistency slave verification units are configured, each with a primary address region and a mirror address region. The mirror data in the mirror address region of one cache consistency slave verification unit is the data in the primary address region of the other cache consistency slave verification unit. Specifically, when a mirroring operation is triggered between two cache consistency slave device verification units, the correctness of the mirrored data in the mirrored address region is verified. The verification is determined by comparing the data in the main address region of one cache consistency slave device verification unit with the mirrored data in the mirrored address region of the other cache consistency slave device verification unit.
[0007] Optionally, the main address region of the cache consistency slave device verification unit is a preset region in the memory of the cache consistency slave device verification unit, and the addresses in this region have corresponding copies in the mirror address region of another cache consistency slave device verification unit; The cache consistency mirror address region of the device verification unit is the region outside the memory of the cache consistency mirror unit.
[0008] Optionally, each cache consistency slave unit manages its own memory through the memory management unit.
[0009] Secondly, embodiments of this application provide a verification method applied to the verification system described in the first aspect above, the method comprising: Trigger a mirroring operation between two cache consistency verification units; The data in the main address region of one cache consistency slave device verification unit is compared with the mirrored data in the mirrored address region of another cache consistency slave device verification unit to verify the correctness of the mirrored data in the mirrored address region.
[0010] Optionally, the step of triggering the mirroring operation between the two cache consistency verification units includes: If an access request sent by the processor to either cache coherency slave verification unit hits the main address region of that cache coherency slave verification unit, a mirroring operation between the two cache coherency slave verification units is triggered.
[0011] Optionally, when the access request is a write request, a mirroring operation is triggered between the two cache consistency verification units, specifically: The cache consistency slave device verification unit writes the write data corresponding to the write request into the main address area corresponding to the write request, and forwards the mirror write request and mirror write data to another cache consistency slave device verification unit, so that the other cache consistency slave device verification unit writes the mirror write data into the mirror address area corresponding to the mirror write request.
[0012] Optionally, when the access request is a read request, a mirroring operation is triggered between the two cache consistency verification units, specifically: The cache consistency slave device verification unit reads data from the main address region corresponding to the read request. If the read data contains errors, the mirror read request is forwarded to another cache consistency slave device verification unit so that the other cache consistency slave device verification unit reads the mirror data from the mirror address region corresponding to the mirror read request and feeds back the mirror data to the cache consistency slave device verification unit.
[0013] Optionally, the mirror write request and mirror write data can be forwarded to another cache consistency slave verification unit via a forwarding sequence; or, The mirror read request is forwarded to another cache consistency slave verification unit via a forwarding sequence.
[0014] Thirdly, embodiments of this application provide a verification device applied to the verification system described in the first aspect above, the device comprising: The triggering module is used to trigger a mirroring operation between two cache consistency verification units. The comparison module is used to compare the data in the main address region of one cache consistency slave device verification unit with the mirrored data in the mirrored address region of another cache consistency slave device verification unit in order to verify the correctness of the mirrored data in the mirrored address region.
[0015] Fourthly, embodiments of this application provide a verification platform, which includes the verification system as described in the first aspect above, for performing the verification method as described in the second aspect above.
[0016] Fifthly, embodiments of this application provide an electronic device including at least one memory and at least one processor, wherein the memory stores one or more computer-executable instructions, and the processor invokes the one or more computer-executable instructions to execute the verification method as described in the second aspect above.
[0017] In a sixth aspect, embodiments of this application provide a storage medium that stores one or more computer-executable instructions, which, when executed, implement the verification method described in the second aspect above.
[0018] In a seventh aspect, embodiments of this application provide a computer program product including one or more computer-executable instructions, wherein when the one or more computer-executable instructions are executed, the verification method described in the second aspect above is implemented.
[0019] This application provides a verification system, including: two cache consistency slave device verification units, each configured with a main address region and a mirror address region, wherein the mirror data in the mirror address region of one cache consistency slave device verification unit is the data in the main address region of the other cache consistency slave device verification unit; wherein, when a mirroring operation is triggered between the two cache consistency slave device verification units, the correctness of the mirror data in the mirror address region is verified; the verification is determined by comparing the data in the main address region of one cache consistency slave device verification unit with the mirror data in the mirror address region of the other cache consistency slave device verification unit.
[0020] As can be seen, the verification system provided in this application includes two cache consistency slave device verification units configured with a main address region and a mirror address region. When a mirroring operation between the two cache consistency slave device verification units is triggered, data can be synchronized between the main address region of one cache consistency slave device verification unit and the mirror address region of the other cache consistency slave device verification unit. Then, the data in the main address region of one cache consistency slave device verification unit is compared with the mirrored data in the mirrored address region of the other cache consistency slave device verification unit to verify the correctness of the mirrored data in the mirrored address region. This avoids the complex process in traditional verification, reduces verification overhead in all aspects, and improves the verification efficiency of the memory address mirroring function.
[0021] Meanwhile, by triggering a mirroring operation between two cache consistency slave verification units and comparing the data in the main address region of one cache consistency slave verification unit with the mirrored data in the mirrored address region of another cache consistency slave verification unit, this application can promptly detect problems in the memory address mirroring function, such as data inconsistency or mirroring operation failure, thereby improving the completeness and reliability of the verification. Attached Figure Description
[0022] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.
[0023] Figure 1 This is an architecture diagram of the verification system provided in the embodiments of this application; Figure 2 This is a schematic diagram of an optional process of the verification method provided in the embodiments of this application; Figure 3 This is a schematic diagram of an optional process for triggering a mirror write request provided in an embodiment of this application; Figure 4 This is a schematic diagram of an optional process for triggering a mirror read request provided in an embodiment of this application; Figure 5 This is a schematic diagram of an optional structure of the verification device provided in the embodiments of this application; Figure 6 This is an optional block diagram of the electronic device provided in the embodiments of this application. Detailed Implementation
[0024] The following will clearly and completely describe the technical solutions in the embodiments of the present application in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without creative efforts shall fall within the scope of protection of the present application.
[0025] As described in the background art, the memory address mirror (DRAM Address Mirror) technology, as an efficient hardware fault tolerance means, is widely used in the protection of core data. Specifically, the memory address mirror is a data redundancy and fault tolerance technology, mainly used to improve the reliability and availability of the computer memory system. The memory address mirror technology sets up a mirror mapping relationship at the memory controller or hardware level. When data is written to a master address, it will also be copied to one or more mirror addresses. This mechanism ensures that when an error occurs in the master address data or a physical memory unit fails, the system can still access the correct data through the mirror address, thus avoiding data loss or system crashes.
[0026] In order to ensure that the memory address mirror function can meet the actual needs of the system and ensure that the system can work reliably both during normal operation and when a fault occurs, the memory address mirror function will be verified.
[0027] In an optional implementation, the memory address mirror function can be verified by combining software simulation and FPGA (Field Programmable Gate Array) prototype verification. However, the process of constructing the verification scenario in this way is extremely complex and time-consuming. During the verification process, it is difficult to accurately trigger and verify the mirror logic. At the same time, if hardware acceleration co-simulation is used, a large amount of time will be consumed in the software-hardware communication link, and frequent data synchronization operations seriously slow down the overall verification progress. In addition, the visibility and signal capture ability of FPGA prototype verification are limited, and it is difficult to effectively detect and accurately locate intermittent or timing-related errors, resulting in a long debugging cycle.
[0028] In another alternative implementation, concurrent access sequences can be constructed on a large System-on-Chip (SoC) bus to verify the memory address mirroring functionality. However, in this approach, the behavior of the mirrored addresses is highly dependent on specific memory access patterns. In randomized testing scenarios, it is difficult to fully cover all boundary cases, making the verification incomplete. Moreover, once a problem is discovered during verification, detailed signal-level analysis is required. This process consumes a significant amount of time to locate the specific microarchitecture components and the root cause of the problem, severely impacting the efficiency of verifying the memory address mirroring functionality.
[0029] It is evident that the current verification efficiency of the memory address mirroring function still needs to be improved.
[0030] In view of this, this application provides a verification system, including: two cache consistency slave device verification units, each configured with a main address region and a mirror address region, wherein the mirror data in the mirror address region of one cache consistency slave device verification unit is the data in the main address region of the other cache consistency slave device verification unit; wherein, when a mirroring operation is triggered between the two cache consistency slave device verification units, the correctness of the mirror data in the mirror address region is verified; the verification is determined by comparing the data in the main address region of one cache consistency slave device verification unit with the mirror data in the mirror address region of the other cache consistency slave device verification unit.
[0031] As can be seen, the verification system provided in this application includes two cache consistency slave device verification units configured with a main address region and a mirror address region. When a mirroring operation between the two cache consistency slave device verification units is triggered, data can be synchronized between the main address region of one cache consistency slave device verification unit and the mirror address region of the other cache consistency slave device verification unit. Then, the data in the main address region of one cache consistency slave device verification unit is compared with the mirrored data in the mirrored address region of the other cache consistency slave device verification unit to verify the correctness of the mirrored data in the mirrored address region. This avoids the complex process in traditional verification, reduces verification overhead in all aspects, and improves the verification efficiency of the memory address mirroring function.
[0032] Meanwhile, by triggering a mirroring operation between two cache consistency slave verification units and comparing the data in the main address region of one cache consistency slave verification unit with the mirrored data in the mirrored address region of another cache consistency slave verification unit, this application can promptly detect problems in the memory address mirroring function, such as data inconsistency or mirroring operation failure, thereby improving the completeness and reliability of the verification.
[0033] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.
[0034] The verification system provided in this application includes two cache consistency slave units (CS). Each cache consistency slave unit is configured with a main address area and a mirror address area. The mirror data in the mirror address area of one cache consistency slave unit is the data in the main address area of the other cache consistency slave unit. Specifically, when a mirroring operation is triggered between two cache consistency slave device verification units, the correctness of the mirrored data in the mirrored address region is verified. The verification is determined by comparing the data in the main address region of one cache consistency slave device verification unit with the mirrored data in the mirrored address region of the other cache consistency slave device verification unit.
[0035] like Figure 1 As shown, each cache consistency verification unit can manage its own memory (e.g., Dynamic Random Access Memory, also known as DRAM) through a Memory Management Unit (UMC, Universal Memory Controller). For example, CS0 manages its own memory DRAM0 through Memory Management Unit UMC0; CS1 manages its own memory DRAM1 through Memory Management Unit UMC1. The Memory Management Unit can invoke the Golden Model to ensure the reliability of the memory management function. The Golden Model is a proven and correct reference model.
[0036] The main address region of a cache coherence slave verification unit is a preset region in the memory of that cache coherence slave verification unit, and the addresses in this region have corresponding copies in the mirror address region of another cache coherence slave verification unit. For example, the main address region of CS0 is a preset region in DRAM0, and the addresses in this region have corresponding copies in the mirror address region of CS1; the main address region of CS1 is a preset region in DRAM1, and the addresses in this region have corresponding copies in the mirror address region of CS0.
[0037] The mirror address region of a cache coherency slave device verification unit is a region outside the memory of that cache coherency slave device verification unit. For example, the mirror address region of CS0 is a region outside DRAM0, and the mirror address region of CS1 is a region outside DRAM1.
[0038] In a concrete implementation, each cache consistency verification unit can set a set of address registers, such as DramBaseAddress 0-5 and DramLimitAddress 0-5, to configure the primary address region and the mirror address region. By setting the values of these registers, the start and end addresses of different types of memory spaces can be defined, thereby determining the range of each region in memory.
[0039] For example, DramBaseAddress 0 / 1 and DramLimitAddress 0 / 1 can indicate ordinary memory areas used to store regular data and program code. DramBaseAddress 2 / 3 and DramLimitAddress 2 / 3 can indicate mirrored address areas. A mirrored address area of one CS is used to store a copy of the primary address area of another CS; it is a backup area for data mirroring. For example, the mirrored address area of CS0 stores a copy of the primary address area of CS1, and the mirrored address area of CS1 stores a copy of the primary address area of CS0. DramBaseAddress 4 / 5 and DramLimitAddress 4 / 5 can indicate primary address areas.
[0040] Understandably, this application can achieve systematic traversal of the memory address space by dynamically constraining the value range of the randomized address registers DramBaseAddress and DramLimitAddress, so that all addresses can be effectively traversed, thereby quickly and efficiently verifying the processor's ability to access mirror addresses.
[0041] The verification system provided in this application includes two cache consistency slave device verification units configured with a main address region and a mirror address region. When a mirroring operation between the two cache consistency slave device verification units is triggered, data can be synchronized between the main address region of one cache consistency slave device verification unit and the mirror address region of the other cache consistency slave device verification unit. Then, the data in the main address region of one cache consistency slave device verification unit is compared with the mirrored data in the mirrored address region of the other cache consistency slave device verification unit to verify the correctness of the mirrored data in the mirrored address region. This avoids the complex process in traditional verification, reduces verification overhead in all aspects, and improves the verification efficiency of memory address mirroring function.
[0042] Meanwhile, by triggering a mirroring operation between two cache consistency slave verification units and comparing the data in the main address region of one cache consistency slave verification unit with the mirrored data in the mirrored address region of another cache consistency slave verification unit, this application can promptly detect problems in the memory address mirroring function, such as data inconsistency or mirroring operation failure, thereby improving the completeness and reliability of the verification.
[0043] refer to Figure 2 , Figure 2 This is a schematic diagram of an optional flow of the verification method provided in an embodiment of this application. The verification method is applied to the verification system described above, such as... Figure 2 As shown, the verification method may include the following steps: Step S100 triggers a mirroring operation between the two cache consistency verification units.
[0044] In an optional implementation, the step of triggering a mirroring operation between two cache consistency slave verification units may include: if an access request sent by the processor to either cache consistency slave verification unit hits the main address region of that cache consistency slave verification unit, then a mirroring operation between the two cache consistency slave verification units is triggered. That is, when data changes in the main address region of one cache consistency slave verification unit, a mirroring operation between the two cache consistency slave verification units is triggered to update the mirrored data in the mirrored address region of the other cache consistency slave verification unit in a timely manner.
[0045] In an optional implementation, when the access request is a write request, a mirroring operation between the two cache consistency slave device verification units is triggered. Specifically, the cache consistency slave device verification unit writes the write data corresponding to the write request into the main address area corresponding to the write request, and forwards the mirrored write request and mirrored write data to another cache consistency slave device verification unit, so that the other cache consistency slave device verification unit writes the mirrored write data into the mirrored address area corresponding to the mirrored write request.
[0046] For details, please refer to Figure 3The exemplary schematic diagram illustrates an optional flow for triggering a mirrored write request. If a write request sent by the processor (e.g., the CPU) to any cache coherence slave verification unit hits the main address region of that cache coherence slave verification unit, a mirroring operation between the two cache coherence slave verification units is triggered. The cache coherence slave verification unit initiating the mirroring operation can be referred to as the Master CS, and its memory management unit can be referred to as the Master UMC; the cache coherence slave verification unit receiving the mirroring operation can be referred to as the Slave CS, and its memory management unit can be referred to as the Slave UMC.
[0047] The cache consistency verification unit, Master CS, can write the write data corresponding to the write request to the main address area (write dram0) corresponding to the write request via Master UMC, storing the data in local memory. Simultaneously, Master CS forwards the mirror write request and mirror write data to Slave CS, enabling Slave CS to write the mirror write data to the mirror address area (write dram1) corresponding to the mirror write request via Slave UMC, achieving data backup. After writing the mirror write data to the mirror address area of Slave CS, Slave UMC sends a write response to Slave CS to confirm successful writing. Upon receiving the write response from Slave UMC, Slave CS further sends a write response to Master CS to confirm the completion of the entire mirror write operation.
[0048] In an optional implementation, when the access request is a read request, a mirroring operation between two cache consistency slave device verification units is triggered. Specifically, the cache consistency slave device verification unit reads the data in the main address region corresponding to the read request. If the read data contains errors, the mirrored read request is forwarded to another cache consistency slave device verification unit, so that the other cache consistency slave device verification unit reads the mirrored data in the mirrored address region corresponding to the mirrored read request and feeds back the mirrored data to the cache consistency slave device verification unit.
[0049] For details, please refer to Figure 4The exemplary schematic diagram illustrates an optional process for triggering a mirror read request. If a read request sent by the processor CPU to any cache coherence slave verification unit hits the main address region of that cache coherence slave verification unit, a mirroring operation between the two cache coherence slave verification units is triggered. The cache coherence slave verification unit, Master CS, can read the data in the main address region read dram0 corresponding to the read request through Master UMC, attempting to obtain the required data from local memory. If an error exists in the read data, Master CS forwards the mirror read request to Slave CS, enabling Slave CS to read the mirror data in the mirror address region read dram1 corresponding to the mirror read request through Slave UMC, and then feeds back the mirror data to Master CS, thus realizing the reading of mirror data. Simultaneously, Slave UMC sends a read response to Slave CS to confirm that the mirror data has been successfully read. After receiving the read response from the Slave UMC, the Slave CS will send a read response to the Master CS to confirm that the entire mirror read operation has been completed.
[0050] Understandably, this application can trigger mirroring operations between two cache consistency verification units (Master CS and Slave CS) by sending read / write requests to the verification system as test stimuli. The read / write requests simulate typical memory access patterns of a real processor, including sequential access, concurrent access, and conflicting access scenarios. By constructing diverse combinations of read and / or write requests, the correctness, consistency, and performance of the memory address mirroring function under different load conditions can be comprehensively verified, ensuring that the memory address mirroring function can operate reliably in a real system environment.
[0051] In an optional implementation, mirror write requests and mirror write data can be forwarded to another cache consistency slave verification unit via a forward sequence; alternatively, mirror read requests can be forwarded to another cache consistency slave verification unit via a forward sequence. For example, the Master CS can forward mirror write requests and mirror write data to the Slave CS via a forward sequence; the Master CS can also forward mirror read requests to the Slave CS via a forward sequence.
[0052] In an optional implementation, two queues, `mirror_req` and `mirror_dat`, can be set up in the verification process of the cache consistency slave device verification unit. The `mirror_req` queue stores mirror read requests and mirror write requests, while the `mirror_dat` queue stores mirror write data. When any cache consistency slave device verification unit triggers a mirror write request, it can pop the corresponding mirror write request from the `mirror_req` queue and simultaneously pop the corresponding mirror write data from the `mirror_dat` queue. Then, it forwards the popped mirror write request and mirror write data to another cache consistency slave device verification unit. Similarly, when any cache consistency slave device verification unit triggers a mirror read request, it can pop the corresponding mirror read request from the `mirror_req` queue and forward the popped mirror read request to another cache consistency slave device verification unit.
[0053] refer to Figure 2 Continue executing step S200, compare the data in the main address region of one cache consistency slave device verification unit with the mirror data in the mirror address region of another cache consistency slave device verification unit to verify the correctness of the mirror data in the mirror address region.
[0054] When an access request sent to any cache consistency slave verification unit hits the primary address area of that cache consistency slave verification unit, that cache consistency slave verification unit will forward the mirror access request to the mirror address area of another cache consistency slave verification unit. For example, if an access request sent to CS0 hits the primary address area of CS0, CS0 will forward the mirror access request to the mirror address area of CS1, where the data backup read or write operation will be completed.
[0055] Subsequently, the correctness of the mirrored data in the mirrored address region can be verified by comparing the data in the main address region of the cache consistency slave device verification unit CS0 with the mirrored data in the mirrored address region of another cache consistency slave device verification unit CS1, thus ensuring the consistency of data between the two CSs.
[0056] As can be seen, the verification method provided in this application, by triggering a mirroring operation between two cache consistency slave device verification units, enables data to be synchronized between the main address region of one cache consistency slave device verification unit and the mirror address region of the other cache consistency slave device verification unit. Then, the data in the main address region of one cache consistency slave device verification unit is compared with the mirrored data in the mirrored address region of the other cache consistency slave device verification unit to verify the correctness of the mirrored data in the mirrored address region. This avoids the complex process in traditional verification, reduces verification overhead in all aspects, and improves the verification efficiency of memory address mirroring function.
[0057] Meanwhile, by triggering a mirroring operation between two cache consistency slave verification units and comparing the data in the main address region of one cache consistency slave verification unit with the mirrored data in the mirrored address region of another cache consistency slave verification unit, this application can promptly detect problems in the memory address mirroring function, such as data inconsistency or mirroring operation failure, thereby improving the completeness and reliability of the verification.
[0058] The verification apparatus provided in the embodiments of this application will be described below. The verification apparatus described below can be considered as a software or hardware functional module required to implement the verification method provided in the embodiments of this application. The content of the verification apparatus described below can be referred to in correspondence with the content of the method described above.
[0059] In the optional implementation, Figure 5 An exemplary schematic diagram of an optional structure of the verification device provided in an embodiment of this application is shown. The verification device is applied to the verification system described above. Figure 5 As shown, the verification device may include: Trigger module 11 is used to trigger a mirroring operation between two cache consistency verification units; The comparison module 12 is used to compare the data in the main address region of one cache consistency slave device verification unit with the mirror data in the mirror address region of another cache consistency slave device verification unit in order to verify the correctness of the mirror data in the mirror address region.
[0060] Optionally, the triggering module 11 is used to trigger a mirroring operation between two cache consistency slave device verification units, including: If an access request sent by the processor to either cache coherency slave verification unit hits the main address region of that cache coherency slave verification unit, a mirroring operation between the two cache coherency slave verification units is triggered.
[0061] Optionally, when the access request is a write request, a mirroring operation is triggered between the two cache consistency verification units, specifically: The cache consistency slave device verification unit writes the write data corresponding to the write request into the main address area corresponding to the write request, and forwards the mirror write request and mirror write data to another cache consistency slave device verification unit, so that the other cache consistency slave device verification unit writes the mirror write data into the mirror address area corresponding to the mirror write request.
[0062] Optionally, when the access request is a read request, a mirroring operation is triggered between the two cache consistency verification units, specifically: The cache consistency slave device verification unit reads data from the main address region corresponding to the read request. If the read data contains errors, the mirror read request is forwarded to another cache consistency slave device verification unit so that the other cache consistency slave device verification unit reads the mirror data from the mirror address region corresponding to the mirror read request and feeds back the mirror data to the cache consistency slave device verification unit.
[0063] Optionally, the mirror write request and mirror write data can be forwarded to another cache consistency slave verification unit via a forwarding sequence; or, The mirror read request is forwarded to another cache consistency slave verification unit via a forwarding sequence.
[0064] This application also provides a verification platform, which includes the verification system described above, for performing the verification method described above.
[0065] This application also provides an electronic device that may include at least one memory and at least one processor. The memory stores one or more computer-executable instructions, and the processor invokes the one or more computer-executable instructions to execute the verification method provided in this application.
[0066] As an optional implementation, refer to Figure 6 , Figure 6 This is an optional block diagram of the electronic device provided in the embodiments of this application. For example... Figure 6 As shown, the electronic device may include at least one processor 21, at least one communication interface 22, at least one memory 23, and at least one communication bus 24.
[0067] In this embodiment, the number of processor 21, communication interface 22, memory 23 and communication bus 24 is at least one, and processor 21, communication interface 22 and memory 23 communicate with each other through communication bus 24.
[0068] Optionally, the processor 21 may be a CPU (Central Processing Unit), GPU (Graphics Processing Unit), NPU (Neural-network Processing Unit), FPGA (Field Programmable Gate Array), TPU (Tensor Processing Unit), AI chip, ASIC (Application Specific Integrated Circuit), or one or more integrated circuits configured to implement the embodiments of this application.
[0069] Optionally, the communication interface 22 can be an interface for a communication module used for network communication.
[0070] The memory 23 may include high-speed RAM, and may also include non-volatile memory, such as at least one disk storage device. The memory 23 stores one or more computer-executable instructions, which the processor 21 invokes to execute the verification method provided in this application embodiment.
[0071] This application also provides a storage medium that stores one or more computer-executable instructions. When the one or more computer-executable instructions are executed, the verification method provided in this application is implemented.
[0072] This application also provides a computer program product, which may include one or more computer-executable instructions. When the one or more computer-executable instructions are executed, they implement the verification method provided in this application.
[0073] The foregoing describes multiple embodiment schemes provided by the embodiments of this application. The optional methods described in each embodiment scheme can be combined and cross-referenced with each other without conflict, thereby extending to a variety of possible embodiment schemes. These can all be considered as the embodiment schemes disclosed and published by the embodiments of this application.
[0074] While the embodiments disclosed above are described in this application, this application is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of this application; therefore, the scope of protection of this application should be determined by the scope defined in the claims.
Claims
1. A verification system, characterized in that, include: Two cache consistency slave verification units are configured, each with a primary address region and a mirror address region. The mirror data in the mirror address region of one cache consistency slave verification unit is the data in the primary address region of the other cache consistency slave verification unit. Specifically, when a mirroring operation is triggered between two cache consistency slave device verification units, the correctness of the mirrored data in the mirrored address region is verified. The verification is determined by comparing the data in the main address region of one cache consistency slave device verification unit with the mirrored data in the mirrored address region of the other cache consistency slave device verification unit.
2. The verification system according to claim 1, characterized in that, The main address region of the cache consistency slave verification unit is a preset region in the memory of the cache consistency slave verification unit, and the addresses in this region have corresponding copies in the mirror address region of another cache consistency slave verification unit; The cache consistency mirror address region of the device verification unit is the region outside the memory of the cache consistency mirror unit.
3. The verification system according to claim 2, characterized in that, Each cache consistency unit manages its own memory through the memory management unit.
4. A verification method, characterized in that, Applied to the verification system as described in any one of claims 1-3, the method comprises: Trigger a mirroring operation between two cache consistency verification units; The data in the main address region of one cache consistency slave device verification unit is compared with the mirrored data in the mirrored address region of another cache consistency slave device verification unit to verify the correctness of the mirrored data in the mirrored address region.
5. The verification method according to claim 4, characterized in that, The step of triggering the mirroring operation between the two cache consistency verification units includes: If an access request sent by the processor to either cache coherency slave verification unit hits the main address region of that cache coherency slave verification unit, a mirroring operation between the two cache coherency slave verification units is triggered.
6. The verification method according to claim 5, characterized in that, When the access request is a write request, a mirroring operation is triggered between the two cache consistency verification units, specifically: The cache consistency slave device verification unit writes the write data corresponding to the write request into the main address area corresponding to the write request, and forwards the mirror write request and mirror write data to another cache consistency slave device verification unit, so that the other cache consistency slave device verification unit writes the mirror write data into the mirror address area corresponding to the mirror write request.
7. The verification method according to claim 5, characterized in that, When the access request is a read request, a mirroring operation is triggered between the two cache consistency verification units, specifically: The cache consistency slave device verification unit reads data from the main address region corresponding to the read request. If the read data contains errors, the mirror read request is forwarded to another cache consistency slave device verification unit so that the other cache consistency slave device verification unit reads the mirror data from the mirror address region corresponding to the mirror read request and feeds back the mirror data to the cache consistency slave device verification unit.
8. The verification method according to claim 6 or 7, characterized in that, The mirror write request and mirror write data are forwarded to another cache consistency slave verification unit via a forwarding sequence; or... The mirror read request is forwarded to another cache consistency slave verification unit via a forwarding sequence.
9. A verification device, characterized in that, Applied to the verification system as described in any one of claims 1 to 3, the apparatus comprises: The triggering module is used to trigger a mirroring operation between two cache consistency verification units. The comparison module is used to compare the data in the main address region of one cache consistency slave device verification unit with the mirrored data in the mirrored address region of another cache consistency slave device verification unit in order to verify the correctness of the mirrored data in the mirrored address region.
10. A verification platform, characterized in that, The verification platform includes the verification system as described in any one of claims 1 to 3, for performing the verification method as described in any one of claims 4 to 8.
11. An electronic device, characterized in that, It includes at least one memory and at least one processor, the memory storing one or more computer-executable instructions, and the processor invoking the one or more computer-executable instructions to perform the verification method as described in any one of claims 4 to 8.
12. A storage medium, characterized in that, The storage medium stores one or more computer-executable instructions, which, when executed, implement the verification method as described in any one of claims 4 to 8.
13. A computer program product, characterized in that, It includes one or more computer-executable instructions, which, when executed, implement the verification method as described in any one of claims 4 to 8.