Communication method, electronic device, computer-readable storage medium, and program product

Abstract

This application relates to the field of electronic device technology, providing a communication method, electronic device, computer-readable storage medium, and program product, applied to an electronic device including an SDIO controller and multiple SDIO modules; each SDIO module establishes a first connection with the SDIO controller through a common SDIO interface and a shared SDIO bus, and establishes a second connection with the SDIO controller through other interfaces; each SDIO module includes a first state and a second state; the method includes: if the SDIO controller receives a first signal indicating SDIO data communication with the second SDIO module in the second state, it terminates the SDIO data communication with the first SDIO module in the first state and controls the first SDIO module to switch to the second state; then, the SDIO controller controls the second SDIO module to switch back to the first state through the second connection, and after the state switch, it performs SDIO data communication with the second SDIO module in the first state through the first connection. Thus, by using the two connections in combination, more functions can be implemented based on a single SDIO interface.

Description

Technical Field

[0001] This application relates to the field of electronic device technology, and in particular to a communication method, electronic device, computer-readable storage medium, and program product. Background Technology

[0002] Secure Digital Input / Output (SDIO) is a high-speed peripheral interface developed from non-volatile memory card interfaces. Simultaneously, with the development of electronic devices and the enhancement of their functions, electronic devices can offer increasingly more extended features, including more features that rely on SDIO interfaces. However, the available SDIO interfaces provided by the chip platforms of existing electronic devices are limited, resulting in some functions being unable to be implemented due to constraints in communication interface resources. Summary of the Invention

[0003] This application provides a communication method, electronic device, computer-readable storage medium, and program product that can expand and implement more special functions in scenarios where the available SDIO interface is limited, thereby avoiding the problem of limited communication interface resources affecting the implementation of functions.

[0004] To achieve the above objectives, the embodiments of this application adopt the following technical solutions:

[0005] In a first aspect, a communication method is provided, applied to an electronic device; the electronic device includes a Secure Input / Output (SDIO) controller and at least two SDIO modules; the at least two SDIO modules establish a first connection with the SDIO controller through the same SDIO interface and a shared SDIO bus; the at least two SDIO modules establish a second connection with the SDIO controller through different first interfaces; wherein the SDIO modules include a first state and a second state, in which the first connection is communicable and in which the first connection is not communicable in the second state; the method includes: the SDIO controller performing SDIO data communication with the first SDIO module through the first connection, the first SDIO module being in the first state; the SDIO controller receiving a first signal, the first signal indicating that the SDIO controller is performing SDIO data communication with the second SDIO module, the second SDIO module being in the second state; the SDIO controller responding to the first signal terminating the SDIO data communication with the first SDIO module and controlling the first SDIO module to switch to the second state; the SDIO controller controlling the second SDIO module to switch back to the first state through the second connection, the SDIO controller performing SDIO data communication with the second SDIO module in the first state through the first connection.

[0006] In this implementation, the SDIO controller establishes two connections with each SDIO module. The first connection, established through the same SDIO interface of the SDIO controller and a shared SDIO bus, is used for SDIO data communication. The second connection (established based on the first interface), in addition to the SDIO bus connection, is used to control the state of the SDIO module. By using these two connections in a time-sharing manner to control multiple connected SDIO modules, one-to-one SDIO data communication can be successfully achieved even with multiple modules connected. This not only avoids communication interference but also ensures that each SDIO module can successfully perform its corresponding function through the SDIO interface without violating the one-to-one SDIO data communication constraint. Based on this, even with limited communication interface resources, more extended functions can be implemented.

[0007] In one possible implementation of the first aspect, the first interface includes a general-purpose input / output (GPIO) interface.

[0008] In this implementation, by utilizing the existing GPIO interfaces on the SDIO controller and SDIO module to establish a second connection outside the SDIO bus, a new connection can be established outside the SDIO bus without adding any additional hardware, thereby avoiding an increase in hardware costs.

[0009] In one possible implementation of the first aspect, communication via the second connection is unaffected by state, so the first signal can be sent directly by the SDIO module. Therefore, the SDIO controller receiving the first signal may include: the SDIO controller receiving the first signal from the second SDIO module via the second connection.

[0010] In one possible implementation of the first aspect, the SDIO controller, in response to a first signal, terminates SDIO data communication with the first SDIO module and controls the first SDIO module to switch to a second state, including: the SDIO controller stops SDIO data communication with the first SDIO module in response to the first signal; the SDIO controller sends a second signal to the first SDIO module through a second connection, and controls the first SDIO module to stop SDIO data communication and switch to the second state through the second signal.

[0011] In this implementation, the SDIO controller first stops SDIO data communication with the first SDIO module, and then controls the first SDIO module to stop SDIO data communication and switch states through the second connection, thereby ensuring that both communicating parties can end SDIO data communication and avoid affecting the SDIO data communication of the second SDIO module.

[0012] In one possible implementation of the first aspect, the SDIO controller, in response to a first signal, terminates SDIO data communication with the first SDIO module and controls the first SDIO module to switch to a second state, including: the SDIO controller, in response to the first signal, sends a second signal to the first SDIO module through a first connection, and controls the first SDIO module to stop SDIO data communication and switch to the second state through the second signal; the SDIO controller stops SDIO data communication with the first SDIO module.

[0013] In this implementation, since both the first and second connections between the first SDIO module and the SDIO controller are available when the first signal is received, the SDIO controller can first control the first SDIO module to stop SDIO data communication and switch its state via the first connection, and then automatically stop SDIO data communication with the first SDIO module. This also allows for a smooth termination of SDIO data communication with the first SDIO module, avoiding interference with SDIO data communication with the second SDIO module.

[0014] In one possible implementation of the first aspect, the SDIO controller controls the second SDIO module to switch to a first state via a second connection, and the SDIO controller performs SDIO data communication with the second SDIO module in the first state via a first connection, including: after the first SDIO module switches to the second state, the SDIO controller sends a third signal to the second SDIO module via the second connection, and controls the second SDIO module to switch back to the first state via the third signal; after the SDIO controller receives a fourth signal from the second SDIO module in the first state via the second connection or the first connection, the SDIO controller performs SDIO data communication with the second SDIO module via the first connection.

[0015] In this implementation, the SDIO controller controls the second SDIO module to switch states via a third signal. Based on a fourth signal sent by the SDIO controller indicating a successful switch to the first state, SDIO data communication with the second SDIO module then occurs via the first connection to ensure reliable communication. Furthermore, because the second SDIO module switches to the first state immediately after the third signal is sent, both the first and second connections of the second SDIO module are available before the fourth signal is sent. Therefore, the fourth signal can be sent via either the first or second connection.

[0016] In one possible implementation of the first aspect, the communication method further includes: after receiving a fifth signal sent by the first SDIO module through the second connection, the SDIO controller determines that the first SDIO module has switched from the first state to the second state.

[0017] In this implementation, after the first SDIO module switches to the second state, it can also send a notification signal indicating successful state switching, i.e., send a fifth signal. Upon receiving the fifth signal, the SDIO controller then establishes SDIO data communication with the second SDIO module, ensuring communication reliability and preventing unexpected communication interference. Simultaneously, since the first SDIO module in the second state only has a second connection for communication, sending the fifth signal through the second connection ensures the accuracy of signal transmission.

[0018] In one possible implementation of the first aspect, the primary purpose of the signals sent via the second connection / first connection is to interrupt the ongoing SDIO data communication by the SDIO controller and switch to SDIO data communication with another SDIO module. Therefore, the transmission of each signal can be specifically implemented using an interrupt output signal and a clock gating signal. Based on this, the first, fourth, and fifth signals are triggered by switching the signal state of the interrupt output signal; the second and third signals are triggered by switching the signal state of the clock gating signal. Specifically, the second signal controls the first SDIO module to stop SDIO data communication and switch to the second state; the third signal controls the second SDIO module to switch to the first state; the fourth signal notifies the SDIO controller that the second SDIO module has switched to the first state; and the fifth signal notifies the SDIO controller that the first SDIO module has switched to the second state.

[0019] In one possible implementation of the first aspect, to ensure the accuracy of the state switching control of each SDIO module, different SDIO modules establish a second connection through different GPIO interfaces. Based on this, different SDIO modules can correspond to different interrupt output signals and clock gating signals. That is, the first SDIO module corresponds to the first interrupt output signal and the first clock gating signal; the second SDIO module corresponds to the second interrupt output signal and the second clock gating signal; and the signal states include high-level and low-level states. Therefore, the triggering of each signal can specifically include: the first signal being triggered by switching the second interrupt output signal to a high-level state; the fourth signal being triggered by switching the second interrupt output signal to a low-level state; the fifth signal being triggered by switching the first interrupt output signal to a high-level state, and then switching the first interrupt output signal to a low-level state after a preset delay; the second signal being triggered by switching the first clock gating signal to a high-level state; and the third signal being triggered by switching the second clock gating signal to a low-level state.

[0020] In one possible implementation of the first aspect, the SDIO controller includes an interrupt register, wherein the bit in the interrupt register corresponding to the second SDIO module is set when the first signal is received; the communication method further includes resetting the bit in the interrupt register corresponding to the second SDIO module.

[0021] In this implementation, since the SDIO controller is connected to multiple different SDIO modules through the same SDIO interface, and these different SDIO modules are in a state where they need to perform SDIO data communication at any time due to actual business needs, the SDIO controller is in a state where it needs to respond to the interrupts of each SDIO module at any time. Based on this, the interrupt register can facilitate the SDIO controller to record interrupt request information and realize interrupt management and response.

[0022] In one possible implementation of the first aspect, the SDIO controller, in response to a first signal, terminates SDIO data communication with the first SDIO module and controls the first SDIO module to switch to a second state, including: when the service priority of the second SDIO module is higher than the service priority of the first SDIO module, the SDIO controller, in response to the first signal, terminates SDIO data communication with the first SDIO module and controls the first SDIO module to switch to the second state; when the service priority of the second SDIO module is lower than the service priority of the first SDIO module, after completing SDIO data communication with the first SDIO module, the SDIO controller, in response to the first signal, controls the first SDIO module to switch to the second state.

[0023] In this implementation, deciding whether to immediately terminate SDIO data communication based on business priority ensures that important services are not suddenly interrupted and affect the normal operation of electronic devices, thereby improving the user experience.

[0024] In one possible implementation of the first aspect, the communication method further includes: after the electronic device is powered on, the SDIO controller receives an initialization request from each SDIO module according to a preset initialization sequence, and the SDIO controller completes the initialization of each SDIO module in response to the initialization request; wherein, according to the initialization sequence, the SDIO controller receives the initialization request of the next SDIO module after the initialization of the previous SDIO module is completed.

[0025] In this implementation, the initialization of each SDIO module can be completed sequentially when the device is powered on, thus ensuring that each SDIO module only needs to be initialized once.

[0026] In one possible implementation of the first aspect, the communication method further includes: the SDIO controller receiving an initialization request from the SDIO module before engaging in SDIO data communication with the SDIO module, and initializing the SDIO module in response to the initialization request. In this implementation, the initialization of each SDIO module can also be performed before SDIO data communication, provided the first connection is communicable. In this way, initialization is required for each SDIO data communication.

[0027] In one possible implementation of the first aspect, at any given time, only one SDIO module is in the first state; at any given time, only one SDIO module communicates with the SDIO controller for SDIO data. This ensures that SDIO data communication is one-to-one, thus adhering to the one-to-one communication principle of SDIO.

[0028] In one possible implementation of the first aspect, at least two SDIO modules are used to implement one or more functions among Bluetooth, Wi-Fi, GPS, and satellite communication. For example, the first SDIO module is an SDIO module that implements Wi-Fi functionality, and the second SDIO module is an SDIO module that implements satellite communication functionality.

[0029] Secondly, this application provides an electronic device, comprising: one or more processors and a memory, the processor including an SDIO controller; the electronic device further comprising at least two SDIO modules, the SDIO controller being connected to the SDIO modules; the memory being coupled to the processor; the memory storing one or more computer program codes, the computer program codes including computer instructions; when the processor executes the computer instructions, the electronic device performs the following steps:

[0030] The SDIO controller communicates with the first SDIO module via a first connection, and the first SDIO module is in a first state. The SDIO controller receives a first signal, which instructs the SDIO controller to communicate with the second SDIO module via a second connection, and the second SDIO module is in a second state. In response to the first signal, the SDIO controller terminates the SDIO data communication with the first SDIO module and controls the first SDIO module to switch to the second state. The SDIO controller controls the second SDIO module to switch back to the first state via a second connection, and the SDIO controller communicates with the second SDIO module in the first state via the first connection.

[0031] In one possible implementation of the second aspect, the first connection is established through an SDIO interface, and the second connection is established through a first interface, which includes a general purpose input / output (GPIO) interface.

[0032] In one possible implementation of the second aspect, when the aforementioned computer instructions are executed by the processor, the electronic device further performs the following steps: the SDIO controller receives a first signal from the second SDIO module via a second connection.

[0033] In one possible implementation of the second aspect, when the aforementioned computer instructions are executed by the processor, the electronic device further performs the following steps: the SDIO controller stops SDIO data communication with the first SDIO module in response to the first signal; the SDIO controller sends a second signal to the first SDIO module through the second connection, and controls the first SDIO module to stop SDIO data communication and switch to the second state through the second signal.

[0034] In one possible implementation of the second aspect, when the aforementioned computer instructions are executed by the processor, the electronic device further performs the following steps: the SDIO controller, in response to the first signal, sends a second signal to the first SDIO module via the first connection, and controls the first SDIO module to stop SDIO data communication and switch to the second state via the second signal; the SDIO controller stops SDIO data communication with the first SDIO module.

[0035] In one possible implementation of the second aspect, when the aforementioned computer instructions are executed by the processor, the electronic device further performs the following steps: after the first SDIO module switches to the second state, the SDIO controller sends a third signal to the second SDIO module through the second connection, and controls the second SDIO module to switch to the first state through the third signal; after the SDIO controller receives a fourth signal from the second SDIO module that has switched to the first state through the second connection or the first connection, the SDIO controller performs SDIO data communication with the second SDIO module through the first connection.

[0036] In one possible implementation of the second aspect, when the aforementioned computer instructions are executed by the processor, the electronic device further performs the following steps: after receiving a fifth signal sent by the first SDIO module through the second connection, the SDIO controller determines that the first SDIO module has switched from the first state to the second state.

[0037] In one possible implementation of the second aspect, the first, fourth, and fifth signals are triggered by switching the signal state of the interrupt output signal; the second and third signals are triggered by switching the signal state of the clock gating signal; wherein, the second signal is used to control the first SDIO module to stop SDIO data communication and switch to the second state; the third signal is used to control the second SDIO module to switch to the first state; the fourth signal is used to notify the SDIO controller that the second SDIO module has switched to the first state; and the fifth signal is used to notify the SDIO controller that the first SDIO module has switched to the second state.

[0038] In one possible implementation of the second aspect, the first SDIO module corresponds to the first interrupt output signal and the first clock gating signal; the second SDIO module corresponds to the second interrupt output signal and the second clock gating signal; the signal states include a high-level state and a low-level state; the first signal is triggered by switching the second interrupt output signal to a high-level state, the fourth signal is triggered by switching the second interrupt output signal to a low-level state; the fifth signal is triggered by switching the first interrupt output signal to a high-level state, and after a preset delay, the first interrupt output signal is switched to a low-level state; the second signal is triggered by switching the first clock gating signal to a high-level state; and the third signal is triggered by switching the second clock gating signal to a low-level state.

[0039] In one possible implementation of the second aspect, the SDIO controller includes an interrupt register, in which the bit corresponding to the second SDIO module is set upon receiving a first signal; when the aforementioned computer instruction is executed by the processor, the electronic device further performs the following steps: resetting the bit corresponding to the second SDIO module in the interrupt register.

[0040] In one possible implementation of the second aspect, when the aforementioned computer instructions are executed by the processor, the electronic device further performs the following steps: when the service priority of the second SDIO module is higher than the service priority of the first SDIO module, the SDIO controller responds to the first signal, terminates the SDIO data communication with the first SDIO module, and controls the first SDIO module to switch to the second state; when the service priority of the second SDIO module is lower than the service priority of the first SDIO module, after completing the SDIO data communication with the first SDIO module, the SDIO controller responds to the first signal and controls the first SDIO module to switch to the second state.

[0041] In one possible implementation of the second aspect, when the aforementioned computer instructions are executed by the processor, the electronic device further performs the following steps: after the electronic device is powered on, the SDIO controller receives an initialization request from each SDIO module according to a preset initialization sequence, and the SDIO controller completes the initialization of each SDIO module in response to the initialization request; wherein, according to the initialization sequence, the SDIO controller receives the initialization request of the next SDIO module after the initialization of the previous SDIO module is completed; or, before engaging in SDIO data communication with the SDIO module, the SDIO controller receives the initialization request of the SDIO module and initializes the SDIO module in response to the initialization request.

[0042] In one possible implementation of the second aspect, at any given time, only one SDIO module is in the first state; at any given time, only one SDIO module communicates with the SDIO controller for SDIO data.

[0043] In one possible implementation of the second aspect, at least two SDIO modules are used to implement one or more functions of Bluetooth, Wi-Fi, GPS, and satellite communication.

[0044] Thirdly, embodiments of this application provide a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor in an electronic device, causes the electronic device to perform a communication method as described in the first aspect and any possible implementation thereof.

[0045] Fourthly, embodiments of this application provide a computer program product that, when run on a computer, causes the computer to perform the method as described in the first aspect and any possible implementation thereof. The computer may be the aforementioned electronic device.

[0046] Fifthly, embodiments of this application provide a chip, which includes an SDIO controller and an interface circuit; the interface circuit reads computer instructions stored in a memory and sends them to the SDIO controller; when the SDIO controller executes the computer instructions, the chip performs the communication method as described in any one of the first aspects.

[0047] Understandably, the beneficial effects achieved by the electronic device of any possible implementation of the second aspect, the computer-readable storage medium of the third aspect, the computer program product of the fourth aspect, and the chip of the fifth aspect can be referred to as the beneficial effects of the first aspect and any possible implementation thereof, which will not be repeated here. Attached Figure Description

[0048] Figure 1 A schematic diagram of a traditional SDIO interface connection;

[0049] Figure 2 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application;

[0050] Figure 3 A software structure block diagram of an electronic device provided in an embodiment of this application;

[0051] Figure 4 A connection diagram of a shared SDIO bus provided in an embodiment of this application;

[0052] Figure 5 A connection diagram illustrating a communication connection of an SDIO module provided in an embodiment of this application;

[0053] Figure 6 A schematic diagram of a GPIO signal provided in an embodiment of this application;

[0054] Figure 7 A schematic diagram of the interaction flow of a communication method provided in an embodiment of this application;

[0055] Figure 8 A schematic diagram illustrating the principle of SDIO module state switching provided in an embodiment of this application;

[0056] Figure 9 This is a structural block diagram of a chip system provided in an embodiment of this application. Detailed Implementation

[0057] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. In the description of the embodiments of this application, the terminology used in the following embodiments is for the purpose of describing specific embodiments only and is not intended to limit the application. Furthermore, to facilitate a clear description of the technical solutions of the embodiments of this application, the terms "first," "second," etc., are used in the embodiments of this application to distinguish identical or similar items with substantially the same function and effect. Those skilled in the art will understand that the terms "first," "second," etc., do not limit the quantity or execution order, and that "first," "second," etc., are not necessarily different. Also, in the description of the embodiments of this application, unless otherwise stated, "multiple" means two or more.

[0058] The SDIO interface is a high-speed peripheral interface developed based on the Secure Digital (SD) card interface. Therefore, the difference between the SDIO interface and the SD card interface is that the SDIO interface is compatible not only with SD cards but also with SDIO devices. SDIO devices are I / O devices that use the SD bus and SD commands; simply put, they are devices that communicate with the host through the SDIO interface.

[0059] In some embodiments, the SDIO device and the host can be two separate devices. For example, the host is a laptop computer, and the SDIO device is a wireless network card. After the laptop computer connects to the wireless network card through the SDIO interface, the laptop computer can access the Internet through the Wi-Fi module in the wireless network card.

[0060] In some embodiments, the SDIO device and the communication host can also be different modules of the same device. Therefore, in the embodiments of this application, the SDIO device can also be referred to as an SDIO module. For example, in electronic devices such as mobile phones and tablets, the host can be the processor / system-on-chip (SOC) of the electronic device, and commonly used SDIO modules in electronic devices include Bluetooth (BT) modules, Wi-Fi (wireless fidelity) modules, and Global Positioning System (GPS) modules.

[0061] In some embodiments, the SDIO module in an electronic device can also be called an SDIO card. The form factor and interface of the SDIO card are compatible with those of the SD card. The difference between the two is that the SD card can usually only perform storage functions, while the SDIO card can not only perform storage functions, but also has various built-in functional modules to achieve other corresponding functions.

[0062] For example, an SDIO card can have a built-in Bluetooth module for Bluetooth functionality, a built-in Wi-Fi module for Wi-Fi functionality, and a built-in GPS module for GPS functionality. Alternatively, an SDIO card can be understood as a chip in an electronic device that uses the SDIO interface to implement Bluetooth, Wi-Fi, and GPS functions. In other embodiments, the SDIO card can also have a built-in multi-functional module, allowing a single SDIO card to perform multiple functions simultaneously. For example, an SDIO card can have a built-in Bluetooth and Wi-Fi combined module to simultaneously implement Bluetooth and Wi-Fi functionality.

[0063] Currently, the number of SDIO interfaces provided by chip platforms in electronic devices, such as System-on-a-Chip (SoCs), is limited; in most cases, an SoC may only provide one SDIO interface. Furthermore, the SDIO interfaces provided by the SoC are currently configured with fixed applications. That is, the SDIO interface provided by the SoC is fixedly configured to only implement specific functions. For example, the SoC may provide one SDIO interface, and this SDIO interface may be fixedly configured to implement functions such as Bluetooth and Wi-Fi. At the same time, due to limitations in hardware resources and communication protocols, the SDIO interface can currently only communicate one-to-one with SDIO modules. In this situation, the electronic device cannot use this SDIO interface to expand and implement functions other than Bluetooth and Wi-Fi.

[0064] However, with the development of electronic devices and the enhancement of their functions, there is an increasing number of feature extensions in electronic devices. In other words, based on business and user needs, there is a demand for extended feature functions in electronic devices. For example, satellite communication (such as satellite phone) functions can be added to electronic devices. However, if the extended feature function relies on the SDIO interface, the limited number of SDIO interfaces, their fixed use of specific functions, and their one-to-one communication with SDIO modules prevent the extension of the feature function. This results in the extended feature function being unable to be implemented due to limited communication interface resources.

[0065] For example, Figure 1 A schematic diagram of a traditional SDIO interface connection is shown.

[0066] refer to Figure 1 In case (1), if the SOC provides only one SDIO interface (such as SDIO interface 1) and has two SDIO modules, SDIO card A and SDIO card B, the SDIO interface can only communicate one-to-one with the SDIO module. Therefore, if SDIO interface 1 is connected to SDIO card A, it cannot be connected to SDIO card B. In this case, the electronic device can only perform the function of SDIO card A and cannot perform the function of SDIO card B. Alternatively, if SDIO interface 1 is connected to SDIO card B, it cannot be connected to SDIO card A. In this case, the electronic device can only perform the function of SDIO card B and cannot perform the function of SDIO card A.

[0067] refer to Figure 1In case (2), when the SOC provides two SDIO interfaces (such as SDIO interface 1 and SDIO interface 2), and there are two SDIO modules, SDIO card A and SDIO card B, since the SDIO interface can only communicate one-to-one with the SDIO module, SDIO interface 1 and SDIO interface 2 can only be connected to one SDIO card respectively. Figure 1 As shown in Figure (2), SDIO interface 1 is connected to SDIO card A for communication, and SDIO interface 2 is connected to SDIO card B for communication. Of course, based on actual needs, SDIO interface 1 can also be connected to SDIO card B for communication, and SDIO interface 2 can be connected to SDIO card A for communication. This application embodiment does not limit this in any way.

[0068] Furthermore, because the SDIO interface is fixed to use specific functions, when communication interface resources are limited, it is usually still better to choose to connect and communicate with the SDIO card that implements the specific function with the fixed configuration.

[0069] For example, if Figure 1 SDIO card A is an SDIO module that implements specific functions with a fixed configuration, while SDIO card B is an SDIO module that implements extended functions. Thus, as... Figure 1 As shown in Figure (1), when SDIO interface 1 communicates with SDIO card A, the extended functions corresponding to SDIO card B cannot be implemented. Conversely, when SDIO interface 1 communicates with SDIO card B, the functions corresponding to SDIO card A cannot be implemented. Figure 1 As shown in (2), although SDIO interface 1 and SDIO interface 2 can connect and communicate with SDIO card A and SDIO card B respectively, enabling the functions corresponding to SDIO card A and SDIO card B to be implemented, if it is necessary to further expand the functionality of SDIO card C, the functionality of SDIO card C cannot be implemented because SDIO interface 1 and SDIO interface 2 are already occupied. Therefore, it can be seen that when electronic devices need to expand and implement more and more functions, but SDIO interfaces are limited, the expanded functions cannot be implemented due to the limited communication interface resources.

[0070] In summary, in traditional communication methods, when electronic devices need to use multiple SDIO modules, the limited communication interface resources prevent the expansion of SDIO modules from being realized.

[0071] To address the issue that the aforementioned extended functions cannot be implemented due to limited communication interface resources, this application provides a communication method. This communication method is applied to an electronic device. In this application embodiment, the electronic device includes an SDIO controller (i.e., a host) and at least two SDIO modules (such as at least two SDIO cards).

[0072] The main implementation principle of the communication method provided in this application embodiment is as follows: In electronic devices, through the SDIO bus sharing scheme, one host (i.e., SDIO controller) can communicate with multiple SDIO modules through a time-division multiplexing bus without affecting the original business applications, thereby solving the problem of limited communication interface resources that prevent the implementation of extended functions.

[0073] Specifically, the electronic device first enables multiple SDIO modules to share the SDIO bus, allowing one SDIO interface to connect to multiple SDIO modules (i.e., one-to-many connection). This physically allows one SDIO interface to establish SDIO connections with multiple SDIO modules (i.e., establishing the first connection). Then, because SDIO has a one-to-one communication limitation, to avoid communication interference caused by multiple connected SDIO modules simultaneously communicating with the host via the SDIO bus, the electronic device establishes a new connection between each SDIO module and the host outside the SDIO bus (i.e., establishing the second connection) through the first interface. It is understood that the first interface can be any existing interface capable of I / O communication; this application embodiment does not impose any limitations on it.

[0074] In one specific embodiment, considering hardware cost, the existing general-purpose input / output (GPIO) interfaces on the host and SDIO module can be directly utilized. An additional GPIO connection (i.e., a second connection) can be established outside the SDIO bus, meaning another GPIO connection can be established between the host and the SDIO module via the GPIO interface. This allows for the establishment of a new connection outside the SDIO bus without adding any hardware, thus avoiding increased hardware costs.

[0075] In other words, in this embodiment, there are two connections between the host and the SDIO module. Besides the existing SDIO interface and SDIO bus connection, there is an additional IO connection established through a first interface, such as the GPIO interface. Furthermore, one of these IO connections is implemented using the shared SDIO bus, and the other utilizes the module's existing conventional GPIO configuration. That is, both IO connections are established without adding any external devices, thus ensuring no additional hardware cost.

[0076] Next, the electronic device uses the added GPIO connection in conjunction with the existing SDIO connection, switching between different states of each SDIO module through time-sharing control to ensure that only one SDIO module can communicate with the host via SDIO data at any given time. Simply put, based on the actual business communication needs of each SDIO module, the newly added GPIO connection controls the switching of the SDIO module's state, ensuring that only one SDIO module is in a state where it can communicate via the SDIO bus (such as the first state). Then, this SDIO module that can communicate via the SDIO bus communicates with the host via the shared SDIO connection. In this way, because different SDIO modules are controlled in a time-sharing manner, the electronic device can successfully achieve one-to-one SDIO data communication even when multiple SDIO modules are connected. This not only avoids communication interference but also ensures that each SDIO module can successfully communicate with the host via the SDIO interface to achieve its corresponding function without violating the one-to-one SDIO data communication constraint.

[0077] Therefore, it can be seen that in the communication method provided in the embodiments of this application, even if the SOC only provides one SDIO interface, even if the communication interface resources are limited, even if the SDIO interface can only communicate one-to-one, the embodiments of this application can still implement more extended functions through this one SDIO interface without affecting the original business applications of SDIO, so that more extended functions can be implemented based on SDIO even when the communication interface resources are limited.

[0078] The aforementioned electronic devices may include at least one of the following: mobile phones, foldable electronic devices, tablet computers, desktop computers, laptop computers, handheld computers, laptops, ultra-mobile personal computers (UMPCs), netbooks, cellular phones, personal digital assistants (PDAs), augmented reality (AR) devices, virtual reality (VR) devices, artificial intelligence (AI) devices, wearable devices, in-vehicle devices, smart home devices, or smart city devices. This application does not impose any specific limitations on the type of electronic device described.

[0079] Figure 2 A schematic diagram of the structure of an electronic device is shown.

[0080] Electronic device 100 may include a processor 110 (i.e., a system-on-a-chip, SOC), an external memory interface 120, an internal memory 121, a universal serial bus (USB) connector 130, a charging management module 140, a power management module 141, a battery 142, antenna 1, antenna 2, a mobile communication module 150, a wireless communication module 160, an audio module 170, a speaker 170A, a receiver 170B, a microphone 170C, a headphone jack 170D, a sensor module 180, buttons 190, a motor 191, an indicator 192, a camera module 193, a display screen 194, and a subscriber identification module (SIM) card interface 195, etc. The sensor module 180 may include a pressure sensor, a gyroscope sensor, a barometric pressure sensor 180C, a magnetic sensor, an accelerometer, a distance sensor, a proximity sensor, a fingerprint sensor, a temperature sensor, a touch sensor, an ambient light sensor, a bone conduction sensor, etc.

[0081] like Figure 2 As shown in the embodiment of this application, the electronic device 100 further includes an SDIO interface and N ≥ 2 SDIO modules, where N is a positive integer. The SDIO interface establishes SDIO connections with these N SDIO modules through a shared SDIO bus.

[0082] It is understood that the structures illustrated in the embodiments of this application do not constitute a specific limitation on the electronic device. In other embodiments of this application, the electronic device may include more or fewer components than illustrated, or combine some components, or split some components, or have different component arrangements. The illustrated components may be implemented in hardware, software, or a combination of software and hardware.

[0083] Processor 110 (such as a system-on-a-chip (SoC)) may include one or more processing units, such as an SDIO controller, application processor (AP), modem processor, graphics processing unit (GPU), image signal processor (ISP), video codec, digital signal processor (DSP), baseband processor, and / or neural network processing unit (NPU). These different processing units may be independent devices or integrated into one or more processors. Processor 110 (i.e., the SoC) can generate operation control signals based on instruction opcodes and timing signals to control instruction fetching and execution.

[0084] In some embodiments, the processor 110 may include one or more interfaces, such as GPIO interfaces, inter-integrated circuit (I2C) interfaces, inter-integrated circuit sound (I2S) interfaces, pulse code modulation (PCM) interfaces, universal asynchronous receiver / transmitter (UART) interfaces, mobile industry processor interfaces (MIPI), subscriber identity module (SIM) interfaces, and / or universal serial bus (USB) interfaces.

[0085] The processor 110 can connect to modules such as SDIO module, touch sensor, audio module, wireless communication module, display screen, and camera module through at least one of the above interfaces.

[0086] In this embodiment, the SDIO controller in the processor 110 can specifically connect and communicate with the SDIO modules. Specifically, the SDIO controller can establish a first connection with multiple SDIO modules via the SDIO interface using a shared SDIO bus. Simultaneously, the SDIO controller can also establish a second connection with each of these multiple SDIO modules via the aforementioned GPIO interface. Then, the SDIO controller performs time-division control on these multiple SDIO modules based on the established first and second connections to achieve service communication with these multiple SDIO modules and realize more extended functions. In some embodiments, the SDIO module can be a functional module capable of implementing Bluetooth, Wi-Fi, GPS, satellite communication, etc. For example, the SDIO module can be a Bluetooth module, Wi-Fi module, GPS module, or satellite communication module that individually implements the corresponding functions. Alternatively, the SDIO module can also be a multi-functional module capable of implementing multiple functions, such as a Bluetooth and Wi-Fi combined functional module.

[0087] The processor 110 may also include a memory for storing instructions and data. In some embodiments, the memory in the processor 110 may be a cache memory. This memory can store instructions or data that the processor 110 has used or that are used frequently. If the processor 110, such as an SDIO controller, needs to use the instruction or data, it can directly retrieve it from this memory. This avoids repeated accesses, reduces the waiting time of the SDIO controller, and thus improves system efficiency.

[0088] It is understood that the interface connection relationships between the modules illustrated in the embodiments of this application are merely illustrative and do not constitute a structural limitation on the electronic device 100. In other embodiments of this application, the electronic device 100 may also employ different interface connection methods or combinations of multiple interface connection methods as described in the above embodiments.

[0089] The external storage interface 120 can be used to connect an external memory card, such as a Micro SD card, to expand the storage capacity of the electronic device 100. The external memory card communicates with the processor 110 through the external storage interface 120 to perform data storage functions. For example, it can save music, video, and other files to the external memory card, or transfer music, video, and other files from the electronic device to the external memory card.

[0090] Internal memory 121 can be used to store computer executable program code, including instructions. Internal memory 121 may include a program storage area and a data storage area. The program storage area may store the operating system, application programs required for at least one function (such as sound playback function, image playback function, etc.), etc. The data storage area may store data created during the use of electronic device 100 (such as audio data, phone book, etc.). In addition, internal memory 121 may include high-speed random access memory, and may also include non-volatile memory, such as at least one disk storage device, flash memory device, universal flash storage (UFS), etc. Processor 110 executes various functional methods or data processing of electronic device 100 by running instructions stored in internal memory 121 and / or instructions stored in memory disposed in the processor.

[0091] The charging management module 140 is used to receive charging input from the charger. The power management module 141 is used to connect the battery 142, and the charging management module 140 is connected to the processor 110. It receives input from the battery 142 and / or the charging management module 140 to supply power to the processor 110, internal memory 121, display screen 194, camera module 193, and wireless communication module 160, etc.

[0092] The wireless communication function of electronic device 100 can be realized through antenna 1, antenna 2, mobile communication module 150, wireless communication module 160, modem processor and baseband processor, etc.

[0093] The wireless communication module 160 can provide solutions for wireless communication applications on the electronic device 100, including wireless local area networks (WLAN) (such as Wi-Fi networks), Bluetooth, Bluetooth Low Energy (BLE), ultra-wideband (UWB), global navigation satellite system (GNSS), frequency modulation (FM), near field communication (NFC), and infrared (IR) technologies. The wireless communication module 160 can be one or more devices integrating at least one communication processing module. The wireless communication module 160 receives electromagnetic waves via antenna 2, performs frequency modulation and filtering of the electromagnetic wave signals, and sends the processed signal to processor 110. The wireless communication module 160 can also receive signals to be transmitted from processor 110, perform frequency modulation and amplification, and convert them into electromagnetic waves for radiation via antenna 2.

[0094] In some embodiments, antenna 1 of electronic device 100 is coupled to mobile communication module 150, and antenna 2 is coupled to wireless communication module 160, enabling electronic device 100 to communicate with networks and other electronic devices via wireless communication technology. This wireless communication technology may include Global System for Mobile Communications (GSM), General Packet Radio Service (GPRS), Code Division Multiple Access (CDMA), Wideband Code Division Multiple Access (WCDMA), Time-Division Code Division Multiple Access (TD-SCDMA), Long Term Evolution (LTE), BT, GNSS, WLAN, NFC, FM, and / or IR technologies. The GNSS may include GPS, Global Navigation Satellite System (GLONASS), BeiDou Navigation Satellite System (BDS), Quasi-Zenith Satellite System (QZSS), and / or Satellite Based Augmentation Systems (SBAS).

[0095] Electronic device 100 can implement display functions through a GPU, display screen 194, and application processor. The GPU is a microprocessor for image processing, connected to the display screen 194 and the application processor. The GPU is used to perform mathematical and geometric calculations and for graphics rendering. Processor 110 may include one or more GPUs, which execute program instructions to generate or modify display information.

[0096] Electronic device 100 can implement audio functions, such as music playback and recording, through audio module 170, speaker 170A, receiver 170B, microphone 170C, headphone jack 170D, and application processor.

[0097] The software system of electronic device 100 can adopt a layered architecture, event-driven architecture, microkernel architecture, microservice architecture, or cloud architecture. This application embodiment uses a layered architecture of Android... TMTaking the system as an example, the software structure of electronic device 100 is illustrated.

[0098] Figure 3 A software architecture block diagram of an electronic device is shown.

[0099] A layered architecture divides software into several layers, each with a clear role and function. Layers communicate with each other through software interfaces. In some embodiments, Android... TM The system is divided into five layers, from top to bottom: application layer, application framework layer, Android runtime (ART) and native C / C++ libraries, hardware abstraction layer (HAL) and kernel layer.

[0100] The application layer can include a series of application packages. For example... Figure 3 As shown, the application package may include applications such as gallery, calendar, maps, WLAN, music, SMS, calls, navigation, Bluetooth, and video.

[0101] The application framework layer provides application programming interfaces (APIs) and a programming framework for applications in the application layer. The application framework layer includes some predefined functions.

[0102] like Figure 3 As shown, the application framework layer may include a window manager, activity manager, input manager, resource manager, notification manager, view system, content provider, etc.

[0103] The window manager provides a window management service (WMS), which can be used for window management, window animation management, surface management, and as a relay station for the input system.

[0104] Content providers store and retrieve data, making that data accessible to applications. This data can include videos, images, audio, phone calls made and received, browsing history and bookmarks, phone books, etc.

[0105] A view system includes visual controls, such as controls for displaying text and controls for displaying images. View systems can be used to build applications. A display interface can consist of one or more views. For example, a display interface including a text notification icon could include views for displaying text and views for displaying images.

[0106] The file explorer provides applications with various resources, such as localized strings, icons, images, layout files, video files, and more.

[0107] The notification manager allows applications to display notifications in the status bar. These notifications can be used to deliver informational messages and can disappear automatically after a short pause, requiring no user interaction. For example, the notification manager can be used to notify users of completed downloads or message alerts. The notification manager can also display notifications as icons or scrolling text in the top status bar, such as notifications from background applications, or as dialog boxes on the screen. Examples include displaying text messages in the status bar, emitting sounds, vibrating electronic devices, and flashing indicator lights.

[0108] The Activity Manager Service (AMS) can be used to start, switch, and schedule system components (such as activities, services, content providers, and broadcast receivers), as well as manage and schedule application processes.

[0109] The input manager can provide an input management service (IMS), which can be used to manage system inputs, such as touchscreen input, keypad input, and sensor input. IMS retrieves events from input device nodes and, through interaction with the WMS, distributes these events to the appropriate windows.

[0110] The Android runtime consists of the core libraries and the Android runtime itself. The Android runtime is responsible for converting source code into machine code. The Android runtime primarily employs ahead-of-time (AOT) compilation and just-in-time (JIT) compilation technologies. The core libraries mainly provide basic Java class library functionalities, such as libraries for basic data structures, mathematics, I / O, tools, databases, and networking. The core libraries provide APIs for users to develop Android applications.

[0111] The native C / C++ library can include multiple functional modules. Examples include: Surface Manager, Media Framework, libc, OpenGL ES, SQLite, and Webkit. The Surface Manager manages the display subsystem and provides 2D and 3D layer blending for multiple applications. The Media Framework supports playback and recording of various common audio and video formats, as well as still image files. The Media Library supports various audio and video encoding formats, such as MPEG4, H.264, MP3, AAC, AMR, JPG, and PNG. OpenGL ES provides drawing and manipulation of 2D and 3D graphics in applications. SQLite provides a lightweight relational database for applications on electronic devices.

[0112] The Hardware Abstraction Layer (HAL) runs in user space, encapsulates kernel drivers, and provides calling interfaces to higher layers. The kernel layer acts as the layer between hardware and software. Figure 3 As shown, the Hardware Abstraction Layer (HAL) may include display HAL, audio HAL, camera HAL, Bluetooth HAL, etc. The kernel layer may include display driver, audio driver, camera driver, Bluetooth driver, etc.

[0113] The communication method proposed in the embodiments of this application will be described in detail below with reference to the accompanying drawings. It should be noted that the communication methods in the following embodiments can all be implemented in the electronic device 100 having the above-described hardware structure.

[0114] Furthermore, for ease of description and understanding, the embodiments in this application are primarily illustrated using a single SDIO interface as an example. However, it is understood that when the SOC provides two or more SDIO interfaces, each SDIO interface can implement extended functions based on the communication method provided in the embodiments of this application, with the same principle, and will not be elaborated further.

[0115] Figure 4 A schematic diagram of a shared SDIO bus connection is shown.

[0116] like Figure 4 As shown, Figure 4 The connection diagram shown in (1) is based on an SDIO interface and two SDIO modules, SDIO Card A and SDIO Card B. Figure 4 The connection diagram shown in (2) is based on an SDIO interface and three SDIO modules: SDIO card A, SDIO card B and SDIO card C.

[0117] refer to Figure 4 In section (1), since the electronic device only includes two SDIO modules, SDIO Card A and SDIO Card B, the electronic device can connect SDIO Card A and SDIO Card B to the same SDIO interface simultaneously by sharing the SDIO bus and using a one-to-two connection method. In this way, it is physically ensured that both SDIO modules can connect to the SDIO controller (i.e., the host) through the same SDIO interface of the SDIO controller (i.e., establish an SDIO connection / first connection). Subsequently, through time-sharing control, it is convenient for SDIO Card A and SDIO Card B to communicate SDIO data with the SDIO controller through the shared SDIO bus to realize the corresponding functions.

[0118] refer to Figure 4In section (2), since the electronic device includes three SDIO modules—SDIO Card A, SDIO Card B, and SDIO Card C—it can connect SDIO Card A, SDIO Card B, and SDIO Card C simultaneously to a single SDIO interface via a shared SDIO bus. This physically ensures that all three SDIO modules can connect to the SDIO controller through the SDIO interface (i.e., establish an SDIO connection / first connection). Subsequently, through time-sharing control, SDIO Card A, SDIO Card B, and SDIO Card C can communicate with the SDIO controller via the shared SDIO bus to achieve their respective module functions.

[0119] In this embodiment of the application, in order to successfully achieve one-to-one SDIO data communication in the case of multiple SDIO modules, in addition to establishing SDIO connections through a shared SDIO bus, it is also necessary to establish GPIO connections through a general GPIO interface.

[0120] Figure 5 A schematic diagram of an SDIO module communication connection is shown.

[0121] like Figure 5 As shown, Figure 5 The connection diagram shown in (1) is based on an SDIO interface and two SDIO modules, SDIO Card A and SDIO Card B. Figure 5 The connection diagram shown in (2) is based on an SDIO interface and three SDIO modules: SDIO card A, SDIO card B and SDIO card C.

[0122] refer to Figure 5 In scenario (1), since the electronic device only includes two SDIO modules, SDIO Card A and SDIO Card B, the electronic device can establish GPIO connections for SDIO Card A and SDIO Card B using different GPIO interfaces, such as... Figure 5 As shown by the dashed line. At this point, SDIO card A and SDIO card B have established two connections with the SDIO controller: one is the GPIO connection shown by the dashed line, and the other is... Figure 5 The solid line in the middle shows the SDIO connection established through the shared SDIO bus.

[0123] refer to Figure 5In scenario (2), since the electronic device includes three SDIO modules—SDIO Card A, SDIO Card B, and SDIO Card C—the electronic device can also establish corresponding GPIO connections for SDIO Card A, SDIO Card B, and SDIO Card C using different GPIO interfaces. At this time, these three SDIO modules also establish two connections with the SDIO controller: an SDIO connection and a GPIO connection.

[0124] Understandable. Figure 4 and Figure 5 The N=2 and N=3 SDIO modules shown are merely examples of embodiments of this application. The number of N can be set according to the actual functional requirements of the electronic device, and this application does not limit this.

[0125] However, it should be noted that to ensure proper SDIO data communication, the number of SDIO modules that can be connected to an SDIO interface cannot be unlimited. The specific number of SDIO modules that can be connected to a single SDIO interface should be determined based on the actual bandwidth capacity of the SDIO interface and the actual bandwidth resources required by each SDIO module.

[0126] In some embodiments, Figure 4 and Figure 5 The SDIO cards A, B, and C shown can be Bluetooth modules, Wi-Fi modules, GPS modules, satellite communication modules, etc.

[0127] It is understandable that, since the embodiments of this application implement more functions through time-sharing control of multiple SDIO modules, the implementation of different functions of different SDIO modules may have a specific order. It should be noted that, based on the actual processing speed and capabilities of the chip, even if different functions are implemented sequentially through time-sharing control, the user may not perceive a significant difference. However, to minimize the impact of time-sharing control on functional usage, the functions corresponding to these multiple SDIO modules under time-sharing control can be functions with significantly different usage scenarios.

[0128] For example, Wi-Fi functionality is typically used indoors or in busy environments, while satellite communication is usually used outdoors or in less populated areas. This means that it's highly unlikely that Wi-Fi and satellite communication will be needed simultaneously. Therefore, time-division control of the SDIO modules implementing Wi-Fi and satellite communication will not affect the use of either function.

[0129] Therefore, in a specific embodiment... Figure 4 and Figure 5 The SDIO card A and SDIO card B shown in (1) can be a Wi-Fi module and a satellite communication module. Figure 4 and Figure 5 Any two of the SDIO cards A, B and C shown in (2) can be Wi-Fi modules and satellite communication modules, and the other can be Bluetooth modules, GPS modules, etc.

[0130] In some embodiments, after establishing two connections with the SDIO module, the electronic device can use the two connections to switch different states of the SDIO module based on the actual business communication needs of the SDIO module, thereby enabling one-to-one SDIO data communication with these multiple SDIO modules, thus ensuring that the functions corresponding to each SDIO module can be realized.

[0131] by Figure 4 For example, suppose SDIO card A is an SDIO module that implements Wi-Fi functionality. SDIO card B is an SDIO module that implements extended functions, such as satellite communication. Then, the SDIO controller in the electronic device can time-division control SDIO cards A and B to perform SDIO data communication separately based on the actual business communication needs, thereby achieving time-division multiplexing of Wi-Fi and satellite communication functions. In this way, the electronic device, through this single SDIO interface, can not only ensure the implementation of the original Wi-Fi function without violating the one-to-one SDIO data communication constraint, but also implement the additional extended function of satellite communication. This removes the limitations on the implementation of extended functions and solves the problem of limited communication interface resources preventing the implementation of extended functions.

[0132] In some embodiments, after establishing a GPIO connection, the SDIO controller and the SDIO module can exchange GPIO signals through the established GPIO connection, using these signals to time-division control the SDIO module to switch between different states. Furthermore, the SDIO controller can multiplex the SDIO bus to select different SDIO modules for SDIO data communication based on their different states, thereby implementing the corresponding functions of each SDIO module.

[0133] In some embodiments, GPIO signals may specifically include interrupt out (INT_OUT) signals and clock gate (CLK_GATE) signals. The GPIO signals exchanged through the established GPIO connection can be implemented by switching the signal states of the INT_OUT and CLK_GATE signals.

[0134] In a specific embodiment, the INT_OUT and CLK_GATE signals can include two signal states: a high level (e.g., logic 1) and a low level (e.g., logic 0). Therefore, GPIO signal transmission can be achieved by switching from a high level to a low level, or vice versa.

[0135] The signal state of the INT_OUT signal can be primarily controlled by the SDIO module. This allows the SDIO module to send GPIO signals to the SDIO controller via the established GPIO connection by switching the INT_OUT signal state. In this embodiment, the SDIO module typically switches the INT_OUT signal state when it has business communication needs or needs to inform the SDIO controller of its local status. Similarly, the signal state of the CLK_GATE signal can be primarily controlled by the SDIO controller. This allows the SDIO controller to send GPIO signals to the SDIO module via the GPIO connection by switching the CLK_GATE signal state. In this embodiment, the SDIO controller typically switches the CLK_GATE signal state when it needs to switch the SDIO module's state.

[0136] Taking SDIO card A and SDIO card B as examples, Figure 6 A schematic diagram of a GPIO signal is shown.

[0137] refer to Figure 6 Between the SDIO controller and SDIO card A, the GPIO signals include the CLK_GATE_A signal, which is mainly controlled by the SDIO controller, and the INT_OUT_A signal, which is mainly controlled by SDIO card A. Similarly, between the SDIO controller and SDIO card B, the GPIO signals include the CLK_GATE_B signal, which is mainly controlled by the SDIO controller, and the INT_OUT_B signal, which is mainly controlled by SDIO card A.

[0138] It is understandable that the aforementioned INT_OUT and CLK_GATE signals are different from the CLK and INT signals of the SDIO interface itself. That is, the existing SDIO interface bus already includes a clock line (CLK) for transmitting clock signals, a command line (CMD) for transmitting commands and responses, and data lines (DATA3) for transmitting data. Simultaneously, the SDIO interface can receive interrupt INT signals by multiplexing data lines. Therefore, the existing SDIO interface can implement interrupt signal reception and interrupt implementation using the existing SDIO bus. However, in order to ensure successful one-to-one SDIO data communication, this application embodiment adds the aforementioned INT_OUT and CLK_GATE signals, etc., as GPIO signals. In other words, to ensure successful one-to-one SDIO data communication, this application embodiment does not use the original CLK / INT method for time-sharing control of multiple SDIO modules, but instead adopts a new GPIO software implementation.

[0139] The following is a detailed explanation of the time-sharing control process.

[0140] Figure 7 A flowchart of a communication method is shown.

[0141] refer to Figure 7 After SDIO card A (such as the first SDIO module) and SDIO card B (such as the second SDIO module) have established two connections, SDIO card A is currently in working / active / activated state (i.e., the first state), and SDIO card B is currently in idle / suspended / standby state (i.e., the second state).

[0142] Understandably, when an SDIO module switches from idle to idle, its Pads are set to a high-impedance state, and CLK is gating (i.e., the CLK signal is turned off to reduce power consumption), indicating that the SDIO connection with the SDIO controller is currently disconnected. In this state (i.e., the first state), the SDIO module cannot communicate with the SDIO controller via the SDIO bus. Conversely, when an SDIO module switches from active to active, both its Pads and CLK are set to normal, indicating that the SDIO connection with the SDIO controller is not disconnected. In this state (i.e., the second state), the SDIO module can communicate with the SDIO controller via the SDIO bus.

[0143] Based on this, such as Figure 7 As shown, SDIO card A, which is in active mode, communicates with the SDIO controller via the SDIO bus. SDIO card B, which is in idle mode, does not communicate with the SDIO controller.

[0144] Therefore, when SDIO card B needs to communicate with the SDIO controller via SDIO data, the SDIO controller receives a first signal. This first signal can be understood as a notification to the SDIO controller that SDIO data communication with the SDIO module is required. Figure 7 In the process shown, the first signal can be regarded as a signal used to instruct the SDIO controller to perform SDIO data communication with the SDIO card B.

[0145] In some embodiments, the first signal may be sent by SDIO card B, such as Figure 7 As shown. Understandably, since the SDIO bus is occupied by SDIO card A for SDIO data communication at this time, in this embodiment of the application, SDIO card B can send a first signal to the SDIO controller through the established GPIO connection (i.e., the second connection).

[0146] In other embodiments, the first signal may not be sent by SDIO card B. For example, when SDIO card B has a service communication requirement, the first signal can be sent to the SDIO controller by other processing units in the SOC. These other processing units can be processing units associated with the second SDIO module. The service communication requirement of the SDIO module can be triggered by user operation using the function corresponding to the SDIO module, or it can be triggered by other related background services, depending on the actual design of the SDIO module. This application embodiment does not impose any limitations on this.

[0147] In some embodiments, when the first signal is sent from the SDIO module to the SDIO controller, the first signal can specifically be triggered by the SDIO card B pulling the INT_OUT_B signal high. That is, when the SDIO card B is in an idle state, the INT_OUT_B signal can be in a low-level state by default. When it needs to request SDIO data communication from the SDIO controller, the SDIO card B can send the first signal to the SDIO controller by pulling the INT_OUT_B signal high, that is, switching INT_OUT_B from a low-level state to a high-level state.

[0148] Next, after receiving the first signal, the SDIO controller can determine that SDIO card B has a service communication requirement. However, in order to conduct SDIO data communication with SDIO card B, the SDIO controller needs to avoid communication interference. Therefore, the SDIO controller needs to terminate SDIO data communication with SDIO card A first.

[0149] In this embodiment, ending SDIO data communication requires both the SDIO controller and the SDIO module to cease SDIO data communication. The SDIO controller can stop SDIO data communication upon receiving a first signal. The SDIO module can stop SDIO data communication by sending a corresponding signal controlled by the SDIO controller.

[0150] In some embodiments, the SDIO controller can send a signal to the SDIO module through an established second connection, instructing the SDIO module to stop SDIO data communication and switch its state to idle. For example... Figure 7 As shown, after receiving the first signal from SDIO card B, the SDIO controller responds to the first signal by stopping SDIO data communication with SDIO card A. Then, the SDIO controller sends a second signal to SDIO card A through the established GPIO connection. This second signal notifies SDIO card A to also terminate SDIO data communication and instructs SDIO card A to switch to an idle state so that SDIO card B can switch to an active state. In some embodiments, the second signal can be triggered by the SDIO controller pulling the CLK_GATE_A signal high.

[0151] In other embodiments, since the SDIO module that needs to stop SDIO data communication is the one currently occupying the SDIO bus, the SDIO controller can also directly send a signal to the SDIO module via the first connection, instructing the SDIO module to stop SDIO data communication and switch its state to idle. Specifically, after receiving the first signal sent by SDIO card B, the SDIO controller, in response to the first signal, first sends a second signal to the first SDIO module via the first connection, notifying SDIO card A to stop SDIO data communication and switch its state to idle. Then, the SDIO controller side also stops SDIO data communication with the first SDIO module.

[0152] In some embodiments, since the first signal received by the SDIO controller is an interrupt signal used to interrupt ongoing SDIO data communication, an interrupt register can be set on the SDIO controller side to facilitate the management and implementation of SDIO module interrupt requests. This interrupt register contains bits corresponding to each SDIO module. When the SDIO controller receives the first signal, it sets the bit in the interrupt register corresponding to the SDIO module receiving the first signal (e.g., sets it to 1). Figure 7For example, the SDIO controller will set the bit corresponding to SDIO card B in the interrupt register (e.g., set it to 1). However, in this embodiment, because one SDIO interface is shared by multiple SDIO modules, the SDIO controller needs to be in a state where it can be interrupted at any time. Therefore, after setting the bit, in order to successfully implement the next interrupt, the SDIO controller also needs to respond to the first signal, clear the interrupt register, and set it to low enable (low level). That is, after receiving the first signal, the SDIO controller also needs to reset the bit corresponding to the SDIO module in the interrupt register (e.g., set it to 0). For example, setting the bit corresponding to SDIO card B to 0.

[0153] After receiving the second signal from the SDIO controller, the SDIO module responds by ending SDIO data communication and switching its local state from active to idle. For example... Figure 7 As shown, after receiving the second signal, SDIO card A, in response, first stops reporting data to the host (SDIO controller). Simultaneously, for data currently being transmitted, it completes all data transmissions in progress. Then, SDIO card A switches to the idle state. Switching to the idle state can be understood as equivalent to disconnecting SDIO data communication; SDIO card A relinquishes the shared SDIO bus. After SDIO card A relinquishes the SDIO bus, SDIO card B can then occupy the SDIO bus for SDIO data communication.

[0154] To ensure the SDIO controller accurately knows that the SDIO module has ended SDIO data communication and switched states, the SDIO module can also send a notification signal to the SDIO controller. For example... Figure 7 As shown, after SDIO card A ends its SDIO data communication with the SDIO controller and completes the state transition, it can send a fifth signal to the SDIO controller through the established GPIO connection. The fifth signal notifies the SDIO controller that the local SDIO connection has been disconnected, and the SDIO controller can then start SDIO data communication with other SDIO modules, such as SDIO card B.

[0155] In some embodiments, the fifth signal can be triggered by SDIO card A pulling INT_OUT_A high. Meanwhile, to facilitate SDIO card A continuing to send the next interrupt to the SDIO controller by pulling INT_OUT_A high, after transmitting the fifth signal by pulling INT_OUT_A high, SDIO card A can pull INT_OUT_A low after a preset delay, i.e., switch from a high-level state to a low-level state.

[0156] After receiving the fifth signal, the SDIO controller can then communicate with the SDIO module corresponding to the first signal. For SDIO data communication to occur, the SDIO module needs to occupy the shared SDIO bus. Therefore, the SDIO controller first needs to send a signal to control the SDIO module corresponding to the first signal to switch its state to active mode.

[0157] like Figure 7 As shown, after receiving the fifth signal sent by SDIO card A, the SDIO controller can respond to the fifth signal by sending a third signal to SDIO card B through the established GPIO connection. The third signal notifies SDIO card B to switch states, that is, to control SDIO card B to switch from idle state to working state.

[0158] In some embodiments, the third signal may specifically be triggered by the SDIO controller pulling the CLK_GATE_B signal low. Therefore, in this embodiment, a high-level CLK_GATE signal indicates the end of SDIO data communication, while a low-level CLK_GATE signal indicates the start of SDIO data communication.

[0159] After receiving the third signal, SDIO card B responds by switching its state from idle to active. Then, to ensure the SDIO controller accurately knows that SDIO card B has switched states and is occupying the SDIO bus, SDIO card B needs to send a notification signal to the SDIO controller; this notification signal is the fourth signal in this embodiment. Understandably, since the third signal has already triggered SDIO card B to switch to active state, both the SDIO and GPIO connections of SDIO card B are now communicative. Therefore, SDIO card B can send the fourth signal to the SDIO controller via either the SDIO or GPIO connection. Of course, to ensure the reliability of signal transmission, the GPIO connection can be chosen to send the fourth signal.

[0160] like Figure 7As shown, SDIO card B sends a fourth signal to the SDIO controller through the established GPIO connection. This fourth signal notifies the SDIO controller that the local state switch has been completed and the local device can begin SDIO data communication. In some embodiments, since SDIO card B has already triggered the transmission of the first signal by pulling INT_OUT_B high, it can trigger the transmission of the fourth signal by pulling INT_OUT_B low. After receiving the fourth signal from SDIO card B, the SDIO controller also clears its interrupt register. Then, since SDIO card B has switched to the active state, it can communicate with the SDIO controller via the SDIO bus.

[0161] Therefore, the embodiments of this application can ensure that different SDIO modules can be switched to communicate with the host for SDIO data based on the service communication needs of different SDIO modules, without violating the one-to-one SDIO data communication limitation, by using the two established connections in conjunction, so as to achieve the corresponding functions.

[0162] Additionally, it is understood that when an SDIO module is in an idle state, it means that the SDIO module cannot communicate with the SDIO controller via the SDIO bus. However, an SDIO module in an idle state can switch to an active state by requesting communication with the SDIO controller through the GPIO connection added in this embodiment of the application, so as to communicate with the SDIO controller for SDIO data.

[0163] Figure 8 A schematic diagram illustrating the principle of SDIO module state switching is shown.

[0164] refer to Figure 8 When SDIO card A is in active mode and SDIO card B is in idle mode, there is an "×" symbol on the SDIO bus corresponding to SDIO card B, while there is no such symbol on the bus corresponding to SDIO card A. This can be interpreted as meaning that SDIO card A can communicate with SDIO via the SDIO bus, while SDIO card B cannot. In other words, both the first and second connections of SDIO card A can communicate. However, the first connection of SDIO card B cannot communicate, while the second connection can.

[0165] Similarly, after the state switch, when SDIO card B is in the active state and SDIO card A is in the idle state, there is an "×" symbol on the SDIO bus corresponding to SDIO card A, but not on the bus corresponding to SDIO card B. This can be understood as meaning that SDIO card B can communicate with SDIO via the SDIO bus, while SDIO card A cannot. In other words, both the first and second connections of SDIO card B can communicate. However, the first connection of SDIO card A cannot communicate, while the second connection can.

[0166] It should be noted that, Figure 7 The process shown and Figure 8 Although the switching principles shown all involve two SDIO modules, in practice, more than three SDIO modules can be included. For example, electronic devices may also include an SDIO card C.

[0167] However, it's understandable that even with three or more SDIO modules, the communication principle and state switching principle are the same. That is, any idle SDIO module can send a first signal to the SDIO controller via the established GPIO connection to request SDIO data communication. In response to the first signal, the SDIO controller terminates SDIO data communication with the active SDIO module and controls it to switch to the idle state via the established GPIO connection. Then, it controls the SDIO module that sent the first signal to switch to the active state and establish SDIO data communication. The specific process can be found above. Figure 7 The process shown and Figure 8 The principle is illustrated, and will not be elaborated further.

[0168] In some embodiments, regarding the initialization of the aforementioned N≥2 SDIO modules, based on actual needs, it can be selected that after the electronic device is powered on, each SDIO module initiates an initialization request with the SDIO controller sequentially according to a predefined initialization order. In this way, each SDIO module only needs to perform initialization once. Alternatively, each SDIO module can also be initialized only when there is a need for SDIO data communication. This is equivalent to requiring an initialization for each SDIO data communication with the SDIO controller. The specific initialization process can adopt existing methods, such as initializing the SDIO modules through CMD commands; this application embodiment does not impose any limitations on this.

[0169] In some embodiments, the SDIO controller can also decide whether to directly respond to the first signal to end the ongoing business communication or to respond to the first signal after the ongoing business communication has ended, based on preset conditions such as the service priority of the SDIO module, the usage frequency of the SDIO module, and the importance of the SDIO module.

[0170] For example, different SDIO modules can be configured with different service priorities. When the service priority of the SDIO module corresponding to the first signal is higher than that of the SDIO module currently engaged in SDIO data communication, the SDIO controller can decide to directly respond to the first signal to terminate the ongoing SDIO data communication, thereby ensuring that SDIO data communication with the higher-priority SDIO module is initiated as soon as possible to achieve the higher-priority function quickly. Conversely, when the service priority of the SDIO module sending the first signal is lower than that of the SDIO module currently engaged in SDIO data communication, the SDIO controller can decide to complete the ongoing SDIO data communication first, wait for the ongoing service to complete, and then respond to the first signal to initiate SDIO data communication with the SDIO module that sent the first signal. Similarly, this ensures that the higher-priority function is implemented as quickly as possible.

[0171] For example, if the SDIO module corresponding to the first signal has a higher usage frequency / importance than the SDIO module currently engaged in SDIO data communication, the SDIO controller can decide to directly respond to the first signal to terminate the ongoing SDIO data communication. This ensures that SDIO data communication with the more frequently used / important SDIO module can be initiated as soon as possible to achieve more important functions. Conversely, if the SDIO module sending the first signal has a lower usage frequency / importance than the SDIO module currently engaged in SDIO data communication, the SDIO controller can decide to complete the ongoing SDIO data communication first, wait for the ongoing service to complete, and then respond to the first signal to initiate SDIO data communication with the SDIO module that sent the first signal.

[0172] For example, the SDIO controller can also use geofencing or time fencing to decide whether to immediately respond to the first signal and terminate ongoing business communication.

[0173] In some embodiments, the logic control of the newly added GPIO signal on the SDIO module side can be defined and implemented in software or in hardware, depending on actual needs. This application embodiment does not impose any limitations on this.

[0174] Another embodiment of this application provides an electronic device, including: one or more processors and a memory. The processor includes an SDIO controller; the electronic device further includes at least two SDIO modules, the SDIO controller being connected to the SDIO modules, such as establishing the first connection and the second connection described above; the memory is coupled to the SDIO controller; the memory stores one or more computer program codes, the computer program codes including computer instructions; when the processor executes the computer instructions, the electronic device implements the communication method described in any of the above embodiments.

[0175] Another embodiment of this application provides a computer-readable storage medium storing a computer program that, when executed by a processor in an electronic device, causes the electronic device to implement the communication method described in any of the above embodiments.

[0176] This application also provides a computer program product that, when run on a computer, causes the computer to perform the various functions or steps described in the above method embodiments.

[0177] This application also provides a chip system, such as... Figure 9 As shown, the chip system 900 includes an SDIO controller 901 and at least one interface circuit 902. The SDIO controller 901 and the interface circuit 902 are interconnected via lines. For example, the interface circuit 902 can be used to receive signals from other devices (e.g., a computer's memory). As another example, the interface circuit 902 can be used to send signals to other devices (e.g., the SDIO controller 901).

[0178] For example, interface circuit 902 can read instructions stored in memory and send those instructions to SDIO controller 901. When the instructions are executed by SDIO controller 901, the computer can perform the steps in the above embodiments. Of course, the chip system may also include other discrete devices, and this application embodiment does not specifically limit this.

[0179] Through the above description of the embodiments, those skilled in the art can clearly understand that, for the sake of convenience and brevity, only the division of the above functional modules is used as an example. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above.

[0180] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another apparatus, or some features may be ignored or not executed. Furthermore, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0181] The units described as separate components may or may not be physically separate. A component shown as a unit can be one or more physical units; that is, it can be located in one place or distributed in multiple different locations. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0182] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0183] If the function of the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a readable storage medium. Based on this understanding, the technical solutions of the embodiments of this application, essentially, or the parts that contribute to the prior art, or all or part of the technical solutions, can be embodied in the form of a software product. This software product is stored in a storage medium and includes several instructions to cause a device (which may be a microcontroller, chip, etc.) or processor to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0184] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A communication method, characterized in that, The method is applied to an electronic device; the electronic device includes a secure input / output (SDIO) controller and at least two SDIO modules; the at least two SDIO modules establish a first connection with the SDIO controller through the same SDIO interface and a shared SDIO bus; the at least two SDIO modules establish a second connection with the SDIO controller through different first interfaces; wherein, the SDIO module includes a first state and a second state, in which the first connection is communicative and in the second state the first connection is not communicative; the method includes: The SDIO controller communicates with the first SDIO module via the first connection, and the first SDIO module is in the first state. The SDIO controller receives a first signal, which is used to instruct the SDIO controller to perform SDIO data communication with the second SDIO module, and the second SDIO module is in the second state. In response to the first signal, the SDIO controller terminates SDIO data communication with the first SDIO module and controls the first SDIO module to switch to the second state; The SDIO controller controls the second SDIO module to switch to the first state through the second connection, and the SDIO controller communicates SDIO data with the second SDIO module in the first state through the first connection.

2. The method according to claim 1, characterized in that, The first interface includes a general purpose input / output (GPIO) interface.

3. The method according to claim 1 or 2, characterized in that, The SDIO controller receiving the first signal includes: the SDIO controller receiving the first signal from the second SDIO module through the second connection.

4. The method according to any one of claims 1-3, characterized in that, In response to the first signal, the SDIO controller terminates SDIO data communication with the first SDIO module and controls the first SDIO module to switch to the second state, including: The SDIO controller stops SDIO data communication with the first SDIO module in response to the first signal; The SDIO controller sends a second signal to the first SDIO module through the second connection, and controls the first SDIO module to stop SDIO data communication and switch to the second state through the second signal.

5. The method according to any one of claims 1-3, characterized in that, In response to the first signal, the SDIO controller terminates SDIO data communication with the first SDIO module and controls the first SDIO module to switch to the second state, including: In response to the first signal, the SDIO controller sends a second signal to the first SDIO module through the first connection, and controls the first SDIO module to stop SDIO data communication and switch to the second state through the second signal. The SDIO controller stops SDIO data communication with the first SDIO module.

6. The method according to any one of claims 1-5, characterized in that, The SDIO controller controls the second SDIO module to switch to the first state via the second connection. The SDIO controller communicates SDIO data with the second SDIO module in the first state via the first connection, including: After the first SDIO module switches to the second state, the SDIO controller sends a third signal to the second SDIO module through the second connection, and controls the second SDIO module to switch back to the first state through the third signal; After receiving a fourth signal from the second SDIO module that has switched to the first state via the second connection or the first connection, the SDIO controller performs SDIO data communication with the second SDIO module via the first connection.

7. The method according to claim 6, characterized in that, The method further includes: After receiving the fifth signal sent by the first SD IO module through the second connection, the SD IO controller determines that the first SD IO module has switched from the first state to the second state.

8. The method according to any one of claims 1-7, characterized in that, The first, fourth, and fifth signals are triggered by switching the signal state of the interrupt output signal; the second and third signals are triggered by switching the signal state of the clock gating signal. Wherein, the second signal is used to control the first SDIO module to stop SDIO data communication and switch to the second state; the third signal is used to control the second SDIO module to switch to the first state; the fourth signal is used to notify the SDIO controller that the second SDIO module has switched to the first state; and the fifth signal is used to notify the SDIO controller that the first SDIO module has switched to the second state.

9. The method according to claim 8, characterized in that, The first SD IO module corresponds to a first interrupt output signal and a first clock gate signal; the second SD IO module corresponds to a second interrupt output signal and a second clock gate signal; the signal states include a high-level state and a low-level state. The first signal is triggered by switching the second interrupt output signal to a high level; the fourth signal is triggered by switching the second interrupt output signal to a low level; the fifth signal is triggered by switching the first interrupt output signal to a high level, and then switching the first interrupt output signal to a low level after a preset delay; the second signal is triggered by switching the first clock gating signal to a high level; and the third signal is triggered by switching the second clock gating signal to a low level.

10. The method according to any one of claims 1-9, characterized in that, The SD IO controller includes an interrupt register, wherein the bit in the interrupt register corresponding to the second SD IO module is set when the first signal is received; the method further includes resetting the bit in the interrupt register corresponding to the second SD IO module.

11. The method according to any one of claims 1-10, characterized in that, In response to the first signal, the SDIO controller terminates SDIO data communication with the first SDIO module and controls the first SDIO module to switch to the second state, including: When the service priority of the second SDIO module is higher than that of the first SDIO module, the SDIO controller responds to the first signal, terminates SDIO data communication with the first SDIO module, and controls the first SDIO module to switch to the second state; When the service priority of the second SDIO module is lower than that of the first SDIO module, the SDIO controller, after completing the SDIO data communication with the first SDIO module, responds to the first signal and controls the first SDIO module to switch to the second state.

12. The method according to any one of claims 1-11, characterized in that, The method further includes: After the electronic device is powered on, the SD IO controller receives initialization requests from each SD IO module according to a preset initialization sequence, and the SD IO controller completes the initialization of each SD IO module in response to the initialization request; wherein, according to the initialization sequence, the SD IO controller receives the initialization request of the next SD IO module only after the initialization of the previous SD IO module is completed. Alternatively, before communicating with the SD IO module via SD IO data, the SD IO controller receives an initialization request from the SD IO module and initializes the SD IO module in response to the initialization request.

13. The method according to any one of claims 1-12, characterized in that, At any given time, only one SD IO module is in the first state; at any given time, only one SD IO module communicates with the SD IO controller for SD IO data.

14. The method according to any one of claims 1-13, characterized in that, The at least two SD IO modules are used to implement one or more functions of Bluetooth, Wi-Fi, GPS, and satellite communication.

15. An electronic device, characterized in that, include: One or more processors and a memory, the processor including a Secure Input / Output (SDIO) controller; the electronic device further including at least two SDIO modules, the SDIO controller being connected to the SDIO modules; the memory being coupled to the processor; the memory storing one or more computer program codes, the computer program codes including computer instructions; when the processor executes the computer instructions, causing the electronic device to perform the communication method as described in any one of claims 1-14.

16. A chip, characterized in that, include: An SDIO controller and an interface circuit; the interface circuit reads computer instructions stored in the memory and sends them to the SDIO controller; when the SDIO controller executes the computer instructions, it causes the chip to perform the communication method as described in any one of claims 1-14.

17. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor of the electronic device, the electronic device performs the communication method as described in any one of claims 1-14.

18. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor in an electronic device, the electronic device performs the communication method as described in any one of claims 1-14.

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