A method and circuit for configuring an on-chip network device
By using a custom protocol and packet format configuration method for on-chip network devices, combined with parity checking and timeout retransmission mechanisms, the problem of insufficient adaptability of traditional configuration methods is solved, enabling efficient and reliable configuration and status reading between heterogeneous nodes.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- 58TH RES INST OF CETC
- Filing Date
- 2026-03-27
- Publication Date
- 2026-06-30
AI Technical Summary
Traditional on-chip network device configuration methods cannot adapt to the differentiated configuration requirements between heterogeneous nodes, and are insufficient for application scenarios with high requirements for real-time performance, dynamic adaptability, and reliability, such as autonomous driving, smart healthcare, and aerospace.
On-chip network device configuration is performed using custom protocols and packet formats. Four basic operation and event packets are defined, and a reliable configuration method and circuit are achieved by combining parity check, triple redundancy and timeout retransmission mechanism.
It realizes distributed configuration and status reading of on-chip network devices, adapts to the differentiated needs of heterogeneous nodes, and improves real-time performance and reliability.
Smart Images
Figure CN122309444A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of digital integrated circuit technology, and in particular to a method and circuit for configuring an on-chip network device. Background Technology
[0002] With the rapid development of artificial intelligence and cloud computing technologies, the demand for chip computing power is increasing. Simply increasing the integration density of a single chip to achieve performance improvements is no longer sustainable due to multiple bottlenecks in physical properties, power consumption, yield, and cost. Network-on-Chip (NoC), as a new on-chip interconnect technology, replaces the centralized bus with a distributed interconnect architecture, fundamentally solving the scalability, power consumption, and bandwidth issues of on-chip communication, and has become a core solution for multi-core SoC interconnect.
[0003] As multi-core chips evolve towards many-core and heterogeneous integration, the number of on-chip network nodes and on-chip network devices continues to increase. To accommodate the diversity of chip functions, on-chip networks often need to support interaction between different functional IP cores, such as computing, storage, and communication. Traditional fixed device configuration methods are no longer suitable for the differentiated configuration needs of heterogeneous nodes. Meanwhile, fields such as autonomous driving, smart healthcare, and aerospace place high demands on the real-time performance, dynamic adaptability, and reliability of on-chip network device configuration methods and circuits. Summary of the Invention
[0004] The purpose of this invention is to provide a method and circuit for configuring an on-chip network device to solve the problems in the background art.
[0005] To address the aforementioned technical problems, this invention provides a method for configuring an on-chip network device, enabling the configuration of the APB interface of the on-chip network device. The configuration method includes: using a custom protocol and transmitting data according to a packet format. The configuration and configuration status reading of on-chip network devices are classified into four basic operations: configuration write request operation, configuration write response operation, configuration read request operation, and configuration read response operation. Four basic event packets are defined: configuration write request event packet, configuration write response event packet, configuration read request event packet, and configuration read response event packet, which correspond to the four basic operations respectively; The control information, address information, and data information to be transmitted are encoded in a unified format to form a complete event packet, which is then divided into micro-chips by the on-chip network circuit and transmitted sequentially.
[0006] In one implementation, the data transmitted in the on-chip network device within one clock cycle is defined as a chip, each event packet consists of several chips, and all event packets include a header chip marking the start position of the event packet, several individual chips, and a tail chip marking the end position of the event packet. The configuration write request event packet and the configuration read response event packet consist of 5 micro-fragments: header micro-fragment, length body micro-fragment, address body micro-fragment, data body micro-fragment, and tail micro-fragment. The configuration write response event packet and the configuration read request event packet consist of four fragments: a header fragment, a length body fragment, an address body fragment, and a trailer fragment; among them, The length micro-fragment is a micro-fragment that carries the length information of the event packet; the address micro-fragment is a micro-fragment that carries the address information for configuration write and configuration read; and the data micro-fragment is a micro-fragment that carries the data information for configuration write and configuration read back.
[0007] In one implementation, the configuration method employs a mechanism combining parity checking, triple modular redundancy, and request-based timeout retransmission to ensure the reliability of the configuration method. The configuration address and configuration data are configured with a parity bit every 8 bits to ensure the correctness of the configuration; Tri-mode redundancy is applied to critical routing information to ensure the correctness of the routing; A request-based timeout retransmission mechanism is adopted to further ensure the reliability of the configuration method.
[0008] In one embodiment, the on-chip network device includes an on-chip network master device and an on-chip network slave device. The on-chip network master device packages configuration control information, address information, and data information into a configuration write request event packet according to its own protocol. The configuration write request event packet is routed to the on-chip network slave device. The configuration circuit of the on-chip network slave device performs parity checking on the configuration write request event packet. If the parity check passes, it returns a configuration write response event packet to notify the on-chip network master device that the configuration is successful. If the parity check fails, it does not return a response packet. In the reconfiguration step, if the on-chip network master device does not receive a response packet after a specified time after sending the configuration write request event packet, it triggers a timeout retransmission.
[0009] In one implementation, the on-chip network master device assembles the address information to be read into a configuration read request event packet according to its own protocol. The configuration read request event packet is routed to the on-chip network slave device to read the data in the address. If the data is successfully read, a configuration read response event packet carrying the read address and read data is returned to the on-chip network master device. In the configuration status reread step, if the on-chip network master device does not receive the read response event packet within a specified time, a timeout retransmission is triggered to reread the data in the address of the on-chip network slave device.
[0010] This invention provides an on-chip network device configuration circuit, comprising three circuit modules: a kernel, a cache, and an encapsulation layer; wherein, The kernel circuit module is functionally divided into two main circuit modules: packet assembly and decompression. Both are controlled by state machines. The decompression circuit module is mainly responsible for parsing event packets into configuration addresses and configuration data, and then passing them to the cache circuit module for caching. The packet assembly circuit module is mainly responsible for reading data from the cache circuit module and reading routing information, length information, and address information from the response information register in the kernel circuit module, encapsulating them into response event packets, and returning them to the on-chip network master device. The encapsulation layer circuit module mainly consists of an APB protocol control state machine and a data conversion submodule. It can read the configuration address and configuration data from the cache circuit module and encapsulate them according to the APB protocol, or parse the APB protocol data into configuration address and configuration data and pass them to the cache circuit module for caching. The buffer circuit module consists of two parts: an input buffer and an output buffer. Each part uses an asynchronous FIFO to solve the problem of data transmission across clock domains.
[0011] This invention provides a configuration method and circuit for on-chip network devices, enabling mutual conversion between proprietary protocols and the APB protocol. Through the designed configuration circuit, on-chip network devices can configure each other and read configuration status, achieving distributed configuration and status reading of the on-chip network system. Any on-chip network device can perform parameter configuration and configuration status reading of the on-chip network system at any time and online, effectively adapting to the differentiated configuration needs among heterogeneous nodes. The reliability of the on-chip network device configuration method and circuit is ensured through triple modulo redundancy, parity checking, and a request-based timeout retransmission mechanism. Attached Figure Description
[0012] Figure 1 This is a diagram illustrating the format of the write request event / read response event configuration; Figure 2 This is a diagram illustrating the format of the write response / read request event packet. Figure 3 This is the overall structure diagram of the configuration circuit; Figure 4 This is a kernel module framework diagram; Figure 5 This is a diagram of the encapsulation layer module framework. Detailed Implementation
[0013] The following detailed description, in conjunction with the accompanying drawings and specific embodiments, provides a further detailed explanation of the on-chip network device configuration method and circuit proposed in this invention. The advantages and features of this invention will become clearer from the following description. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this invention.
[0014] The configuration method of this invention employs a custom protocol and transmits data according to a packet format. The configuration and configuration status reading of the on-chip network device are categorized into four basic operations: configuration write request operation, configuration write response operation, configuration read request operation, and configuration read response operation. Four basic event packets are defined: configuration write request event packet, configuration write response event packet, configuration read request event packet, and configuration read response event packet, each corresponding to one of the four basic operations.
[0015] The control information, address information, and data information to be transmitted are encoded in a unified format (proprietary protocol) to form a complete event packet, which is then divided into micro-chips by the on-chip network circuitry and transmitted sequentially. A micro-chip is defined as the data transmitted by the on-chip network within one clock cycle, and each event packet consists of several micro-chips. All event packets contain a header micro-chip marking the start of the event packet, several individual micro-chips, and a tail micro-chip marking the end of the event packet.
[0016] The header microchip is primarily used to carry routing information, protocol information, and event information. The routing information (such as source router address and destination router address) carried in the header microchip is used to control the routing of event packets within the on-chip network. The protocol information is used to mark the configuration protocol, and the event information is used to mark the type of the current event packet. Triple modular redundancy is used for routing, protocol, and event information to improve reliability. The body microchip can be further divided into length body microchips, address body microchips, and data body microchips. The length body microchip marks the data length of the event packet, the address body microchip marks the operation address of the event packet, and the data body microchip carries the data for configuration write requests and configuration read response events. Valid information in the body microchip is encoded using a parity check code every 8 bits to ensure the correctness of configuration writes and reads.
[0017] Both configuring write request event packets and configuring read response event packets require payload data, so each consists of 5 fragments: header fragment, length body fragment, address body fragment, data body fragment, and trailer fragment. The specific format is as follows: Figure 1 As shown; the configuration write response event packet and the configuration read request event packet do not require payload data, so they are both composed of 4 fragments: header fragment, length body fragment, address body fragment, and tail fragment, with the specific format as follows. Figure 2 As shown.
[0018] The configuration and reconfiguration steps are as follows: The on-chip network master device will package configuration control information, address information, and data information into a configuration write request event packet according to its own protocol and output it to the on-chip network. At the same time, it will also cache the request event packet in the retransmission buffer and will not send the next request event packet until the retransmission buffer is released.
[0019] After the configuration write request event packet enters the on-chip network, it is routed according to the routing information in the header microchip until it reaches the destination on-chip network slave device. The configuration circuit in the on-chip network slave device decodes and verifies the configuration write request event packet. If the verification is successful, it returns a configuration write response event packet to notify the on-chip network master device that the configuration is successful. The on-chip network master device then releases the retransmission buffer and begins the next data transmission. During the reconfiguration process, if the on-chip network master device has not received a response event packet before the retransmission timeout, it retrieves the cached request event packet from the retransmission buffer and retransmits it after the timeout. Regardless of whether the retransmission is successful or not, the retransmission buffer is released, and the next data transmission begins.
[0020] The steps for reading the configuration status and rereading the configuration status are as follows: In the configuration status reading step, the on-chip network master device assembles the address information into a configuration read request event packet according to its own protocol and outputs it to the on-chip network. At the same time, it caches the request event packet in the retransmission buffer and does not send the next request event packet until the retransmission buffer is released.
[0021] After the configuration read request event packet enters the on-chip network, it is routed according to the routing information in the header microchip until it reaches the destination on-chip network slave device. The configuration circuit in the on-chip network slave device decodes and verifies the configuration read request event packet. If the verification is successful, it performs APB protocol conversion, retrieves the data in the read address, and encapsulates the retrieved APB data into a read response event packet and returns it to the on-chip network master device to notify the on-chip network master device that the configuration read was successful, releases the retransmission buffer, and begins the next data transmission.
[0022] In the reread step, if the on-chip network master device does not receive a read response event packet before the retransmission timeout, it retrieves the cached request event packet from the retransmission buffer and retransmits it after the timeout. Regardless of whether the retransmission is successful or not, the retransmission buffer is released, and the next data transmission begins.
[0023] The configuration circuit framework of the present invention is as follows: Figure 3 As shown, the whole consists of three major modules: Kernel, Buffer, and Shell.
[0024] The kernel is the core of the configuration circuit, containing two main functional modules: packet assembly and unpacking. Figure 4 As shown. The core task of the packet assembly module is to read data from the buffer and complete the encapsulation; the unpacking module is responsible for parsing the data from the on-chip network and writing the parsing results into the buffer. The unpacking module consists of a verification submodule, an input control state machine, and a data parsing module. Its workflow is as follows: 1. The verification submodule first performs parity checks on the address information and data information in the request event packets from the on-chip network; 2. After successful verification, the input control state machine and data parsing module parse the data, dividing it into two categories: 1) One type is configuration address (Addr), configuration data (Data), operation type (cfg_wr, 1 indicates configuration write operation, 0 indicates configuration read operation) and protocol type (cfg_sel). All of these data will be cached in the downstream buffer. 2) Another type is the routing information, length information, and address information required by the response event packet. All of these are written into the response information register of the packet assembly module for use when assembling response event packets.
[0025] The packet assembly module consists of an output control state machine, a data encapsulation submodule, a response information register, and a data register. Once the data parsing by the unpacking module is complete and passes verification, the packet assembly module begins operation, and its workflow is as follows: 1. Encapsulate header micro-chip, length body micro-chip, and address body micro-chip. Read routing information, length information, and address information from the response information register and encapsulate them sequentially into header micro-chip, length body micro-chip, and address body micro-chip. 2. Encapsulate data body fragments: Read data from the data register and encapsulate it into data body fragments (if it is a configuration write operation, the response event packet will not contain data body fragment encapsulation).
[0026] 3. Encapsulate the tail microchip; this completes the encapsulation of the entire response event packet.
[0027] The buffer, serving as a data buffer for the configuration circuit, connects the Kernel and Shell modules to implement data buffering functionality. The buffer can be divided into an input buffer and an output buffer, each using an asynchronous FIFO to handle cross-clock domain data transmission, ensuring secure and efficient data transfer.
[0028] Shell is responsible for parsing and encapsulating the APB protocol, and consists of two main functional blocks: data conversion and the APB protocol control state machine. Figure 5 As shown, the data read from the buffer is converted into configuration address and configuration data by the data conversion module. The APB protocol control state machine then converts the configuration address and configuration data into APB signals and outputs them to the on-chip network slave device.
[0029] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.
Claims
1. A method for configuring an on-chip network device, characterized in that, To configure the APB interface of the on-chip network device, the configuration method includes: using a custom protocol and transmitting according to a packet format; The configuration and configuration status reading of on-chip network devices are classified into four basic operations: configuration write request operation, configuration write response operation, configuration read request operation, and configuration read response operation. Four basic event packets are defined: configuration write request event packet, configuration write response event packet, configuration read request event packet, and configuration read response event packet, which correspond to the four basic operations respectively; The control information, address information, and data information to be transmitted are encoded in a unified format to form a complete event packet, which is then divided into micro-chips by the on-chip network circuit and transmitted sequentially.
2. The on-chip network device configuration method as described in claim 1, characterized in that, The data transmitted in the on-chip network device within one clock cycle is defined as a chip. Each event packet consists of several chips. All event packets contain a header chip that marks the start of the event packet, several individual chips, and a tail chip that marks the end of the event packet. The configuration write request event packet and the configuration read response event packet consist of 5 micro-fragments: header micro-fragment, length body micro-fragment, address body micro-fragment, data body micro-fragment, and tail micro-fragment. The configuration write response event packet and the configuration read request event packet consist of four fragments: a header fragment, a length body fragment, an address body fragment, and a trailer fragment; among them, The length micro-fragment is a micro-fragment that carries the length information of the event packet; the address micro-fragment is a micro-fragment that carries the address information for configuration write and configuration read; and the data micro-fragment is a micro-fragment that carries the data information for configuration write and configuration read back.
3. The on-chip network device configuration method as described in claim 1, characterized in that, The configuration method employs a combination of parity checking, triple modular redundancy, and request-based timeout retransmission to ensure its reliability. The configuration address and configuration data are configured with a parity bit every 8 bits to ensure the correctness of the configuration; Tri-mode redundancy is applied to critical routing information to ensure the correctness of the routing; A request-based timeout retransmission mechanism is adopted to further ensure the reliability of the configuration method.
4. The on-chip network device configuration method as described in claim 1, characterized in that, The on-chip network device includes an on-chip network master device and an on-chip network slave device. The on-chip network master device assembles configuration control information, address information, and data information into a configuration write request event packet according to its own protocol. The configuration write request event packet is routed to the on-chip network slave device. The configuration circuit of the on-chip network slave device performs parity check on the configuration write request event packet. If the parity check passes, it returns a configuration write response event packet to notify the on-chip network master device that the configuration is successful. If the parity check fails, it does not return a response packet. In the reconfiguration step, if the on-chip network master device does not receive a response packet after a specified time after sending the configuration write request event packet, it triggers a timeout retransmission.
5. The on-chip network device configuration method as described in claim 4, characterized in that, The on-chip network master device assembles the address information to be read into a configuration read request event packet according to its own protocol. The configuration read request event packet is routed to the on-chip network slave device to read the data in the address. If the data is successfully read, a configuration read response event packet carrying the read address and read data is returned to the on-chip network master device. In the configuration status reread step, if the on-chip network master device does not receive the read response event packet within a specified time, it triggers a timeout retransmission and rereads the data in the address of the on-chip network slave device.
6. A configuration circuit based on the on-chip network device configuration method according to any one of claims 1-5, characterized in that, It includes three circuit modules: kernel, cache, and encapsulation layer; among them, The kernel circuit module is functionally divided into two main circuit modules: packet assembly and decompression. Both are controlled by state machines. The decompression circuit module is mainly responsible for parsing event packets into configuration addresses and configuration data, and then passing them to the cache circuit module for caching. The packet assembly circuit module is mainly responsible for reading data from the cache circuit module and reading routing information, length information, and address information from the response information register in the kernel circuit module, encapsulating them into response event packets, and returning them to the on-chip network master device. The encapsulation layer circuit module mainly consists of an APB protocol control state machine and a data conversion submodule. It can read the configuration address and configuration data from the cache circuit module and encapsulate them according to the APB protocol, or parse the APB protocol data into configuration address and configuration data and pass them to the cache circuit module for caching. The buffer circuit module consists of two parts: an input buffer and an output buffer. Each part uses an asynchronous FIFO to solve the problem of data transmission across clock domains.