Configurable on-chip memory system and method, processor chip, and electronic device

Abstract

This application relates to a configurable on-chip memory system and method, a processor chip, and an electronic device, belonging to the field of electronic technology. The on-chip memory system includes a memory, a multi-level configuration unit, an arbitration circuit, and a selection circuit. The memory contains multiple memory rows, each including a data area and a configurable area. The multi-level configuration unit generates configuration signals indicating the storage mode of the configurable area for each memory row. The arbitration circuit prioritizes and arbitrates configuration signals from different levels, outputting a selection signal. The selection circuit is connected to both the memory and the arbitration circuit. Based on the selection signal, the selection circuit selects whether to write ECC checksums or metadata to the configurable area during a write operation, and selects whether to output data from the configurable area to the ECC checksum branch or the metadata branch during a read operation. This application can improve storage resource utilization and computational efficiency while ensuring reliability requirements.

Description

Technical Field

[0001] This application belongs to the field of electronic technology, specifically relating to a configurable on-chip storage system and method, a processor chip, and an electronic device. Background Technology

[0002] In modern high-performance processors, on-chip Static Random Access Memory (SRAM) is a critical resource determining computational performance. Register File (VRF) and Shared Memory (SMEM), as on-chip storage units closest to the computing core, directly impact parallel computing efficiency with their access speed and capacity. In General Purpose Graphics Processing Unit (GPGPU) or GPU architectures, both types of storage resources reside within the Streaming Multiprocessor (SM), exhibiting extremely low access latency and extremely high bandwidth, making them core resources determining the parallel computing performance of GPGPU or GPU. Specifically, the register file is thread-private, used to store local variables and intermediate computation results; shared memory is shared within thread blocks, used to achieve high-speed data exchange and collaboration between threads. Working together, they constitute the data exchange hub for parallel computing within the SM.

[0003] To improve data reliability and prevent soft errors caused by cosmic rays, electromagnetic interference, and other sources, on-chip storage typically incorporates Error Correcting Code (ECC) technology. Common Single Error Correction Double Error Detection (SECDED) codes generate and store additional check bits during data writing. A typical configuration involves 64-bit data with an 8-bit ECC checksum, resulting in approximately 12.5% ​​additional storage overhead. This technology is widely used in scientific computing and AI training. Scientific computing demands extremely high data reliability and has zero tolerance for errors; AI training, due to its high cost, valuable data, and low-precision format sensitivity to errors, also heavily relies on ECC protection.

[0004] As semiconductor manufacturing processes continue to shrink, the difficulty and cost of scaling memory cell sizes are increasing, making the area overhead caused by ECC (Electronic Compute Control) more and more prominent. Therefore, how to improve storage resource utilization and computing efficiency while ensuring reliability requirements is an urgent problem to be solved. Summary of the Invention

[0005] In view of this, this application provides a configurable on-chip storage system and method, processor chip and electronic device to improve storage resource utilization and computing efficiency while ensuring reliability requirements.

[0006] The embodiments of this application are implemented as follows: In a first aspect, embodiments of this application provide a configurable on-chip storage system, including: a memory, a multi-level configuration unit, an arbitration circuit, and a selection circuit; the memory includes multiple storage rows, each storage row including a data area and a configurable area; the multi-level configuration unit is used to generate configuration signals indicating the storage mode of the configurable area of ​​each storage row; the arbitration circuit is connected to the multi-level configuration unit, the arbitration circuit is used to perform priority arbitration on configuration signals from different levels, and output a selection signal; the selection circuit is connected to the memory and the arbitration circuit respectively, the selection circuit is used to select, during a write operation, to write an ECC checksum or metadata to the configurable area, and during a read operation, to select to output the data of the configurable area to the ECC checksum branch or the metadata branch.

[0007] In the above implementation scheme, the on-chip storage system with the above structure generates configuration signals through multi-level configuration units. An arbitration circuit prioritizes these configuration signals from different levels and outputs a selection signal. This selection signal allows the selection circuit to write ECC checksums or metadata into the configurable area during write operations and output the data from that area to the ECC checksum branch or metadata branch during read operations. Based on this, this application can flexibly configure the storage mode (storing ECC checksums or metadata) of the configurable area according to the actual needs of the computing scenario. On-chip storage space originally used for storing ECC checksums can be reused for storing metadata (such as scaling factors and non-zero indexes) in scenarios where ECC is not enabled or configured to store other data. This allows the same physical storage area to provide different functions for different thread bundles at different time slices, achieving dynamic switching of storage modes. Through this mechanism, this application effectively improves storage resource utilization and reduces hardware overhead while ensuring reliability requirements.

[0008] In one possible implementation of the first aspect embodiment, the multi-level configuration unit includes: an operand-level configuration unit and an instruction-level configuration unit; the operand-level configuration unit is used to generate a first configuration signal at the operand level; and the instruction-level configuration unit is used to generate a second configuration signal at the instruction level.

[0009] In the above implementation scheme, by setting up operand-level configuration units and instruction-level configuration units, this application can perform fine-grained configuration of the storage mode of configurable regions at both the instruction and operand levels. Through this design, this application can flexibly allocate storage resources for computing tasks of different granularities based on the different attributes of instructions and operands, enabling high-precision computing tasks to obtain ECC protection and low-precision computing tasks to obtain metadata storage space, thereby further improving the utilization efficiency of storage resources and meeting the diverse needs for dynamic switching of storage modes in complex computing scenarios.

[0010] In one possible implementation of the first aspect embodiment, the multi-level configuration unit further includes at least one of a thread bundle-level configuration unit, a thread block-level configuration unit, and a dispatch-level configuration unit; the thread bundle-level configuration unit is used to generate a third configuration signal at the thread bundle level; the thread block-level configuration unit is used to generate a fourth configuration signal at the thread block level; and the dispatch-level configuration unit is used to generate a fifth configuration signal at the dispatch level.

[0011] In the above implementation scheme, by further adding at least one of the thread bundle-level configuration unit, thread block-level configuration unit, and dispatch-level configuration unit, a multi-level, progressive configuration system is constructed, from dispatch level (coarse-grained) to thread block level, thread bundle level, and then to instruction level and operand level (fine-grained). This system can flexibly configure the storage mode of configurable areas according to different granularities of computing tasks, achieving step-by-step coverage from coarse-grained to fine-grained. The upper-level configuration provides default values ​​for the lower-level configuration, and the lower-level configuration can override the upper-level configuration according to actual needs, thereby effectively reducing the transmission overhead of configuration signals while ensuring system flexibility. Therefore, this application provides refined storage resource management capabilities for complex heterogeneous computing scenarios such as mixed-precision computing and sparse matrix operations, further improving storage resource utilization and computing efficiency. In a possible implementation of the first aspect embodiment, the arbitration circuit includes: a target arbitrator, used to arbitrate the first configuration signal and the second configuration signal, and output a target arbitration result, wherein the target arbitration result is the selection signal.

[0012] In the above implementation scheme, by setting a target arbitrator to arbitrate the first configuration signal and the second configuration signal, when the first configuration signal and the second configuration signal exist at the same time, the configuration that finally takes effect can be determined according to the preset priority rules (the first configuration signal has the highest priority), thereby realizing progressive coverage from the instruction level to the operand level. The instruction-level configuration can provide a unified default behavior for multiple operands under the same instruction, while the operand-level configuration can be personalized for specific operands to meet the differentiated needs of storage mode in mixed precision computing scenarios.

[0013] In one possible implementation of the first aspect embodiment, the arbitration circuit includes: a first arbitrator, a second arbitrator, a third arbitrator, a fourth arbitrator, and a fifth arbitrator; the first arbitrator is connected to the dispatch-level configuration unit and the global-level configuration unit respectively, and is used to arbitrate the global configuration signal from the global-level configuration unit and the fifth configuration signal, and output a first arbitration result; the second arbitrator is connected to the first arbitrator and the thread block-level configuration unit respectively, and is used to arbitrate the first arbitration result and the fourth configuration signal, and output a second arbitration result; the third arbitrator is connected to the second arbitrator and the thread bundle-level configuration unit respectively, and is used to arbitrate the second arbitration result and the third configuration signal, and output a third arbitration result; the fourth arbitrator is connected to the third arbitrator and the instruction-level configuration unit respectively, and is used to arbitrate the third arbitration result and the second configuration signal, and output a fourth arbitration result; the fifth arbitrator is connected to the fourth arbitrator and the operand-level configuration unit respectively, and is used to arbitrate the fourth arbitration result and the first configuration signal, and output a fifth arbitration result, wherein the fifth arbitration result is the selection signal.

[0014] In the above implementation scheme, a distributed arbitration structure is adopted, in which first to fifth arbitrators are connected in series and arbitrate configuration signals of adjacent levels respectively, thereby achieving efficient processing of multi-level configuration signals. Specifically, the distributed arbitration structure decomposes the originally complex multi-input priority judgment into multiple simple two-level arbitration units. Each arbitrator only needs to process two input signals (such as the arbitration result of the previous level and the configuration signal of the current level). The logic is simple, the path is short, and it is easy to pipelining design, thereby significantly reducing single-level logic latency and facilitating timing convergence.

[0015] In one possible implementation of the first aspect embodiment, the operand-level configuration unit is configured to generate the first configuration signal according to the data precision of the operand in the instruction; if the data precision of the operand is a first precision, the first configuration signal indicates that the configurable area is used to store ECC checksums; if the data precision of the operand is a second precision, the first configuration signal indicates that the configurable area is used to store metadata; wherein the bit width of the data with the first precision is higher than the bit width of the data with the second precision.

[0016] In the above implementation scheme, the operand-level configuration unit automatically generates a first configuration signal based on the data precision of the operands: when the data precision is the first precision (high bit width), it indicates that the configurable area can store ECC checksums; when the data precision is the second precision (low bit width), it indicates that the configurable area can store metadata. This mechanism enables adaptive configuration of storage modes without explicit software intervention, ensuring that high bit width data receives ECC protection and that low bit width data efficiently reuses the checksum area. This achieves on-demand allocation of storage resources under different precision calculation scenarios, further improving storage resource utilization and overall system performance.

[0017] In one possible implementation of the first aspect embodiment, the selection circuit includes: a write multiplexer and a read multiplexer; a first input of the write multiplexer is coupled to the ECC check branch to receive the ECC checksum, a second input is coupled to the metadata branch to receive the metadata, and an output is coupled to the write data path of the memory; an input of the read multiplexer is coupled to the read data path of the memory to receive data stored in a configurable area, a first output of the read multiplexer is coupled to the ECC check branch, and a second output of the read multiplexer is coupled to the metadata branch.

[0018] In the above implementation scheme, parallel processing of read and write operations is achieved by independently controlling the write and read paths using write multiplexers and read multiplexers, respectively. Specifically, the write multiplexer is responsible for selecting whether to write the ECC checksum or metadata to the configurable area during a write operation, while the read multiplexer is responsible for selecting whether to output the data from the configurable area to the ECC checksum branch or the metadata branch during a read operation. The two paths are independent of each other, allowing read and write operations to occur simultaneously without blocking each other, thereby effectively improving the access throughput of the storage system. The read-write separation architecture also provides the hardware foundation for row-level dynamic hybrid mode and time-sharded multiplexing, enabling different storage rows to maintain high-efficiency read and write concurrency capabilities under different modes, further improving the overall system performance. In one possible implementation of the first aspect embodiment, the selection signal is further used to enable or disable the ECC verification branch; when the selection signal indicates that data of the configurable area is output to the ECC verification branch, the ECC decoder in the ECC verification branch is enabled; when the selection signal indicates that data of the configurable area is output to the metadata branch, the ECC decoder in the ECC verification branch is disabled.

[0019] In the above implementation scheme, the enable and disable of the ECC decoder are controlled by multiplexing the selection signal, eliminating the need for a separate enable signal and effectively reducing hardware overhead. Specifically, when the selection signal indicates that data from the configurable area is output to the ECC verification branch, the ECC decoder is enabled to perform error detection and correction on the read data; when the selection signal indicates that data from the configurable area is output to the metadata branch, the ECC decoder is disabled to avoid unnecessary circuit switching. This on-demand enable design ensures that the ECC decoder only operates in scenarios where error correction protection is truly needed, and remains in a low-power state in scenarios where error correction is not required, such as metadata mode, thereby effectively reducing the overall system power consumption.

[0020] In one possible implementation of the first aspect embodiment, during a write operation, the selection signal is written to the configurable area along with the ECC checksum or the metadata; during a read operation, the selection signal read from the configurable area is used to control the path selection of the selection circuit.

[0021] In the above implementation scheme, by writing the selection signal along with the ECC check code or metadata into the configurable area during the write operation, and by directly controlling the path selection of the selection circuit by the read selection signal during the read operation, this design allows each storage line to independently carry its own mode identifier, and completes the correct selection of the read path without the need for external configuration registers or real-time arbitration, effectively reducing the complexity of the control logic and the signal transmission overhead.

[0022] In one possible implementation of the first aspect embodiment, the metadata includes a scaling factor used to map second-precision data to a range of third-precision data representations.

[0023] In the above implementation scheme, by introducing a scaling factor, this application can efficiently utilize the storage resources of the configurable region in low-precision computing scenarios. Specifically, the scaling factor is used in the quantization and dequantization processes in low-precision computing: in the quantization stage, the high-precision (e.g., third-precision) master data is divided by the scaling factor to compress it to the representable range of the low-precision (e.g., logarithmic precision) format; in the dequantization stage, the low-precision calculation result is multiplied by the scaling factor to restore it to the high-precision dynamic range. When the configurable region is configured in metadata mode, this region can be used to store the scaling factor, thereby achieving synchronous memory access of data and the scaling factor in calculations such as low-precision matrix multiplication.

[0024] In one possible implementation of the first aspect embodiment, the metadata includes a non-zero index that indicates the position of the compressed non-zero element in the uncompressed sparse matrix.

[0025] In the above implementation scheme, by introducing non-zero indexes, this application can efficiently utilize the storage resources of the configurable region in sparse computing scenarios. Specifically, the non-zero indexes are used to indicate the position information of non-zero elements in the sparse matrix before compression. When the configurable region is configured in metadata mode, the region can be used to store non-zero indexes, so that even after compressing and storing the sparse matrix (only saving non-zero values), the correct operands can still be accurately located and selected from the original data stream for computation during the calculation process.

[0026] Secondly, embodiments of this application also provide a processor chip, including an on-chip storage system provided as described in the first aspect embodiments and / or in combination with any possible implementation of the first aspect embodiments.

[0027] Thirdly, embodiments of this application also provide an electronic device, including the processor chip provided in the second aspect of the embodiments described above.

[0028] Fourthly, embodiments of this application also provide a configurable on-chip storage method, comprising: performing priority arbitration on configuration signals from different levels of a multi-level configuration unit and outputting a selection signal; wherein the configuration signal is used to indicate the storage mode of a configurable region for each storage row of the memory; the memory is connected to an ECC verification branch and a metadata branch respectively, the ECC verification branch is used to transmit ECC check codes, and the metadata branch is used to transmit metadata; during a write operation, according to the selection signal, selecting to write the ECC check code or metadata to the corresponding configurable region of the memory; during a read operation, according to the selection signal, selecting to output the data of the configurable region to the ECC verification branch or the metadata branch.

[0029] The technical effects of any of the implementation methods in the second to fourth aspects can be referred to the technical effects of the same or similar implementation methods in the first aspect, and will not be repeated here.

[0030] Other features and advantages of this application will be set forth in the following description. The objectives and other advantages of this application can be realized and obtained through the structures specifically pointed out in the written description and the accompanying drawings. Attached Figure Description

[0031] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the accompanying drawings used in the embodiments will be briefly described below. Obviously, the drawings described below are only some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings. The above and other objects, features, and advantages of this application will become clearer through the accompanying drawings.

[0032] Figure 1A schematic diagram of an on-chip storage system provided in an embodiment of this application is shown.

[0033] Figure 2 This illustration shows a schematic diagram of the principle of memory read / write control provided in an embodiment of this application.

[0034] Figure 3 This illustration shows a schematic diagram of a storage mode for an operand-level configuration memory provided in an embodiment of this application.

[0035] Figure 4a This diagram illustrates a storage mode of an instruction-level configuration memory provided in an embodiment of this application.

[0036] Figure 4b This illustration shows a schematic diagram of another instruction-level configuration memory storage mode provided in an embodiment of this application.

[0037] Figure 5 This illustration shows a schematic diagram of a storage mode for a dispatch-level configuration memory provided in an embodiment of this application.

[0038] Figure 6 This diagram illustrates a configuration hierarchy of a memory mode according to an embodiment of this application.

[0039] Figure 7 A schematic diagram of the structure of an electronic device provided in an embodiment of this application is shown. Detailed Implementation

[0040] The technical solutions of the embodiments of this application will now be described with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. The following embodiments are provided as examples to more clearly illustrate the technical solutions of this application, and should not be used to limit the scope of protection of this application. Those skilled in the art will understand that, without conflict, the following embodiments and features can be combined with each other.

[0041] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, relational terms such as "first," "second," etc., in the description of this application are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus.

[0042] Furthermore, the term "and / or" in this application is merely a description of the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can represent three situations: A exists alone, A and B exist simultaneously, and B exists alone.

[0043] In the description of the embodiments of this application, unless otherwise expressly specified and limited, the technical term "connection" can be a direct connection or an indirect connection through an intermediate medium.

[0044] To improve storage resource utilization and computational efficiency while ensuring reliability, embodiments of this application provide a configurable on-chip storage system and method, processor chip, and electronic device. Given that different computing scenarios have different requirements for ECC (Extended Computation Control), for example, scientific computing and AI training have extremely high data reliability requirements, necessitating strong protection from ECC; while AI inference (especially low-precision inference) has a higher tolerance for errors and requires the storage of metadata such as scaling factors (SF) and non-zero indexes to improve computational efficiency. Therefore, this application reuses on-chip storage space originally used for storing ECC checksums for storing metadata (such as scaling factors and non-zero indexes) in scenarios where ECC is not enabled (or configured to store other data). This allows the same physical storage area to provide different functions for different thread bundles at different time slices, achieving dynamic switching, thereby improving storage utilization and reducing hardware overhead.

[0045] The solution provided in this application enables dynamic, fine-grained, and functional reuse of the ECC parity bit area of ​​on-chip storage space, allowing the same physical storage area to dynamically switch its function for different thread bundles according to time slices, effectively improving storage resource utilization and computing efficiency while ensuring reliability requirements.

[0046] The following is combined Figure 1The configurable on-chip storage system provided in the embodiments of this application will be described. The on-chip storage system includes: a memory, a multi-level configuration unit, an arbitration circuit, and a selection circuit. Figure 1 Only the case with two selection circuits is shown. In some implementations, the on-chip memory system may contain only one selection circuit, or more selection circuits, such as one selection circuit for each memory row. Figure 1 The dashed lines indicate optional features, meaning the arbitration circuit can also be connected to a memory to store the selection signal. In some possible implementations, the on-chip memory system may also include an ECC check branch or a metadata branch, wherein the ECC check branch is used to output an ECC checksum or to verify a received ECC checksum, and the metadata branch is used to output or receive metadata.

[0047] The memory comprises multiple storage rows, each consisting of a data area and a configurable area. The data area stores master data, while the configurable area stores the ECC checksum corresponding to the master data, or metadata associated with the master data. For example, the data area stores 64 bits of data, while the configurable area stores an 8-bit ECC checksum or metadata.

[0048] The ECC checksum is generated by performing ECC verification on the master data; the metadata may include a non-zero index, which indicates the position of the compressed master data (non-zero elements) in the sparse matrix before compression; or the metadata may include a scaling factor (SF), which maps the second-precision master data to the range that the third-precision data can represent. The bit width of the second-precision data is higher or lower than the bit width of the third-precision data. When the second precision is low, the third precision can be high, and vice versa.

[0049] The memory in this application can be of various types, including but not limited to static random access memory (SRAM), dynamic random access memory (DRAM), and magnetoresistive random access memory (MRAM). In the following examples, SRAM will be used primarily for illustration, but this should not be construed as a limitation on the scope of protection of this application.

[0050] In some possible implementations, the metadata may simultaneously include a scaling factor and a non-zero index. Correspondingly, the metadata branch may include two paths: a first metadata branch and a second metadata branch. The first metadata branch is used to transmit the scaling factor, and the second metadata branch is used to transmit the non-zero index. In the following examples, we will primarily illustrate the case where the metadata simultaneously includes a scaling factor and a non-zero index.

[0051] The scaling factor is a core technology for implementing low-precision matrix multiplication. Essentially, it's a multiplier used to overcome the inherent limitation of the limited dynamic range of low-precision formats. The scaling factor is primarily used in the quantization and dequantization processes of low-precision computations: during quantization, high-precision data (such as FP16 and BF16) is divided by the scaling factor to compress it to the representable range of low-precision formats (such as FP8, FP6, and FP4) to prevent data overflow or precision loss; during dequantization, the low-precision calculation result is multiplied by the scaling factor (or another related inverse scaling factor) to restore the high-precision dynamic range, supporting subsequent high-precision computations. Through this mechanism, the scaling factor can maintain model accuracy while ensuring computational efficiency, where the bit width of high-precision data is higher than that of low-precision data.

[0052] In this application, the bit width of the metadata matches the bit width of the ECC checksum. Taking the SECDED code with single-correction and double-detection as an example, common configurations include 32 bits of data with a 7-bit checksum, or 64 bits of data with an 8-bit checksum. 128 bits of data requires a 9-bit checksum. In tensor computation scenarios with precision lower than FP8, an 8-bit scaling factor is typically configured for every 32 or 16 data points.

[0053] For example, in the FP4 data format, 64 bits can store 16 data points. If an 8-bit scaling factor is configured at a granularity of 16 data points, then this configuration is exactly the same as the configuration of 64-bit data with an 8-bit SECDED checksum.

[0054] For example, in the FP4 data format, 128 bits can store 32 data. If an 8-bit scaling factor is configured at a granularity of 32 data, then in the 9-bit SECDED checksum corresponding to the 128-bit data, 8 bits can be used to store the scaling factor, and the remaining 1 bit can be used to identify whether the current storage row stores the ECC checksum or the scaling factor, or used as other identification information, or left blank as a reserved bit.

[0055] For example, in the FP8 data format, 128 bits can store 16 data. If an 8-bit scaling factor is configured at a granularity of 16 data, then in the 9-bit SECDED checksum corresponding to the 128-bit data, 8 bits can be used to store the scaling factor, and the remaining 1 bit can be used to identify whether the current storage row stores the ECC checksum or the scaling factor, or used as other identification information, or left blank as a reserved bit.

[0056] Through the above bit-width matching design, this application can efficiently reuse the original parity bit area as metadata storage space while maintaining ECC protection capabilities, thereby improving storage resource utilization.

[0057] A non-zero index is an auxiliary data structure used to record the position information of non-zero elements in a sparse matrix. Essentially, it belongs to index encoding and is used to indicate the relative position of each non-zero element in the original dense matrix. When storing sparse matrices in a compressed manner (i.e., only storing non-zero values), this index can accurately locate and select the required operands from the original data stream during subsequent computations, thereby achieving efficient computation. Taking a 2:4 sparse granularity as an example, the rule is as follows: in each row of the matrix, every four consecutive elements form a sub-block, and each sub-block contains exactly two non-zero elements, with the other two being zero. The position of each non-zero element is represented by a 2-bit encoding. For data in fp16 and bf16 formats, 64 bits can store 4 data items, requiring an 8-bit non-zero index. This configuration is exactly the same as the configuration of 64-bit data with an 8-bit SECDED checksum. For data in f8, s8, and u8 formats, 64 bits can store 8 data items. If we take a pairwise 4:8 sparse granularity (i.e., every 2 data items share a non-zero index) as an example, then a total of 8 non-zero indexes are required, which also matches the configuration of 64-bit data with an 8-bit SECDED checksum.

[0058] Based on the above bit-width matching design, this application can efficiently reuse the original parity bit area as storage space for non-zero indexes while maintaining ECC protection capabilities, thereby improving storage resource utilization.

[0059] In some possible implementations, the bit width of the configurable region matches the bit width of the ECC checksum and the selection signal. When the metadata includes both a scaling factor and a non-zero index, the selection signal requires 2 bits to indicate to the selection circuitry that it should select one of the following: the ECC checksum (ECC), the scaling factor (SF), or the non-zero index. For example, if the data region has a bit width of 128 bits, the corresponding ECC checksum bit width is 9 bits, and the selection signal bit width is 2 bits, then the configurable region has a bit width of 11 bits, where the metadata is either an 8-bit scaling factor or an 8-bit non-zero index. As another example, if the data region has a bit width of 64 bits, the corresponding ECC checksum bit width is 8 bits, and the selection signal bit width is 2 bits, then the configurable region has a bit width of 10 bits, where the metadata is either an 8-bit scaling factor or an 8-bit non-zero index.

[0060] The multi-level configuration unit is connected to the arbitration circuit and is used to generate configuration signals indicating the configurable region storage mode for each storage row. The arbitration circuit is also connected to the selection circuit, which prioritizes the configuration signals from different levels and outputs a selection signal to the selection circuit. This selection signal instructs the selection circuit to select the corresponding data for transmission.

[0061] In some possible implementations, such as Figure 1 As shown, the arbitration circuit can also be connected to a memory to store the corresponding selection signal in the memory, so that during a read operation, the selection circuit (such as DEMUX) can select the data transmission path of the configurable area based on the stored selection signal.

[0062] The selection circuit is connected to the memory and the arbitration circuit respectively. The selection circuit is used to select whether to write the ECC check code or metadata to the configurable area during a write operation, and to select whether to output the data of the configurable area to the ECC check branch or the metadata branch during a read operation, based on the selection signal.

[0063] Optionally, the selection circuit includes a write multiplexer (such as a MUX) and a read multiplexer (such as a DEMUX). The first input of the write multiplexer is coupled to the ECC check branch to receive the ECC checksum, the second input is coupled to the metadata branch to receive metadata, and the output is coupled to the write data path of the memory. The input of the read multiplexer is coupled to the read data path of the memory to receive data stored in the configurable area, the first output of the read multiplexer is coupled to the ECC check branch, and the second output of the read multiplexer is coupled to the metadata branch. It is understood that when there are two metadata branches, the write multiplexer also includes a third input, wherein the second and third inputs of the write multiplexer are respectively connected to the two metadata branches. Similarly, the read multiplexer also includes a third output, wherein the second and third outputs of the read multiplexer are respectively connected to the two metadata branches.

[0064] In some possible implementations, the principle of the on-chip storage system is as follows: Figure 2 As shown, the selection circuit includes a MUX and a DEMUX. In the circuit, the MUX is used to select one output from multiple inputs, and the DEMUX is used to assign one input to one of the multiple outputs. In the selection circuit of this application, the write path typically uses the MUX to select and write ECC checksums or metadata to the configurable area, and the read path typically uses the DEMUX to distribute data from the configurable area to the ECC checksum branch or the metadata branch. The ECC checksum branch may include an encoder (ECCencode) located on the write path and a decoder (ECC decode) located on the read path.

[0065] Understandable Figure 2 The example shown only illustrates a data area used to store 64 bits of data, while a configurable area is used to store 8 bits of ECC checksum or metadata, and also stores 2 bits of select signals. The data area can also store other bits of data, such as 128 bits or 32 bits; therefore, this example should not be construed as limiting the scope of this application.

[0066] In some possible implementations, during a write operation, the selection signal can be written to the configurable area along with the ECC checksum or metadata; during a read operation, the selection signal read from the configurable area is used to control the path selection of the selection circuit. In some possible implementations, the selection signal can also enable or disable the ECC check branch. For example, when the selection signal indicates that data from the configurable area should be output to the ECC check branch, the ECC decoder in the ECC check branch is enabled; when the selection signal indicates that data from the configurable area should be output to the metadata branch, the ECC decoder in the ECC check branch is disabled.

[0067] In some possible implementations, the multi-level configuration unit includes an operand-level configuration unit and an instruction-level configuration unit. The operand-level configuration unit generates a first configuration signal at the operand level to configure the storage mode of the configurable region at the operand level; the instruction-level configuration unit generates a second configuration signal at the instruction level to configure the storage mode of the configurable region at the instruction level. The first configuration signal has a higher priority than the second configuration signal. When both configuration units simultaneously generate configuration signals indicating the configurable region storage mode for the same storage row, only the first configuration signal with the higher priority is used.

[0068] In one possible implementation, when generating the first configuration signal at the operand level, the operand-level configuration unit may generate the first configuration signal based on the data precision of the operand in the instruction. If the operand data precision is a first precision (e.g., high precision), the first configuration signal indicates that a configurable area is used to store ECC checksums; if the operand data precision is a second precision (e.g., low precision), the first configuration signal indicates that a configurable area is used to store metadata. The bit width of the data with the first precision is higher than the bit width of the data with the second precision.

[0069] For example, when the operands are in FP64 format, they are typically used for high-precision scientific computing, which requires extremely high data reliability. Therefore, the corresponding first configuration signal indicates that the configurable area stores ECC checksums. When the operands are matrices in FP16 or BF16 format, they are often used in AI training or sparse computing scenarios, requiring non-zero indices to improve computational efficiency. Therefore, the first configuration signal indicates that the configurable area stores non-zero indices. When the operands are matrices in FP8 or FP4 format, they are often used in low-precision inference scenarios, requiring scaling factors to achieve quantization and dequantization. Therefore, the first configuration signal indicates that the configurable area stores scaling factors.

[0070] In some possible implementations, when generating the first configuration signal at the operand level, the operand-level configuration unit may also determine the first configuration signal based on the OPERAND flag bit carried in the instruction. The OPERAND flag bit, as an explicit field in the instruction encoding, is used to indicate the storage mode of the configurable region corresponding to the current operand. For example, if the OPERAND flag bit carried in the instruction indicates a first mode, the first configuration signal indicates that the configurable region is used to store ECC checksums; if the OPERAND flag bit indicates a second mode, the first configuration signal indicates that the configurable region is used to store metadata.

[0071] In practical applications, the two methods mentioned above can be used in combination: when the instruction does not carry the OPERAND flag or the flag is invalid, the operand-level configuration unit can automatically generate the first configuration signal according to the data precision of the operand; when the instruction carries a valid OPERAND flag, the indication of the flag is taken as the standard to achieve overriding of the default mode.

[0072] Understandably, an instruction can carry different operands, and different operands can correspond to different storage modes in the configurable regions, such as... Figure 3 As shown. For example, the configurable areas of the storage rows corresponding to Operand1 and Operand2 are used to store their corresponding ECC; the configurable areas of the storage rows corresponding to Operand3 and Operand5 are used to store their associated Index; and the configurable areas of the storage rows corresponding to Operand4 and Operand6 are used to store their associated SF. In this example, the bit width of the configurable area is 10 bits, of which 8 bits store ECC or metadata and 2 bits store the selection signal.

[0073] The instruction-level configuration unit generates a second configuration signal at the instruction level to configure the storage mode of the configurable region at the instruction level. Specifically, each instruction contains a specific instruction field that identifies how the operands of that instruction use the SRAM checksum region. The instruction-level configuration unit generates the corresponding second configuration signal by parsing this instruction field. The second configuration signal generated by the instruction-level configuration unit can override the first configuration signal generated by the operand-level configuration unit to achieve higher priority control. That is, the storage mode of the configurable region for the corresponding memory row of operands in different types of instructions can be different, as shown in the schematic diagram. Figure 4a or Figure 4bAs shown. For example, the configurable area of ​​the operand-corresponding storage row of a High Performance Computing (HPC) instruction is used to store its corresponding ECC, the configurable area of ​​the operand-corresponding storage row of a sparse matrix instruction is used to store its associated Index, and the configurable area of ​​the operand-corresponding storage row of a low-precision matrix instruction is used to store its associated SF.

[0074] When the multi-level configuration unit includes an operand-level configuration unit and an instruction-level configuration unit, the arbitration circuit may include a target arbitrator for arbitrating the first configuration signal and the second configuration signal and outputting a target arbitration result, wherein the target arbitration result is the selection signal mentioned above.

[0075] In some possible implementations, the multi-level configuration unit further includes at least one of a thread bundle-level configuration unit, a thread block-level configuration unit, and a dispatch-level configuration unit. The thread bundle-level configuration unit generates a third configuration signal at the thread bundle level (Warp) to configure the storage mode of the configurable region at the thread bundle level; the thread block-level configuration unit generates a fourth configuration signal at the thread block level (Thread Block) to configure the storage mode of the configurable region at the dispatch level; and the dispatch-level configuration unit generates a fifth configuration signal at the dispatch level (Dispatch) to configure the storage mode of the configurable region at the dispatch level. Through the hierarchical design of the above configuration units, this application realizes a multi-level, progressive configuration system from the dispatch level (coarse-grained) to the thread block level, thread bundle level, and then to the instruction level and operand level (fine-grained).

[0076] A dispatch task can contain multiple thread blocks, each containing multiple threads (e.g., 1024 threads), with 32 threads forming a warp. All threads within the same warp execute the same instruction stream, and each instruction typically contains one or more operands.

[0077] Similar to the aforementioned instructions or operands, different dispatch tasks can employ different storage models, such as... Figure 5As shown, for example, the kernel of Dispatch 1 performs scientific computing tasks, and its configurable region is configured in ECC mode; the kernel of Dispatch 2 performs sparse matrix training tasks, and its configurable region is configured in non-zero index mode; the kernel of Dispatch 3 performs low-precision inference tasks, and its configurable region is configured in scaling factor mode. In this example, the bit width of the configurable region is 10 bits, of which 8 bits store ECC or metadata and 2 bits store selection signals. Similarly, different thread blocks or different thread bundles under the same dispatch can also be configured with different storage modes according to actual needs, which will not be elaborated here.

[0078] In one possible implementation, the configuration hierarchy of the storage mode for the configurable region is as follows: Figure 6 As shown, a total of six levels are involved, forming a hierarchical configuration system. In this system, each level can inherit the default configuration of the level above it, and can also override the configuration of the level above it according to actual needs, thereby achieving multi-granularity and highly flexible configuration management. Specifically, as... Figure 6 As shown, the configuration hierarchy from top to bottom is as follows: L1—Global Level (Global Hardware Switch): This level corresponds to the aforementioned global configuration unit and is implemented by the CPU or the CPU-side GPU driver initializing registers. Its function is to set the chip-level default security baseline, such as configuring all configurable regions to ECC mode by default. This level serves as a "security bottom line" that cannot be overridden by software runtime, providing fundamental protection for the entire chip.

[0079] L2 — Dispatch level (task-level default), this level corresponds to the aforementioned dispatch-level configuration unit and is controlled by the Work Distributor. Each dispatch has its own global flag to identify how all operands under that dispatch use the SRAM checksum region. When the CPU starts a kernel, this global flag is passed through the launch descriptor to generate the fifth configuration signal for the dispatch level, which configures the default storage mode of the configurable regions of memory accessed by the kernel during execution. For example, scientific computing kernels default to ECC mode for configurable regions, while AI inference kernels default to metadata mode.

[0080] L3—Thread Block Level: This level corresponds to the aforementioned thread block level configuration unit and is controlled by the Resource Manager within the Streaming Multiprocessor (SM). Different thread blocks can have different storage strategies, and the thread block level configuration unit generates a fourth configuration signal accordingly. For example, thread block A enables ECC protection when processing high-precision accumulation; thread block B uses metadata storage space when processing low-precision quantization, and both can coexist on the same SM.

[0081] L4—Thread Bundle Level. This level corresponds to the aforementioned thread bundle level configuration unit and is controlled by the thread bundle scheduler (WarpScheduler). Different thread bundles within the same thread block, or even the same thread bundle at different execution stages, can switch storage modes. The thread bundle level configuration unit generates a third configuration signal for the thread bundle level accordingly. For example, a thread bundle might enable ECC mode during gradient accumulation in the first half and disable ECC and reuse the parity bit as the scaling factor storage area during weight quantization in the second half.

[0082] L5 — Instruction Level (Explicitly Specified at the Instruction Level), this level corresponds to the aforementioned instruction-level configuration unit and is controlled by the instruction decoder. Specific attribute bit fields are extended in the instruction set to explicitly declare the storage mode required by the current instruction. The instruction-level configuration unit generates a second configuration signal based on this. For example, an instruction can explicitly declare "This read requires ECC protection" or "This write requires storing metadata," thereby temporarily overriding the default settings at the thread bundle level.

[0083] L6 — Operand Level. This level corresponds to the aforementioned operand level configuration unit, is controlled by the operand collector, and has the highest priority. The operand level configuration unit generates the first configuration signal for the operand level based on the data precision of the operands in the instruction or the OPERAND flag bit carried in the instruction.

[0084] Through the aforementioned six-level configuration system, this application achieves multi-level, progressive configuration management, from the dispatch level (coarse-grained) to the thread block level, thread bundle level, and then to the instruction level and operand level (fine-grained). The upper-level configuration provides default values ​​for the lower-level configuration, and the lower-level configuration can override the upper-level configuration according to actual needs. This effectively reduces the transmission overhead of configuration signals while ensuring system flexibility, and achieves efficient utilization of storage resources.

[0085] In modern high-performance computing scenarios, there's a tendency to place different types of instructions into different warps within the same dispatch to reduce the number of accesses to high-bandwidth memory. Whether tasks are divided into multiple dispatches or merged into a single dispatch, as long as these tasks are scheduled to execute on the same streaming multiprocessor (SM), different types of instructions will inevitably be running in parallel at the same time. Different types of instructions may use register files (VRFs) at different addresses within the same SM, allowing the parity bit regions of the VRFs corresponding to different instructions to store different types of slave data. This fine-grained hybrid execution mode places higher demands on the dynamic configuration capabilities of on-chip memory resources.

[0086] Therefore, based on the aforementioned six-level configuration system, this application can achieve row-level dynamic hybrid mode. At any given time, a portion of the memory rows can be configured in the first mode, using the configurable area to store ECC checksums; another portion of the memory rows can be configured in the second mode, using the configurable area to store metadata corresponding to the master data (such as scaling factors or non-zero indexes). Through a dynamic address remapping mechanism, the configurable areas of different memory rows can work collaboratively in hybrid mode, flexibly adapting to the aforementioned complex execution scenarios.

[0087] Building upon this, this application also supports dynamic switching on the timeline. In ECC-disabled mode, the same physical storage region can provide different functions for different thread bundles at different time slices. For example, in the Single Instruction Multiple Threads (SIMT) architecture of GPGPU, three thread bundles can access SRAM in an interleaved manner: Thread bundle A is used for high-performance computing and requires ECC to be enabled to ensure high accuracy and high reliability; Thread bundle B is used for large model training and requires the use of sparse matrices to reduce data handling and double computing power; Thread bundle C is used for large model inference, where low-precision local batch data can be extended in numerical representation range by sharing scaling factors to avoid long-tail data loss.

[0088] Through the aforementioned row-level dynamic hybrid and time-slicing reuse mechanism, this application achieves flexible support for complex heterogeneous computing scenarios. Its control logic and hardware architecture differ from traditional static space allocation schemes, and can effectively improve storage resource utilization and computing efficiency while ensuring reliability requirements.

[0089] To avoid additional logical latency caused by each configuration level, this application adopts an "inheritance + differential" transmission mechanism. Default inheritance: Lower-level configurations directly use the configuration values ​​of higher-level configurations by default. For example, if the dispatch level is set to ECC mode, all thread blocks, thread bundles, and instructions under that dispatch will default to ECC mode, requiring no additional signal transmission. Differential overriding: A valid overriding signal is generated only when a certain level needs to change its default configuration; other levels maintain their inherited state.

[0090] Priority arbitration logic can be designed at the entry point of the SRAM controller to determine the final mode according to the order of priority from high to low: if a valid configuration signal is provided at L6 (operand level), the L6 mode is used; otherwise, if a valid configuration signal is provided at L5 (instruction level), the L5 mode is used; otherwise, if a valid configuration signal is provided at L4 (thread bundle level), the L4 mode is used; otherwise, if a valid configuration signal is provided at L3 (thread block level), the L3 mode is used; otherwise, the default mode of L2 (dispatch level) is used. This arbitration logic ensures that the finest-grained configuration has the highest priority, with the upper-level configuration serving as the default value for the lower level, thus achieving flexible and efficient configuration management.

[0091] When adopting the aforementioned six-level hierarchical configuration architecture, one possible implementation involves a distributed arbitration circuit comprising: a first arbitrator, a second arbitrator, a third arbitrator, a fourth arbitrator, and a fifth arbitrator. Each arbitrator is connected in series, arbitrating the configuration signals of adjacent levels and passing the arbitration result to the next level. This distributed arbitration structure offers advantages such as logical simplicity and ease of pipelining, helping to reduce single-level logic latency and improve timing convergence.

[0092] Understandably, in some scenarios, the five arbitrators mentioned above can be combined into one arbitrator. This arbitrator is simultaneously coupled to each level of configuration unit, and performs unified arbitration on the configuration signals of all levels according to preset priority rules, directly outputting the final selection signal.

[0093] The first arbitrator is connected to the dispatch-level configuration unit and the global-level configuration unit respectively, and is used to arbitrate the global configuration signal and the fifth configuration signal from the global-level configuration unit and output the first arbitration result.

[0094] The second arbitrator is connected to the first arbitrator and the thread block-level configuration unit, respectively, and is used to arbitrate the first arbitration result and the fourth configuration signal, and output the second arbitration result.

[0095] The third arbitrator is connected to the second arbitrator and the thread bundle-level configuration unit, respectively, and is used to arbitrate the second arbitration result and the third configuration signal, and output the third arbitration result.

[0096] The fourth arbitrator is connected to the third arbitrator and the instruction-level configuration unit, respectively, and is used to arbitrate the third arbitration result and the second configuration signal, and output the fourth arbitration result.

[0097] The fifth arbitrator is connected to the fourth arbitrator and the operand-level configuration unit, respectively, and is used to arbitrate the fourth arbitration result and the first configuration signal, and output the fifth arbitration result, wherein the fifth arbitration result is a selection signal.

[0098] In some implementations, this application provides two optional configuration schemes, each applicable to different configuration levels.

[0099] Option A: Static mapping based on physical partitions (applicable to L2 to L4 levels). This option does not require frequent mode switching between clock cycles for the same physical memory row. Instead, it divides the memory array into different logical regions, and the configuration of the L2 to L4 levels determines which physical region a thread bundle is mapped to. For example, the first 50% of the SRAM can be fixed in ECC mode, and the last 50% in metadata mode. This option has the advantages of simple implementation and low power consumption.

[0100] Option B: Utilizing multiplexers (suitable for L5 to L6 levels) to address scenarios requiring dynamic switching. A lightweight multiplexer is placed at each of the SRAM entry and exit points, determining the storage mode of the configurable region based on the final selection signal. During write operations, the write multiplexer at the entry point selects to write either the ECC checksum or metadata to the configurable region of the currently accessed memory row, based on the final selection signal. During read operations, the read multiplexer at the exit point selects to output the configurable region data of the currently accessed memory row to either the ECC checksum branch or the metadata branch, based on the final selection signal. Both multiplexers are time-divisionally controlled by the same selection signal, ensuring consistency between write and read operations.

[0101] This application also provides a processor chip that includes the aforementioned on-chip storage system. The processor chip described in this application can be of various types, including but not limited to GPUs, GPGPUs, artificial intelligence accelerators, Neural Network Processing Units (NPUs), Tensor Processing Units (TPUs), and Field-Programmable Gate Arrays (FPGAs). By integrating the aforementioned configurable on-chip storage system into various processor chips, the utilization rate of chip storage resources and computational efficiency can be effectively improved, meeting the reliability and flexibility requirements of different application scenarios.

[0102] The processor chip provided in this application embodiment has the same implementation principle and technical effect as the aforementioned on-chip storage system embodiment. For the sake of brevity, any parts not mentioned in the processor chip embodiment can be referred to the corresponding content in the aforementioned on-chip storage system embodiment. This application also provides a configurable on-chip storage method applied to the above-described on-chip storage system. The method includes: performing priority arbitration on configuration signals from different levels of a multi-level configuration unit and outputting a selection signal; during a write operation, selecting, based on the selection signal, to write an ECC checksum or metadata to the corresponding configurable region of the memory; during a read operation, selecting, based on the selection signal, to output data from the configurable region to either the ECC checksum branch or the metadata branch. The configuration signal indicates the configurable region storage mode for each storage row.

[0103] The method provided in this application embodiment has the same implementation principle and technical effect as the aforementioned on-chip storage system embodiment. For the sake of brevity, any part not mentioned in the method embodiment can be referred to the corresponding content in the aforementioned on-chip storage system embodiment.

[0104] This application also provides an electronic device that includes the aforementioned processor chip. Figure 7 As shown, the electronic device includes: a central processing unit, a transceiver, a memory, a communication bus, and a processor chip. The transceiver, memory, processor chip, and central processing unit are electrically connected directly or indirectly to achieve data transmission or interaction. For example, these components can be electrically connected to each other through one or more communication buses or signal lines. The transceiver is used to send and receive data. The memory stores computer programs, which include at least one software functional module that can be stored in the memory in the form of software or firmware or embedded in the operating system (OS) of the electronic device. The central processing unit works in conjunction with the processor chip to execute the software functional modules or computer programs stored in the memory.

[0105] The memory can be, but is not limited to, Random Access Memory (RAM), Read Only Memory (ROM), Programmable Read-Only Memory (PROM), Erasable Programmable Read-Only Memory (EPROM), Electrically Erasable Programmable Read-Only Memory (EEPROM), etc.

[0106] The aforementioned electronic devices include, but are not limited to: servers, cloud computing devices, high-performance computing clusters, artificial intelligence computing platforms, autonomous driving computing platforms, personal computers, laptops, tablets, smartphones, IoT devices, wearable devices, augmented reality devices, and virtual reality devices. By applying these processor chips to various electronic devices, the computing performance, storage resource utilization, and energy efficiency of the devices can be significantly improved, meeting the demands for high reliability, high flexibility, and high-performance computing in different scenarios.

[0107] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0108] In addition, the functional modules in the various embodiments of this application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0109] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A configurable on-chip storage system, characterized in that, include: The memory comprises multiple storage rows, each storage row including a data area and a configurable area; A multi-level configuration unit is used to generate configuration signals that indicate the configurable zone storage mode for each storage row; An arbitration circuit, connected to the multi-level configuration unit, is used to perform priority arbitration on configuration signals from different levels and output a selection signal. The selection circuit is connected to the memory and the arbitration circuit respectively. The selection circuit is used to select, during a write operation, to write the ECC check code or metadata to the configurable area, and during a read operation, to select to output the data of the configurable area to the ECC check branch or the metadata branch.

2. The system according to claim 1, characterized in that, The multi-level configuration unit includes: Operand-level configuration unit, used to generate the first configuration signal at the operand level; The instruction-level configuration unit is used to generate instruction-level second configuration signals.

3. The system according to claim 2, characterized in that, The multi-level configuration unit further includes at least one of the following: thread bundle-level configuration unit, thread block-level configuration unit, and dispatch-level configuration unit; The thread bundle-level configuration unit is used to generate a third configuration signal at the thread bundle level; The thread block-level configuration unit is used to generate a fourth configuration signal at the thread block level; The dispatch-level configuration unit is used to generate the fifth configuration signal at the dispatch level.

4. The system according to claim 2, characterized in that, The arbitration circuit includes a target arbitrator, used to arbitrate the first configuration signal and the second configuration signal, and output a target arbitration result, wherein the target arbitration result is the selection signal.

5. The system according to claim 3, characterized in that, The arbitration circuit includes: The first arbitrator is connected to the dispatch-level configuration unit and the global-level configuration unit respectively, and is used to arbitrate the global configuration signal from the global-level configuration unit and the fifth configuration signal, and output the first arbitration result; The second arbitrator is connected to the first arbitrator and the thread block-level configuration unit respectively, and is used to arbitrate the first arbitration result and the fourth configuration signal, and output the second arbitration result. The third arbiter is connected to the second arbiter and the thread bundle-level configuration unit respectively, and is used to arbitrate the second arbitration result and the third configuration signal, and output the third arbitration result. The fourth arbitrator is connected to the third arbitrator and the instruction-level configuration unit, respectively, and is used to arbitrate the third arbitration result and the second configuration signal, and output the fourth arbitration result; The fifth arbitrator is connected to the fourth arbitrator and the operand-level configuration unit, respectively, and is used to arbitrate the fourth arbitration result and the first configuration signal, and output a fifth arbitration result, wherein the fifth arbitration result is the selection signal.

6. The system according to claim 2, characterized in that, The operand-level configuration unit is used to generate the first configuration signal according to the data precision of the operands in the instruction; If the data precision of the operand is a first precision, then the first configuration signal indicates that the configurable area is used to store ECC checksums; if the data precision of the operand is a second precision, then the first configuration signal indicates that the configurable area is used to store metadata; wherein, the bit width of the data with the first precision is higher than the bit width of the data with the second precision.

7. The system according to any one of claims 1-6, characterized in that, The selection circuit includes: A write multiplexer is provided, wherein the first input of the write multiplexer is coupled to the ECC check branch to receive the ECC check code, the second input is coupled to the metadata branch to receive the metadata, and the output is coupled to the write data path of the memory. A read multiplexer is provided, wherein the input of the read multiplexer is coupled to the read data path of the memory to receive data stored in the configurable area, the first output of the read multiplexer is coupled to the ECC check branch, and the second output of the read multiplexer is coupled to the metadata branch.

8. The system according to any one of claims 1-7, characterized in that, The selection signal is also used to enable or disable the ECC verification branch; When the selection signal indicates that data of the configurable area should be output to the ECC verification branch, the ECC decoder in the ECC verification branch is enabled. When the selection signal indicates that data from the configurable area should be output to the metadata branch, the ECC decoder in the ECC verification branch is disabled.

9. The system according to any one of claims 1-8, characterized in that, During a write operation, the selection signal is written to the configurable area along with the ECC checksum or the metadata; during a read operation, the selection signal read from the configurable area is used to control the path selection of the selection circuit.

10. The system according to any one of claims 1-9, characterized in that, The metadata includes a scaling factor used to map second-precision data to the range of data that can be represented by third-precision data.

11. The system according to any one of claims 1-10, characterized in that, The metadata includes a non-zero index, which indicates the position of the compressed non-zero element in the sparse matrix before compression.

12. A processor chip, characterized in that, Including the on-chip storage system as described in any one of claims 1-11.

13. An electronic device, characterized in that, Including the processor chip as described in claim 12.

14. A configurable on-chip storage method, characterized in that, include: Priority arbitration is performed on configuration signals from different levels of the multi-level configuration unit to output a selection signal; wherein, the configuration signal is used to indicate the storage mode of the configurable area of ​​each storage row of the memory; the memory is connected to an ECC check branch and a metadata branch respectively, the ECC check branch is used to transmit ECC check codes, and the metadata branch is used to transmit metadata; During a write operation, the selection signal is used to select whether to write the ECC checksum or metadata to the corresponding configurable area of ​​the memory. During a read operation, based on the selection signal, the data of the configurable area is selected to be output to either the ECC verification branch or the metadata branch.

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