A PCIe reset linkage network card configuration method and device

Abstract

The application relates to the technical field of network card configuration, and discloses a PCIe reset linkage network card configuration method and device, wherein the method comprises the following steps: listening to change events of a plurality of configuration items, and writing the first configuration state of the configuration item which is changed into a special snapshot storage partition; monitoring a PCIe bus hardware reset signal in real time, and within a hardware time sequence window before a network card chip enters a reset state, forcibly writing full-amount configuration states of the plurality of configuration items into the special snapshot storage partition; after the network card chip completes PCIe reset, reading snapshot data packets and performing validity checking, loading the snapshot data packets which pass the checking into an on-chip SRAM; and respectively performing configuration recovery on each functional module in the network card, and the total time length of the configuration recovery does not exceed a preset time length, so that the technical problems that configuration saving depends on a host operating system and a drive and configuration is completely lost in an uncontrollable reset scene in the prior art are solved.

Description

Technical Field

[0001] This invention relates to the field of network card configuration technology, and in particular to a network card configuration method and apparatus with PCIe reset linkage. Background Technology

[0002] With the rapid development of cloud computing, distributed storage, and AI large-scale model training technologies, the network bandwidth of a single node in a data center server has increased significantly. As the core entry point between the server and the network, the network interface card (NIC) directly determines the service quality of the entire system due to its business continuity. In actual operation, servers frequently trigger PCIe reset events due to maintenance, failures, or upgrades. Therefore, the rapid recovery capability of the NIC configuration has become a key factor restricting the high availability of data centers.

[0003] In existing technologies, the persistence and recovery of network interface card (NIC) configurations rely on the full involvement of the host operating system and drivers. During normal server operation, the driver synchronously writes the configuration to the host's local storage. After a reset, it is necessary to wait for the operating system kernel to boot, the PCIe bus enumeration to complete, and the driver to load before the driver reissues all configuration parameters to the NICs one by one. The overall recovery time is generally in the range of seconds or even minutes. However, in existing technologies, when uncontrollable scenarios such as PERST# hard reset, abnormal power loss, or motherboard global fault reset occur, the host CPU has already stopped working, the operating system and driver's operating environment completely disappears, and the triggering and execution of configuration saving cannot be established. Therefore, the latest dynamic configuration of the NIC during operation is completely lost, and the NIC directly returns to its factory state after a reset, resulting in a complete service interruption. This cannot meet the high availability requirements of scenarios with extremely low interruption tolerance. Summary of the Invention

[0004] This invention provides a network card configuration method and device with PCIe reset linkage. This invention solves the technical problems in the prior art where configuration saving depends on the host operating system and driver, and the configuration is completely lost in uncontrollable reset scenarios. This invention does not rely on host driver intervention throughout the process, and strictly controls the total time for complete configuration recovery within a preset time. Compared with the recovery time of seconds to minutes in the prior art, the service recovery window is greatly compressed.

[0005] In a first aspect, the present invention provides a network card configuration method with PCIe reset linkage, the network card configuration method with PCIe reset linkage includes: Listen for change events of multiple configuration items and write the first configuration state of the changed configuration item to a dedicated snapshot storage partition; Real-time monitoring of the PCIe bus hardware reset signal and, within the hardware timing window before the network card chip enters the reset state, forcibly writing the full configuration status of the multiple configuration items to the dedicated snapshot storage partition; After the network card chip completes the PCIe reset, it reads the snapshot data packet from the dedicated snapshot storage partition and performs validity verification. The snapshot data packet that passes the verification is loaded into the on-chip SRAM. Based on the snapshot data packets in the on-chip SRAM, the configuration of each functional module in the network card is restored, and the total time for configuration restoration does not exceed the preset time.

[0006] In conjunction with the first aspect, in a first implementation of the first aspect of the present invention, the step of listening to change events of multiple configuration items and writing the first configuration state of the changed configuration item to a dedicated snapshot storage partition includes: Based on the change frequency and business importance level of multiple configuration items, snapshot update trigger conditions and update granularity are set for each configuration item to obtain a differentiated update strategy for each configuration item; Listen for change events of multiple configuration items; The first configuration state of the changed configuration item is read and written to the dedicated snapshot storage partition based on the differentiated update strategy. No write operation is performed on the configuration item that has not been changed.

[0007] In conjunction with the first aspect, in the second implementation of the first aspect of the present invention, the plurality of configuration items include FEC mode, LRO parameters, SDI VLAN table, PF rate limiting, and SerDes mapping relationship. The snapshot update trigger condition and update granularity are set for each configuration item based on the change frequency and service importance level of the plurality of configuration items, resulting in a differentiated update strategy for each configuration item, including: When the configuration item is FEC mode and LRO parameter, the snapshot update trigger condition in the differential update strategy of the configuration item is set to be triggered immediately after the corresponding register write operation occurs; When the configuration item is SDI VLAN table and PF rate limit, the snapshot update trigger condition in the differentiated update policy of the configuration item is set to trigger in batches after the cumulative changes reach the update granularity threshold. When the configuration item is a SerDes mapping relationship, the snapshot update trigger condition in the differential update strategy of the configuration item is set to trigger a full write once after the network card initialization is completed and no further triggers are made.

[0008] In conjunction with the first aspect, in a third implementation of the first aspect of the present invention, the step of real-time monitoring of the PCIe bus hardware reset signal and, within the hardware timing window before the network card chip enters the reset state, forcibly writing the full configuration state of the plurality of configuration items to the dedicated snapshot storage partition includes: The constant power domain auxiliary power supply supplies power to the constant power domain hardware circuit of the network card chip. The constant power domain hardware circuit performs real-time level sampling of the PCIe bus hardware reset signal. When the PCIe bus hardware reset signal is detected to transition from high level to low level, a forced write trigger signal is sent to the snapshot write controller. Based on the forced write trigger signal, within the hardware timing window before the network card chip enters the reset state, the snapshot write controller performs a forced write to the full configuration state of multiple configuration items, and solidifies the full configuration state to the dedicated snapshot storage partition.

[0009] In conjunction with the first aspect, in the fourth implementation of the first aspect of the present invention, the step of performing a forced write to the full configuration state of multiple configuration items through the snapshot write controller within the hardware timing window before the network card chip enters the reset state, based on the forced write trigger signal, and solidifying the full configuration state to the dedicated snapshot storage partition, includes: Based on the forced write trigger signal, the snapshot write controller sequentially reads the full configuration status of multiple configuration items, appends an integrity check value to the end of the full configuration status, and assembles them into a snapshot data packet. The snapshot data packet is written to the dedicated snapshot storage partition via the SPI bus, and a snapshot validity flag is written to a fixed address in the dedicated snapshot storage partition after the snapshot data packet is written, thus completing the solidification of the full configuration state.

[0010] In conjunction with the first aspect, in a fifth implementation of the first aspect of the present invention, the step of reading snapshot data packets from the dedicated snapshot storage partition and performing validity verification after the network interface card chip completes a PCIe reset, and loading the verified snapshot data packets into the on-chip SRAM, includes: After the network card chip completes the PCIe reset, it reads the snapshot data packet from the dedicated snapshot storage partition and performs a validity check on the snapshot data packet to obtain the validity check result. If the validity check result is successful, the snapshot data packet is loaded into the on-chip SRAM; if the validity check result is unsuccessful, the factory default configuration data is read from the factory default configuration area of ​​the on-chip FLASH and loaded into the on-chip SRAM.

[0011] In conjunction with the first aspect, in the sixth implementation of the first aspect of the present invention, the step of reading snapshot data packets from the dedicated snapshot storage partition after the network card chip completes the PCIe reset and performing validity verification on the snapshot data packets to obtain a validity verification result includes: After the network interface card chip completes a PCIe reset, it reads snapshot data packets from the dedicated snapshot storage partition; Recalculate the first checksum of the snapshot data packet and compare the first checksum with the second checksum stored in the snapshot data packet; When the first check value and the second check value are the same, the validity check result is determined to be valid; when the first check value and the second check value are different, the validity check result is determined to be invalid.

[0012] In conjunction with the first aspect, in the seventh implementation of the first aspect of the present invention, the step of configuring and restoring each functional module in the network card based on the snapshot data packets in the on-chip SRAM, and the total duration of configuration restoration not exceeding a preset duration, includes: The second configuration state of each configuration item is extracted sequentially from the snapshot data in the on-chip SRAM, and the second configuration state of each configuration item is written into the function control register of the corresponding function module. After all the function control registers of all functional modules are written, a configuration recovery ready signal is sent to the PCIe link state machine so that the host driver skips the full configuration delivery process and directly enters the service forwarding state after receiving the configuration recovery ready signal, and the total time from the snapshot data packet being loaded into the on-chip SRAM to the issuance of the configuration recovery ready signal does not exceed the preset time.

[0013] In conjunction with the first aspect, in the eighth implementation of the first aspect of the present invention, the step of sending a configuration recovery ready signal to the PCIe link state machine after the function control registers of all functional modules have been written, so that the host driver skips the full configuration delivery process and directly enters the service forwarding state after receiving the configuration recovery ready signal, and the total time from the snapshot data packet being loaded into the on-chip SRAM to the issuance of the configuration recovery ready signal does not exceed a preset time, includes: After the function control registers of all functional modules have been written, a configuration recovery ready signal is sent to the PCIe link state machine. After completing the PCIe link enumeration, the host driver reads the snapshot reported by the network card and restores the status successfully. When the snapshot recovery success status is "snapshot recovery successful", the full configuration distribution process is skipped and the service forwarding state is directly entered. The total time from the snapshot data packet being loaded into the on-chip SRAM to the issuance of the configuration recovery ready signal does not exceed the preset time.

[0014] Secondly, the present invention provides a network interface card (NIC) configuration device with PCIe reset linkage, the PCIe reset linkage NIC configuration device comprising: The monitoring module is used to monitor change events of multiple configuration items and write the first configuration state of the changed configuration item to a dedicated snapshot storage partition; The write module is used to monitor the PCIe bus hardware reset signal in real time and, within the hardware timing window before the network card chip enters the reset state, force the full configuration status of the multiple configuration items to be written to the dedicated snapshot storage partition. The verification module is used to read snapshot data packets from the dedicated snapshot storage partition and perform validity verification after the network card chip completes PCIe reset, and load the verified snapshot data packets into the on-chip SRAM. The configuration recovery module is used to perform configuration recovery on each functional module in the network card based on the snapshot data packets in the on-chip SRAM, and the total configuration recovery time does not exceed the preset time.

[0015] The technical solution provided by this invention solves the technical problems of existing technologies where configuration saving depends on the host operating system and drivers, and configuration is completely lost in uncontrollable reset scenarios, by using the falling edge of the PCIe bus hardware reset signal as the hardware trigger source for snapshot hardening, combined with the real-time monitoring mechanism of the network card chip's constant power domain hardware circuit. Compared to the passive solution in existing technologies where configuration saving can only be performed by the driver during the normal shutdown process of the host, this invention independently completes the configuration hardening before reset at the network card chip side, covering all PCIe reset scenarios such as normal restart, hot reset, abnormal power failure, and motherboard global hard reset, completely eliminating the dependence on the online status of the host CPU and operating system. At the same time, this invention adopts differentiated update trigger conditions and update granularity for different configuration items such as FEC mode, LRO parameters, SDI VLAN table, PF rate limit, and SerDes mapping relationship, based on the change frequency and service importance level. Snapshot writing is only performed on the changed configuration items, which significantly reduces the erase and write frequency of on-chip FLASH while ensuring the real-time performance of snapshots, effectively extending the life of FLASH hardware. Furthermore, after the reset is completed, the network card firmware autonomously completes the snapshot validity verification and configuration loading before the PCIe link is re-enumerated. The configuration is restored module by module according to the functional priority order of SerDes mapping relationship, FEC mode, PF rate limit, LRO parameters, and SDI VLAN table configuration. The entire process does not rely on host driver intervention, and the total time for complete configuration restoration is strictly controlled within the preset time. Compared with the restoration time of seconds to minutes in the prior art, the service restoration window is greatly compressed.

[0016] Other features and advantages of the invention will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other advantages of the invention are realized and obtained in accordance with the structures particularly pointed out in the description, claims and drawings.

[0017] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of an embodiment of the network card configuration method with PCIe reset linkage in this invention. Figure 2 This is a schematic diagram illustrating the monitoring of change events for multiple configuration items in an embodiment of the present invention; Figure 3 This is a schematic diagram of the on-chip FLASH configuration snapshot-dedicated storage circuit in an embodiment of the present invention; Figure 4 This is a schematic diagram illustrating the monitoring of the PCIe bus hardware reset signal in an embodiment of the present invention; Figure 5 This is a schematic diagram of the PCIe reset signal detection and high-speed differential channel interface circuit in an embodiment of the present invention; Figure 6 This is a schematic diagram of validity verification in an embodiment of the present invention; Figure 7 This is a schematic diagram illustrating the configuration recovery in an embodiment of the present invention; Figure 8 This is a schematic diagram of an embodiment of the network card configuration device with PCIe reset linkage in this invention. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0020] The terms "comprising" and "having," and any variations thereof, used in the embodiments of this invention are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the steps or units listed, but may optionally include other steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or devices.

[0021] To facilitate understanding of this embodiment, a detailed description of a PCIe reset-linked network card configuration method disclosed in this embodiment of the invention will be provided first. For example... Figure 1 As shown, this method includes the following steps: 101. Listen for change events of multiple configuration items and write the first configuration state of the changed configuration item to a dedicated snapshot storage partition; 102. Monitor the PCIe bus hardware reset signal in real time and, within the hardware timing window before the network card chip enters the reset state, force the full configuration status of multiple configuration items to be written to the dedicated snapshot storage partition. This invention independently completes the configuration persistence before reset at the network card chip level, covering all PCIe reset scenarios such as normal restart, hot reset, abnormal power failure, and motherboard global hard reset, completely eliminating dependence on the online status of the host CPU and operating system. Simultaneously, this invention employs differentiated update trigger conditions and update granularity for different configuration items such as FEC mode, LRO parameters, SDI VLAN table, PF rate limiting, and SerDes mapping relationships, based on their change frequency and service importance. Snapshot writing is performed only on the changed configuration items, significantly reducing the frequency of on-chip FLASH erase / write operations while ensuring real-time snapshot performance, effectively extending the FLASH hardware lifespan.

[0022] 103. After the network card chip completes the PCIe reset, it reads the snapshot data packets from the dedicated snapshot storage partition and performs validity verification. The snapshot data packets that pass the verification are loaded into the on-chip SRAM. 104. Based on the snapshot data packets in the on-chip SRAM, the configuration of each functional module in the network card is restored, and the total time for configuration restoration does not exceed the preset time.

[0023] After the reset is completed, the network card firmware automatically completes the snapshot validity verification and configuration loading before the PCIe link is re-enumerated. The configuration is restored module by module according to the functional priority order of SerDes mapping relationship, FEC mode, PF rate limit, LRO parameters, and SDI VLAN table configuration. The whole process does not rely on host driver intervention, and the total time of complete configuration restoration is strictly controlled within the preset time. Compared with the restoration time of seconds to minutes in the prior art, the service restoration window is greatly compressed.

[0024] In this embodiment, by using the falling edge of the PCIe bus hardware reset signal as the hardware trigger source for snapshot hardening, combined with the real-time monitoring mechanism of the network card chip's constant power domain hardware circuit, the technical problems of configuration saving relying on the host operating system and drivers, and complete configuration loss in uncontrollable reset scenarios, are solved. Compared to the passive solution in the prior art where configuration saving can only be performed by the driver during the normal shutdown process of the host, this invention independently completes the configuration hardening before reset at the network card chip side, covering all PCIe reset scenarios such as normal restart, hot reset, abnormal power failure, and motherboard global hard reset, completely eliminating the dependence on the online status of the host CPU and operating system. At the same time, this invention adopts differentiated update trigger conditions and update granularity for different configuration items such as FEC mode, LRO parameters, SDI VLAN table, PF rate limiting, and SerDes mapping relationship, based on the change frequency and service importance level. Snapshot writing is only performed on the changed configuration items, which significantly reduces the erase and write frequency of on-chip FLASH while ensuring the real-time performance of snapshots, effectively extending the life of FLASH hardware. Furthermore, after the reset is completed, the network card firmware autonomously completes the snapshot validity verification and configuration loading before the PCIe link is re-enumerated. The configuration is restored module by module according to the functional priority order of SerDes mapping relationship, FEC mode, PF rate limit, LRO parameters, and SDI VLAN table configuration. The entire process does not rely on host driver intervention, and the total time for complete configuration restoration is strictly controlled within the preset time. Compared with the restoration time of seconds to minutes in the prior art, the service restoration window is greatly compressed.

[0025] In one specific embodiment, such as Figure 2 As shown, the process of executing step 101 can specifically include the following steps: 111. Based on the change frequency and business importance level of multiple configuration items, set snapshot update trigger conditions and update granularity for each configuration item to obtain differentiated update strategies for each configuration item; 112. Listen for change events of multiple configuration items; 113. Read the first configuration state of the changed configuration items and write the first configuration state to the dedicated snapshot storage partition based on the differentiated update strategy. No write operation is performed on the configuration items that have not been changed.

[0026] like Figure 3The diagram shows the circuit connection between the network card chip and the external SPI NOR FLASH memory chip. The chip select signal of the FLASH chip is connected in series to the SPI_FLSH_CE_N signal, driven by E830_SPI_CE_N and pulled up to VDD_P3V3; the data output DO is connected to SPI_MISO, corresponding to E830_SPI_DQ1; the write protection WP# is connected to SPI_WP_N, corresponding to E830_SPI_DQ2; VCC is connected to the VDD_P3V3 power supply with a decoupling capacitor in parallel; HOLD# is connected to SPI_HOLD_N, corresponding to E830_SPI_DQ3; the clock CLK is connected to SPI_CLK; and the data input DI is connected to SPI_MOSI, corresponding to E830_SPI_DQ0. A 33Ω resistor is connected in series with each signal line for impedance matching. The FLASH chip serves as the physical carrier of the on-chip FLASH and undertakes the storage function of the dedicated snapshot storage partition. The network card chip performs write and read operations on the snapshot data of the key configuration items to the dedicated snapshot storage partition through the SPI bus (SPI_CLK, SPI_MOSI, SPI_FLSH_CE_N signals).

[0027] Specifically, based on the frequency of changes to each configuration item during runtime and its impact on link availability, forwarding performance, and virtualization isolation, different update triggering methods and write granularities are assigned to different configuration items. Configuration items that need to maintain consistency as soon as possible after modification adopt an immediate triggering strategy. Configuration items that may fluctuate continuously during service operation and whose frequent rewrites increase storage write pressure adopt a cumulative triggering strategy. Configuration items that remain stable after initialization adopt a single-time fixation strategy, thus forming differentiated update strategies. Configurations directly related to link establishment and reception processing, such as FEC mode and LRO parameters, can have their update flags set immediately after a write operation occurs in the corresponding register. Configurations that may be continuously adjusted during service operation, such as SDI VLAN tables and PF rate limiting, first record each change in the on-chip cache, and then write it to disk uniformly after the cumulative changes reach the preset update granularity. The update granularity can be set to 4 times. Since the SerDes mapping relationship is mainly determined during the initialization phase and does not change frequently afterward, a full write is performed after the network card initialization is completed, and it will not repeatedly enter the periodic snapshot path during subsequent operation.

[0028] In this embodiment, the configuration monitoring logic inside the network interface card (NIC) chip continuously monitors the register address ranges of multiple configuration items. It captures write events, entry change actions, and parameter update requests to the target register at an event level. Only the status bit corresponding to the configuration item that is modified is set, and the latest image of that configuration item is retained in the on-chip SRAM. When the monitoring logic detects that a configuration item meets the triggering conditions specified by its policy, the snapshot maintenance thread reads the first configuration state of that configuration item from the corresponding register group or cache and writes it to a dedicated snapshot storage partition according to a preset data organization format. For configuration items that do not meet the triggering conditions, even if a partial intermediate state change occurs, it is only retained in the on-chip cache and status flags, and does not immediately enter the external storage write path, ensuring that the snapshot content is primarily in a stable and business-meaningful state.

[0029] In this embodiment, the write path relies on a dedicated hardware connection between the network interface card (NIC) chip and the external SPI NOR FLASH memory chip. When the NIC chip is preparing to write a snapshot, it first pulls the SPI_FLSH_CE_N low to select the target FLASH device, and then outputs a serial clock via SPI_CLK to send the configuration item identifier, data length, and configuration status data to the external memory chip via SPI_MOSI. After the write is completed, the chip select signal is released and the chip waits for the device to complete its internal programming. Because the dedicated snapshot storage partition is isolated from the firmware area and the default configuration area, each configuration item can be bound to a fixed offset address or a fixed page range. During runtime snapshot maintenance, the target area can be directly located, reducing the additional addressing overhead in the recovery path.

[0030] In one specific embodiment, multiple configuration items include FEC mode, LRO parameters, SDI VLAN table, PF rate limiting, and SerDes mapping relationship. The process of executing step 111 can specifically include the following steps: (1) When the configuration item is FEC mode and LRO parameter, the snapshot update trigger condition in the differential update strategy of the configuration item is set to be triggered immediately after the corresponding register write operation occurs; (2) When the configuration item is SDI VLAN table and PF rate limit, set the snapshot update trigger condition in the differential update policy of the configuration item to trigger in batch after the cumulative changes reach the update granularity threshold; (3) When the configuration item is a SerDes mapping relationship, the snapshot update trigger condition in the differential update strategy of the configuration item is set to trigger a full write after the network card initialization is completed and no further triggering is performed.

[0031] Specifically, independent change monitoring entry points, dirty flag bits, and snapshot write rules are established for FEC mode, LRO parameters, SDI VLAN table, PF rate limiting, and SerDes mapping relationship, respectively. The triggering method is divided according to the actual change rhythm and service impact range of each configuration item. FEC mode and LRO parameters are directly related to physical layer error correction capability and receive path aggregation performance. If the register cannot be synchronized to the dedicated snapshot storage partition as soon as possible after the register is rewritten, the link parameter recovery may be delayed or the receive side performance parameters may fall back when a reset occurs. Therefore, the FEC mode register address segment and LRO parameter register address segment should be connected to write operation real-time monitoring logic. As long as the write enable signal and the target address are detected, the corresponding dirty flag bit is immediately set to valid, and the snapshot maintenance thread prioritizes the snapshot update task of the corresponding configuration item, sends the latest configuration status to the snapshot group frame buffer, and then starts a targeted disk write. Immediate trigger is used to describe the moment when the dirty flag is set, and periodic thread is used to describe the moment when the disk is written. It takes into account both the need for rapid hardening after register changes and the regular scheduling load of network card firmware, so that FEC mode and LRO parameters are basically in a near real-time update state after being rewritten.

[0032] In this embodiment, the SDI VLAN table and PF rate limiting exhibit continuous modification characteristics during service operation. Especially during virtualized network migration, tenant switching, or bandwidth reshaping adjustments, table entries and rate limiting parameters may change multiple times in a short period of time. If the immediate triggering method is used, the dedicated FLASH partition will repeatedly perform page programming within a short window, increasing SPI bus usage and write / erase pressure. Therefore, a cumulative batch triggering strategy is more suitable. Independent change counters are set for the SDI VLAN table and PF rate limiting. Each valid update increments the corresponding counter by 1, and the latest state is written to the on-chip SRAM mirror area. When the count value reaches the update granularity threshold, a snapshot write is performed uniformly. The update granularity threshold can be set to 4 times to achieve a balance between snapshot freshness and non-volatile storage lifetime. Since continuous modifications within 4 times are still in the same round of service adjustment, centralized writing helps reduce invalid persistence without prolonging the time for valid configuration to be written to disk. If a stable configuration window appears before the count reaches 4, the snapshot maintenance thread can perform a write operation within a longer backup period to prevent the latest business status from remaining in the on-chip image for an extended period without entering the dedicated snapshot storage partition.

[0033] In this embodiment, the SerDes mapping relationship corresponds to the binding relationship between physical channels and logical ports. In engineering, this is established during the network card initialization phase and rarely changes after service operation begins. Therefore, after the initialization completion signal is established, the SerDes mapping relationship undergoes a full write operation and subsequent trigger entries are disabled. The initialization completion signal can be composed of three conditions: chip power-on self-test completion, basic register loading completion, and channel mapping table verification passing. When all three conditions are met, the SerDes mapping relationship is read from the register group as a whole, assembled into a complete snapshot frame, and written to the corresponding area of ​​the dedicated snapshot storage partition. After successful writing, the SerDes mapping snapshot enable bit is switched to the off state.

[0034] In one specific embodiment, such as Figure 4 As shown, the process of executing step 102 can specifically include the following steps: 121. The constant power domain auxiliary power supply supplies power to the constant power domain hardware circuit of the network card chip. The constant power domain hardware circuit performs real-time level sampling of the PCIe bus hardware reset signal. When the PCIe bus hardware reset signal is detected to change from high level to low level, a forced write trigger signal is sent to the snapshot write controller. like Figure 5 The diagram shows the schematic of the PCIe physical layer interface and PCIe bus hardware reset signal detection circuit of the network card chip. It includes 16 PCIe receive differential pairs and 16 PCIe transmit differential pairs. Each transmit channel has a 220nF DC blocking coupling capacitor in series, and both transmit and receive differential traces are routed with an 85Ω impedance. The PCIe bus hardware reset signal detection circuit includes: the PCIe bus hardware reset signal PCIE_RST# output from the server motherboard is directly connected to a signal conditioning circuit consisting of pull-down resistors, filter capacitors, and ESD protection devices after being pulled up by the constant voltage domain auxiliary power supply. This circuit is then connected to the chip, serving as the hardware input for the network card chip's constant voltage domain hardware circuit to perform real-time level sampling of the PCIe bus hardware reset signal. When the PCIe bus hardware reset signal is detected to transition from high to low, the snapshot write controller is triggered to forcibly write the current configuration state of all critical configuration items to a dedicated snapshot storage partition.

[0035] Specifically, the PCIe bus hardware reset signal detection link is arranged within the constant power domain of the network card chip, allowing reset sampling, falling edge determination, and forced write triggering to operate independently from the main logic power domain. The PCIE_RST# output from the server motherboard is first directly introduced into the signal conditioning branch via a zero-ohm resistor, and then enters the front-end shaping network composed of pull-down resistors, filter capacitors, and ESD protection devices. At the same time, the PCIe physical layer interface is still arranged according to the high-speed link specification with 16 receive differential pairs and 16 transmit differential pairs. After the constant power domain hardware logic continuously samples the input reset level, it internally sets up a level synchronization unit, a falling edge determination unit, and a trigger latch unit. When the sampling result flips from high level to low level, the falling edge determination unit immediately outputs a valid trigger pulse, and the trigger latch unit holds the trigger result until the snapshot write controller confirms receipt, avoiding trigger loss when the reset signal edge is too narrow or the main logic is about to fail. Since the trigger link is powered entirely by the constant power domain, the transmission of the trigger signal from the input to the snapshot write controller does not require waiting for the host CPU, operating system, or driver to participate. Therefore, after the valid falling edge of PERST# appears, the snapshot write controller can obtain the write start condition before the chip's main logic reset process.

[0036] 122. Based on the forced write trigger signal, within the hardware timing window before the network card chip enters the reset state, the full configuration state of multiple configuration items is forcibly written through the snapshot write controller, and the full configuration state is solidified to the dedicated snapshot storage partition.

[0037] In this embodiment, upon receiving the forced write trigger signal, the process proceeds in the order of "immediate takeover, window-based solidification, and handover of the reset process upon completion." The snapshot write controller bypasses the normal trigger path of the runtime differential maintenance phase and instead initiates a full state extraction targeting FEC mode, LRO parameters, SDI VLAN table, PF rate limiting, and SerDes mapping relationship. The dedicated snapshot storage partition is solidified before the chip actually enters the reset state. The time window between the falling edge of the PCIe reset signal and the main logic failure is short. This time window is primarily used for trigger latching, critical state freezing, and snapshot submission path selection, and does not undertake the task of writing the entire packet via the SPI bus. The SPI write operation is completed during the runtime incremental maintenance phase or the supplementary submission phase after reset exit.

[0038] In one specific embodiment, the process of performing step 122 may specifically include the following steps: (1) Based on the forced write trigger signal, the full configuration status of multiple configuration items is sequentially read by the snapshot write controller, and an integrity check value is appended to the end of the full configuration status before being assembled into a snapshot data packet; (2) Write the snapshot data packet to the dedicated snapshot storage partition via the SPI bus, and write the snapshot validity flag at a fixed address of the dedicated snapshot storage partition after the snapshot data packet is written to complete the solidification of the full configuration state.

[0039] Specifically, upon receiving a forced write trigger signal, the snapshot write controller immediately switches to the pre-reset full-scale solidification mode and performs a sequential read of the register areas corresponding to the FEC mode, LRO parameters, SDI VLAN table, PF rate limit, and SerDes mapping relationship. This sequential read follows a fixed order, ensuring the stable arrangement of configuration items within the snapshot data packet. Subsequent reads, verifications, and parsing after the reset can also proceed in the same order, preventing confusion at the recovery entry point due to changes in the configuration item organization order. During the read process, the snapshot write controller extracts the complete configuration state of each configuration item from the on-chip register area and encapsulates it into continuous data segments according to a pre-agreed data organization format. After all configuration state data is concatenated, an integrity check value is appended to the end, ensuring that the assembled snapshot data packet possesses both state-carrying and verification capabilities.

[0040] In this embodiment, the snapshot write controller writes snapshot data packets to a dedicated snapshot storage partition via the SPI bus. The write link uses SPI_CLK, SPI_MOSI, and SPI_FLSH_CE_N to drive the clock, transmit serial data, and control the chip select. Complete data packets are sequentially written into a predetermined storage area using page programming. Since the write operation occurs within the hardware timing window before the PCIe reset takes effect, the write phase directly performs continuous solidification on the dedicated snapshot storage partition, eliminating the need for runtime itemized writing. Simultaneously, the constant power domain is continuously powered by the auxiliary power supply, and the SPI write process is unaffected by the main power domain reset. Therefore, the snapshot write controller can maintain necessary serial write capability even after the reset edge. After all snapshot data packets are written and a write operation completion acknowledgment is received from the FLASH, the controller writes a snapshot validity flag at a fixed address in the dedicated snapshot storage partition. The flag is set to 0xA5A5A5A5, a fixed value used to quickly distinguish between "snapshot has been completely solidified" and "snapshot incomplete or invalid" states during the reset recovery phase. After completing the snapshot data packet writing and validity flag writing, it is considered that the full configuration state of multiple configuration items has been solidified. Then, the write controller returns a write completion response to the upstream detection logic, allowing the subsequent reset process to continue.

[0041] In one specific embodiment, such as Figure 6 As shown, the process of executing step 103 can specifically include the following steps: 131. After the network card chip completes the PCIe reset, it reads the snapshot data packets from the dedicated snapshot storage partition, performs validity verification on the snapshot data packets, and obtains the validity verification result; 132. If the validity check result is successful, the snapshot data packet is loaded into the on-chip SRAM; if the validity check result is unsuccessful, the factory default configuration data is read from the factory default configuration area of ​​the on-chip FLASH and loaded into the on-chip SRAM.

[0042] Specifically, after the network interface card (NIC) firmware boots, the firmware bootloader accesses the dedicated snapshot storage partition via the SPI bus, first obtaining the snapshot data packet formed by the most recent forced firmware, and then generating a validity verification result based on this. Only snapshot data packets that meet the valid snapshot determination conditions are allowed to continue into the on-chip SRAM loading path; if the valid snapshot determination conditions are not met, the recovery path immediately switches to the default configuration loading path to avoid corrupted snapshots, half-written snapshots, or snapshots without historical data directly participating in the functional module recovery, thereby affecting the correctness of link establishment, traffic scheduling, and virtualization isolation configuration. The configuration source after reset no longer depends on the host-side software environment, but is autonomously determined by the NIC chip-side storage area to enter the recovery process. Therefore, the recovery preparation work can be completed before the host driver takes over again.

[0043] In this embodiment, when the validity check result is successful, the firmware bootloader loads the complete snapshot data packet into the on-chip SRAM and establishes a snapshot buffer in the on-chip SRAM for the subsequent recovery stage. The data content corresponding to the FEC mode, LRO parameters, SDI VLAN table, PF rate limit and SerDes mapping relationship in the snapshot data packet is organized into a buffer data format that can be directly written to the function control register. When the validity check result is unsuccessful, the firmware bootloader no longer uses the snapshot content in the dedicated snapshot storage partition, but instead reads the factory default configuration data from the factory default configuration area of ​​the on-chip FLASH and loads the factory default configuration data into the on-chip SRAM, so that the network card chip can at least return to a backup path that is bootable, enumerable and can enter the normal initialization process.

[0044] In one specific embodiment, the process of performing step 131 may specifically include the following steps: (1) After the network card chip completes the PCIe reset, read the snapshot data packets from the dedicated snapshot storage partition; (2) Recalculate the first check value of the snapshot data packet and compare the first check value with the second check value stored in the snapshot data packet; (3) When the first check value and the second check value are the same, the validity check result is determined to be that the check is passed; when the first check value and the second check value are different, the validity check result is determined to be that the check is not passed.

[0045] Specifically, after the network card chip completes the PCIe reset, the firmware bootloader retrieves the complete snapshot data packet from the dedicated snapshot storage partition via the SPI access path and temporarily stores the read snapshot data packet in the verification buffer, thereby avoiding repeated access to external storage in the recovery path. The verification logic recalculates the first verification value for the main body of the snapshot data packet. The calculation rule of the first verification value is consistent with the second verification value attached to the end of the snapshot data packet during the write-to-hard stage, so that the read stage and the write stage follow the same integrity judgment criteria, ensuring that the comparison results are repeatable and traceable. After the first checksum is calculated, the verification logic extracts the second checksum from the end of the snapshot data packet and performs a bit-by-bit comparison between the first and second checksums. If the comparison results are consistent, it indicates that the snapshot data packet stored in the dedicated snapshot storage partition was not damaged, truncated, or abnormally rewritten after being solidified before the reset. The validity verification result is determined to be valid, and the recovery process can continue to use this snapshot data packet as the data source for configuration recovery. If the comparison results are inconsistent, it indicates that there is an integrity abnormality in the snapshot data packet during the writing, saving, or reading process. The recovery entry point determines the validity verification result to be invalid and blocks the mismatched snapshot from continuing to participate in configuration recovery.

[0046] In one specific embodiment, such as Figure 7 As shown, the process of executing step 104 can specifically include the following steps: 141. Extract the second configuration status of each configuration item sequentially from the snapshot data in the on-chip SRAM, and write the second configuration status of each configuration item into the function control register of the corresponding function module one by one. 142. After all the function control registers of all functional modules are written, a configuration recovery ready signal is sent to the PCIe link state machine so that the host driver skips the full configuration delivery process and directly enters the service forwarding state after receiving the configuration recovery ready signal, and the total time from the snapshot data packet being loaded into the on-chip SRAM to the issuance of the configuration recovery ready signal does not exceed the preset time.

[0047] Specifically, the firmware bootloader directly invokes the hierarchical fast recovery executor, reads the already organized second configuration state from various snapshot buffer register groups in the on-chip SRAM, and writes it to the function control registers of each functional module according to the functional dependencies. The on-chip SRAM has already split the snapshot data packet into FEC mode snapshot buffer registers, LRO parameter snapshot buffer registers, SDI VLAN table snapshot buffer registers, PF rate-limiting snapshot buffer registers, and SerDes mapping snapshot buffer registers. Therefore, the recovery execution phase does not need to perform parsing on external storage again, but directly extracts the target fields from the on-chip SRAM and writes them back to the chip's internal register group, thereby compressing the recovery link length and reducing external bus access latency. The recovery process proceeds in the following order: SerDes mapping, FEC mode, PF rate limiting, LRO parameters, and SDI VLAN table. The SerDes mapping corresponds to the binding relationship between physical high-speed differential transceiver channels and logical ports, and must be restored first. FEC mode relates to the physical layer error correction strategy and must be loaded before link re-establishment. PF rate limiting recovery restores the bandwidth scheduling boundary to its pre-reset state. LRO parameter recovery maintains the original aggregation performance of the receive path. The SDI VLAN table is written back to the corresponding registers after the aforementioned critical links stabilize, thus restoring the Layer 2 isolation relationship to the snapshot state. After each configuration write is completed, the recovery executor reads the readback value or completion status bit of the corresponding function control register to confirm that the second configuration state in the on-chip SRAM has been stably written to the target register, preventing register write mismatches due to the incomplete readiness of some modules after reset. The entire item-by-item recovery process is autonomously completed by the network interface card (NIC) firmware.

[0048] In this embodiment, the recovery executor sends a configuration recovery ready signal to the PCIe link state machine only after the readback contents of all target function control registers are consistent with the second configuration state in the on-chip SRAM, the ready states of each functional module are valid, and the snapshot recovery success state is set. Subsequently, the PCIe link enumeration process continues. After completing the PCIe link enumeration, the host driver reads the snapshot recovery success state reported by the network card, and can then skip the full configuration distribution process and directly enter the service forwarding state. Meanwhile, the total time from the snapshot data packet being loaded into the on-chip SRAM to the issuance of the configuration recovery ready signal is controlled by a preset time, for example, limiting the complete recovery process to within 100ms.

[0049] In one specific embodiment, the process of performing step 142 may specifically include the following steps: (1) After all the function control registers of all functional modules have been written, a configuration recovery ready signal is sent to the PCIe link state machine; (2) After completing the PCIe link enumeration, the host driver reads the snapshot reported by the network card and restores the status successfully; (3) When the snapshot recovery success status is snapshot recovery success, skip the full configuration distribution process and directly enter the service forwarding status, and the total time from the snapshot data packet being loaded into the on-chip SRAM to the configuration recovery ready signal being issued does not exceed the preset time.

[0050] Specifically, a dedicated recovery handshake link is established between the hierarchical fast recovery executor and the PCIe link state machine, and the recovery completion determination is based on the premise that all functional module registers have been successfully written. In the previous recovery phase, the SerDes mapping relationship, FEC mode, PF rate limit, LRO parameters, and the second configuration state corresponding to the SDI VLAN table have been written back to the target function control register from the on-chip SRAM item by item. Therefore, after the last type of configuration is written, the hierarchical fast recovery executor continues to read the readback value or completion status bit of each target register and performs a general verification of the entire recovery result. Only when the readback content of all target registers is consistent with the second configuration state in the on-chip SRAM, and all functional modules have entered the working state, does the hierarchical fast recovery executor set the configuration recovery ready signal to the PCIe link state machine, so that the PCIe link enumeration process can continue to advance. This avoids the link state machine prematurely releasing the subsequent enumeration process before the local configuration is stable, thereby ensuring that the network card seen by the host side is in the state of critical configuration recovery completion.

[0051] In this embodiment, after the PCIe link enumeration is completed, the host driver reads the snapshot recovery success status flag reported by the network interface card (NIC). The snapshot recovery success status flag can be synchronously written to the status register or status buffer by the recovery executor after issuing the configuration recovery ready signal, and provided to the host driver for reading after the PCIe configuration space becomes accessible. When the host driver reads that the snapshot recovery success status is successful, it determines that the NIC has autonomously completed the recovery of critical configurations, and then skips the full redistribution path of configuration items such as FEC mode, LRO parameters, SDI VLAN table, PF rate limiting, and SerDes mapping relationship, directly entering the service forwarding state. The host driver's responsibility changes from "reconstructing all running configurations after reset" to "confirming the autonomous recovery result and resuming services after enumeration," thereby eliminating the long recovery latency caused by the reliance on the operating system, driver loading, and item-by-item configuration distribution in traditional solutions.

[0052] The PCIe reset-linked network card configuration method in this embodiment of the invention has been described above. The PCIe reset-linked network card configuration device in this embodiment of the invention is described below. Please refer to [link to relevant documentation]. Figure 8 One embodiment of the network card configuration device with PCIe reset linkage in this invention includes: The listening module 801 is used to listen for change events of multiple configuration items and write the first configuration state of the changed configuration item to a dedicated snapshot storage partition. The write module 802 is used to monitor the PCIe bus hardware reset signal in real time and, within the hardware timing window before the network card chip enters the reset state, force the full configuration status of multiple configuration items to be written to the dedicated snapshot storage partition. The verification module 803 is used to read snapshot data packets from the dedicated snapshot storage partition and perform validity verification after the network card chip completes PCIe reset, and load the verified snapshot data packets into the on-chip SRAM. The configuration recovery module 804 is used to perform configuration recovery on each functional module in the network card based on the snapshot data packets in the on-chip SRAM, and the total configuration recovery time does not exceed the preset time.

[0053] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the above systems and units can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0054] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0055] The above-described embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A network card configuration method with PCIe reset linkage, characterized in that, include: Listen for change events of multiple configuration items and write the first configuration state of the changed configuration item to a dedicated snapshot storage partition; The system monitors the PCIe bus hardware reset signal in real time and, within the hardware timing window before the network interface card (NIC) chip enters the reset state, forces the full configuration state of the multiple configuration items to be written to the dedicated snapshot storage partition. Specifically, this includes: supplying power to the NIC chip's constant-current domain hardware circuit via a constant-current domain auxiliary power supply; sampling the PCIe bus hardware reset signal in real time through the constant-current domain hardware circuit; and, when the PCIe bus hardware reset signal is detected to transition from high to low, sending a forced write trigger signal to the snapshot write controller. Based on the forced write trigger signal, within the hardware timing window before the NIC chip enters the reset state, the snapshot write controller performs a forced write of the full configuration state of the multiple configuration items, thus solidifying the full configuration state to the dedicated snapshot storage partition. After the network card chip completes the PCIe reset, it reads the snapshot data packet from the dedicated snapshot storage partition and performs validity verification. The snapshot data packet that passes the verification is loaded into the on-chip SRAM. Based on the snapshot data packets in the on-chip SRAM, the configuration of each functional module in the network card is restored, and the total duration of the configuration restoration does not exceed a preset duration. Specifically, this includes: extracting the second configuration state of each configuration item from the snapshot data in the on-chip SRAM in sequence, writing the second configuration state of each configuration item into the function control register of the corresponding functional module one by one; after the function control registers of all functional modules are written, a configuration restoration ready signal is sent to the PCIe link state machine, so that the host driver skips the full configuration distribution process and directly enters the service forwarding state after receiving the configuration restoration ready signal, and the total duration from the snapshot data packets being loaded into the on-chip SRAM to the issuance of the configuration restoration ready signal does not exceed the preset duration.

2. The network card configuration method with PCIe reset linkage according to claim 1, characterized in that, The process of monitoring change events for multiple configuration items and writing the first configuration state of the changed configuration item to a dedicated snapshot storage partition includes: Based on the change frequency and business importance level of multiple configuration items, snapshot update trigger conditions and update granularity are set for each configuration item to obtain a differentiated update strategy for each configuration item; Listen for change events of multiple configuration items; The first configuration state of the changed configuration item is read and written to the dedicated snapshot storage partition based on the differentiated update strategy. No write operation is performed on the configuration item that has not been changed.

3. The network card configuration method with PCIe reset linkage according to claim 2, characterized in that, The multiple configuration items include FEC mode, LRO parameters, SDI VLAN table, PF rate limiting, and SerDes mapping relationship. Based on the change frequency and service importance level of these multiple configuration items, snapshot update trigger conditions and update granularity are set for each configuration item, resulting in differentiated update strategies for each configuration item, including: When the configuration item is FEC mode and LRO parameter, the snapshot update trigger condition in the differential update strategy of the configuration item is set to be triggered immediately after the corresponding register write operation occurs; When the configuration item is SDI VLAN table and PF rate limit, the snapshot update trigger condition in the differentiated update policy of the configuration item is set to trigger in batches after the cumulative changes reach the update granularity threshold. When the configuration item is a SerDes mapping relationship, the snapshot update trigger condition in the differential update strategy of the configuration item is set to trigger a full write once after the network card initialization is completed and no further triggers are made.

4. The network card configuration method with PCIe reset linkage according to claim 1, characterized in that, Based on the forced write trigger signal, within the hardware timing window before the network card chip enters the reset state, the snapshot write controller performs a forced write to the full configuration state of multiple configuration items, thus solidifying the full configuration state to the dedicated snapshot storage partition. This includes: Based on the forced write trigger signal, the snapshot write controller sequentially reads the full configuration status of multiple configuration items, appends an integrity check value to the end of the full configuration status, and assembles them into a snapshot data packet. The snapshot data packet is written to the dedicated snapshot storage partition via the SPI bus, and a snapshot validity flag is written to a fixed address in the dedicated snapshot storage partition after the snapshot data packet is written, thus completing the solidification of the full configuration state.

5. The network card configuration method with PCIe reset linkage according to claim 1, characterized in that, After the network interface card chip completes a PCIe reset, the step of reading snapshot data packets from the dedicated snapshot storage partition and performing validity verification, and loading the verified snapshot data packets into the on-chip SRAM, includes: After the network card chip completes the PCIe reset, it reads the snapshot data packet from the dedicated snapshot storage partition and performs a validity check on the snapshot data packet to obtain the validity check result. If the validity check result is successful, the snapshot data packet is loaded into the on-chip SRAM; if the validity check result is unsuccessful, the factory default configuration data is read from the factory default configuration area of ​​the on-chip FLASH and loaded into the on-chip SRAM.

6. The network card configuration method with PCIe reset linkage according to claim 5, characterized in that, After the network interface card (NIC) chip completes a PCIe reset, snapshot data packets are read from the dedicated snapshot storage partition, and the validity of the snapshot data packets is verified to obtain the validity verification result, including: After the network interface card chip completes a PCIe reset, it reads snapshot data packets from the dedicated snapshot storage partition; Recalculate the first checksum of the snapshot data packet and compare the first checksum with the second checksum stored in the snapshot data packet; When the first check value and the second check value are the same, the validity check result is determined to be valid; when the first check value and the second check value are different, the validity check result is determined to be invalid.

7. The network card configuration method with PCIe reset linkage according to claim 1, characterized in that, After the function control registers of all functional modules are written, a configuration recovery ready signal is sent to the PCIe link state machine. This allows the host driver to skip the full configuration delivery process and directly enter the service forwarding state upon receiving the configuration recovery ready signal. Furthermore, the total time from the snapshot data packet being loaded into the on-chip SRAM to the issuance of the configuration recovery ready signal does not exceed a preset time, including: After the function control registers of all functional modules have been written, a configuration recovery ready signal is sent to the PCIe link state machine. After completing the PCIe link enumeration, the host driver reads the snapshot reported by the network card and restores the status successfully. When the snapshot recovery success status is "snapshot recovery successful", the full configuration distribution process is skipped and the service forwarding state is directly entered. The total time from the snapshot data packet being loaded into the on-chip SRAM to the issuance of the configuration recovery ready signal does not exceed the preset time.

8. A network card configuration device with PCIe reset linkage, characterized in that, A network card configuration method for performing PCIe reset linkage as described in any one of claims 1-7 includes: The monitoring module is used to monitor change events of multiple configuration items and write the first configuration state of the changed configuration item to a dedicated snapshot storage partition; The write module is used to monitor the PCIe bus hardware reset signal in real time and, within the hardware timing window before the network card chip enters the reset state, force the full configuration state of the multiple configuration items to be written to the dedicated snapshot storage partition. Specifically, the write module is used to supply power to the constant power domain hardware circuit of the network card chip by the constant power domain auxiliary power supply, and to sample the PCIe bus hardware reset signal in real time through the constant power domain hardware circuit. When the PCIe bus hardware reset signal is detected to transition from high level to low level, a forced write trigger signal is sent to the snapshot write controller. Based on the forced write trigger signal, within the hardware timing window before the network card chip enters the reset state, the snapshot write controller performs a forced write to the full configuration state of the multiple configuration items, thus solidifying the full configuration state to the dedicated snapshot storage partition. The verification module is used to read snapshot data packets from the dedicated snapshot storage partition and perform validity verification after the network card chip completes PCIe reset, and load the verified snapshot data packets into the on-chip SRAM. The configuration recovery module is used to perform configuration recovery on each functional module in the network card based on the snapshot data packets in the on-chip SRAM, and the total time for configuration recovery does not exceed a preset time. Specifically, the configuration recovery module is used to extract the second configuration state of each configuration item from the snapshot data in the on-chip SRAM in sequence, and write the second configuration state of each configuration item into the function control register of the corresponding functional module one by one. After the function control registers of all functional modules are written, a configuration recovery ready signal is sent to the PCIe link state machine, so that the host driver skips the full configuration delivery process and directly enters the service forwarding state after receiving the configuration recovery ready signal, and the total time from the snapshot data packet being loaded into the on-chip SRAM to the issuance of the configuration recovery ready signal does not exceed the preset time.

Images