Image Transmission and Processing Method and System Based on PAL Camera Input

Abstract

This invention relates to the field of image transmission and processing technology, specifically disclosing an image transmission and processing method and system based on PAL camera input, including a PAL camera video input unit, an A / D video decoding and conversion unit, an FPGA data receiving and forwarding unit, and an ARM architecture processing system connected in sequence; after receiving digital image data, the ARM architecture processing system arranges the odd and even rows according to the odd and even field signals and stores them in DDR memory, calculates the absolute difference of grayscale pixel by pixel between the previous frame and the current frame and accumulates them to obtain the sum of grayscale differences between frames. If the sum is greater than a preset threshold, the data of each row of odd field is copied and inserted into the adjacent even row to form a complete frame before output; otherwise, the odd and even field data are arranged in an interleaved row manner to form a complete frame before output.

Description

Technical Field

[0001] This invention relates to the field of image transmission and processing technology, and specifically discloses an image transmission and processing method and system based on PAL camera input. Background Technology

[0002] In PAL analog video acquisition and processing systems, interlaced scanning can cause problems such as line misalignment and jagged edges when displaying images. This is especially problematic when moving objects are present; simply using odd-even field interlacing for deinterlacing can easily produce motion artifacts like trailing and tearing. Existing systems typically use a fixed deinterlacing method, which struggles to balance image quality in both static and dynamic scenes and lacks intelligent detection and adaptive processing capabilities for moving areas, impacting overall display quality and system applicability. Summary of the Invention

[0003] This invention aims to solve the problem that existing image processing systems based on PAL camera input lack intelligent judgment of the motion state of the image during interlaced video conversion, resulting in artifacts such as jagged edges and trailing in dynamic scenes, and insufficient processing efficiency and clarity in static scenes. Therefore, it provides an image transmission and processing system that can adaptively select the deinterlacing mode based on the inter-frame motion detection results.

[0004] This invention provides an image transmission and processing system based on PAL camera input. The system includes a PAL camera video input unit, an A / D video decoding and conversion unit, an FPGA data receiving and forwarding unit, and an ARM architecture processing system. The PAL camera video input unit is connected to the A / D video decoding and conversion unit, which is connected to the FPGA data receiving and forwarding unit. The FPGA data receiving and forwarding unit is connected to the ARM architecture processing system via a PCIe interface. The ARM architecture processing system, upon receiving digital image data from the FPGA data receiving and forwarding unit, processes the data according to... The even-field signal arranges the image data in odd and even rows and stores it in DDR memory. The previous frame image stored in DDR memory is retrieved and the absolute difference of gray level is calculated pixel by pixel with the current frame image. The absolute difference of gray level of all pixels in the whole frame is accumulated and summed to obtain the total gray level difference between frames. If the total gray level difference between frames is greater than a preset threshold, it is determined that there is motion in the picture. The data of each row of odd field is copied in sequence and inserted into the next even-numbered row to form a complete frame data, which is then output and displayed through the HDMI interface. If the total gray level difference between frames is not greater than the preset threshold, it is determined that there is no large motion in the picture. The odd and even field data are arranged in an alternating row to form a complete frame data, which is then output and displayed through the HDMI interface.

[0005] This invention provides an image transmission and processing method based on PAL camera input. The PAL camera video input unit acquires PAL-format analog video images and transmits the image data to an A / D video decoding and conversion unit. The A / D video decoding and conversion unit decodes the serial signal of the received analog image into line signals, field signals, parity field flag signals, and digital image data, and transmits them to an FPGA data receiving and forwarding unit according to a pre-configured format. The FPGA data receiving and forwarding unit determines the parity or evenness of the input video based on the parity field enable signal and stores the digital image data in a block random access memory (BRAM). When it receives an output enable signal from the ARM architecture processing system and the enable signal is valid, it transfers the data in the BRAM to a first-in-first-out (FIFO) buffer, prioritizing odd-field data and then even-field data. The data is sequentially transmitted to the ARM architecture processing system via the PCIe interface. After receiving the digital image data, the ARM architecture processing system arranges the image data into odd and even rows according to the odd and even field signals and stores it in the DDR memory. It retrieves the previous frame image stored in the DDR memory and calculates the absolute difference of grayscale pixel by pixel with the current frame image. It then sums up the absolute differences of grayscale of all pixels in the entire frame to obtain the total grayscale difference between frames. If the total grayscale difference between frames is greater than a preset threshold, it is determined that there is motion in the picture. The data of each row of odd field is copied sequentially and inserted into the next even-numbered row to form a complete frame data, which is then output and displayed through the HDMI interface. If the total grayscale difference between frames is not greater than the preset threshold, it is determined that there is no significant motion in the picture. The data of odd and even fields is arranged in an alternating row pattern to form a complete frame data, which is then output and displayed through the HDMI interface.

[0006] The beneficial technical effects of this invention are as follows: by using an ARM architecture processing system to calculate the sum of grayscale differences between frames and comparing it with a preset threshold, intelligent judgment of the motion state of the image is achieved; when large motion is detected, a deinterlacing method of copying odd field data and inserting even-numbered rows is adopted to effectively suppress motion artifacts; when there is no large motion, an odd-even field staggered arrangement method is adopted to preserve image details and clarity in static scenes, thereby improving the image display quality in different scenes. Attached Figure Description

[0007] Figure 1 This is a block diagram of an image transmission and processing system based on PAL camera input according to the present invention.

[0008] Figure 2 This is a flowchart of the data processing and transmission process of the present invention. Detailed Implementation

[0009] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0010] like Figure 1As shown, the system includes: a PAL camera video input unit, an A / D video decoding and conversion unit, an FPGA data receiving and forwarding unit, and an ARM architecture processing system.

[0011] In this embodiment, the PAL camera can be, for example, a standard PAL analog camera; the A / D video decoding and conversion unit uses an MS7026; the microcontroller uses an STM32F410; the FPGA data receiving and forwarding unit uses a K325T; and the ARM architecture processing system uses an RK3588. The entire system includes a PAL camera video input unit connected to the A / D video decoding and conversion unit, the A / D video decoding and conversion unit connected to the FPGA data receiving and forwarding unit, and the FPGA data receiving and forwarding unit connected to the ARM architecture processing system. The image processing flow is as follows: Figure 2 As shown.

[0012] The PAL camera video input unit includes a PAL camera and an external dimming module; the A / D video decoding and conversion unit includes an A / D conversion chip and a microcontroller for configuring the input mode; the FPGA data receiving and forwarding unit includes an FPGA chip and its Flash memory chip; and the ARM architecture processing system includes an ARM architecture CPU, DDR memory, and an output display interface and a display.

[0013] The peripheral dimming module automatically adjusts the aperture or fill light intensity of the PAL camera based on the image brightness analysis results fed back by the ARM architecture processing system to ensure image quality.

[0014] After the PAL camera video input unit is powered on, it starts to output images. After receiving commands from the ARM architecture processing system, it starts to adjust the format, exposure time, and frequency of the input video. Finally, the generated image data is sent to the A / D video decoding and conversion unit.

[0015] After receiving the analog image from the PAL camera video input unit, the A / D video decoding and conversion unit decodes the serial signal into line, field, and odd / even field marker signals and digital image data, and then transmits them to the FPGA data receiving and forwarding unit according to the format pre-configured by the microcontroller.

[0016] After receiving the digital image input from the A / D video decoding and conversion unit, the FPGA data receiving and forwarding unit buffers multiple lines of images, merges them into a large data packet, and sends it to the ARM architecture processing system.

[0017] The microcontroller configured with input mode is connected to the A / D conversion chip via the I2C communication protocol. By configuring the registers in the A / D conversion chip, different resolutions and output video formats can be achieved, including odd / even field control of the video, progressive scan or interlaced scan.

[0018] After receiving the digital image signal from the A / D video decoding and conversion unit, the FPGA data receiving and forwarding unit first determines the odd or even field of the input video based on the odd / even field enable signal, then receives the data and stores it in the BRAM; when it receives the output enable signal from the ARM architecture processing system and the enable signal is valid, it transfers the data from the BRAM to the FIFO, and the FPGA first sends the odd field video, then sends the even field video, which is transmitted to the ARM architecture processing system for processing through the PCIe interface.

[0019] After receiving image data signals from the FPGA, the ARM architecture processing system arranges the image data into odd and even rows according to the odd and even field signals, and stores the arranged image data in DDR memory. The ARM architecture processing system retrieves the previous frame image stored in DDR memory, calculates the absolute grayscale difference pixel-by-pixel with the current frame image, and sums the absolute grayscale differences of all pixels in the entire frame to obtain the sum of grayscale differences (SAD) between frames. The preset threshold can be set according to the actual image resolution and application scenario. For example, at a resolution of 576×720, the threshold can be set as the product of the total number of pixels in the frame and the grayscale variation tolerance of a single pixel, with an actual value range of 10. 5 Up to 10 7 The magnitude of the motion is determined by the SAD (Solution Aspect Ratio). If the SAD exceeds a preset threshold, it is determined that there is motion in the image. The ARM architecture processing system copies the data from each row of the odd field sequentially and inserts them into the next even-numbered row to form a complete frame. Finally, as an optional step, the frame data is filtered and then output for display via the HDMI interface. If the SAD is not greater than the preset threshold, it is determined that there is no significant motion in the image. The ARM architecture processing system arranges the odd and even field data in an alternating row arrangement and optionally performs filtering before finally outputting for display via the HDMI interface.

[0020] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above descriptions are merely specific embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. An image transmission and processing system based on PAL camera input, characterized in that, The system includes a PAL camera video input unit, an A / D video decoding and conversion unit, an FPGA data receiving and forwarding unit, and an ARM architecture processing system. The PAL camera video input unit is connected to the A / D video decoding and conversion unit, which is connected to the FPGA data receiving and forwarding unit. The FPGA data receiving and forwarding unit is connected to the ARM architecture processing system via a PCIe interface. The ARM architecture processing system, upon receiving digital image data from the FPGA data receiving and forwarding unit, performs parity row processing on the image data based on parity field signals. The data is arranged and stored in DDR memory. The previous frame image stored in DDR memory is retrieved and the absolute difference of grayscale is calculated pixel by pixel with the current frame image. The absolute difference of grayscale of all pixels in the whole frame is accumulated and summed to obtain the total grayscale difference between frames. If the total grayscale difference between frames is greater than a preset threshold, it is determined that there is motion in the picture. The data of each row of odd field is copied in sequence and inserted into the next even numbered row to form a complete frame data and then output for display through HDMI interface. If the total grayscale difference between frames is not greater than the preset threshold, it is determined that there is no large motion in the picture. The odd and even field data are arranged in an alternating row to form a complete frame data and then output for display through HDMI interface.

2. The system according to claim 1, characterized in that, The PAL camera video input unit includes a PAL camera; the A / D video decoding and conversion unit includes an A / D conversion chip and a microcontroller; the FPGA data receiving and forwarding unit includes an FPGA chip and its Flash memory chip; the ARM architecture processing system includes an ARM architecture central processing unit, DDR memory, and an output display interface; the PAL camera video input unit may also include a peripheral dimming module, used to automatically adjust the aperture or fill light intensity of the PAL camera based on the image brightness analysis results fed back by the ARM architecture processing system.

3. The system according to claim 2, characterized in that, The microcontroller is connected to the A / D conversion chip via the I2C communication protocol. The microcontroller configures the video resolution, odd / even field control, and progressive scan or interlaced scan format by configuring the registers in the A / D conversion chip.

4. The system according to claim 1, characterized in that, The FPGA data receiving and forwarding unit is used to determine the odd or even field of the input video based on the odd / even field enable signal after receiving the digital image signal from the A / D video decoding and conversion unit, and store the data in the block random access memory; when it receives the output enable signal from the ARM architecture processing system and the enable signal is valid, it transfers the data in the block random access memory into the first-in-first-out buffer, and transmits it to the ARM architecture processing system through the PCIe interface in the order of odd field data first and even field data second.

5. The system according to claim 1, characterized in that, The ARM architecture processing system is also used to filter the frame data after it has been formed into complete frame data and before it is output through the HDMI interface.

6. An image transmission and processing method based on PAL camera input, characterized in that, The PAL camera video input unit acquires PAL-format analog video images and transmits the image data to the A / D video decoding and conversion unit. The A / D video decoding and conversion unit decodes the received analog image's serial signal into line signals, field signals, parity field flag signals, and digital image data, and transmits them to the FPGA data receiving and forwarding unit according to a pre-configured format. The FPGA data receiving and forwarding unit determines the parity of the input video based on the parity field enable signal and stores the digital image data in the block random access memory (BRAM). When it receives and activates the output enable signal from the ARM architecture processing system, it transfers the data from the BRAM to the first-in-first-out (FIFO) buffer and transmits it to the FPGA via the PCIe interface in the order of odd-field data first, followed by even-field data. The ARM architecture processing system receives digital image data, arranges the image data into odd and even rows according to the odd and even field signals, and stores it in DDR memory. It retrieves the previous frame image stored in DDR memory and calculates the absolute difference of grayscale pixel by pixel with the current frame image. It then sums the absolute differences of grayscale of all pixels in the entire frame to obtain the total grayscale difference between frames. If the total grayscale difference between frames is greater than a preset threshold, it is determined that there is motion in the picture. The data of each row of odd field is copied in sequence and inserted into the next even-numbered row to form a complete frame data, which is then output and displayed through the HDMI interface. If the total grayscale difference between frames is not greater than the preset threshold, it is determined that there is no significant motion in the picture. The odd and even field data are arranged in an alternating row pattern to form a complete frame data, which is then output and displayed through the HDMI interface.

7. The method according to claim 6, characterized in that, The microcontroller in the A / D video decoding and conversion unit is connected to the A / D conversion chip via the I2C communication protocol. By configuring the registers in the A / D conversion chip, the video resolution, odd / even field control, and progressive scan or interlaced scan format can be configured. The A / D video decoding and conversion unit transmits digital image data to the FPGA data receiving and forwarding unit according to the format pre-configured by the microcontroller.

8. The method according to claim 6, characterized in that, After receiving the digital image signal from the A / D video decoding and conversion unit, the FPGA data receiving and forwarding unit determines the odd or even field of the input video based on the odd / even field enable signal and stores the data in the block random access memory. When it receives the output enable signal from the ARM architecture processing system and the enable signal is valid, it transfers the data in the block random access memory into the first-in-first-out buffer and transmits it to the ARM architecture processing system through the PCIe interface in the order of odd field data first and even field data second.

9. The method according to claim 6, characterized in that, The ARM architecture processing system calculates the absolute grayscale difference pixel by pixel between the current frame and the previous frame, and sums up the absolute grayscale differences of all pixels in the entire frame to obtain the total grayscale difference between frames. The total grayscale difference between frames is then compared with a preset threshold to determine whether there is motion in the image.

10. The method according to claim 6, characterized in that, If the sum of the grayscale differences between frames is greater than a preset threshold, the ARM architecture processing system will copy the data of each row of the odd field sequentially and insert them into the next even-numbered row to form a complete frame data and then output it for display through the HDMI interface; if the sum of the grayscale differences between frames is not greater than the preset threshold, the ARM architecture processing system will arrange the odd and even field data in an alternating row pattern to form a complete frame data and then output it for display through the HDMI interface.

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