A hybrid readout system and method for full-span and multi-region-of-interest imaging detectors

Abstract

This invention discloses a full-frame and multi-region-of-interest (ROI) hybrid readout system and method suitable for wide-swath imaging detectors, comprising a detector section and a peripheral logic control section. The peripheral logic control section includes a full-frame windowed hybrid readout module, a high-speed buffer and data marking module, a FIFO buffer array, and a FIFO framing array. The full-frame windowed hybrid readout module divides the full-frame period into n sub-frame periods; within each sub-frame, the detector sequentially outputs a segment of the full-frame image data and complete data for all N preset ROI windows. The high-speed buffer and data marking module acquires and marks row and column address information; the FIFO buffer array, based on the markings, distributes the data to the FIFO areas of the full-frame data and each window's data; the FIFO framing array stitches the full-frame segments into a complete full-frame image frame and frames each window's data into an independent windowed image frame for output. This invention fundamentally solves the contradiction between "low speed in full-frame" and "loss of global coverage in windowed images."

Description

Technical Field

[0001] This invention relates to the fields of microelectronics and image sensors, specifically to a full-frame and multi-region-of-interest hybrid readout system and method suitable for wide-swath imaging detectors. Background Technology

[0002] With the rapid development of technologies such as remote sensing, machine vision, and security monitoring, the performance requirements for imaging systems are increasing. These systems not only need to acquire global scene information with a wide field of view (i.e., "full-frame image"), but also require continuous, high-speed, and high-resolution detailed observation of multiple specific key targets or regions of interest scattered throughout the scene (i.e., "windowed areas"). This high-level demand for "seeing both the forest and the trees" has become an important development direction for modern imaging systems. Wide-swath imaging detectors, especially CMOS image sensors, as the core devices for achieving these requirements, have pixel counts exceeding hundreds of millions, providing extremely high spatial resolution. However, traditional detector readout methods are gradually showing their limitations when facing such complex application requirements.

[0003] Currently, wide-swath imaging detectors mainly support the following two readout modes:

[0004] Full-frame readout mode: In this mode, the entire pixel array is read out after each exposure. Its advantage lies in acquiring complete scene information, providing comprehensive environmental context for subsequent analysis. However, as the pixel size of detectors continues to increase, the amount of data generated in full-frame mode is extremely large, leading to a significant reduction in the readout frame rate and placing enormous pressure on the system's data bandwidth. This limitation makes full-frame mode unsuitable for real-time monitoring of dynamic targets or rapidly changing scenes.

[0005] Windowed Readout Mode: This mode effectively reduces the amount of data per frame and significantly improves the readout frame rate by reading only pixel data within one or more user-preset rectangular windows and discarding data from areas outside the window. While windowed mode offers a speed advantage in capturing local details, its inherent drawback lies in the loss of global information. Because background data outside the window is completely discarded, the connection between the target and its global environment is severed, leading to a significant impact on subsequent data analysis, target behavior understanding, and other applications due to the lack of global contextual information.

[0006] In current wide-swath detector applications, systems typically have to choose between "full-swath low-speed" and "windowed scanning with a loss of overall context," making it difficult to simultaneously meet the dual requirements of global situational awareness and local detail capture. For example, in applications such as Earth observation satellites monitoring ships in specific areas, UAVs tracking multiple targets in wide-area urban areas, and industrial production lines simultaneously detecting defects in multiple products, operators do not want to miss the instantaneous state of key targets while waiting for a slow full-swath scan, nor do they want to fail to capture newly emerging targets or lose the correlation between targets and the global environment due to a fixed windowed scanning.

[0007] In existing technologies, the paper "High Speed ​​readout architecture for CMOS image sensor: A dual approach using adaptive reconfigurable Systems and low-power SAR ADCS" (J. Lee, 2026) from Delft University of Technology proposes a scheme for dynamically switching between full-frame mode and region of interest (ROI) mode. However, this scheme focuses on switching between a single ROI and full-frame mode to capture high-speed small targets, and does not support continuous monitoring of multiple arbitrarily distributed ROIs of varying sizes simultaneously. Furthermore, in high-speed ROI tracking mode, this scheme often sacrifices the integrity of the entire image, failing to provide users with a complete and uninterrupted global scene image while acquiring local details. This means the system still cannot meet the requirement of simultaneously achieving global situational awareness and high-frame-rate detailed investigation of multiple local targets.

[0008] Therefore, there is an urgent need in this field for a new detector readout method and circuit architecture that can simultaneously read out the full-frame image and multiple arbitrarily distributed regions of interest in a scene while being compatible with existing readout circuits, thereby simultaneously meeting the system's dual requirements for global situational awareness and local detail capture. Summary of the Invention

[0009] To address the problems existing in current wide-swath imaging detector readout technologies, this invention proposes a hybrid readout system and method for full-frame and multi-region-of-interest (ROI) imaging detectors. This system can simultaneously acquire complete scene information of the full-frame image and high-frame-rate detail information of multiple ROI regions within a single full-frame imaging cycle. This satisfies the dual requirements of application scenarios for global information acquisition and high-frame-rate detailed examination of local targets, resolving the contradiction between "low speed in full-frame imaging" and "loss of global information when opening windows".

[0010] To achieve the above objectives, the technical solution of the present invention is as follows:

[0011] On the one hand, the present invention proposes a full-frame and multi-region-of-interest hybrid readout system suitable for wide-swath imaging detectors, including a detector section and a peripheral logic control section;

[0012] The detector section includes a detector array, and row control circuits, column control circuits, pixel readout circuits, an ADC analog-to-digital converter array, and a detector control module connected to the detector array; the detector section directly transmits the digital pixel data output by the ADC analog-to-digital converter array to the peripheral logic control section via a data bus.

[0013] The peripheral logic control section includes a full-width windowed hybrid readout module, a high-speed buffer and data marking module, a FIFO buffer array, a FIFO frame array, and a synchronization control bus;

[0014] The detector section is connected to the peripheral logic control section via the synchronous control bus; the high-speed buffer and data tagging module receives digital pixel data streams from the ADC analog-to-digital converter array of the detector section.

[0015] The full-frame windowed hybrid readout module is used to send control commands to the detector control module and coordinate the operation of the high-speed buffer and data tagging module, the FIFO buffer array and the FIFO frame array; the full-frame windowed hybrid readout module is configured to execute a hybrid readout timing sequence that divides a complete full-frame period TF into n sub-frame periods Tsub, such that Tsub=TF / n;

[0016] The detector control module is used to control the row control circuit, column control circuit, pixel readout circuit and ADC analog-to-digital converter array according to the control instructions to perform mixed readout of full frame and multiple regions of interest. Specifically, within each subframe period Tsub, the detector control module controls the detector to perform mixed readout operation, and in a continuous data stream, outputs a full frame image data block for stitching a complete full frame image, followed by complete data of N preset region of interest windows, where N is an integer greater than or equal to 2.

[0017] The high-speed buffer and data marking module, located in the peripheral logic control section, is the first-level off-chip circuit for receiving data from the detector section. This module includes a high-speed data buffer and a row / column marking unit. The high-speed data buffer receives and temporarily stores digital pixel data streams from the ADC analog-to-digital converter array of the detector section to match the writing timing of the subsequent FIFO buffer array. The row / column marking unit is connected to the synchronization control bus, obtains the row and column address information of the currently read pixel from the row control circuit and column control circuit via the synchronization control bus, and marks the pixel data with the row and column address information as a data header before each pixel data is output to the subsequent FIFO buffer array.

[0018] The FIFO buffer array is used to receive and temporarily store the tagged mixed read data from the high-speed buffer and data tagging module, and delete redundant data under control; the FIFO buffer array contains a full-width data FIFO area and multiple independent window data FIFO areas, which are used to divert the received data to the corresponding FIFO area according to the row and column position tags.

[0019] The FIFO framing array is used to separate and frame the effective data processed by the FIFO buffer array into full-frame image data and windowed image data. Specifically, the FIFO framing array splices full-frame image data blocks from different subframes in the full-frame data FIFO area into a complete full-frame image frame, and frames the data in each window data FIFO area into independent windowed image frames for output.

[0020] In this system, the data flow and inter-module coordination are as follows: Driven by the row and column control circuits, the detector array converts the optical signal into an analog electrical signal; the pixel readout circuit reads the analog electrical signal and sends it to the ADC (Analog-to-Digital Converter) array, converting it into digital pixel data; the digital pixel data then crosses the chip's internal and external boundaries and is transmitted to the high-speed buffer and data marking module of the peripheral logic control section; the high-speed buffer and data marking module performs high-speed temporary storage on the received digital pixel data stream and obtains row and column address information from the detector section through the synchronization control bus, appending row and column position marks to each pixel data; the marked mixed pixel data stream then enters the FIFO buffer array; under the control of the full-frame windowed mixed readout module, the FIFO buffer array, based on the row and column position marks carried by each pixel data, converts the data into digital pixel data. Pixel data is split and stored in the full-frame data FIFO area or the window data FIFO area corresponding to its region of interest window. During this process, redundant data caused by the spatial overlap between the full-frame slice and the region of interest window is deleted. The effective data after splitting and filtering then enters the FIFO frame array. The full-frame image data blocks in the full-frame data FIFO area are sequentially stitched into complete full-frame image frames, and the data in each window data FIFO area are encapsulated into independent windowed image frames. Finally, one full-frame image frame stream and N independent windowed image frame streams are output in parallel from the FIFO frame array. The entire data stream process is uniformly coordinated by the synchronization control signal sent by the full-frame windowed hybrid readout module to the detector control module, the high-speed buffer and data tagging module, the FIFO buffer array, and the FIFO frame array through the synchronization control bus.

[0021] In a further preferred embodiment, the full-frame windowed hybrid readout module can be configured to switch between two operating modes:

[0022] Full-frame hybrid readout mode: In this mode, the complete full-frame image is read out in slices within multiple consecutive subframes, and all preset region of interest windows are read out synchronously within each subframe.

[0023] Window Hybrid Readout Mode: In this mode, the full-frame image is viewed as being stitched together from multiple specific windows. Within each subframe, a portion of the window image used to stitch the full-frame is read out, and all preset regions of interest window images are read out simultaneously.

[0024] A further preferred embodiment, to support stable synchronous output of N region of interest windows, includes a window configuration double-buffered register in the peripheral logic control section. This register consists of a spare register and a working register. When the system needs to update the window configuration, the position, size, and number parameters of the new region of interest windows are written to the spare register. At the beginning boundary of each full-frame period, the contents of the spare register are loaded entirely into the working register. The output of the working register is connected to the configuration input of the full-frame windowed hybrid readout module, thereby driving the hybrid readout operation of the current frame period. This mechanism ensures that during dynamic parameter reconfiguration, the currently output full-frame or windowed image frame will not experience tearing or data loss due to partial updates.

[0025] A further preferred embodiment, to avoid line address conflicts during mixed readout, includes a line address arbitrator within the line control circuit; the input of the line address arbitrator is connected to the full-frame windowed mixed readout module, receiving the current subframe full-frame data block line range and the line ranges of all preset region of interest windows from the full-frame windowed mixed readout module; the output of the line address arbitrator is connected to the line gating signal generation logic of the line control circuit.

[0026] When the read rows required for the full-frame image data block overlap with the read rows required for any region of interest window within a subframe period, the line address arbitrator executes the read of the full-frame data block first, and then executes the read of each region of interest window according to a preset priority rule, and automatically skips the repeated line read operations in the overlapping area; the line address arbitrator is implemented through a lookup table, which stores the non-repeating, sorted read line address sequence pre-calculated based on the current subframe and window configuration, so that the line strobe signal generation logic can execute the read in sequence.

[0027] In a further preferred embodiment, the detector section and the peripheral logic control section use the same clock source, and digital circuit synchronous logic timing is used to realize synchronous control of internal and external data of the detector.

[0028] A further preferred option is to use a high-speed SPI bus for the synchronous control bus.

[0029] On the other hand, this invention proposes a hybrid readout method for full-frame and multi-region of interest sensors suitable for wide-swath imaging detectors, comprising the following steps:

[0030] Step 1, Frame Division: Divide a full-frame period into n subframes;

[0031] Step 2, Hybrid Readout: Within each subframe, the detector is controlled to perform a hybrid readout operation, simultaneously outputting partial data of the full-frame image and all data of at least one region of interest window in a single data stream;

[0032] Step 3, Data Tagging: Tag the row and column position information of the pixel data in the mixed data stream output from Step 2;

[0033] Step 4: Data Filtering: Based on the row and column position information, filter out valid full-frame image data blocks and region of interest window data from the mixed data stream;

[0034] Step 5, Data Framing and Output: The selected valid full-frame image data blocks are stitched together into a complete full-frame image frame, and the data of each region of interest window are framed into independent windowed image frames and output.

[0035] Step 6: Repeat steps 2 to 5 until all n subframes have been processed, and output one full-frame image and n frames of region of interest images.

[0036] Step 7: Repeat steps 1-6 to complete the acquisition and output of multi-frame full-frame and multi-region-of-interest windowed images.

[0037] In a further preferred embodiment, in step 2, the hybrid readout operation is performed based on either a full-width hybrid readout mode or a window hybrid readout mode.

[0038] A further preferred embodiment involves, before executing step 1 or step 2, using the window configuration double-buffered register, atomically and dynamically reconfiguring the windowing parameters during the vertical blanking period before the start of the full-frame period. Specifically, when the system needs to update the window configuration, the position, size, and number parameters of the new region of interest window are written into the spare register of the window configuration double-buffered register. At the beginning boundary of each full-frame period, the contents of the spare register are loaded into the working register. The output of the working register directly drives the full-frame windowed hybrid readout module to generate the hybrid readout timing within the current frame period, thereby ensuring that parameter updates do not cause tearing or data loss in the currently output full-frame or windowed image frame.

[0039] In a further preferred embodiment, in step 2, the hybrid readout operation generates a readout address sequence without row conflicts through a row address arbitrator. Specifically, before the start of each subframe, the row address arbitrator receives the current subframe full-frame data block row range and the row ranges of all preset region of interest windows from the full-frame windowed hybrid readout module at its input. The pre-calculation module inside the row address arbitrator generates a readout row address sequence without repetition and ordered by priority through sorting and deduplication operations, and writes it into a lookup table. The row address arbitrator outputs the readout row address sequence to the row strobe signal generation logic of the row control circuit through its output. During the subframe period, the row control circuit reads addresses from the lookup table sequentially for scanning, thereby avoiding repeated scanning of the same row between full-frame readout and windowed readout.

[0040] In a further preferred embodiment, in step 3, the data marking is performed by a high-speed buffer and data marking module located in the peripheral logic control section; this module receives digital pixel data streams from the ADC analog-to-digital converter array of the detector section, performs high-speed temporary storage, and obtains row and column address information from the row control circuit and column control circuit through the synchronous control bus, and marks the row and column address information as data headers on each pixel data.

[0041] In a further preferred embodiment, the filtering in step 4 includes deleting interval data or invalid data used for full-frame image stitching.

[0042] In a further preferred embodiment, the full-frame image frame output in step 5 has a different output frame rate than each windowed image frame, wherein the output frame rate fROI of each windowed image frame is n times the output frame rate fFull of the full-frame image frame, i.e., fROI = n × fFull.

[0043] Beneficial effects

[0044] Compared with the prior art, the present invention has the following significant advantages:

[0045] 1. It achieves high-speed parallel acquisition of complete global images and multiple local images, resolving the contradiction between "low speed for full-frame" and "loss of global coverage when opening windows".

[0046] In existing technologies, the Delft University of Technology's solution only supports switching between a single region of interest (ROI) and full-frame mode to capture high-speed small targets. In high-speed ROI tracking, this often sacrifices the integrity of the full-frame image, failing to simultaneously provide users with a complete global scene image and detailed images of multiple local targets. This invention, through a subframe partitioning mechanism and hybrid readout timing, divides a full-frame period (TF) into n subframe periods (Tsub). Each subframe sequentially outputs a full-frame slice data block and complete data for all N ROI windows. This achieves the synchronous and continuous capture and output of a complete full-frame image and N independent high-frame-rate windowed images within a single system. The frame rate fROI of each windowed image reaches n times the full-frame frame rate fFull, i.e., fROI = n × fFull, achieving a unification of "global situational awareness" and "high-frame-rate detailed investigation of multiple local targets."

[0047] 2. It has extremely high flexibility and dynamic adaptability, and ensures the robustness of dynamic reconfiguration.

[0048] Existing technologies typically employ a piecewise update approach when dynamically adjusting windowing parameters, which can easily lead to tearing or frame loss in the current output image when parameters are partially updated. This invention introduces a dual-buffered window configuration register consisting of a spare register and a working register. New window parameters are first written to the spare register, and then loaded entirely into the working register at the beginning boundary of each full-frame cycle, completing the parameter switching and ensuring that the readout operation of the current frame is always based on a complete and consistent window configuration. Combined with a mechanism that performs updates during the vertical blanking period before the start of the full-frame cycle, this invention supports multiple window definitions of arbitrary position, size, and number, and can dynamically update window settings between frames and even subframes, enhancing responsiveness to dynamic scenes and sudden targets while avoiding image quality degradation caused by parameter updates.

[0049] 3. It avoids row address conflicts during mixed reading, ensuring determinism and low latency in the reading process.

[0050] In hybrid readout mode, the readout lines required for full-frame segmentation and the readout lines required for multiple region of interest (ROI) windows are prone to spatial overlap. Without proper handling, this can lead to readout timing conflicts or duplicate readouts. This invention addresses this by incorporating a line address arbitrator within the line control circuit. This arbitrator receives the current subframe full-frame data block line range and the line ranges of all open windows from the full-frame windowed hybrid readout module. A pre-calculation module performs sorting and deduplication operations to generate a unique, priority-based readout line address sequence, which is then written into a lookup table. The line control circuit can then scan sequentially to avoid line address conflicts. This hardware-implemented conflict resolution mechanism ensures determinism and low latency in the hybrid readout process, offering higher reliability and real-time performance compared to existing solutions that rely on software scheduling or temporary interrupt handling.

[0051] 4. High hardware efficiency, easy integration, and significant system bandwidth optimization effect.

[0052] The solution of this invention is mainly based on the optimization and enhancement of the existing CMOS readout circuit architecture. Specifically, it adds only a row address arbitrator and supporting control logic on-chip, and adds a high-speed buffer and data marking module, as well as a FIFO buffer array and FIFO frame array composed of a full-frame data FIFO area and multiple independent window data FIFO areas off-chip. No major modifications to the pixel array itself are required, resulting in high technological maturity and ease of implementation and integration in existing chip design flows. Simultaneously, by outputting a separated, data-optimized full-frame image frame stream and N independent windowed image frame streams, the system backend can apply different processing priorities, compression strategies, and transmission channels to different data streams, thereby reducing the overall data bandwidth pressure on the system and improving overall system efficiency. Compared with the traditional solution that always performs full-frame readout, this invention has a significant advantage in data bandwidth utilization efficiency.

[0053] 5. It realizes hardware-level real-time splitting and parallel framing of mixed data streams, avoiding the bandwidth constraints of a single memory interface.

[0054] This invention establishes a high-speed buffer and data marking module at the first stage of the peripheral logic control section. It utilizes a synchronous control bus to obtain pixel row and column address information from the on-chip row and column control circuit in real time and marks the data in the data stream. After marking, the mixed data stream enters the FIFO buffer array and is automatically split into the corresponding full-frame data FIFO area or window data FIFO area based on the row and column position markings. This pipeline architecture of off-chip marking—hardware splitting—parallel framing completes data classification and reassembly in real time at the hardware level, avoiding the bandwidth constraints of a single memory interface and eliminating the need for backend processor intervention, thus ensuring stable system operation at high data rates.

[0055] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0056] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which:

[0057] Figure 1 The present invention provides a principle block diagram of a hybrid readout system for full-frame and multi-region of interest suitable for wide-swath imaging detectors;

[0058] Figure 2 : A schematic diagram of the full-frame hybrid readout mode provided by this invention;

[0059] Figure 3 : A schematic diagram of the windowed hybrid readout mode provided by the present invention. Detailed Implementation

[0060] The embodiments of the present invention are described in detail below. These embodiments are exemplary and intended to explain the present invention, and should not be construed as limiting the present invention.

[0061] This embodiment aims to overcome the shortcomings of existing wide-swath imaging detector readout technology and provide a hybrid readout circuit system and method for full-span and multi-region of interest imaging detectors. It makes full use of the existing full-span readout mode or windowed readout mode of the detector. The peripheral logic devices of the detector coordinate the synchronization of the chip row control circuit and column control circuit and control information. Under unified timing scheduling, it realizes hybrid access and data extraction of the detector pixel array.

[0062] I. System Overall Architecture

[0063] like Figure 1 As shown, this invention provides a readout circuit system, including a detector section and a peripheral logic control section. The detector section is connected to the detector's peripheral logic devices via a high-speed synchronous control bus to achieve precise synchronization of row and column exposure, reset, and readout control. In this embodiment, the detector section and the detector's peripheral logic devices use the same clock source for their synchronization logic circuits, and digital circuit synchronization logic timing is used to achieve synchronous control of data inside and outside the detector. The synchronization control bus uses a high-speed SPI bus.

[0064] (a) Detector section

[0065] The detector section includes a detector array, row control circuit, column control circuit, pixel readout circuit, ADC analog-to-digital converter array, and detector control module.

[0066] The detector array is a large-scale CMOS image sensor array consisting of M×N pixels. In this embodiment, a 250 million-pixel detector array with a resolution of 17280×15360 is used.

[0067] The row control circuit is responsible for generating row strobe signals, controlling which row in the pixel array is activated and read out. In this invention, the row control circuit can perform two scanning modes: conventional line-by-line sequential scanning and window-based skip scanning.

[0068] The column control circuit is responsible for processing the pixel signals of the activated row, including column amplifiers, correlation double sampling circuits, etc.

[0069] The pixel readout circuit reads out the analog electrical signal and sends it to the ADC analog-to-digital converter array.

[0070] An ADC (Analog-to-Digital Converter) array contains multiple parallel analog-to-digital converters used to convert analog pixel signals into digital signals. The converted digital pixel data is then directly transmitted via a data bus to the high-speed buffer and data tagging module of the peripheral logic control section.

[0071] The detector control module is the core control unit of this invention, implemented using a single programmable logic device and containing a microcontroller. It receives control commands from the full-amplitude and windowed hybrid readout module in the peripheral logic control section via a synchronous control bus, parses the full-amplitude and windowed parameters, generates corresponding timing control signals, and coordinates the operation of the row and column circuits and the ADC array.

[0072] (ii) Peripheral logic control section

[0073] The peripheral logic control section includes a full-width windowed hybrid readout module, a high-speed buffer and data tagging module, a FIFO buffer array, a FIFO frame array, and a synchronization control bus.

[0074] 1. Full-frame windowed hybrid readout module

[0075] The full-width windowed hybrid readout module is the core control unit of the peripheral logic control section. It is used to send control commands to the detector control module and coordinate the operation of the high-speed buffer and data tagging module, FIFO buffer array and FIFO frame array.

[0076] This module is configured to execute a hybrid readout timing sequence that divides a complete full-frame period TF (set to 1 second in this embodiment) into n sub-frame periods Tsub, such that Tsub = TF / n. Within each sub-frame period Tsub, the detector control module controls the detector to perform a hybrid readout operation, outputting a full-frame image data block for stitching together a complete full-frame image in a continuous data stream, followed by complete data for N preset region of interest windows. In this embodiment, N is set to 4, and each window size is 640 × 512 pixels.

[0077] Specifically, in this embodiment, the full-frame windowed hybrid readout module includes a subframe timer. This timer uses the detector line period as the base time unit and divides the full-frame period TF evenly into n subframe periods Tsub according to a preset number of subframes n, such that Tsub = TF / n. At the beginning of each subframe period, the subframe timer loads the line count value corresponding to the current subframe. After the full-frame data block has read the line count, it automatically switches to the region of interest window readout stage. When the subframe timer returns to zero, the current subframe ends, and the next subframe automatically begins. After looping n times, it outputs exactly one full-frame image and n frames of region of interest window images.

[0078] This module can be configured to switch between two working modes:

[0079] (1) Full-frame hybrid readout mode: In this mode, the complete full-frame image is read out in segments within multiple consecutive subframes, and all preset region of interest window images are read out synchronously within each subframe. In this embodiment, the number of columns in the full-frame is 512, and the full-frame period TF is divided into 30 subframes (n=30).

[0080] (2) Window Hybrid Readout Mode: In this mode, the full-frame image is considered to be stitched together from multiple specific windows. Within each subframe, a portion of the window image used to stitch the full-frame is read out, and all preset regions of interest window images are read out simultaneously. In this embodiment, the full-frame incremental block size is 1920×1536 pixels, and the number of subframes is 90.

[0081] 2. Configure double-buffered registers for the window (not shown in the diagram).

[0082] To support stable synchronous output and dynamic configuration of N region of interest windows, the peripheral logic control section includes a window configuration double-buffered register. This double-buffered register consists of two levels: a spare register and a working register.

[0083] When the system needs to update the window configuration, the external system controller (such as a host computer or the system main control chip) writes the position, size, and number of new region of interest windows into the spare register. The parameters include the start row address, end row address, start column address, end column address, and the number of windows N for each window. During the vertical blanking period before the start of each full-frame period, the contents of the spare register are loaded into the working register in one go. The output of the working register is connected to the configuration input of the full-frame windowed hybrid readout module, directly driving the generation of the hybrid readout timing within the current frame period.

[0084] The double buffering mechanism ensures the atomicity of parameter updates, meaning that all new parameters take effect simultaneously at a fixed moment, preventing intermediate states where some windows have been updated while others remain with the old values. This eliminates image tearing or data frame loss caused by partial parameter updates.

[0085] 3. Row address arbitrator (not shown in the diagram)

[0086] To resolve potential row address conflicts between the full-width readout window and multiple region of interest windows during mixed readout, this embodiment integrates a row address arbitrator based on a lookup table within the row control circuit.

[0087] The arbitrator's input is connected to the full-frame windowed hybrid readout module, receiving the current subframe full-frame data block line range and the line ranges of all preset region of interest windows from this module. Its output is connected to the line strobe signal generation logic of the line control circuit.

[0088] The arbitrator's workflow is as follows: Before the start of each subframe, it receives the full-frame data block row range and the row ranges of all open windows in the current subframe; all the above row addresses are input into a pre-computation module; the pre-computation module generates a non-repeating, priority-ordered sequence of read row addresses through sorting and deduplication operations, and writes it into a lookup table; the row control circuit reads the addresses from the lookup table sequentially during the subframe period. The priority rule is: readout of the full-frame data block is performed first, followed by readout of each region of interest window. This mechanism fundamentally avoids repeatedly scanning the same row between different readout tasks, resolves timing conflicts, and ensures determinism and low latency in the readout process.

[0089] 4. High-speed buffer and data tagging module (named Buffer and High-speed Interface in the diagram)

[0090] The high-speed buffer and data tagging module is located in the peripheral logic control section and is the first-level off-chip circuit that receives data from the detector section.

[0091] This module receives the digital pixel data stream directly transmitted from the ADC analog-to-digital converter array in the detector section via the data bus, and buffers it at high speed to match the writing timing of the subsequent FIFO buffer array. Simultaneously, this module obtains the row and column address information of the currently read pixel from the row and column control circuits in the detector section via the synchronization control bus, and marks the row and column position information as a data header on each pixel data during the data buffering process. The marked data also includes frame headers, timestamps, ROI numbers, and other information, providing a basis for subsequent data distribution in the FIFO buffer array.

[0092] 5. FIFO buffer array

[0093] The FIFO buffer array receives the tagged and mixed pixel data stream from the high-speed buffer and data tagging module. Internally, it contains a full-frame data FIFO area and multiple independent window data FIFO areas (corresponding to 4 window FIFO areas in this embodiment).

[0094] Under the control of the full-frame windowed hybrid readout module, the FIFO buffer array divides the pixel data into corresponding FIFO areas according to the row and column position markers carried by each pixel data: pixels belonging to the full-frame segment data block are stored in the full-frame data FIFO area, and pixels belonging to a certain region of interest window are stored in the window data FIFO area corresponding to that window. During this process, redundant data caused by the spatial overlap between the full-frame segment and the region of interest window is automatically deleted, thereby realizing the extraction of effective full-frame and windowed information.

[0095] 6. FIFO frame array

[0096] The FIFO frame array reads the split data from the FIFO buffer array and consists of a set of independent first-in-first-out memories, including a full-width FIFO and multiple windowed FIFOs.

[0097] The full-frame FIFO is used to buffer and stitch together full-frame image data: it sequentially stitches together full-frame image data blocks from different subframes within the full-frame data FIFO area to complete a full-frame image frame. Each windowed FIFO encapsulates the data in its corresponding window data FIFO area into an independent windowed image frame. Finally, one full-frame image frame stream and N independent windowed image frame streams are output in parallel from the FIFO frame array.

[0098] II. Overall Description of Data Flow and Control Flow

[0099] The following is an overall description of the data flow and control flow of this system within a complete full-frame cycle, in order to clarify the collaborative working relationship between the modules.

[0100] (a) Control Flow

[0101] The external system controller writes the window configuration parameters into the spare register of the window configuration double buffer register; during the vertical blanking period before the start of each full-frame period, the contents of the spare register are loaded into the working register, driving the full-frame windowed hybrid readout module to update the hybrid readout timing parameters of the current frame; the full-frame windowed hybrid readout module sends line exposure, reset and readout control commands to the detector control module through the synchronous control bus, and directly controls the working timing of the high-speed buffer and data marking module, FIFO buffer array and FIFO frame array.

[0102] (ii) Data Flow

[0103] Driven by row and column control circuits, the detector array converts optical signals into analog electrical signals. The pixel readout circuit reads the analog electrical signals and sends them to the ADC (Analog-to-Digital Converter) array, converting them into digital pixel data. The digital pixel data is transmitted across the chip's internal and external boundaries via a data bus to the high-speed buffer and data marking module in the peripheral logic control section. This module performs high-speed temporary storage of the data stream and obtains row and column address information through the synchronous control bus to complete data marking. The marked mixed pixel data stream enters the FIFO buffer array and is automatically split into the full-frame data FIFO area or the corresponding window data FIFO area according to the row and column position markings, with redundant data being deleted synchronously. The effective data after splitting and filtering enters the FIFO frame array, where the full-frame data is sequentially stitched into complete full-frame image frames, and each window's data is encapsulated into an independent windowed image frame. The two image frame streams are output in parallel. The entire process is coordinated by the full-frame windowed mixed readout module to ensure the coordinated operation of all parts.

[0104] III. Hybrid Readout Method Flow

[0105] Based on the aforementioned hardware, this embodiment provides a hybrid readout method for full-frame and multi-region-of-interest (MOI) readout suitable for wide-swath imaging detectors, comprising the following steps:

[0106] Step 1: Atomic update of frame division and window configuration:

[0107] During the vertical blanking period before the start of a full-frame period, the position, size, and number parameters of all N preset region of interest windows are atomically updated using a window-configured double-buffered register. Then, a full-frame period (TF) is divided into n sub-frame periods (Tsub). Within each full-frame, the frame is further divided into n sub-frames according to the increasing column number of the full-frame, and detector row exposure begins according to either full-frame hybrid readout mode or window hybrid readout mode.

[0108] Step 2, Mixed Readout

[0109] Within each subframe, the control detector performs a hybrid readout operation, simultaneously outputting partial data of the full-frame image and all data of at least one region of interest window in a single data stream. Within each subframe, full-frame pixels and windowed pixels are output in a hybrid readout mode, a windowed readout mode, and according to the subframe parameter configuration.

[0110] Specifically, the full-frame windowed hybrid readout module sends the full-frame data block row range of the current subframe and the row range of all windowed windows to the row address arbitrator. The row address arbitrator performs sorting and deduplication operations through the pre-calculation module, generating a non-repeating, priority-ordered readout row address sequence and writing it into the lookup table. The row control circuit performs row gating scanning according to the address sequence of the lookup table, thereby outputting the full-frame image data block and the complete data of all N region of interest windows of the subframe sequentially in a continuous data stream. After the digital pixel data stream is output from the ADC analog-to-digital converter array, it is directly transmitted to the high-speed buffer and data tagging module of the peripheral logic control section through the data bus.

[0111] Step 3, Data Tagging

[0112] The high-speed buffer and data marking module receives digital pixel data streams from the ADC analog-to-digital converter array of the detector section, performs high-speed temporary storage, and obtains row and column address information from the row control circuit and column control circuit through the synchronous control bus, marking the row and column address information as data headers on each pixel data.

[0113] Step 4: Data Filtering

[0114] The FIFO buffer array receives the tagged data stream from the high-speed buffer and data tagging module. Under the control of the full-frame windowed hybrid readout module, the pixel data is automatically split and stored into the full-frame data FIFO area or the window data FIFO area corresponding to the window of the region of interest, based on the row and column position tags carried by each pixel data. In this process, redundant data caused by the overlap between the full-frame segmentation and the region of interest window space is deleted.

[0115] Step 5: Data framing and output

[0116] The FIFO frame array sequentially stitches together full-frame image data blocks from different subframes in the full-frame data FIFO area into a complete full-frame image frame. It also encapsulates the data in each window data FIFO area into independent windowed image frames, outputting the full-frame image and multi-region-of-interest (ROI) windowed images according to both the full-frame and windowed frame protocols. The output full-frame image frame and each windowed image frame have different output frame rates. The output frame rate fROI of each windowed image frame is n times the output frame rate fFull of the full-frame image frame, i.e., fROI = n × fFull.

[0117] Step 6, Subframe Loop

[0118] Repeat steps 2 through 5 until all n subframes have been processed, completing the acquisition and output of one full-frame image and n frames of multiple arbitrarily windowed images. For example... Figure 2 As shown, in the full-frame hybrid readout mode, the full-frame information of the interval subframes is incremented in fixed columns without intervals or repetition to achieve multi-frame coverage of the full image. Multiple windowed information at arbitrary positions within each subframe are read out along with the occupied row, and the corresponding row and column window information is retrieved in the data merging and filtering section. For example... Figure 3 As shown, in the window hybrid readout mode, the full-frame information in each subframe is read out using multiple windows for full-frame readout and useless information. The useless information is also used for full-frame information stitching. The interval subframes are arranged in order from left to right and from top to bottom of the array without intervals or repetition to achieve multi-frame coverage of the full-frame image. Multiple windowed information at arbitrary positions in each subframe are read out according to the occupied rows and columns.

[0119] Step 7, Multi-frame loop

[0120] Repeat steps 1 to 6 to continuously acquire and output multiple frames of full-frame and multi-region-of-interest windowed images.

[0121] IV. Experimental Verification and Data Comparison

[0122] To verify the technical effectiveness of this invention, a hardware simulation platform was constructed based on the aforementioned 17280×15360 detector model and four 640×512 pixel region of interest (ROI) windows. With the full-frame period (TF) set to 1 second (full-frame frame rate fFull=1fps), and using a full-frame hybrid readout mode, the TF was divided into 30 sub-frames (n=30). Therefore, the theoretical frame rate for each ROI window is fROI=30fps.

[0123] In the simulation, a model based on existing technology (the proposed solution) was run simultaneously as a control group. This control group polled and tracked four targets at a total rate of 30 fps within one second. The simulation results are compared in the table below:

[0124]

[0125] Simulation data shows that, within the same full-frame imaging cycle, the proposed solution provides complete global situational awareness (1fps full-frame image) while simultaneously offering stable, conflict-free 30fps high-frame-rate detailed images for each local target. Existing solutions, on the other hand, can only poll and track multiple targets at the cost of sacrificing global image quality and segmented local frame rates. This verifies the significant advancement of the proposed solution in resolving the contradiction between global situational awareness and high-frame-rate detailed analysis of multiple local targets.

[0126] V. Detailed Procedures for Two Readout Modes

[0127] The readout process for the two readout modes, full-frame hybrid mode and windowed hybrid mode, is described in detail below. The detector target surface is 17280×15360, the number of windows is 4, the window size is 640×512, the number of full-frame incremental columns in full-frame hybrid readout mode is 512, and the size of the full-frame incremental block in windowed hybrid readout mode is 1920×1536.

[0128] (I) Full-frame mixed mode readout process

[0129] The full-width windowed hybrid readout module is set to full-width hybrid mode, and the generation driver configuration is sent to the detector control module.

[0130] Step 1: Within each full-frame, divide the frame into 30 (15360 / 512) subframes according to the window frame rate. The first frame covers rows 0-511. Four windows are positioned arbitrarily within the array, generating corresponding row positions. Window 1 corresponds to 512 rows, window 2 corresponds to 512 rows, and windows 3 and 4, due to overlap, generate a total of 768 rows. The row address arbitrator receives the above row range, sorts and removes duplicates using the pre-calculation module, generates a conflict-free read address sequence, and writes it into the lookup table.

[0131] Step 2: Within the subframe, 2304 rows are generated. The row control circuit performs row selection according to the lookup table order. The row and column control and pixel reading are performed sequentially for exposure and reading. The first subframe generates a total of 2304×17280 pixel information.

[0132] Step 3: The generated information is directly transmitted to the peripheral logic control section via the data bus, enters the high-speed buffer and data marking module, performs data temporary storage, and obtains the row and column address information from the row / column control circuit through the synchronous control bus. The full-width row and column information, the row and column position information of window 1, window 2, window 3, and window 4 are stored together with the generated pixel information in the FIFO buffer array as the data information header.

[0133] Step 4: The full-frame windowed hybrid readout module controls the FIFO buffer array to distinguish the subframe information into full-frame and window information according to the row and column position marks. All the full-frame 512×17280 pixel information enters the full-frame data FIFO area, and the 640×512 pixel information of each of the four windows enters the corresponding window data FIFO area. During the process, invalid information occupied by the windowed window is filtered out.

[0134] Step 5: The separated full-frame information and windowed information are fed into the FIFO frame array, and the full-frame image and multi-interest region windowed image are output according to the full-frame frame protocol and the windowed frame protocol.

[0135] Step 6: Repeat steps 2-5 until the last subframe is processed. For each subframe, add 512×17280 pixels of new full-frame information vertically, and add four 640×512 pixel windowed information. For example... Figure 2 As shown, in the full-frame hybrid readout mode, the full-frame image of the detector is generated through 30 subframes, during which 30 frames of real-time images in four windows are generated. Before processing each subframe, if it is necessary to dynamically adjust the window parameters, atomic updates can be performed during the vertical blanking period through the window configuration double buffer register. Multiple windowed images can be moved between subframes.

[0136] Step 7: Repeat steps 1-6 to complete the acquisition and output of multi-frame full-frame and multi-region-of-interest windowed images.

[0137] (II) Windowed Hybrid Mode Readout Process

[0138] The full-width windowed hybrid readout module is set to windowed hybrid mode, and the generated driver configuration is sent to the detector control module.

[0139] Step 1: Allocate 3 windows within the subframe as full-frame readout windows. Each window can generate 1536×1920 blocks of full-frame information. The subframe can be divided into 10×9 frames, totaling 90 frames. The 4 windows are positioned arbitrarily within the array according to their settings, generating corresponding row positions: window 1 corresponds to 640×512 blocks of information, window 2 corresponds to 640×512 blocks of information, window 3 corresponds to 640×512 blocks of information, and window 4 corresponds to 640×512 blocks of information. The row address arbitrator receives the above row range, sorts and removes duplicates using the pre-calculation module, generates a conflict-free readout address sequence, and writes it into the lookup table.

[0140] Step 2: Within the subframe, based on the generated full-frame and windowed block information, the row control circuit performs row selection according to the lookup table order, and the row and column control and pixel reading are performed sequentially for exposure and reading. The first subframe generates a total of one 1536×1920 block of information and four windows of 640×512 blocks of information.

[0141] Step 3: Generate 5 block information and transmit them directly to the peripheral logic control section via the data bus. Enter the high-speed buffer and data marking module for temporary data storage. Obtain the row and column address information from the row / column control circuit through the synchronous control bus. Store the full-frame block information row and column position, window 1, window 2, window 3, and window 4 row and column position information as data headers together with the generated pixel information into the FIFO buffer array.

[0142] Step 4: The full-frame windowed hybrid readout module controls the FIFO buffer array to distinguish the subframe information into full-frame and window information according to the row and column position marks. The full-frame 1536×1920 pixel information enters the full-frame data FIFO area, and the 640×512 pixel information of each of the four windows enters the corresponding window data FIFO area.

[0143] Step 5: The separated full-frame information and windowed information are fed into the FIFO frame array, and the full-frame image and multi-interest region windowed image are output according to the full-frame frame protocol and the windowed frame protocol.

[0144] Step 6: Repeat steps 2-5 until the last subframe is processed. In each subframe, add 1536×1920 pixels of new full-frame information horizontally or vertically in the pixel increment column, and add four 640×512 pixel window information. For example... Figure 3 As shown, the full-frame image of the detector was generated through 90 subframes, during which 90 frames of real-time images in four windows were generated. Before processing each subframe, if it is necessary to dynamically adjust the window parameters, atomic updates can be performed during the vertical blanking period through the window configuration double buffer register. Multiple windowed images can be moved between subframes.

[0145] Step 7: Repeat steps 1-6 to complete the acquisition and output of multi-frame full-frame and multi-region-of-interest windowed images.

[0146] The two types of read stream instructions define multiple regions of interest (ROI) windowing regions, each uniquely determined by its start row address, end row address, start column address, and end column address. These windowing positions can be arbitrarily distributed across the entire width, and their number is limited only by the circuit's buffer capacity.

[0147] Both readout modes can simultaneously output full-frame and multi-interest region windows. The full-frame hybrid mode has a high frame rate for full-frame data acquisition, while the multi-interest region windowing mode has a high frame rate for multi-interest region windowing acquisition. The two modes and their respective parameters can be further optimized and used selectively according to the needs of the scenario.

[0148] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention without departing from the principles and spirit of the present invention.

Claims

1. A hybrid readout system for full-frame and multi-region-of-interest (MOI) imaging detectors, characterized in that: Includes the detector section and the peripheral logic control section; The detector section includes a detector array, and row control circuits, column control circuits, pixel readout circuits, an ADC analog-to-digital converter array, and a detector control module connected to the detector array; the detector section directly transmits the digital pixel data output by the ADC analog-to-digital converter array to the peripheral logic control section via a data bus. The peripheral logic control section includes a full-width windowed hybrid readout module, a high-speed buffer and data marking module, a FIFO buffer array, a FIFO frame array, and a synchronization control bus; The detector section is connected to the peripheral logic control section via the synchronous control bus; The full-frame windowed hybrid readout module is used to send control commands to the detector control module and coordinate the operation of the high-speed buffer and data tagging module, the FIFO buffer array and the FIFO frame array; the full-frame windowed hybrid readout module is configured to execute a hybrid readout timing sequence that divides a complete full-frame period TF into n sub-frame periods Tsub, such that Tsub=TF / n; The detector control module is used to control the row control circuit, column control circuit, pixel readout circuit and ADC analog-to-digital converter array according to the control instructions to perform mixed readout of full frame and multiple regions of interest; within each subframe period Tsub, the detector control module controls the detector to perform mixed readout operation, and in a continuous data stream, outputs a full frame image data block for stitching a complete full frame image, followed by complete data of N preset region of interest windows, where N is an integer greater than or equal to 2; The high-speed buffer and data tagging module, located in the peripheral logic control section, is the first-level off-chip circuit for receiving data from the detector section. The module includes a high-speed data buffer and a row and column tagging unit. The high-speed data buffer is used to receive and temporarily store digital pixel data streams from the ADC analog-to-digital converter array of the detector section. The row and column marking unit is connected to the synchronization control bus. It obtains the row and column address information of the currently read pixel from the row control circuit and the column control circuit through the synchronization control bus. Before each pixel data is output to the subsequent FIFO buffer array, the row and column address information is marked as a data header on the pixel data. The FIFO buffer array is used to receive and temporarily store the tagged mixed readout data from the high-speed buffer and data tagging module; the FIFO buffer array contains a full-frame data FIFO area and multiple independent window data FIFO areas, which are used to split the received data into the corresponding FIFO areas according to the row and column position tags, and delete redundant data caused by the overlap between the full-frame fragment and the region of interest window space during the data splitting process. The FIFO frame array is used to stitch together full-frame image data blocks from different sub-frames in the full-frame data FIFO area into a complete full-frame image frame, and to frame the data in each window data FIFO area into independent windowed image frames for output.

2. The full-frame and multi-region-of-interest hybrid readout system according to claim 1, characterized in that, The full-width windowed hybrid readout module can be configured to switch between two working modes: Full-frame hybrid readout mode: In this mode, the complete full-frame image is read out in slices within multiple consecutive subframes, and all preset region of interest windows are read out synchronously within each subframe. Window Hybrid Readout Mode: In this mode, the full-frame image is viewed as being stitched together from multiple specific windows. Within each subframe, a portion of the window image used to stitch the full-frame is read out, and all preset regions of interest window images are read out simultaneously.

3. The full-frame and multi-region-of-interest hybrid readout system according to claim 1, characterized in that, The peripheral logic control section also includes a window configuration double-buffered register; the window configuration double-buffered register consists of two levels: a spare register and a working register; when the system needs to update the window configuration, the position, size, and number parameters of the new region of interest window are written into the spare register; at the beginning boundary of each full-frame period, the contents of the spare register are loaded into the working register as a whole, and the output of the working register is connected to the configuration input of the full-frame windowed hybrid readout module, thereby driving the hybrid readout operation of the current frame period.

4. The full-frame and multi-region-of-interest hybrid readout system according to claim 1, characterized in that, The line control circuit includes a line address arbitrator; the input of the line address arbitrator is connected to the full-frame windowed hybrid readout module, and receives the line range of the current subframe full-frame data block and the line range of all preset region of interest windows from the full-frame windowed hybrid readout module; the output of the line address arbitrator is connected to the line gating signal generation logic of the line control circuit. When the read rows required for the full-frame image data block overlap with the read rows required for any region of interest window within a subframe period, the line address arbitrator first executes the read of the full-frame data block according to a preset priority rule, then executes the read of each region of interest window, and automatically skips repeated line read operations in the overlapping area; the line address arbitrator is implemented through a lookup table, which stores a non-repeating, sorted read line address sequence pre-calculated based on the current subframe and window configuration.

5. The full-frame and multi-region-of-interest hybrid readout system according to claim 1, characterized in that, The full-frame windowed hybrid readout module contains a subframe timer. This subframe timer uses the detector line period as the base time unit and divides the full-frame period TF into n subframe periods Tsub according to a preset number of subframes n. At the beginning of each subframe period, the subframe timer loads the line count value corresponding to the current subframe. After the full-frame data block has read the line count, it automatically switches to the region of interest window readout stage. When the subframe timer returns to zero, the current subframe ends and the next subframe automatically begins.

6. The full-frame and multi-region-of-interest hybrid readout system according to claim 1, characterized in that, The detector section and the peripheral logic control section use the same clock source, and digital circuit synchronous logic timing is used to realize synchronous control of data inside and outside the detector.

7. A hybrid readout method for full-frame and multi-region-of-interest (MOI) imaging detectors, applicable to the system described in any one of claims 1 to 6, characterized in that, Includes the following steps: Step 1, Frame Division: Divide a full-frame period TF into n sub-frame periods Tsub; Step 2, Hybrid Readout: Within each subframe period Tsub, the detector is controlled to perform a hybrid readout operation, outputting a full-frame image data block for stitching together a complete full-frame image in a data stream, followed by complete data for N preset region of interest windows, where N is an integer greater than or equal to 2. Step 3, Data Marking: The high-speed buffer and data marking module located in the peripheral logic control section receives the digital pixel data stream from the ADC analog-to-digital converter array of the detector section, performs high-speed temporary storage, and obtains the row and column address information from the row control circuit and column control circuit through the synchronous control bus, and marks the row and column address information as the data header on each pixel data. Step 4, Data Filtering: The FIFO buffer array splits the received data into the full-frame data FIFO area or the corresponding window data FIFO area according to the row and column position information, and deletes redundant data caused by the overlap between the full-frame fragment and the window space of the region of interest during the splitting process. Step 5, Data framing and output: The FIFO framing array stitches together the full-frame image data blocks from different subframes in the full-frame data FIFO area into a complete full-frame image frame, and frames the data in each window data FIFO area into independent windowed image frames for output. Step 6: Repeat steps 2 to 5 until all n subframes have been processed, and output one full-frame image and n frames of N region of interest window images. Step 7: Repeat steps 1-6 to complete the acquisition and output of multi-frame full-frame and multi-region-of-interest windowed images.

8. The method for hybrid readout of full-frame and multi-region of interest according to claim 7, characterized in that, In step 2, the hybrid readout operation is performed based on either a full-frame hybrid readout mode or a window hybrid readout mode. In the full-frame hybrid readout mode, the complete full-frame image is read out in segments within multiple consecutive subframes, and all preset region of interest (ROI) window images are read out synchronously within each subframe. In the window hybrid readout mode, the full-frame image is considered to be stitched together from multiple specific windows, and a portion of the window image used to stitch the full-frame is read out within each subframe, while all preset ROI window images are read out synchronously.

9. The method for hybrid readout of full-frame and multi-region of interest according to claim 7, characterized in that, Before executing step 1 or step 2, the double-buffered register is configured via windowing to achieve atomic dynamic reconfiguration of the windowing parameters during the vertical blanking period before the start of the full-frame period. When the system needs to update the window configuration, the position, size, and number parameters of the new region of interest window are written into the spare register of the window configuration double buffer register. At the beginning boundary of each full-frame period, the contents of the spare register are loaded into the working register. The output of the working register directly drives the full-frame windowed hybrid readout module to generate the hybrid readout timing in the current frame period.

10. The method for hybrid readout of full-frame and multi-region of interest according to claim 7, characterized in that, In step 2, the hybrid read operation generates a row-conflict-free read address sequence through a row address arbitrator: Before the start of each subframe, the line address arbiter receives the current subframe full-frame data block line range and the line ranges of all preset region of interest windows from the full-frame windowed hybrid readout module at its input. The pre-computation module inside the line address arbiter generates a non-repeating, priority-ordered readout line address sequence through sorting and deduplication operations, and writes it into a lookup table. The line address arbiter outputs the readout line address sequence to the line strobe signal generation logic of the line control circuit through its output. The line control circuit scans sequentially within the subframe period.

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