A method of manufacturing a semiconductor device
By using oxide and nitride barrier layers combined with high-temperature annealing and low-temperature heat treatment in the fabrication of CMOS image sensors, the problem of white pixels caused by metal impurities was solved, improving imaging quality and yield, and enhancing contact link performance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- GEKKO SEMICON (SHANGHAI) CO LTD
- Filing Date
- 2024-12-25
- Publication Date
- 2026-06-30
AI Technical Summary
In the manufacturing process of existing CMOS image sensors, metal impurities cause an increase in the number of white pixels, affecting image quality and yield, which is difficult to improve further using existing methods.
In the manufacturing process of CMOS image sensors, a combination of oxide barrier layers and nitride barrier layers is used, along with high-temperature rapid annealing and low-temperature long-term heat treatment. This increases the monitoring of the interlayer dielectric layer thickness and deposits a SiCxNy layer after chemical mechanical polishing to form an interlayer barrier layer, thereby improving the capacitance delay and contact link performance of contact vias.
It effectively reduces metal impurity contamination, decreases the number of white pixels, improves the imaging quality and yield of CMOS image sensors, improves the capacitance delay problem of contact links, and enhances overall performance.
Smart Images
Figure CN122318338A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of semiconductor manufacturing, and specifically relates to a method for manufacturing a semiconductor device. Background Technology
[0002] Complementary metal-oxide-semiconductor (CMOS) image sensors, as device units that convert optical signals into digital electrical signals, are widely used in various emerging fields such as smartphones, tablets, automobiles, and medical devices. CIS converts incident photons into electrons through a pixel array. After one integration cycle, the collected electrons are converted into digital signals through analog and digital circuits and transmitted to the sensor's output terminal.
[0003] With the rapid development of information technology, the performance requirements for CIS devices are becoming increasingly stringent, especially in terms of sensitivity, resolution, dynamic range, and power consumption. White pixel count (WP), as one of the key parameters for evaluating CIS device performance, directly affects image quality. The WP problem is mainly caused by metal impurities contaminating the device during manufacturing. The presence of metal impurities not only affects the photoelectric conversion efficiency of pixels but may also lead to abnormal image signals. Although the industry has taken some measures to reduce metal impurities in silicon wafers, such as internal and external adsorption methods, these methods often cannot completely solve the WP problem. Currently, domestic development is mainly based on 55nm CMOS process technology, with industry yields generally above 90%. With technological advancements, once the yield reaches this high level, the room for further improvement significantly decreases and the difficulty increases greatly. However, continuing to improve the yield remains an important and unavoidable issue in the mass production stage. Research has found that the main reason for the inability to further improve the yield is the WP problem.
[0004] Therefore, there is an urgent need to develop a manufacturing method for CMOS image sensors to reduce metal impurity contamination and thus reduce white pixel density. Summary of the Invention
[0005] The purpose of this invention is to provide a method for manufacturing a CMOS image sensor to reduce metal impurity contamination, decrease white pixels, and improve yield.
[0006] To achieve the above objectives, the present invention provides a method for manufacturing a semiconductor device, comprising:
[0007] Step 1, providing a wafer, the wafer including a substrate and a gate layer formed above the substrate, the gate layer having a plurality of spaced isolation trenches; the substrate is ion implanted to form an active drain region;
[0008] Step 2: Deposit an oxide barrier layer on the surface of the isolation trench and above the gate layer in a self-aligned manner;
[0009] Step 3: Perform high-temperature rapid annealing on the wafer to activate the source and drain regions;
[0010] Step 4, low-temperature heat treatment: temperature is 550℃~650℃, treatment time is 1h~5h;
[0011] Step 5: Deposit at least one nitride barrier layer on the surface of the oxide barrier layer;
[0012] Step 6: Deposit an interlayer medium layer to fill the isolation trench;
[0013] Step 7: A contact via is formed above the gate layer by photolithography and etching processes to expose the gate layer;
[0014] Step 8: Fill the contact via with conductive metal to form an ohmic contact.
[0015] Optionally, the high-temperature rapid annealing temperature is 1000℃~1100℃ and the time is 1s~5s.
[0016] Optionally, in step 5, the nitride barrier layer comprises at least one silicon nitride layer.
[0017] Optionally, step 6 includes:
[0018] Step 6.1: Deposit a first interlayer dielectric layer, which at least partially fills the isolation trench and covers the nitride barrier layer above the gate layer;
[0019] Step 6.2: Deposit a second interlayer dielectric layer to fill the isolation trench and cover the first interlayer dielectric layer above the gate layer;
[0020] Step 6.3: Perform surface planarization treatment on the wafer by chemical mechanical polishing;
[0021] The density of the second interlayer dielectric layer is higher than that of the first interlayer dielectric layer.
[0022] Optionally, the method for depositing the first interlayer dielectric layer includes sub-atmospheric chemical vapor deposition, wherein the material of the first interlayer dielectric layer comprises silicon oxide.
[0023] Optionally, the method for depositing the second interlayer dielectric layer includes plasma-enhanced chemical vapor deposition, wherein the material of the second interlayer dielectric layer comprises undoped silicon glass (NSG).
[0024] Optionally, step 6 further includes: taking several positions radially from the center to the edge of the wafer as monitoring points, performing thickness monitoring at the monitoring points through a thickness monitoring module, obtaining the thickness ratio information T2 / T1 of the first interlayer dielectric layer T1 and the second interlayer dielectric layer T2, and outputting it to a photolithography process module; step 7 further includes: the photolithography process module searching its pre-stored database for etching deviations associated with the thickness ratio information T2 / T1; and then adjusting the critical dimension parameters of the photolithography process according to the etching deviations so that the critical dimensions of the subsequent etching process meet the process requirements; the pre-stored database stores datasets of etching deviations corresponding to different thickness ratio information T2 / T1; the etching deviation refers to the difference between the critical dimension of the photolithography process and the critical dimension of the etching process.
[0025] Optionally, the method for performing thickness monitoring includes:
[0026] Step 6.1.1: Upon completion of step 6.1, measure and record the thickness T1 of the first interlayer dielectric layer at the monitoring point. 0 ;
[0027] Step 6.2.1: Upon completion of step 6.2, measure and record the total thickness T of the interlayer medium at the monitoring point. 0 Obtain the thickness T2 of the second interlayer dielectric layer at the monitoring point. 0 T2 0 =T 0 -T1 0 ;
[0028] Step 6.3.1: Upon completion of step 6.3, measure and record the total thickness T of the interlayer dielectric layer at the monitoring point, and obtain the polishing thickness ΔT, where ΔT = T. 0 -T;
[0029] Step 6.4.1: Calculate the ratio of the current thickness of the first interlayer medium layer T1 to the current thickness of the second interlayer medium layer T2 corresponding to the monitoring point when step 6.3 is completed, and obtain the thickness ratio information T2 / T1.
[0030] Optionally, when T2 0 When ≥ΔT, T1=T1 0 T2 = T2 0 -ΔT; when T2 0 When <ΔT, T1 = T 0 -ΔT, T2=0.
[0031] Optionally, after step 6 and before step 7, the method further includes: depositing a capping layer on the wafer to repair surface defects caused by the chemical mechanical polishing, the capping layer covering the interlayer dielectric layer.
[0032] Optionally, the capping layer comprises a silicon oxide layer.
[0033] Optionally, at least one SiC layer is also deposited on the capping layer. x N y Layer, the SiC x N y The layer covers the cover layer, where x≥0, y>0.
[0034] Optionally, the SiC is formed x N y Layered methods include PECVD or ALD.
[0035] Optionally, prior to step 8, the method further includes forming at least one interlayer barrier layer on the sidewall of the contact via.
[0036] Optionally, the interlayer barrier layer comprises a titanium nitride layer.
[0037] Optionally, the method for depositing the titanium nitride layer includes:
[0038] Step 8.01: Introduce titanium source gas, which forms a titanium source precursor under thermal decomposition, and adsorbs and deposits a titanium source precursor layer at least on the sidewall and bottom of the contact via.
[0039] Step 8.02: Introduce hydrogen-containing gas and nitrogen-containing gas to generate hydrogen-containing plasma and nitrogen-containing plasma under the action of radio frequency source. The hydrogen-containing plasma and nitrogen-containing plasma react with the titanium source precursor layer to form titanium nitride layer.
[0040] Step 8.03: Repeat steps 8.01 and 8.02 N times in an alternating cycle until the thickness of the titanium nitride layer reaches the set thickness, where N is a positive integer.
[0041] Optionally, the titanium source gas is TDMAT.
[0042] Optionally, in step 8.01, the process temperature is 350℃~450℃.
[0043] Compared with the prior art, the technical solution of the present invention has at least the following beneficial effects:
[0044] This invention involves depositing an oxide barrier layer and then performing rapid high-temperature annealing followed by a low-temperature, long-term heat treatment step before depositing a nitride barrier layer. This reduces metal impurity contamination and decreases white pixel density.
[0045] Furthermore, the present invention adds a thickness monitoring module in the deposition of the interlayer dielectric layer step, which can feed back the thickness ratio information T2 / T1 of the first interlayer dielectric layer and the second interlayer dielectric layer T2 to the photolithography process module online. By adjusting the first feature size CD1 of the wafer region corresponding to different thickness ratios in the photolithography process module, the uniformity of the second feature size CD2 in the etching process module can be improved, and its abnormal jump points can be effectively improved.
[0046] Furthermore, the present invention deposits a SiN layer on the wafer surface after chemical mechanical polishing planarization, which can effectively block the diffusion of impurity elements such as O from the first interlayer dielectric layer (Harp) to the metal interface, thereby reducing the resistance of the circuit structure.
[0047] Furthermore, to reduce the contact resistance between the gate layer and the conductive metal filled in the contact via, before filling the conductive metal, the invention further includes forming at least one interlayer barrier layer (e.g., a titanium nitride layer) on the sidewall of the contact via. This invention improves the jump point problem of capacitance delay in the contact link by repeatedly depositing the titanium nitride layer, thereby increasing yield without introducing excessive additional costs. Attached Figure Description
[0048] Figure 1 This is a flowchart of a method for manufacturing a semiconductor device according to the present invention.
[0049] Figures 2-10 This is a partial cross-sectional schematic diagram of the wafer formed in each step of the manufacturing method of a semiconductor device according to the present invention.
[0050] Figure 11 This is a comparison chart of the WP performance test results of wafers prepared in Example 1 and Comparative Example 1 of the present invention, where a represents Example 1 and b represents Comparative Example 1.
[0051] Figure 12 This is a flowchart of an improved step 6 of the present invention.
[0052] Figure 13 The present invention is a SiC-formed x N y A schematic diagram of a partial cross-section of the wafer.
[0053] Figure 14 This is a partial cross-sectional schematic diagram of a wafer with an interlayer barrier layer formed according to the present invention.
[0054] Figure 15 This is a partial cross-sectional schematic diagram of the wafer formed in Embodiment 2 of the present invention.
[0055] Attached image labels:
[0056] Substrate 10
[0057] Gate oxide layer 20
[0058] Gate layer 30
[0059] Isolation trench 31
[0060] Gate wall 32
[0061] Oxide liner 33
[0062] Oxide barrier layer 41
[0063] Nitride barrier layer 42
[0064] First interlayer dielectric layer 51
[0065] Second interlayer dielectric layer 52
[0066] Covering layer 61
[0067] SiC x N y Floor 62
[0068] Mask layer 70
[0069] Amorphous carbon layer 71
[0070] SiON layer 72
[0071] Anti-reflective layer 73
[0072] Photoresist 74
[0073] Feature structure 75
[0074] First feature size CD1
[0075] Second feature size CD2
[0076] Contact via 80
[0077] Interlayer barrier layer 81
[0078] Conductive metal layer 82. Detailed Implementation
[0079] The technical solution of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0080] In the description of this invention, it should be noted that the terms "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.
[0081] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal communication between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.
[0082] The “isolation trench” mentioned in this article can be a trench or a gap, and its function is to fill the interlayer dielectric layer to electrically isolate active devices.
[0083] In the FSI (Fractional Solid Injection) process, the process segments affecting the silicon substrate are mainly located in the front and middle stages, including the active region process, the pixel ion implantation process, and the gate and silicide block process. These process segments have a particularly significant impact on silicide barrier (WP). The silicide block process is a critical step in CIS (Computer Integrated Systems) manufacturing. Commonly used barrier dielectric materials include oxide and silicon nitride (SiN), which can be fabricated using SACVD and PECVD processes, respectively. Although these processes have relatively low process temperatures (approximately 400°C) and short process times, they still cannot completely prevent the diffusion of metal impurities, leading to WP issues.
[0084] Therefore, this invention adds a low-temperature, long-term heat treatment step after forming the oxide barrier layer, and then forms the nitride barrier layer, which can reduce metal impurity contamination and significantly reduce white pixels.
[0085] like Figure 1 As shown, the method for manufacturing a semiconductor device provided by the present invention includes:
[0086] Step S1: A wafer is provided, the wafer including a substrate 10 and a gate layer 30 formed on the substrate, the gate layer 30 having a plurality of spaced isolation trenches 31; the substrate 10 is ion implanted to form an active drain region.
[0087] In this embodiment, the substrate 10 is a silicon substrate. In other embodiments, the substrate 10 may also include other compound semiconductors, such as silicon carbide, gallium arsenide, indium arsenide, or indium phosphide.
[0088] See Figure 2 The wafer has undergone processing operations, including epitaxial growth of a gate oxide layer 20 on the substrate 10, formation of the gate structure, and source / drain ion implantation. The gate structure on the wafer is formed by the isolation trench 31 spacing the gate layer 30. The gate structure also includes a gate wall 32, which can be a SiN layer. This can be achieved by conformally depositing a SiN layer on the wafer surface, then selectively etching away the SiN layer on the flat surface, retaining the sidewalls, resulting in a SiN layer that only covers the sidewalls of the gate layer 30. In some embodiments, to avoid potential damage to the gate layer 30 during etching to form the gate wall 32, an oxide liner 33 is conformally deposited on the wafer surface before forming the gate wall 32.
[0089] Step S2, deposit an oxide barrier layer 41 on the surface of the isolation trench 31 and above the gate layer 30.
[0090] The oxide barrier layer 41 serves as a silicide block, covering areas where metal silicide formation is not desired, preventing silicide formation in these areas during subsequent salicide processes. The oxide barrier layer 41 can be silicon oxide. The oxide barrier layer 41 can be deposited using a conformal deposition method. The conformal deposition method includes at least one of sub-atmospheric chemical vapor deposition (SACVD), chemical vapor deposition (CVD), or plasma-enhanced chemical vapor deposition (PECVD).
[0091] See Figure 3 The oxide barrier layer 41 uniformly covers the surface of the isolation trench 31 and the gate layer 30. In this example, a silicon oxide thin film is deposited using SACVD, which can be prepared using silane (SiH4) and oxygen (O2) as reactants. The process temperature is approximately 300℃ to 500℃, the pressure is 100mTorr to 500mTorr, and the time to form a silicon oxide film with a thickness of nm is approximately 5 min to 30 min. In this example, since both the oxide barrier layer 41 and the oxide layer pad 33 are silicon oxide thin films, they are marked with the same yellow color. There are two layers of silicon oxide on the gate layer 30. The silicon oxide adjacent to the gate layer 30 is the oxide layer pad 33, and the oxide barrier layer 41 is on top of it. The right side of the gate wall 32 is the oxide layer pad 33, and the left side is the oxide barrier layer 41.
[0092] Step S3: Perform high-temperature rapid annealing on the wafer to activate the source and drain regions.
[0093] In some embodiments, a rapid thermal annealing (RTA) device is used to perform rapid thermal annealing of the wafer at a temperature range of 1000℃-1100℃ for 1s-5s under normal pressure. This can effectively activate the impurity atoms in the source and drain regions of the silicon wafer, laying a good foundation for the subsequent performance optimization of semiconductor devices.
[0094] Step S4, low-temperature heat treatment: temperature is 550℃~650℃, treatment time is 1h~5h.
[0095] This invention discovers that by feeding a wafer that has undergone high-temperature rapid annealing into a furnace tube for low-temperature long-term heat treatment, followed by the formation of a nitride barrier layer (e.g., a SiN layer), white pixels can be significantly reduced. The "low-temperature long-term heat treatment" mentioned herein refers to the temperature and time relative to the high-temperature rapid annealing step.
[0096] Step S5, deposit at least one nitride barrier layer 42 on the surface of the oxide barrier layer 41, such as Figure 4 As shown.
[0097] In some embodiments, the nitride barrier layer 42 comprises at least one silicon nitride layer. As an example, a SiN layer is formed using PECVD, with silane (SiH4) and ammonia (NH3) as raw material gases, undergoing a chemical reaction in a plasma environment to generate a silicon nitride (SiN) film. Silane and ammonia are typically mixed and introduced into the reaction chamber at a specific flow rate ratio, for example, silane flow rate of 10 sccm-50 sccm and ammonia flow rate of 50 sccm-200 sccm. This flow rate ratio can be adjusted according to the desired characteristics of the SiN film (such as nitrogen-silicon ratio, film density, etc.). The pressure is 4 Torr-7 Torr. The deposition time depends on the desired SiN film thickness. If a SiN film thickness of 50 nm-200 nm is desired, the deposition time may be 2 min-10 min. For example, when the silane flow rate is 30 sccm, the ammonia flow rate is 60 sccm, the pressure is 4-7 Torr, and the temperature is 470°C, it may take about 2 minutes to deposit a SiN film about 200 nanometers thick.
[0098] The self-aligned silicide block of the present invention comprises an oxide barrier layer 41 (e.g., oxide) and a nitride barrier layer 42 (e.g., SiN) as a dielectric isolation layer for blocking. Oxide is commonly fabricated using SACVD, and SiN is commonly fabricated using PECVD. However, both SACVD and PECVD processes have a process temperature of approximately 400°C and a relatively short process time. The present invention introduces an additional, longer heat treatment step between the formation of oxide (step S2) and the formation of SiN (step S5), resulting in a significant reduction in white pixel density and an improvement in white pixel performance of approximately 30%.
[0099] Step S6: Deposit an interlayer medium layer to fill the isolation trench.
[0100] The preceding process steps (such as photolithography and etching) can cause unevenness on the wafer surface, resulting in features like steps and trenches. Interlayer dielectric layers can fill these uneven areas (isolation trenches in this case) using appropriate deposition and smoothing techniques (such as chemical mechanical polishing, CMP), achieving wafer surface planarization. This is crucial for subsequent photolithography processes, as photolithography requires a relatively flat surface to ensure the accuracy of pattern transfer.
[0101] The interlayer dielectric layer can also serve as an electrical isolation layer, for example, to isolate different conductive layers and prevent short circuits between them.
[0102] To achieve a better gap-filling effect, a high aspect ratio process (HARP) is typically used to fill the gaps, forming an HARP interlayer dielectric layer (ILD Harp). However, ILD Harp has a relatively loose texture. When the isolation trench is filled solely with Harp, numerous surface defects and high roughness occur during subsequent mechanical polishing steps, which is detrimental to device performance. Therefore, this invention fills the trench in stages (first stage + second stage). In the first stage, a first interlayer dielectric layer is filled, which has good filling performance. Then, in the second stage, a second interlayer dielectric layer is used to completely fill the isolation trench, requiring good machinability. The density of the second interlayer dielectric layer is higher than that of the first interlayer dielectric layer. Specifically, the step of filling the isolation trench 31 includes:
[0103] Step S6.1: Deposit a first interlayer dielectric layer 51, at least partially filling the isolation trench 30 and covering the nitride barrier layer 42 above the gate layer, as shown. Figure 5 As shown.
[0104] The material of the first interlayer dielectric layer of the present invention comprises ILD Harp. The method for depositing the first interlayer dielectric layer comprises subatmospheric chemical vapor deposition (SACVD), using silicon sources (such as silane SiH4) and some oxygen-containing compounds (such as oxygen O2 or nitrous oxide N2O) as reactant gases. Because the deposit formed in the isolation trench is more difficult to remove by an exhaust pump than the flat surface at the top of the trench, the thickness of the ILD Harp deposited in the isolation trench is higher than the thickness of the ILD Harp on its platform surface, such as... Figure 5 As shown.
[0105] Step S6.2: Deposit the second interlayer dielectric layer 52, fill the isolation trench 30, and cover the first interlayer dielectric layer 51 above the gate layer, as shown. Figure 6 As shown.
[0106] The material of the second interlayer dielectric layer 52 comprises undoped silicon glass (NSG). Because NSG is harder than ILDHarp but has poorer via-filling properties, it can be used as a CMP mask layer to achieve better wafer uniformity. The method for depositing the second interlayer dielectric layer 52 includes plasma-enhanced chemical vapor deposition (PECVD).
[0107] Step S6.3 involves surface planarization of the wafer via chemical mechanical polishing (CMP), such as... Figure 7 As shown.
[0108] The purpose of chemical mechanical polishing (CMP) is to ensure the flatness of the entire wafer. CMP can remove excess interlayer dielectric layers from the wafer surface. Depending on process requirements, the second interlayer dielectric layer 52 can be completely or partially removed, resulting in a flat wafer surface with low roughness, facilitating subsequent epitaxial layer deposition. Alternatively, after completely removing the second interlayer dielectric layer 52, further polishing may be performed to remove part of the first interlayer dielectric layer 51. This invention does not limit this process; the degree of polishing is sufficient to achieve the desired flatness and roughness of the wafer surface according to the process settings.
[0109] In some embodiments, after step S6, the process further includes depositing a capping layer 61 on the wafer to repair surface defects (e.g., scratches) caused by the chemical mechanical polishing, wherein the capping layer 61 covers the interlayer dielectric layer, such as... Figure 8 As shown. The capping layer 61 comprises a silicon oxide layer.
[0110] Step S7: A contact via is formed above the gate layer by photolithography and etching processes to expose the gate layer.
[0111] The photolithography process includes: forming a mask layer 70 on the cover layer 61 (if any) of the wafer, the mask layer 70 comprising, from bottom to top, an amorphous carbon layer 71, a SiON layer 72, an anti-reflective layer 73, and a photoresist (PR) 74; and using the photomask, exposing and developing to obtain a photoresist pattern, which includes a feature structure 75 having a first feature size CD1, such as... Figure 9 As shown.
[0112] The etching process includes: using the mask layer 70 as a mask, transferring the feature structure 75 of the photoresist pattern downward toward the substrate until the gate layer 30 is exposed, forming a contact via 80, the contact via 80 having a second feature size CD2, such as... Figure 10 As shown.
[0113] Step S8: Fill the contact via with conductive metal to form an ohmic contact.
[0114] Example 1
[0115] A wafer is provided, the wafer comprising a substrate and a gate layer formed above the substrate, the gate layer having a plurality of spaced isolation trenches; the substrate is ion implanted to form an active drain region. Using the SCVD method with SiH4 and O2 as reactants, at 400°C, a pressure of 200 mTorr, and a reaction time of 20 min, a silicon monoxide layer is self-aligned and deposited on the surface of the isolation trenches and above the gate layer. The wafer is then subjected to rapid thermal annealing (RTA) at 900°C under normal pressure for 10 s. Then, the wafer undergoes low-temperature heat treatment at 580°C for 80 min. Finally, using PECVD, a SiN layer is deposited on the surface of the silicon monoxide layer by introducing SiH4 at a flow rate of 20 sccm, NH3 at a flow rate of 50 sccm, and O2 at a flow rate of 30 sccm at a process temperature of 400°C. An interlayer dielectric layer is deposited using conventional methods to fill the isolation trench; then, contact vias are formed above the gate layer via photolithography and etching processes to expose the gate layer. Conductive metal is filled into the contact vias to form ohmic contacts.
[0116] The wafer processed in Example 1 was tested using white pixels, as shown below. Figure 11 As shown in a, there are fewer white pixels.
[0117] Comparative Example 1
[0118] The difference from Example 1 is that no low-temperature heat treatment step was performed; that is, the SiN layer was directly deposited after high-temperature rapid annealing.
[0119] The wafer processed in Comparative Example 1 was tested using white pixels, as shown below. Figure 11 As shown in b, the number of white pixels P70 and P90 is significantly increased compared to Example 1. Figure 11 In this context, P stands for Probability Plot, used to describe the numerical distribution. Generally, it represents a statistical analysis of values from smallest to largest. For example, P70 or P90 represent the WP values corresponding to 70% or 90%, respectively. It can be seen that the low-temperature heat treatment added in Example 1 can effectively reduce white pixels, improving white pixel performance by approximately 30%.
[0120] Practice has shown that the main failure bins of CMOS devices are Bin12 (pixel bus) and Bin63 (static random access memory, SRAM). The pixel bus connects the pixel cells to peripheral circuits for data transmission, while the SRAM serves as a temporary register storing signals from the pixels. Both play a crucial role in device speed and the capacitance delay (RC) of contacts / vias in the back-end-of-line (BEOL) process. Extensive experiments were conducted to improve Bin12 and Bin63, including: high melting point (HM) and low deposition rate of polysilicon (Poly HM), no-damage cleaning (NDC) backside cleaning, and single batch run removal of pad oxide. However, failure dies and abnormally high points in contact chain performance still exist at the edge of the wafers in Bin12 / 63, indicating that there must be other unidentified influencing factors.
[0121] As process dimensions continue to shrink, the process window becomes increasingly narrow. If fluctuations in abnormal online data on the production line cannot be monitored or adjusted, it will significantly impact products, especially those in mass production. Most process lines employ a data feedback mechanism between two modules, such as data interaction between the lithography module (containing the ETCH AEI CD dataset) and the etching module (containing the LITHO ADI CD dataset), which is relatively crude and lagging.
[0122] This invention unexpectedly discovered a correlation between CT chain RC and Bin12 / 63, suggesting that improving the performance of the contact chain may indirectly improve Bin12 / 63. Research revealed that the NSG to Harp ratio varies within the wafer due to differences in thin film (TF) deposition and CMP polishing uniformity, leading to variations in CT depth or CT etching OE amount. To address this, this invention adds a thickness monitoring module, enabling data exchange between the three process modules (in this example, the thickness monitoring module / lithography module / etching module) to better adjust online stability and improve yield. The thickness monitoring module detects the Harp / NSG ratio in different regions within the wafer, allowing for better online monitoring and process adjustment, resulting in better online data uniformity within the wafer. This invention automatically feeds back the NSG / Harp ratio information to the lithography module. By adjusting the first feature size CD1 of the wafer region corresponding to different NSG / Harp ratios in the lithography module, the uniformity of the second feature size CD2 in the etching module can be improved, effectively reducing abnormal jump points.
[0123] like Figure 12 As shown, in some embodiments, step S6 further includes: taking several positions radially from the center to the edge of the wafer as monitoring points, performing thickness monitoring at the monitoring points using a thickness monitoring module, obtaining the thickness ratio information T2 / T1 of the first interlayer dielectric layer and the second interlayer dielectric layer T2, and outputting it to a photolithography process module. As an example, the method for performing thickness monitoring includes: step S6.1.1, upon completion of step S6.1, measuring and recording the thickness T1 of the first interlayer dielectric layer at the monitoring point. 0 Step S6.2.1: Upon completion of step S6.2, measure and record the total thickness T of the interlayer medium at the monitoring point. 0 Obtain the thickness T2 of the second interlayer dielectric layer at the monitoring point. 0 T2 0 =T 0 -T1 0 Step S6.3.1: Upon completion of step S6.3, measure and record the total thickness T of the interlayer dielectric layer at the monitoring point, and obtain the polishing thickness ΔT, where ΔT = T. 0 -T; Step S6.4.1, calculate the ratio of the current thickness of the first interlayer dielectric layer T1 to the current thickness of the second interlayer dielectric layer T2 corresponding to the monitoring point when step S6.3 is completed, to obtain the thickness ratio information T2 / T1. When T2 0 When ≥ΔT, T1=T1 0 T2 = T2 0 -ΔT; when T2 0 When <ΔT, T1 = T0 -ΔT, T2 = 0. Step S7 further includes: the photolithography process module searching its pre-stored database for etching deviations associated with the thickness ratio information T2 / T1; and then adjusting the critical dimension parameters (e.g., CD1) of subsequent photolithography processes according to the etching deviations, so that the critical dimensions (e.g., CD2) of subsequent etching processes meet the process requirements; the pre-stored database stores datasets of etching deviations corresponding to different thickness ratio information T2 / T1; the etching deviation refers to the difference between the critical dimension of the photolithography process and the critical dimension of the etching process.
[0124] This invention also found that when the interlayer dielectric layer filling the isolation trench contains Harp, due to the relatively loose texture of Harp, even with optimized process parameters, it is still difficult to ensure a void-free environment. Impurities such as water and gas remaining in the voids, under the influence of the BSI process heat treatment, cause oxygen elements to diffuse upwards, resulting in abnormal O element distribution, which in turn affects the conductivity of the contact vias. Therefore, this invention also deposits at least one SiC layer on the capping layer 61. x N y Layer 62, the SiC x N y Layer 62 covers the covering layer 61, where x≥0, y>0, as shown below. Figure 13 As shown. The SiC is formed. x N y The method for layer 62 includes PECVD or ALD. In some embodiments, the SiC x N y Layer 62 is a SiN layer. The SiC added in this invention... x N y The layer can effectively block the diffusion of impurity elements such as O from the Harp to the metal interface, resulting in a high-resistivity circuit structure.
[0125] To further reduce the contact resistance between the gate layer and the conductive metal filled in the contact via, before filling the contact via in step S8, the method further includes: forming at least one inter-hole barrier layer (ILB) 81 on the sidewall of the contact via, such as... Figure 14 As shown. As an example, the interlayer barrier layer 81 comprises a titanium nitride layer.
[0126] The method for depositing the titanium nitride layer includes:
[0127] Step 8.01: Introduce titanium source gas, which forms a titanium source precursor under thermal decomposition, and deposits a titanium source precursor layer at least on the sidewalls and bottom of the contact via; the titanium source gas is TDMAT (TetrakisDi-MethyI Amino Titanium), with the molecular formula Ti[N(CH3)2]4. The process temperature is 350℃~450℃.
[0128] Step 8.02: Introduce hydrogen-containing gas and nitrogen-containing gas to generate hydrogen-containing plasma and nitrogen-containing plasma under the action of radio frequency source. The hydrogen-containing plasma and nitrogen-containing plasma react with the titanium source precursor layer to form titanium nitride layer.
[0129] Step 8.03: Repeat steps 8.01 and 8.02 N times in an alternating cycle until the thickness of the titanium nitride layer reaches the set thickness, where N is a positive integer.
[0130] Example 2
[0131] The wafer to be filled with contact vias is placed in a processing chamber. TDMAT is introduced into the processing chamber as a titanium source gas. At a temperature of 405°C, TDMAT thermally decomposes to form a titanium source precursor. H2 / N2 is introduced for the first time, and the radio frequency source is turned on. After plasma treatment for 45 seconds, 25 Å TiN is formed. The above steps are repeated twice more to finally form 75 Å TiN. Figure 15 As shown, a conductive metal layer 82 is formed by filling the surface of the interlayer barrier layer 81 in the contact via 80 with a conductive metal (e.g., W) for electrical connection. Testing showed that the 75Å TiN layer prepared in this embodiment exhibits better contact with the conductive metal layer 82 compared to existing one-time prepared 75Å TiN layers, significantly reducing abnormal jump points and greatly improving product yield. This embodiment does not involve particularly complex process changes; it only improves the jump point problem in CT chain RC by changing the processing time and cycle number each time, thereby increasing yield without introducing excessive additional costs. This method is applicable to all processes using TIN as a barrier layer.
[0132] In summary, this invention, after forming an oxide barrier layer and undergoing rapid high-temperature annealing, adds a low-temperature, long-term heat treatment step to form a nitride barrier layer, which can effectively reduce metal impurity contamination, reduce white pixels, and improve CMOS device performance.
[0133] Although the present invention has been described in detail through the preferred embodiments above, it should be understood that the above description should not be considered as a limitation of the present invention. Various modifications and substitutions to the present invention will be apparent to those skilled in the art after reading the above description. Therefore, the scope of protection of the present invention should be defined by the appended claims.
Claims
1. A method for manufacturing a semiconductor device, characterized in that, Include: Step 1, providing a wafer, the wafer including a substrate and a gate layer formed above the substrate, the gate layer having a plurality of spaced isolation trenches; the substrate is ion implanted to form an active drain region; Step 2: Deposit an oxide barrier layer on the surface of the isolation trench and above the gate layer; Step 3: Perform high-temperature rapid annealing on the wafer to activate the source and drain regions; Step 4, low-temperature heat treatment: temperature is 550℃~650℃, treatment time is 1h~5h; Step 5: Deposit at least one nitride barrier layer on the surface of the oxide barrier layer; Step 6: Deposit an interlayer medium layer to fill the isolation trench; Step 7: A contact via is formed above the gate layer by photolithography and etching processes to expose the gate layer; Step 8: Fill the contact via with conductive metal to form an ohmic contact.
2. The method for manufacturing a semiconductor device as described in claim 1, characterized in that, The high-temperature rapid annealing temperature is 1000℃~1100℃, and the time is 1s~5s.
3. The method for manufacturing a semiconductor device as described in claim 1, characterized in that, In step 5, the nitride barrier layer comprises at least one silicon nitride layer.
4. The method for manufacturing a semiconductor device as described in claim 1, characterized in that, Step 6 includes: Step 6.1: Deposit a first interlayer dielectric layer, which at least partially fills the isolation trench and covers the nitride barrier layer above the gate layer; Step 6.2: Deposit a second interlayer dielectric layer to fill the isolation trench and cover the first interlayer dielectric layer above the gate layer; Step 6.3: Perform surface planarization treatment on the wafer by chemical mechanical polishing; The density of the second interlayer dielectric layer is higher than that of the first interlayer dielectric layer.
5. The method for manufacturing a semiconductor device as described in claim 4, characterized in that, The method for depositing the first interlayer dielectric layer includes sub-atmospheric chemical vapor deposition, wherein the material of the first interlayer dielectric layer includes silicon oxide.
6. The method for manufacturing a semiconductor device as described in claim 4, characterized in that, The method for depositing the second interlayer dielectric layer includes plasma-enhanced chemical vapor deposition, wherein the material of the second interlayer dielectric layer comprises undoped silicon glass.
7. The method for manufacturing a semiconductor device as described in claim 4, characterized in that, Step 6 further includes: taking several positions radially from the center to the edge on the wafer as monitoring points, performing thickness monitoring at the monitoring points through a thickness monitoring module, obtaining the thickness ratio information T2 / T1 of the first interlayer dielectric layer and the second interlayer dielectric layer T2, and outputting it to a photolithography process module. Step 7 further includes: the photolithography process module searching its pre-stored database for etching deviations associated with the thickness ratio information T2 / T1; and then adjusting the critical dimension parameters of the photolithography process according to the etching deviations so that the critical dimensions of the subsequent etching process meet the process requirements; the pre-stored database stores datasets of etching deviations corresponding to different thickness ratio information T2 / T1; the etching deviation refers to the difference between the critical dimension of the photolithography process and the critical dimension of the etching process.
8. The method for manufacturing a semiconductor device as described in claim 7, characterized in that, The method for performing thickness monitoring includes: Step 6.1.1, at the completion of said step 6.1, measuring and recording the thickness T1 of the first interlayer dielectric layer at the monitoring point 0 ; Step 6.2.1, at the completion of said step 6.2, measure and record the total thickness T of the interlayer medium layer at the monitoring point 0 , obtaining the thickness T2 of the second interlayer medium layer at the monitoring point 0 0 = T 0 - T1 0 ; Step 6.3.1: Upon completion of step 6.3, measure and record the total thickness T of the interlayer dielectric layer at the monitoring point, and obtain the polishing thickness ΔT, where ΔT = T. 0 -T; Step 6.4.1: Calculate the ratio of the current thickness of the first interlayer medium layer T1 to the current thickness of the second interlayer medium layer T2 corresponding to the monitoring point when step 6.3 is completed, and obtain the thickness ratio information T2 / T1.
9. The method for manufacturing a semiconductor device as described in claim 8, characterized in that, When T2 0 When ≥ΔT, T1=T1 0 T2 = T2 0 -ΔT; when T2 0 When <ΔT, T1 = T 0 -ΔT, T2=0.
10. The method for manufacturing a semiconductor device as claimed in claim 1, characterized in that, After step 6 and before step 7, the process further includes: depositing a capping layer on the wafer to repair surface defects caused by the chemical mechanical polishing, the capping layer covering the interlayer dielectric layer.
11. The method for manufacturing a semiconductor device as described in claim 10, characterized in that, The capping layer comprises a silicon oxide layer.
12. The method for manufacturing a semiconductor device as described in claim 10, characterized in that, At least one SiC layer is also deposited on the capping layer. x N y Layer, the SiC x N y The layer covers the cover layer, where x≥0, y>0.
13. The method for manufacturing a semiconductor device as described in claim 12, characterized in that, Forming the SiC x N y Layered methods include PECVD or ALD.
14. A method for manufacturing a semiconductor device according to any one of claims 1-13, characterized in that, Prior to step 8, the method further includes: forming at least one interlayer barrier layer on the sidewall of the contact via.
15. The method for manufacturing a semiconductor device as described in claim 14, characterized in that, The interlayer barrier layer comprises a titanium nitride layer.
16. The method for manufacturing a semiconductor device as described in claim 15, characterized in that, The method for depositing the titanium nitride layer includes: Step 8.01: Introduce titanium source gas, which forms a titanium source precursor under thermal decomposition, and adsorbs and deposits a titanium source precursor layer at least on the sidewall and bottom of the contact via. Step 8.02: Introduce hydrogen-containing gas and nitrogen-containing gas to generate hydrogen-containing plasma and nitrogen-containing plasma under the action of radio frequency source. The hydrogen-containing plasma and nitrogen-containing plasma react with the titanium source precursor layer to form titanium nitride layer. Step 8.03: Repeat steps 8.01 and 8.02 N times in an alternating cycle until the thickness of the titanium nitride layer reaches the set thickness, where N is a positive integer.
17. The method for manufacturing a semiconductor device as described in claim 16, characterized in that, The titanium source gas is TDMAT.
18. The method for manufacturing a semiconductor device as described in claim 16, characterized in that, In step 8.01, the process temperature is 350℃~450℃.