High-resolution time-programmable burst pulse generator based on embedded processor

Abstract

This invention discloses a high-resolution timing-programmable burst pulse generator based on an embedded processor, which realizes multi-channel, high-precision, and fully programmable burst pulse output for optical module testing. It combines the advantages of low cost, high integration, low power consumption, and high timing accuracy. It includes an embedded processor module, a host computer configuration module, a USB-IIC bridge communication module, and an embedded main control module. The embedded processor module adopts the GD32E5 series chip and has a built-in SHRTIM timer with a DMA burst transfer unit and multiple pulse output channels. The host computer configuration module establishes data interaction with the embedded main control module through the USB-IIC bridge communication module to provide a visual configuration interface and support users to customize the configuration parameters of each pulse signal. The embedded main control module receives and parses the configuration parameters, stores them in the FLASH parameter storage area, and completes the hardware configuration. The system waits for the rising edge of the external AUX signal to trigger the signal throughout the process. After triggering, it synchronously outputs 6 high-precision pulse signals.

Description

Technical Field

[0001] This invention belongs to the field of high-precision timing pulse generation technology, specifically relating to a high-resolution timing programmable burst pulse generator based on an embedded processor, which can be used for ONU burst transmission testing, OLT burst reception testing, and burst optical signal intensity detection in PON testing. Background Technology

[0002] In PON optical communication systems, a multi-ONU time-division burst uplink transmission mechanism is adopted. The OLT optical module needs to meet the burst reception performance. Its burst response timing, burst reception sensitivity, RSSI power monitoring accuracy, etc. are the core indicators for measuring the performance of the optical module. The corresponding testing work puts forward extremely high requirements for pulse timing accuracy, multi-channel timing matching degree, pulse programmability flexibility, etc.

[0003] Currently, high-precision burst pulse generators in the industry are generally based on FPGA hardware architecture. However, this approach has several inherent drawbacks: First, FPGA chips are expensive, peripheral circuits are complex, and dedicated high-speed clocks, configuration chips, and regulated power supplies are required, resulting in a bloated hardware architecture that hinders miniaturization and mass production. Second, FPGAs rely on Verilog and VHDL hardware description languages ​​for development. Modifications to timing logic require recompilation, programming, and downloading, making online dynamic parameter configuration impossible. This leads to long debugging cycles, high maintenance costs, and extremely poor programmability. Third, a pure FPGA architecture can only generate pulse timing data and requires an external embedded processor to handle human-machine interaction, data communication, parameter storage, and other business logic, resulting in low system integration and structural redundancy. Fourth, FPGAs have high power consumption and generate a lot of heat, making them unsuitable for portable and integrated optical module testing equipment applications.

[0004] Meanwhile, the timing resolution of existing conventional embedded timer pulse generation schemes is generally insufficient, making it impossible to achieve high-precision timing control below the nanosecond level. Furthermore, it is difficult to output irregular, numerous, and ultra-short-interval nanosecond-level burst pulses, which cannot accurately simulate the burst working timing of real PON systems. This results in low optical module testing accuracy and incomplete test scenario coverage, failing to meet the refined testing requirements of high-end optical modules.

[0005] In summary, existing pulse generation equipment suffers from technical pain points such as insufficient accuracy, high cost, poor flexibility, low integration, and cumbersome debugging and maintenance. There is an urgent need for a low-cost, high-resolution, multi-channel programmable pulse generation solution that supports irregular burst pulse output. Summary of the Invention

[0006] The main objective of this invention is to provide a high-resolution timing programmable burst pulse generator based on an embedded processor, which solves the technical problems of high cost, poor flexibility, and low integration of traditional FPGA solutions, as well as insufficient timing accuracy and inability to output irregular nanosecond-level burst pulses in conventional embedded solutions. It realizes multi-channel, high-precision, fully programmable burst pulse output for optical module testing, and has the advantages of low cost, high integration, low power consumption and high timing accuracy.

[0007] To achieve the above objectives, the solution of the present invention is: A high-resolution timing programmable burst pulse generator based on an embedded processor includes an embedded processor module, a host computer configuration module, a USB-IIC bridge communication module, and an embedded main control module. The embedded processor module uses a GD32E5 series chip and integrates an ultra-high precision SHRTIM timer. The SHRTIM timer, after being multiplied by 64, can reach a maximum operating frequency of 11.5GHz and a timing resolution as low as 90ps to meet the requirements of high-precision timing control below the nanosecond level. Furthermore, the SHRTIM timer has a DMA burst transfer unit and multiple pulse output channels. The host computer configuration module communicates via the USB-IIC bridge communication module. The USB-IIC bridging communication module establishes data interaction with the embedded main control module to provide a visual configuration interface, supporting user-defined configuration parameters for each pulse signal. These configuration parameters include pulse width, relative timing position, output polarity, and pulse count. After being packaged using a customized data protocol, the data is transmitted to the embedded main control module via the USB-IIC bridging communication module. The embedded main control module receives and parses the configuration parameters, stores them in its internal FLASH parameter storage area, and completes the hardware configuration. The system waits for the rising edge of the external AUX signal to trigger the signal, and upon triggering, synchronously outputs six high-precision pulse signals.

[0008] This invention features six independent pulse output channels, including two Ben signal channels, two RSSI_Trig signal channels, and two Reset signal channels. The two Ben signal channels and two RSSI_Trig signal channels are single-pulse output channels, with each channel's pulse width, relative timing position, and output polarity independently programmable. The two Reset signal channels are multi-pulse burst output channels, maintaining consistent pulse quantity, pulse width, and relative timing position parameters for synchronized output timing. Their output polarity is independently programmable, allowing for the output of irregular nanosecond-level burst pulse sequences where the pulse quantity, pulse width, and relative timing position are all arbitrarily programmable. "Irregular" means that there is no fixed multiple relationship between the three.

[0009] Preferably, the embedded main control module has built-in parameter preprocessing logic. After the system powers on or receives parameter updates from the host computer, it automatically completes parameter verification and timing sorting to check whether multiple pulses output by the Reset signal channel conflict and rearrange them according to the delay time from smallest to largest. It adopts a differentiated timing processing mechanism: first, it verifies the number of Reset signal pulses and the pulse period parameters of each channel to determine whether they exceed the single-cycle output threshold of the SHRTIM timer; for different parameter over-limit scenarios, a differentiated timing processing mechanism is adopted, specifically: when all parameters are within limits (exceeding the parameter threshold), the SHRTIM timer is directly configured. The IM timer completes single-cycle pulse output, configuring the high and low level timing trigger points of the two Ben and two RSSI_Trig signals to four independent output channels, and configuring up to four sets of Reset pulse timing trigger points to two complementary Reset output channels. When the Ben and RSSI_Trig signal periods exceed the limit, the waveform segmented output is achieved through the interruption of the SHRTIM timer to ensure the integrity and accuracy of the single pulse timing. When the number of Reset signal pulses or the period exceeds the limit, the memory waveform table timing segmentation algorithm is activated in conjunction with the DMA burst transfer unit to complete irregular burst pulse output.

[0010] Preferably, the memory waveform table timing segmentation algorithm allocates a dedicated timing parameter storage area in the system RAM to optimally segment and arrange irregular Reset multi-pulse sequences. Under the premise of satisfying the single-cycle output limit of the SHRTIM timer, it maximizes the filling pulse switching timing points, reserves redundant time for DMA transfer processing, and balances waveform output integrity and system stability.

[0011] Preferably, each channel of the SHRTIM timer is equipped with an independent offset counting unit, which can realize pulse edge delay offset calibration. Its CMP, PER, and DELAY timing registers are all equipped with a hardware double-buffered shadow register mechanism, which is divided into an immediate register and a shadow register. The software writes the timing parameters of the next pulse to the immediate register in real time and temporarily stores them in the shadow register without interfering with the current waveform output. The "timer period counter reset to zero" is configured as the update trigger event. After the trigger, the parameters of the shadow register are batch reloaded to the immediate register to realize seamless switching of pulse timing parameters and completely eliminate timing tearing, glitches, and jump problems.

[0012] Preferably, the DMA burst transfer unit is linked with the SHRTIM timer to support batch automatic updates of multiple timing registers. During the current pulse deformation output process, the system uses the DMA burst transfer unit to batch transfer the CMP and PER timing parameters of the next pulse from the memory waveform table to the shadow register of the SHRTIM timer. After the current pulse output is completed, the hardware automatically triggers the reload parameters and seamlessly switches to the next irregular pulse timing. There is no CPU point-by-point intervention throughout the process. Only the pulse sequence parameters need to be sent in advance to achieve fully automatic and closed-loop hardware completion of burst pulse sequence output.

[0013] Preferably, the DMA burst transmission unit triggers an interrupt after the system completes the output of the entire burst pulse sequence according to the preset total transmission length. In the interrupt service function, the timing parameters of the first cycle of the memory waveform table are automatically reloaded, the system is reset to the ready-to-trigger state, and waits for the next AUX rising edge trigger signal to realize cyclic pulse output.

[0014] Preferably, the Ben signal channel is used to control the optical module to switch burst reception modes, simulating the burst uplink timing of multiple ONUs in a PON system; the Reset signal channel is used to reset the optical module's receiving channel during burst intervals, eliminating DC offset and gain memory effects; the RSSI_Trig signal channel is used to locate the effective power range of the burst optical signal, trigger optical power sampling, and achieve accurate testing of the burst performance of the optical module.

[0015] After adopting the above technical solution, the present invention has the following technical effects: (1) It breaks through the precision bottleneck of traditional embedded solutions and uses the SHRTIM timer built into the GD32E5 series chip to achieve a timing resolution of up to 90ps, which meets the requirements of PON optical module testing for ultra-high timing accuracy and is suitable for the refined testing scenarios of high-end optical modules. (2) It adopts a differentiated timing processing mechanism to support the segmented output of out-of-limit parameters. Combined with the memory waveform table timing segmentation algorithm and DMA hardware automatic transfer, it can realize the output of any number of irregular nanosecond-level burst pulses and adapt to the timing requirements of various test scenarios. (3) Based on the mature embedded processor single-chip architecture, there is no need to connect expensive FPGA chips and supporting peripheral circuits. Compared with the traditional FPGA solution, the hardware cost is greatly reduced and the overall system architecture is simplified. (4) The timing parameters can be dynamically configured online through the host computer. Modifying the parameters does not require recompiling and burning the hardware logic. The software is highly programmable, which greatly shortens the debugging cycle, reduces maintenance costs, and is far more flexible than traditional FPGA solutions. (5) All functions are integrated into a single embedded processor, without the need for an additional external main control chip to process business logic. The system has a high degree of integration, and the power consumption of the chip itself is much lower than that of the FPGA. It can be adapted to portable, miniaturized low-power test equipment scenarios. (6) The parameters of the 6 pulse output channels can be configured independently, and the timing of each channel is triggered synchronously. The high accuracy of timing matching between channels is ensured by relying on the unified hardware clock, which can meet the timing requirements of multiple signals in PON testing. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of a specific embodiment of the present invention.

[0017] Figure 2 This is a schematic diagram illustrating the multi-channel pulse output requirements of a specific embodiment of the present invention.

[0018] Figure 3 This is a timing diagram of pulse segmentation and parameter update in a specific embodiment of the present invention.

[0019] Figure 4 This is a schematic diagram of the parameter configuration interface provided by the human-computer interaction module in a specific embodiment of the present invention. Detailed Implementation

[0020] To further explain the technical solution of the present invention, the present invention will be described in detail below using a precision of 1 ns as an example through specific embodiments.

[0021] refer to Figure 1 As shown, this invention discloses a high-resolution timing programmable burst pulse generator based on an embedded processor. Its core hardware adopts the GD32E5 series embedded processor, and relies on the chip's built-in SHRTIM ultra-high precision timer and DMA controller to achieve high-precision pulse output. The system consists of a host computer configuration module, a USB-IIC bridge module, an embedded main control module, a FLASH parameter storage area, an ultra-high precision SHRTIM timer, a DMA burst transmission unit, and 6 pulse output channels.

[0022] refer to Figure 4 As shown, users can complete parameter configuration through the host computer's visual interface. They can customize the pulse width, relative timing offset, and output polarity of the two Ben channels and the two RSSI_Trig channels. At the same time, they can configure the number of pulses, single pulse width, pulse interval, and independent output polarity of the two Reset channels. All configuration parameters are packaged and encapsulated through a customized private protocol and transmitted to the embedded main control chip via the USB-IIC bridging module.

[0023] refer to Figure 2As shown, after receiving protocol data, the embedded main control chip completes parsing and verification, and solidifies the valid parameters into the FLASH parameter storage area inside the embedded main control module to achieve parameter retention even after power failure. Simultaneously, it completes the underlying hardware initialization configuration: the SHRTIM timer is configured to be triggered by an external signal, and the pulse mode is set to single-pulse mode; the pre-loading function is enabled, and the shadow register update condition is set to counter toggle. The DMA burst transfer function is started, specifying that the period of the sub-timer in the SHRTIM timer and the compare register are included in the list of registers to be updated via burst DMA; then, the DMA burst transfer unit is configured, with the trigger source being the timer compare event, and the transfer direction being from the memory waveform table to the data register (BDMADR) of the DMA burst transfer unit. The source address pointer increments, and the target address is fixed. Based on the high-precision timer DMA burst transfer mechanism, the data sent to the BDMADR register is redirected one by one to the registers associated in the above update list; after the system initialization is completed, the user parameters are mapped to the timer timing register configuration logic; the hardware automatically and continuously detects the external AUX trigger signal, and when the AUX signal generates a rising edge, it synchronously starts the 6-channel pulse timing output.

[0024] During the system parameter preprocessing stage, the main control chip automatically identifies parameter over-limit states: For Ben and RSSI_Trig single-pulse signals, if the timing parameters exceed the timer single-cycle threshold (taking 1ns accuracy as an example, the timer single-cycle threshold is 65.5μs), a timer interrupt continuation method is used to complete the waveform output, ensuring that the single-pulse timing is distortion-free; for Reset multi-pulse signals, if the number of pulses is greater than 4 or the overall timing exceeds the single-cycle threshold, the memory waveform table timing segmentation algorithm is activated to construct an optimal timing parameter table in RAM, segmenting and optimizing the irregular multi-pulse sequence to maximize the utilization of timer single-cycle resources and reserve sufficient DMA transfer processing redundancy time. The principle of segmentation optimization is as follows: segmentation is performed when the number of pulses is greater than 4 or the overall timing exceeds the single-cycle threshold; simultaneously, timing checks are performed on the next segment. If the high or low level duration of the first pulse in its starting segment is less than 4 clock cycles, the segment is re-merged and allocated with the previous segment.

[0025] During the timing output process, the hardware characteristics of the SHRTIM timer are fully utilized: independent offset counting units for each channel achieve precise delay calibration of pulse edges, and hardware double-buffered shadow registers enable seamless hot updates of parameters; the system uses the timer period counter returning to zero as the update trigger event, and automatically reloads the timing parameters for the next period after the current period waveform is output, completely avoiding waveform glitches and timing jumps.

[0026] refer to Figure 3As shown, in conjunction with the DMA burst transfer mechanism, the system can move the next stage CMP and PER timing parameters from the memory waveform table in advance through DMA hardware during the current pulse output stage, and update the timer register group in batches. The entire process does not require CPU participation in calculation and parameter rewriting, and the CPU utilization is extremely low. Through the hardware pipeline closed-loop mechanism, the system can achieve fully automatic continuous output of irregular nanosecond-level burst pulse sequences. The timing accuracy is determined only by the hardware timer and is not affected by system scheduling or interrupt delay.

[0027] The memory waveform table data consists of segmented timer cycles and multiple comparator values, with each data group being 22 bytes long. Since the DMA source address range supports a maximum of 128KB, theoretically, the maximum length of each triggered output pulse signal group is approximately 390ms, with a maximum total of 20,000 pulses. If a larger number of pulse signals are required in a practical application, the DMA module's double-buffering mechanism can be used to alternately output data from the two memory waveform tables. This allows for simultaneous updating of the two waveform tables during transmission, enabling the output of up to 230,000 programmable irregular pulse signals based on 1MB of memory.

[0028] Once the entire burst pulse sequence has been output, the DMA module triggers a transmission completion interrupt based on the preset transmission length. The interrupt service function automatically reloads the carrier waveform table with initial timing parameters, and the system is reset to standby trigger state, waiting for the next AUX rising edge trigger. This allows for multiple cyclic burst pulse outputs.

[0029] The Reset signal can accurately output GPON standard pulse width pulses, support multi-pulse irregular timing arrangement, and achieve a stable timing resolution of 90ps, meeting the high-precision testing requirements below nanosecond level; the Ben signal accurately simulates PON burst enable timing and can flexibly configure the protection interval duration; the RSSI_Trig signal can accurately match the stable range of burst optical signals, realize high-precision optical power sampling triggering, and fully meet the full-dimensional burst performance testing requirements of high-end PON optical modules.

[0030] Compared with the prior art, the present invention has the following key advantages through the above solution: (1) Ultra-high timing accuracy to meet the requirements of refined testing This invention is based on the GD32E5's built-in SHRTIM ultra-high precision timer. Relying on the ultra-high clock frequency of 11.5GHz and the extreme timing resolution of 90ps, it achieves high-precision timing control at the nanosecond level. Combined with the hardware double-buffered shadow register's glitch-free parameter switching mechanism, it ensures the extreme accuracy of multi-channel pulse width and relative timing position. It can perfectly reproduce the nanosecond-level PON standard burst timing and greatly improve the testing accuracy of optical modules.

[0031] (2) Supports irregular multi-pulse burst output, with strong scene adaptability. By combining a self-developed memory waveform table timing segmentation algorithm with a DMA hardware burst transfer mechanism, the traditional timer single-cycle output limitation is broken, enabling the output of irregular Reset burst pulse sequences with arbitrary number, arbitrary pulse width, and arbitrary nanosecond intervals. The entire process is fully automated in hardware with no CPU scheduling delay, and the waveform has excellent continuity and stability, covering the burst testing needs of optical modules in all scenarios.

[0032] (3) Significantly reduce hardware costs and simplify system architecture Abandoning the traditional FPGA core solution, it adopts a general-purpose embedded processor to realize all timing control, pulse generation and data interaction functions. It does not require a dedicated FPGA chip and complex peripheral circuits, the hardware structure is extremely simple, the mass production cost is greatly reduced, and it is suitable for large-scale production applications.

[0033] (4) The software has strong programmability, high flexibility and maintainability. This invention is based on embedded C language firmware development and supports online dynamic configuration of all parameters such as pulse quantity, pulse width, timing, and polarity by the host computer. It can quickly adapt to different test scenarios without modifying the hardware circuit or recompiling and burning. It has a short development cycle, convenient debugging, and extremely low cost for later upgrades and maintenance, overcoming the shortcomings of FPGA solutions, such as high development difficulty and cumbersome iteration.

[0034] (5) High system integration, suitable for miniaturized and low-power scenarios The single embedded chip integrates all functions such as pulse generation, timing control, IIC communication, parameter storage, and system management, eliminating the need for an FPGA+MCU composite architecture and resulting in a compact system structure. At the same time, the embedded processor features low power consumption and low heat generation, making it suitable for the application requirements of portable and integrated optical signal testing equipment.

[0035] (6) Multiple channels are independently controllable, and the timing matching accuracy is high. The six output channels have clearly defined functions and are independently programmable. The parameters of the single-pulse channel are fully customizable, the timing of the multi-pulse channels is synchronized, the polarity is independently controllable, and the timing linkage of the multi-channel is precise, perfectly matching the timing requirements of multi-channel collaborative testing of PON optical modules.

[0036] The above embodiments and figures are not intended to limit the product form and style of the present invention. Any appropriate changes or modifications made by those skilled in the art should be considered as not departing from the patent scope of the present invention.

Claims

1. A high-resolution timing-programmable burst pulse generator based on an embedded processor, characterized in that: It includes an embedded processor module, a host computer configuration module, a USB-IIC bridging communication module, and an embedded main control module; The embedded processor module uses the GD32E5 series chip and has a built-in SHRTIM timer. The SHRTIM timer has a maximum operating frequency of 11.5GHz after being multiplied by 64, and the timing resolution is reduced to 90ps. The SHRTIM timer also has a DMA burst transfer unit and multiple pulse output channels. The host computer configuration module establishes data interaction with the embedded main control module through the USB-IIC bridge communication module to configure the configuration parameters of each pulse signal. The configuration parameters include pulse width, relative timing position, output polarity, and number of pulses. The embedded main control module receives and parses the configuration parameters, and then stores the parsed configuration parameters in the internal FLASH parameter storage area and completes the hardware configuration. After the rising edge of the external AUX signal is triggered, six pulse signals are output synchronously.

2. The high-resolution timing-programmable burst pulse generator based on an embedded processor as described in claim 1, characterized in that: The six pulse signals are output through six pulse output channels, including two Ben signal channels, two RSSI_Trig signal channels, and two Reset signal channels. The two Ben signal channels and two RSSI_Trig signal channels are single-pulse output channels, with each channel's pulse width, relative timing position, and output polarity independently programmable. The two Reset signal channels are multi-pulse burst output channels, maintaining consistent pulse quantity, pulse width, and relative timing position parameters for synchronized output timing. Their output polarity is independently programmable, allowing for the output of irregular nanosecond-level burst pulse sequences where the pulse quantity, pulse width, and relative timing position are all arbitrarily programmable.

3. The high-resolution timing-programmable burst pulse generator based on an embedded processor as described in claim 2, characterized in that: The embedded main control module has built-in parameter preprocessing logic. After the system powers on or the parameters are updated, it automatically completes parameter verification and timing sorting to check whether multiple pulses output by the Reset signal channel conflict and rearrange them according to the delay time from smallest to largest. It adopts a differentiated timing processing mechanism: when all parameters are within limits, the SHRTIM timer is directly configured to complete single-cycle pulse output; when the Ben and RSSI_Trig signal cycles exceed the limits, the waveform segmented output is achieved by interrupting the SHRTIM timer; when the number of Reset signal pulses or the cycle exceeds the limits, the memory waveform table timing segmentation algorithm is started in combination with the DMA burst transmission unit to complete irregular burst pulse output.

4. The high-resolution timing-programmable burst pulse generator based on an embedded processor as described in claim 3, characterized in that: The memory waveform table timing segmentation algorithm allocates a timing parameter storage area in the system RAM to perform optimal segmentation and arrangement of irregular Reset multi-pulse sequences. Under the premise of meeting the single-cycle output limit of the SHRTIM timer, it maximizes the filling pulse switching timing points and reserves redundant time for DMA transfer processing.

5. The high-resolution timing-programmable burst pulse generator based on an embedded processor as described in claim 3, characterized in that: Each channel of the SHRTIM timer is equipped with an independent offset counting unit, which can realize pulse edge delay offset calibration. Its CMP, PER, and DELAY timing registers are all equipped with a hardware double-buffered shadow register mechanism, which is divided into an immediate register and a shadow register. The software writes the timing parameters of the next pulse to the immediate register in real time and temporarily stores them in the shadow register. The "timer period counter reset to zero" is configured as the update trigger event. After the trigger, the parameters of the shadow register are batch reloaded to the immediate register to realize seamless switching of pulse timing parameters.

6. The high-resolution timing-programmable burst pulse generator based on an embedded processor as described in claim 5, characterized in that: The DMA burst transfer unit is linked with the SHRTIM timer to support batch automatic updates of multiple timing registers. During the current pulse deformation output process, the system uses the DMA burst transfer unit to batch transfer the CMP and PER timing parameters of the next pulse in the memory waveform table to the shadow register of the SHRTIM timer. After the current pulse output is completed, the hardware automatically triggers the reload parameters and seamlessly switches to the next irregular pulse timing.

7. The high-resolution timing-programmable burst pulse generator based on an embedded processor as described in claim 6, characterized in that: The DMA burst transmission unit triggers an interrupt after the system completes the output of the entire burst pulse sequence according to the preset total transmission length. In the interrupt service function, the timing parameters of the first cycle of the memory waveform table are automatically reloaded, the system is reset to the ready-to-trigger state, and waits for the next AUX rising edge trigger signal to realize the cyclic pulse output.

8. The high-resolution timing-programmable burst pulse generator based on an embedded processor as described in claim 2, characterized in that: The Ben signal channel is used to control the optical module to switch burst reception modes, simulating the burst uplink timing of multiple ONUs in a PON system; the Reset signal channel is used to reset the optical module's receiving channel during burst intervals, eliminating DC offset and gain memory effects; the RSSI_Trig signal channel is used to locate the effective power range of the burst optical signal, trigger optical power sampling, and achieve accurate testing of the burst performance of the optical module.

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