Clock generation circuit

Abstract

One example discloses a clock generation circuit comprising: a clock base circuit configured to receive a clock request (req_pulse) signal having a pulse width; wherein the clock base circuit is configured to generate a clock output signal having a predetermined number of cycles based on the pulse width of the clock request (req_pulse) signal.

Description

Technical Field

[0001] This specification relates to systems, methods, apparatus, devices, articles of manufacture, and instructions for clock generation. Background Technology

[0002] As chip size (e.g., large-scale ICs) has increased rapidly, digital design techniques for circuits using synchronous clocks have continued to evolve. However, many circuit designs in these systems are unable to include sufficiently fast synchronous clocks, and therefore their capabilities are limited, making it difficult to ensure the correct operation of circuit functions, such as when receiving event-based trigger signals that rapidly request such operations.

[0003] These are applications where asynchronous clocks will better serve such functionality and enable high-speed circuit operation. However, many such asynchronous circuit designs may exhibit glitches due to noise in their internal signal paths and / or noise generated by their asynchronous clocks. Such signal glitches are partly responsive to the signal requests they receive based on asynchronous events. Summary of the Invention

[0004] According to one example embodiment, a clock generation circuit includes: a clock base circuit configured to receive a clock request (req_pulse) signal having a pulse width; wherein the clock base circuit is configured to generate a clock output signal having a predetermined number of cycles based on the pulse width of the clock request (req_pulse) signal.

[0005] In another example embodiment, the clock base circuitry includes a flip-flop configured to cycle a clock output signal; and a clock output signal is acquired at the clock input port of the flip-flop.

[0006] In another example embodiment, a short req pulse suppression circuit is also included, which is configured to generate a request pulse merging (req_merge) signal.

[0007] In another example embodiment, the short req pulse suppression circuit is configured to keep the req_merge signal in a high logic state for a predetermined time after the pulse width of the clock request (req_pulse) signal ends.

[0008] In another example embodiment, the predetermined time is configured to allow a complete cycle of generating the clock output (clk_out) signal by the clock base circuitry before the clock output (clk_out) signal terminates.

[0009] In another example embodiment, the short req pulse suppression circuit includes an OR gate.

[0010] In another example embodiment, the clock request (req_pulse) signal received by the short request pulse suppression circuit passes directly through the OR gate to generate the rising edge of the req_merge signal.

[0011] In another example embodiment, the rising edge of the req_merge signal generates the rising edge of the clock output (clk_out) signal.

[0012] In another example embodiment, the short req pulse suppression circuit includes a first flip-flop and a second flip-flop.

[0013] In another example embodiment, both the first and second flip-flops are configured to receive a clock output (clk_out) signal at their clock input port (CK).

[0014] In another example embodiment, both the first and second flip-flops couple their Q output ports to an OR gate.

[0015] In another example embodiment, the first flip-flop is configured to receive a clock request (req_pulse) signal at its D input port; and the D input port of the second flip-flop is coupled to the Q output port of the first flip-flop.

[0016] In another example embodiment, the short req pulse suppression circuit is configured to extend the req_merge signal to ensure that the req_merge signal goes low after the clock output signal (clk_out) goes low.

[0017] In another example embodiment, the short req pulse suppression circuit is configured to extend the req_merge signal even if the clock request (req_pulse) signal goes low before the clock output signal (clk_out) goes low.

[0018] In another example embodiment, the clock request (req_pulse) signal is a first clock request signal with a first pulse width, and the set of clock signal cycles is a first set of clock signal cycles; and the clock generation circuit is configured to receive a second clock request signal with a second pulse width, and generate a second set of clock signal cycles in response.

[0019] In another example embodiment, the second set of clock signal cycles is longer than the first set of clock signal cycles because the second pulse width is wider than the first pulse width.

[0020] The foregoing discussion is not intended to represent every example embodiment or every implementation within the scope of the present or future claims. Various example embodiments are also illustrated in the drawings and the following detailed description.

[0021] The various exemplary embodiments can be more fully understood by considering the following specific implementations in conjunction with the accompanying drawings. Attached Figure Description

[0022] Figure 1 An example of a clock generation circuit.

[0023] Figure 2 This represents an example clock base circuit within a clock generation circuit.

[0024] Figure 3 This represents an example short request pulse suppression circuit within a clock generation circuit.

[0025] Figure 4 Example timing diagram showing a clock generation circuit.

[0026] Figure 5 This section presents an example comparison between the clock generation circuit and other clock generation circuits (not shown).

[0027] While this disclosure allows for various modifications and alternatives, details thereof have been illustrated by way of example in the drawings and will be described in detail. However, it should be understood that other embodiments besides the specific embodiments described are also possible. All modifications, equivalents, and alternative embodiments falling within the spirit and scope of the appended claims are also covered. Detailed Implementation

[0028] Examples of asynchronous clock generation circuits are presented below. These example clock generation circuits have controllable duty cycles, durations, and stable periods, and are glitch-free regardless of how frequently asynchronous requests for clock signals are received.

[0029] Even when input noise is mixed with the clock request signal, the clock cycles generated by these example clock generation circuits maintain the periodicity of the output clock. Each clock cycle output has a full cycle (i.e., no short clock pulses). These example circuits are duty-cycle adjustable and require only a clock request signal to generate a controllable number of output clock cycles. These example clock generation circuits are particularly helpful for asynchronous circuit designs where an external oscillator cannot be provided.

[0030] Figure 1 Example 100 represents a clock generation circuit. Example clock generation circuit 100 includes clock request generation circuit 102, clock base circuit 104, and short req pulse suppression circuit 106.

[0031] Clock request generation circuit 102 asynchronously receives various clock request input signals 108 from other circuits (not shown) that require clock signals to perform their functions. In response, clock request generation circuit 102 processes these various clock request input signals 108 to generate a request pulse (req_pulse) signal. The req_pulse signal has a specific pulse width. The specific pulse width instructs clock base circuit 104 to generate a specific number of clock signal cycles before entering a state of rest.

[0032] The clock base circuit 104 indirectly receives the req_pulse signal as a request pulse merging signal (req_merge) from the short req pulse suppression circuit 106. In response, the clock base circuit 104 generates a clock output signal (clk_out) containing a specific number of clock signal cycles. (The following is in...) Figures 2-4 The operation of the clock base circuit 104 combined with the short req pulse suppression circuit 106 is discussed in the paper.

[0033] Figure 2 This represents an example clock base circuit 200 within the clock generation circuit 100. The clock base circuit 200 generates a clock output signal (clk_out) in response to a request pulse merging signal (req_merge).

[0034] The clock base circuit 200 includes an AND gate, a flip-flop (FF), a T1 delay, a T2 delay, and an XOR gate. The flip-flop (FF) has a clock input port (CK), a D input, and a Q output. The clock output signal (clk_out) is obtained at the clock input port (CK) of the flip-flop (FF).

[0035] Initially, FF is in a reset state, with Q of FF being 0, so the clock base signal (clk_base) is 1. Since the req_merge signal is initially 0, the AND gate output is also 0, so clk_out is 0.

[0036] If the `req_merge` signal becomes 1, the clock output signal (`clk_out`) is immediately generated by the AND gate output. The clock output signal (`clk_out`) cycles between logic 0 and logic 1. The high duration (logic 1) is set by T1, and the low duration (logic 0) is set by T2. Therefore, the duty cycle of the clock output signal (`clk_out`) can be adjusted by setting T1 and T2 to different values.

[0037] Then, when the req_merge signal becomes 0, the clock output signal (clk_out) also becomes 0.

[0038] Since if the req_merge signal becomes 0 while the clock output signal (clk_out) is still 1, the high duration (logic 1) of the clock output signal (clk_out) may be less than T1, which may not be optimal for the circuit (not shown) receiving the clock output signal (clk_out). The short req pulse suppression circuit 106 prevents this situation, as will be discussed later. Figure 3 As discussed in the text.

[0039] Figure 3 Example 300 shows a short request pulse suppression circuit 302 within the clock generation circuit 100. The short pulse suppression circuit 302 is configured to prevent the clock output signal (clk_out) from terminating prematurely during the last cycle before entering stillness.

[0040] To achieve this, the short req pulse suppression circuit 302 is configured to keep the req_merge signal in a high logic state for a predetermined time after the pulse width of the clock req_pulse ends. The predetermined time is configured to allow a complete cycle of the clock output (clk_out) signal to be generated by the clock base circuit before the clock output (clk_out) signal is terminated.

[0041] The short request pulse suppression circuit 302 includes a three-input OR gate, a first FF (flip-flop) with a clock input port (CK), a D input, and a Q output, and a second FF (flip-flop) with a clock input port (CK), a D input, and a Q output.

[0042] The req_pulse signal received by the short request pulse suppression circuit 302 is directly passed through an OR gate to quickly generate the rising edge of the req_merge signal, and then passed through an AND gate in the clock base circuit 200 to become a clock output signal (clk_out). This speed is improved because the CK input of the flip-flop is also used as the clock output signal (clk_out).

[0043] Because of the OR gate, the pulse width of the req_pulse signal determines the number of cycles of the clock output signal (clk_out).

[0044] To prevent any clock output signal (clk_out) from shortening the cycle, the req_pulse signal should become 0 after the clock output signal (clk_out) becomes 0. However, for the case where the req_pulse signal becomes 0 before the clock output signal (clk_out) becomes 0, the short pulse suppression circuit 302 extends the req_merge signal to ensure that the req_merge signal becomes 0 after the clock output signal (clk_out) becomes 0.

[0045] To achieve this extension, the `req_pulse` signal is first recorded via the rising edge of `clk_out` using the CK port of the first FF (flip-flop). The output of the first FF (flip-flop) is the `req_lat_r` signal. Then, the `req_lat_r` signal is recorded via the falling edge of `clk_out` using the CK port of the second FF (flip-flop). The output of the second FF (flip-flop) is the `req_lat_f` signal.

[0046] Finally, an OR gate is used to merge the req_pulse, req_lat_r, and req_lat_f signals into a single req_merge signal. The req_merge signal then enters an AND gate in the clock base circuit 200. The req_lat_r and req_lat_f signals extend the high duration (logic 1) of the req_merge signal to ensure that the req_merge signal does not go low (logic 0) until the clock output (clk_out) signal has completed its full high duration (logic 1).

[0047] Therefore, even when the request pulse (req_pulse) signal is a very short pulse that includes glitches and / or other noise, the complete cycle of the clock output (clk_out) signal will not be shortened / cut off.

[0048] When no request pulse (req_pulse) signal is present, there is no transition at the short req pulse suppression circuit 302, and therefore the clock output signal (clk_out) does not cycle. This achieves low power consumption for the clock generation circuit 100. Therefore, the clock generation circuit 100 is turned on / off only by the request pulse (req_pulse) signal.

[0049] Figure 4 Example timing diagram 400 shows clock generation circuit 100.

[0050] Example timing diagram 400 shows a first request pulse (req_pulse) signal 402 having a first pulse width for generating a first set of clock signal cycles 404, and a second request pulse (req_pulse) signal 406 having a second pulse width for generating a second set of clock signal cycles 408.

[0051] Component 410 indicates that when there is no request pulse (req_pulse) signal, there is no clock output (clk_out) signal.

[0052] Figure 5 Example comparison 500 between clock generation circuit 100 and other clock generation circuits (not shown).

[0053] In many example embodiments, the functionality described above is implemented using logic gates, dedicated chips, firmware, and / or other hardware. However, in some example embodiments, this functionality may be implemented as a set of software instructions stored in a non-transitory computer-readable or computer-usable medium.

[0054] It will be readily understood that the components, as generally described herein and illustrated in the accompanying drawings, can be arranged and designed in a wide variety of different configurations. Therefore, the detailed descriptions of the various embodiments illustrated in the accompanying drawings are not intended to limit the scope of this disclosure, but merely to illustrate various embodiments. While various aspects of the embodiments are presented in the drawings, the drawings are not necessarily drawn to scale unless specifically indicated otherwise.

[0055] The invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The described embodiments should be considered in all respects as illustrative rather than restrictive. Therefore, the scope of the invention is indicated by the appended claims rather than by a detailed description thereof. All modifications falling within the equivalent meaning and scope of the claims should be covered within their scope.

[0056] References to features, advantages, or similar language throughout this specification do not imply that all features and advantages achievable using the invention should be included in or in any single embodiment of the invention. In fact, language relating to features and advantages should be understood to mean that a particular feature, advantage, or characteristic described in connection with an embodiment is included in at least one embodiment of the invention. Therefore, the discussion of features and advantages and similar language throughout this specification may (but need not) refer to the same embodiment.

[0057] Furthermore, the features, advantages, and characteristics described in this invention can be combined in one or more embodiments in any suitable manner. Those skilled in the art will recognize that, in view of the description herein, this invention can be practiced without one or more of the specific features or advantages of a particular embodiment. In other instances, additional features and advantages that may not be present in all embodiments of the invention may be identified in certain embodiments.

[0058] Throughout this specification, references to "an embodiment," "an embodiment," or similar language mean that a particular feature, structure, or characteristic described in connection with the indicated embodiment is included in at least one embodiment of the invention. Therefore, the phrases "in an embodiment," "in an embodiment," and similar language throughout this specification may (but not necessarily) all refer to the same embodiment.

Claims

1. A clock generation circuit, characterized in that, include: The clock base circuit is configured to receive a clock request req_pulse signal with a pulse width; The clock base circuit is configured to generate a clock output signal with a predetermined number of cycles based on the pulse width of the clock request req_pulse signal.

2. The clock generation circuit according to claim 1, characterized in that: The clock base circuit includes a flip-flop configured to cycle the clock output signal; and The clock output signal is obtained at the clock input port of the trigger.

3. The clock generation circuit according to claim 1, characterized in that: Additionally, a short req pulse suppression circuit is included, which is configured to generate a request pulse merging req_merge signal.

4. The clock generation circuit according to claim 3, characterized in that: The short req pulse suppression circuit is configured to keep the req_merge signal in a high logic state for a predetermined time after the pulse width of the clock request req_pulse signal ends.

5. The clock generation circuit according to claim 4, characterized in that: The predetermined time is configured such that a complete cycle of the clock output clk_out signal can be generated by the clock base circuit before the clock output clk_out signal terminates.

6. The clock generation circuit according to claim 3, characterized in that: The short req pulse suppression circuit includes an OR gate.

7. The clock generation circuit according to claim 6, characterized in that: The clock request req_pulse signal received by the short request pulse suppression circuit passes directly through the OR gate to generate the rising edge of the req_merge signal.

8. The clock generation circuit according to claim 7, characterized in that: The rising edge of the req_merge signal generates the rising edge of the clock output clk_out signal.

9. The clock generation circuit according to claim 6, characterized in that: The short req pulse suppression circuit includes a first flip-flop and a second flip-flop.

10. The clock generation circuit according to claim 9, characterized in that: Both the first and second flip-flops are configured to receive the clock output clk_out signal at their clock input port CK.

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