Data transmission apparatus and system

Abstract

This application provides a data transmission device and system that improves data transmission efficiency. The device includes a processing module 1 and a transceiver module 2, which are connected. The processing module 1 sends input data, which is data to be sent to a JTAG slave device, to the transceiver module 2. The transceiver module 2 stores the input data and sends it to the JTAG slave device. In this application embodiment, by setting the transceiver module to store the input data, the acquisition and transmission of input data are decoupled, allowing the processing module to acquire multiple transmission data at once based on actual needs and transmit them through the transceiver module, thereby improving data transmission efficiency.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to a data transmission device and system. Background Technology

[0002] During the manufacturing, design, and subsequent use of chips, joint test action group (JTAG) technology can be used to optimize chips, such as for debugging, verification, and upgrades.

[0003] In JTAG technology, data can be shifted in one by one through the Test Data Input (TDI) line and shifted out one by one through the Test Data Output (TDO) line, and then the chip's operating status can be determined based on the shifted-out data.

[0004] In JTAG technology, data is shifted in and out bit by bit, resulting in low data transmission efficiency. Summary of the Invention

[0005] This application provides a data transmission device and system that can improve data transmission efficiency to a certain extent.

[0006] To achieve the above objectives, this application adopts the following technical solution:

[0007] In a first aspect, embodiments of this application provide a data transmission apparatus. The apparatus includes a processing module and a transceiver module, which are connected together.

[0008] The processing module sends input data to the transceiver module. This input data is the data that needs to be sent to the JTAG slave device of the Joint Working Test Group. The transceiver module stores the input data and sends it to the JTAG slave device.

[0009] Optionally, the processing module can send input data to the transceiver module based on the input data storage status of the transceiver module. This input data storage status indicates the state in which the transceiver module stores the input data.

[0010] Based on the above technical solution, by setting up a transceiver module to store input data, and having the transceiver module send the input data to the JTAG slave device, the acquisition and transmission of input data are decoupled. That is, the processing module can acquire input data and send it to the transceiver module, which then handles the transmission. In this way, since the processing module does not need to send input data, it can acquire multiple input data sets at once based on actual testing needs and send these multiple sets to the transceiver module.

[0011] Because transceiver module 2 can store input data, it ensures that even if the processing module acquires and sends multiple input data entries, these entries will not be lost and will be accurately sent to the JTAG slave device. Based on actual usage requirements, this transceiver module can accurately send the stored input data to the JTAG slave device according to relevant protocol standards (such as JTAG data standards).

[0012] Furthermore, while the transceiver module is sending input data, the processing module can also acquire the input data needed for the next test. In this way, after the transceiver module completes sending the current input data, the processing module can directly send the next required input data to the transceiver module, which will then store and resend it, thereby improving the utilization rate of the data transmission line between the data transmission device and the JTAG slave device and increasing data transmission efficiency.

[0013] Based on the first aspect, in some implementations of the first aspect, the transceiver module is also used to store output data from the JTAG slave device. This output data may be obtained by the JTAG slave device based on input data. The processing module is also used to read the output data from the transceiver module.

[0014] Optionally, the processing module can read output data from the transceiver module based on the output data storage status of the transceiver module. This output data storage status indicates the state in which the transceiver module stores the output data.

[0015] Based on the above implementation, the transceiver module can acquire and store the output data of the JTAG slave device. Thus, when the processing module needs to obtain this output data, it can directly retrieve all the data output by the JTAG slave device from the transceiver module, without having to read the output data from the JTAG slave device bit by bit. This improves the efficiency of output data acquisition and further enhances the data transmission efficiency between the processor and the JTAG slave device.

[0016] Based on the first aspect, in some implementations of the first aspect, the processing module is also used to send status data to the transceiver module, and the status data is used to control the working status of the JTAG slave device. The transceiver module is also used to store the status data and send the status data to the JTAG slave device.

[0017] Optionally, the processing module can send status data to the transceiver module based on the status data storage status of the transceiver module. This status data storage status is used to indicate the state of the status data stored by the transceiver module.

[0018] Based on the above implementation, the processing module sends status data to the transceiver module, enabling the transceiver module to send status data to the JTAG slave device. In this way, the JTAG slave device can determine its current operating status based on this status data, and then perform different data transmissions based on different operating states, thereby improving data transmission accuracy.

[0019] Based on the first aspect, in some implementations of the first aspect, the transceiver module may include a status register. This status register is used to indicate the input data storage status, output data storage status, and / or status data storage status of the transceiver module. The processing module is also used to determine the input data storage status, output data storage status, and / or status data storage status of the transceiver module based on the status register.

[0020] Based on the above implementation, the transceiver module can use a status register to indicate whether it can currently receive input data and / or status data sent by the processing module, and whether the processing module can currently read output data. This ensures the accuracy of data transmission between the processing module and the transceiver module, avoids data loss due to the transceiver module's inability to read or write, and thus improves the accuracy of data transmission.

[0021] Based on the first aspect, in some implementations of the first aspect, the transceiver module includes a data register. This data register is used to store input data, output data, and / or status data.

[0022] Based on the above implementation method, by setting a data register in the transceiver module to store input data, output data and / or status data, the complexity of the transceiver module can be reduced and the data transmission performance can be improved while ensuring the accuracy of the data stored in the transceiver module.

[0023] Based on the first aspect, in some implementations of the first aspect, the transceiver module is a JTAG controller.

[0024] Secondly, embodiments of this application provide a data transmission system, which includes a data transmission device and a JTAG slave device as described in the first aspect.

[0025] Thirdly, embodiments of this application provide a data transmission method that can be applied to the data transmission system of the second aspect. The method includes: a processing module sending input data to a transceiver module. The input data is data to be sent to a JTAG slave device of the Joint Working Test Group. The transceiver module stores the input data and sends the input data to the JTAG slave device.

[0026] Optionally, the processing module can send input data to the transceiver module based on the input data storage status of the transceiver module. This input data storage status indicates the state in which the transceiver module stores the input data.

[0027] Based on the third aspect, in some implementations of the third aspect, the transceiver module can also store output data from the JTAG slave device. This output data is obtained by the JTAG slave device based on the input data. The processing module can read the output data from the transceiver module.

[0028] Optionally, the processing module can read output data from the transceiver module based on the output data storage status of the transceiver module. This output data storage status indicates the state in which the transceiver module stores the output data.

[0029] Based on the third aspect, in some implementations of the third aspect, the processing module can also send status data to the transceiver module. This status data is used to control the operating status of the JTAG slave device. The transceiver module can store the status data and send it to the JTAG slave device.

[0030] Optionally, the processing module can send status data to the transceiver module based on the status data storage status of the transceiver module. This status data storage status is used to indicate the state of the status data stored by the transceiver module.

[0031] Based on the third aspect, in some implementations of the third aspect, the transceiver module may include a status register, which is used to indicate the input data storage status, output data storage status, and / or status data storage status of the transceiver module. The processing module may determine the input data storage status, output data storage status, and / or status data storage status of the transceiver module based on the status register.

[0032] The solutions provided in the second and third aspects above are used to realize or cooperate in realizing the function of the device described in the first aspect above, and therefore can achieve the same or corresponding beneficial effects as the first aspect, which will not be elaborated here. Attached Figure Description

[0033] Figure 1 This is a schematic diagram of the architecture of a data transmission device provided in an embodiment of this application.

[0034] Figure 2 This is a schematic diagram of a data transmission process provided in an embodiment of this application.

[0035] Figure 3 This is a schematic diagram of the architecture of another data transmission device provided in the embodiments of this application.

[0036] Figure 4 This is a schematic diagram of another data transmission process provided in an embodiment of this application.

[0037] Figure 5 This is a schematic diagram of the architecture of a JTAG slave device provided in an embodiment of this application.

[0038] Figure 6 This is a schematic diagram of the state transition of a TAP state machine provided in an embodiment of this application.

[0039] Figure 7 This is a schematic diagram of another data transmission process provided in an embodiment of this application.

[0040] Figure 8 This is a schematic diagram of the architecture of another data transmission device provided in the embodiments of this application.

[0041] Figure 9 This is a schematic diagram of the architecture of another data transmission device provided in the embodiments of this application.

[0042] Figure 10 This is a schematic diagram of the architecture of a data transmission system provided in an embodiment of this application.

[0043] Figure 11 This is a flowchart illustrating a data transmission method provided in an embodiment of this application. Detailed Implementation

[0044] To enable those skilled in the art to better understand the solutions in this application, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0045] In this document, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Here, A and B can be single or multiple. "At least one of the following" or similar expressions are used to represent any combination of the listed items. For example, at least one of A, B, and / or C can represent: A existing alone, B existing alone, C existing alone, A and B existing simultaneously, B and C existing simultaneously, A and C existing simultaneously, and A, B, and C existing simultaneously. Here, A, B, and C can be single or multiple.

[0046] The terms "first" and "second," etc., used in the specification and claims of this application are used to distinguish different objects, not to describe a specific order of objects. For example, "first target object" and "second target object," etc., are used to distinguish different target objects, not to describe a specific order of target objects.

[0047] In the embodiments of this application, the words "exemplarily" or "for example" are used to indicate examples, illustrations, or explanations. Any embodiment or design described as "exemplarily" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design solutions. Specifically, the use of the words "exemplarily" or "for example" is intended to present the relevant concepts in a specific manner.

[0048] In the description of the embodiments in this application, unless otherwise stated, "multiple" means two or more. For example, multiple processing units means two or more processing units; multiple systems means two or more systems.

[0049] In chip technology, data transmission between the JTAG slave device and the JTAG slave device can usually be achieved through a data transmission device, so as to enable operations such as debugging, verification, and upgrading of the JTAG slave device, and to ensure or improve the working performance of the JTAG slave device. Figure 1 This is a schematic diagram of a data transmission system provided in an embodiment of this application. Figure 1 As shown, the data transmission system includes a data transmission device and a JTAG slave device.

[0050] Alternatively, the data transmission device may also be referred to as a JTAG master device, and the JTAG slave device may be a field programmable gate array (FPGA) device.

[0051] Combination Figure 1 Data transmission between the data transmission device and the JTAG slave device can be achieved through the test clock input (TCK) signal, the test mode selection input (TMS) signal, the TDI signal, and the TDO signal.

[0052] The TCK signal is used to provide a clock reference for JTAG slave devices to ensure that all JTAG signals (such as TMS, TDI, and TDO signals) can be sampled and processed at the same time. This ensures that all signals are sampled and processed on the same clock edge (such as the rising edge of TCK), so that the processing of each signal can be kept precisely synchronized.

[0053] The TMS signal is used to control the operating state of JTAG slave devices. In each clock cycle, the JTAG slave device can determine its own operating state through the value of the TMS signal (0 or 1), enabling different data transmissions in different operating states, such as data reception or data transmission.

[0054] The TDI signal is used to transmit data to the JTAG slave device. In each clock cycle, one data item can be input to the JTAG slave device via the TDI pin.

[0055] The TDO signal is used to transmit data from the JTAG slave device to the data transmission device, so as to realize the debugging, verification and other related processing of the JTAG slave device based on the data output by the JTAG slave device.

[0056] However, since data transmission devices and JTAG slave devices typically use serial communication to transmit data, due to the nature of serial communication, if multiple signals are sent simultaneously, the previous bit will be overwritten by the next bit. Therefore, the data transmission device can only process data bit by bit, resulting in poor data transmission efficiency.

[0057] Combination Figure 2 , Figure 2 This application provides a data transmission flowchart for a JTAG testing scenario. The data transmission device needs to send one bit of TMS signal each time to indicate the working status of the JTAG slave device; send one bit of TDI signal; and obtain one bit of TDO signal from the JTAG slave device. After receiving the TDO signal, the data transmission device verifies the data carried by the TDO signal to complete one transmission cycle. After completing the verification of the TDO signal, the data transmission device needs to obtain the TMS and TDI signals required for the next cycle to execute the next cycle, and repeat the above process to verify the JTAG slave device.

[0058] In the above process, the time it takes for the data transmission device to acquire data once (typically, the central processing unit of the data transmission device needs to complete at least one cycle to acquire data) is much longer than the time it takes to transmit one bit of data through the data transmission line between the data transmission device and the JTAG slave device. Therefore, during data transmission, the data transmission line is idle for most of the time, resulting in low utilization and poor data transmission efficiency.

[0059] Based on this, embodiments of this application provide a data transmission device that can improve the data transmission efficiency between the data transmission device and the JTAG slave device.

[0060] The data transmission apparatus provided in the embodiments of this application will be explained below. (Refer to...) Figure 3 , Figure 3 This is a schematic diagram of a data transmission device provided in an embodiment of this application, such as... Figure 3 As shown, the device includes a processing module 1 and a transceiver module 2. The processing module 1 and the transceiver module 2 are connected.

[0061] Processing module 1 is used to send input data to transceiver module 2. This input data is the data that needs to be sent to the JTAG slave device.

[0062] Transceiver module 2 is used to store the input data and send the input data to the JTAG slave device.

[0063] Optionally, the input data can be flexibly selected based on the actual usage scenario. For example, the input data can be data that needs to be transmitted to the JTAG slave device via the TDI line. In this scenario, the transceiver module 2 can send the input data to the JTAG slave device via the TDI line based on the JTAG data transmission standard.

[0064] In some embodiments, the processing module 1 may acquire input data based on a compressed file and send the input data to the transceiver module 2.

[0065] For example, processing module 1 can obtain a compressed file and obtain input data based on the compressed file. The compressed file can be a compressed file that includes input data that needs to be sent to the JTAG slave device in scenarios such as JTAG slave device verification and upgrade, such as a serial vector format (SVF) file.

[0066] For example, processing module 1 can decompress the compressed file, obtain the input data, and send the input data to transceiver module 2. Transceiver module 2 stores the input data and sends it to the JTAG slave device.

[0067] In some instances, the transceiver module 2 can be flexibly selected based on actual usage requirements. For example, the transceiver module 2 can be a JTAG controller.

[0068] In some embodiments, combined with Figure 3 The data transmission process between the data transmission device and the JTAG slave device can be as follows: Figure 4 As shown.

[0069] Combination Figure 4 The transmission process includes the following steps:

[0070] (1) Processing module 1 acquires multi-digit input data.

[0071] (2) Processing module 1 sends the multi-bit input data to transceiver module 2.

[0072] (3) The transceiver module 2 stores the multi-bit input data.

[0073] (4) The transceiver module 2 sends the input data bit by bit to the JTAG slave device.

[0074] Optionally, during the process of the transceiver module 2 sending input data to the JTAG slave device, the processing module 1 can acquire multiple bits of input data again, and use the multiple bits of input data as a loop to acquire input data in a loop, and then send it to the JTAG slave device through the transceiver module 2.

[0075] Based on the aforementioned data transmission device and technical solution, by setting up a transceiver module to store input data, and having the transceiver module send the input data to the JTAG slave device, the acquisition and transmission of input data are decoupled. That is, the processing module can acquire input data and send it to the transceiver module, which then transmits the input data. In this way, since the processing module does not need to send input data, it can acquire multiple input data sets at once based on actual usage requirements and send these multiple sets of input data to the transceiver module.

[0076] Because transceiver module 2 can store input data, it ensures that even if the processing module acquires and sends multiple input data entries, these entries will not be lost and will be accurately sent to the JTAG slave device. Based on actual usage requirements, this transceiver module can accurately send the stored input data to the JTAG slave device according to relevant protocol standards (such as JTAG data standards).

[0077] Furthermore, while the transceiver module is sending input data, the processing module can also acquire the input data needed for the next test. In this way, after the transceiver module completes sending the current input data, the processing module can directly send the next required input data to the transceiver module, which will then store and resend it, thereby improving the utilization rate of the data transmission line between the data transmission device and the JTAG slave device and increasing data transmission efficiency.

[0078] In some embodiments, transceiver module 2 may also store output data from JTAG slave devices.

[0079] Processing module 1 reads the output data from transceiver module 2.

[0080] This output data can be the output data obtained by the JTAG slave device based on the input data.

[0081] Optionally, the transceiver module 2 can read the output data from the JTAG slave device according to the relevant protocol based on actual usage requirements. For example, the transceiver module 2 can sequentially obtain the data output by the JTAG slave device from the TDO pin of the JTAG slave device based on the JTAG protocol and store it.

[0082] In some scenarios, considering that processing module 1 may also need data output from the JTAG slave device, such as in JTAG slave device boundary detection and other verification scenarios, processing module 1 may also need to acquire data from the TDO line to verify the JTAG slave device based on the TDO line data. Therefore, in the above method, the transceiver module can acquire and store the output data of the JTAG slave device. In this way, when the processing module needs to acquire this output data, it can directly obtain all the data output by the JTAG slave device from the transceiver module, without having to read the output data from the JTAG slave device bit by bit, thereby improving the efficiency of output data acquisition and further improving the data transmission efficiency between the processing module and the JTAG slave device.

[0083] Optionally, the method by which the transceiver module 2 obtains the output data can be flexibly selected based on the actual application scenario. Combined with... Figure 5 , Figure 5 A schematic diagram of the architecture of a JTAG slave device provided in this application embodiment, such as... Figure 5 As shown, the JTAG slave device includes one or more shift registers. The transceiver module 2 sends the input data to the shift register of the JTAG slave device through the TDI line. After receiving the input data, the shift register can shift out the old data (i.e., the output data) in the shift register and send it to the transceiver module 2 through the TDO line.

[0084] In some embodiments, the processing module 1 may also send status data to the transceiver module 2, which is used to control the working status of the JTAG slave device.

[0085] The transceiver module 2 can store the status data and send the status data to the JTAG slave device.

[0086] Optionally, the processing module sends status data to the transceiver module, enabling the transceiver module to send status data to the JTAG slave device. In this way, the JTAG slave device can determine its current operating status based on this status data, and then perform different data transmissions based on different operating states, thereby improving data transmission accuracy.

[0087] In some embodiments, the processing module 1 may acquire input data based on a compressed file and send the input data to the transceiver module 2.

[0088] For example, processing module 1 can obtain a compressed file and obtain input data based on the compressed file. The compressed file can be a compressed file containing status data that needs to be sent to the JTAG slave device in scenarios such as JTAG slave device verification and upgrade, such as an SVF file.

[0089] This status data can be flexibly selected based on the actual usage scenario. For example, in the JTAG test scenario described above, this status data can be data input via a TMS signal. In this scenario, the transceiver module 2 can send this status data to the JTAG slave device via the TMS line, so that the JTAG slave device can determine the current test status based on this status data and then perform different tests.

[0090] For example, combining Figure 5 The JTAG slave device may include a test access port (TAP) state machine, which is used to control the working state of the JTAG slave device. The transceiver module 2 can send status data to the TAP state machine of the JTAG slave device through the TMS line to adjust the state of the TAP state machine, thereby adjusting the test state of the JTAG slave device based on the state switching of the TAP state.

[0091] In some embodiments, the switching relationship between the TMS signal and the TAP state machine state is as follows: Figure 6 As shown. Combined with Figure 6 The next state of the TAP state machine can be adjusted by the value of the TMS signal (high level 1 or low level 0).

[0092] For example: if TMS = 1, that is, the TMS signal is high, the state machine will switch from the current state to the next state in the next clock cycle; if TMS = 0, that is, the TMS signal is low, the state machine will remain in the current operating mode in the next clock cycle until TMS switches to high.

[0093] Combination Figure 6 The switching relationship between the TMS signal and the TAP state machine state can be shown in Table 1.

[0094] Table 1

[0095]

[0096]

[0097] The Test-Logic-Reset state is the test logic reset state, used to indicate the reset of the state machine, that is, to indicate that all registers and internal logic return to the initial state.

[0098] In this state, as shown in Table 1, if the TMS signal is low at the next rising edge of TCK, the TAP state machine will enter the Run-Test / Idle state; if the TMS signal remains high, the TAP state machine will remain in the Test-Logic-Reset state.

[0099] The Run-Test / Idle state is the idle state for running tests, i.e., the idle state for scanning operations. It is used to indicate that the state machine has entered the normal operating state, i.e., to indicate that the JTAG slave device can execute user programs or wait for instructions.

[0100] In this state, as shown in Table 1, if the TMS signal remains low, the TAP state machine will remain in the Run-Test / Idle state; if the TMS signal is high at the next rising edge of TCK, the TAP state machine will enter the Select-DR-Scan state.

[0101] The Select-DR-Scan state is the selection of the data register (DR) for scanning. In this state, the TAP state machine can prepare to perform operations such as shifting data on the DR, updating register contents, or capturing the current register state.

[0102] In this state, as shown in Table 1, if the TMS signal is low at the next rising edge of TCK, the TAP state machine will enter the Capture-DR state; if the TMS signal is high at the next rising edge of TCK, the TAP state machine will enter the Select-IR-Scan state.

[0103] The Capture-DR state is the capture data register state, used to capture data from the data register and load the captured data into the shift register, so as to ensure that the data transmission device can send new data to the data register through the TDI signal, or obtain the captured data from the shift register through the TDO signal.

[0104] In this state, as shown in Table 1, if the TMS signal is low at the next rising edge of TCK, the TAP state machine will enter the Shift-DR state; if the TMS signal is high at the next rising edge of TCK, the TAP state machine will enter the Exit1-DR state.

[0105] The Shift-DR state is the shift data register state. In this state, during each clock cycle, such as at the rising edge of each TCK signal, the TDI-Shift Register-TDO serial channel will shift one bit to the right. That is, one bit of data from TDI will be shifted into the shift register, and the bit of data in the shift register closest to TDO will be shifted to the TDO pin.

[0106] In this state, as shown in Table 1, if the TMS signal remains low, the TAP state machine will remain in the Shift-DR state, i.e., it will continue to perform shift operations; if the TMS signal is high at the next rising edge of TCK, the TAP state machine will enter the Exit1-DR state.

[0107] The Exit1-DR state is the exit data register state 1, which means exiting either the Shift-DR state or the Capture-DR state.

[0108] In this state, as shown in Table 1, if the TMS signal is low at the next rising edge of TCK, the TAP state machine will enter the Pause-DR state; if the TMS signal is high at the next rising edge of TCK, the TAP state machine will enter the Update-DR state, so as to choose to pause the shift operation or load the shift data based on the actual usage requirements.

[0109] The Pause-DR state is the pause data register state. In this state, the TAP state machine will pause the shift operation of the aforementioned TDI-Shift Register-TDO serial channel.

[0110] In this state, as shown in Table 1, if the TMS signal remains low, the TAP state machine will remain in the Pause-DR state; if the TMS signal is high at the next rising edge of TCK, the TAP state machine will enter the Exit2-DR state.

[0111] The Exit2-DR state is the exit data register state 2, which is equivalent to exiting the Pause-DR state. In this state, the TAP state machine exits the shift pause state to choose whether to end the DR scan or re-enter the Shift-DR state based on actual usage needs.

[0112] In this state, as shown in Table 1, if the TMS signal is low at the next rising edge of TCK, the TAP state machine will re-enter the Shift-DR state; if the TMS signal is high at the next rising edge of TCK, the TAP state machine will enter the Update-DR state, and the DR scan has ended.

[0113] The Update-DR state is the data register update state. In this state, the TAP state machine will end the DR scan and load the data in the shift register into the destination register.

[0114] In this state, as shown in Table 1, if the TMS signal is low at the next rising edge of TCK, the TAP state machine will enter the Run-Test / Idle state; if the TMS signal is high at the next rising edge of TCK, the TAP state machine will enter the Select-DR-Scan state.

[0115] Select-IR-Scan is the selection state for scanning the Instruction Register (IR). In this state, the TAP state machine can prepare to perform operations such as shifting data, updating register contents, or capturing the current register state on the IR.

[0116] In this state, as shown in Table 1, if the TMS signal is low at the next rising edge of TCK, the TAP state machine will enter the Capture-IR state; if the TMS signal is high at the next rising edge of TCK, the TAP state machine will enter the Test-Logic-Reset state.

[0117] The Capture-IR state is the command register capture state, used to capture data from the command register and load the captured data into a shift register. This ensures that the data transmission device can send new data to the command register via the TDI signal or retrieve the captured data from the shift register via the TDO signal. Optionally, in this state, the value in the command register is fixed at 0b0000001, and this value is placed in the shift register connected between TDI and TDO.

[0118] In this state, as shown in Table 1, if the TMS signal is low at the next rising edge of TCK, the TAP state machine will enter the Shift-IR state; if the TMS signal is high at the next rising edge of TCK, the TAP state machine will enter the Exit1-IR state.

[0119] The Shift-IR state is the shift instruction register state. In this state, within each clock cycle, such as on the rising edge of each TCK signal, the TDI-Shift Register-TDO serial channel shifts one bit to the right. That is, one bit of data from TDI is shifted into the shift register, and the bit closest to TDO in the shift register is shifted onto the TDO pin. Optionally, in this state, JTAG instructions are shifted bit by bit from the TDI pin into the shift register, while 0b0000001 in the shift register is shifted bit by bit out from the TDO pin.

[0120] In this state, as shown in Table 1, if the TMS signal remains low, the TAP state machine will remain in the Shift-IR state, i.e., it will continue to perform shift operations; if the TMS signal is high at the next rising edge of TCK, the TAP state machine will enter the Exit1-IR state.

[0121] The Exit1-IR state is the exit instruction register state 1, which means exiting either the Shift-IR state or the Capture-IR state.

[0122] In this state, as shown in Table 1, if the TMS signal is low at the next rising edge of TCK, the TAP state machine will enter the Pause-IR state; if the TMS signal is high at the next rising edge of TCK, the TAP state machine will enter the Update-IR state to select whether to pause the shift operation or load the shift data based on actual usage requirements.

[0123] The Pause-IR state is the pause instruction register state. In this state, the TAP state machine will pause the shift operation of the aforementioned TDI-Shift Register-TDO serial channel.

[0124] In this state, as shown in Table 1, if the TMS signal remains low, the TAP state machine will remain in the Pause-IR state; if the TMS signal is high at the next rising edge of TCK, the TAP state machine will enter the Exit2-IR state.

[0125] The Exit2-IR state is the exit instruction register state 2, which is to exit the Pause-IR state. In this state, the TAP state machine will exit the shift pause state to choose whether to end the IR scan or re-enter the Shift-IR state based on actual usage needs.

[0126] In this state, as shown in Table 1, if the TMS signal is low at the next rising edge of TCK, the TAP state machine will re-enter the Shift-IR state; if the TMS signal is high at the next rising edge of TCK, the TAP state machine will enter the Update-IR state to end the IR scan.

[0127] The Update-IR state is the update instruction register state. In this state, the TAP state machine will end the IR scan and load the data in the shift register into the destination register.

[0128] In this state, as shown in Table 1, if the TMS signal is low at the next rising edge of TCK, the TAP state machine will enter the Run-Test / Idle state; if the TMS signal is high at the next rising edge of TCK, the TAP state machine will enter the Select-DR-Scan state.

[0129] Optionally, referring to Table 1 above, the processing module 1 sends status data to the transceiver module 2, which in turn sends status data to the JTAG slave device, such as sending status data to the TAP state machine of the JTAG slave device, thereby adjusting the test status of the JTAG slave device; and the processing module 1 sends test data to the transceiver module 2, which in turn sends test data to the JTAG slave device, such as sending test data to the data register or instruction register of the JTAG slave device via the TDI pin, thereby realizing the testing of the JTAG slave device.

[0130] Optionally, the transceiver module 2 can obtain output data from the JTAG slave device, such as by obtaining output data from the JTAG slave device through the TDO pin. The processing module 1 then obtains the output data from the transceiver module 2 and verifies the JTAG slave device based on the output data, thereby realizing the testing of the JTAG slave device.

[0131] In some embodiments, combined with Figure 3 The data transmission process between the data transmission device and the JTAG slave device can be as follows: Figure 7 As shown.

[0132] Combination Figure 7 The transmission process includes the following steps:

[0133] (1) Processing module 1 acquires multi-bit status data and input data.

[0134] (2) Processing module 1 sends multi-bit status data and multi-bit input data to transceiver module 2.

[0135] (3) The transceiver module 2 stores multiple status data and multiple input data.

[0136] (4) The transceiver module 2 sends status data and input data bit by bit.

[0137] (5) JTAG sends output data bit by bit from the device to transceiver module 2.

[0138] (6) The transceiver module 2 acquires the output data bit by bit.

[0139] (7) Transceiver module 2 stores the output data.

[0140] (8) Processing module 1 reads output data from transceiver module 2.

[0141] Optionally, such as Figure 7 As shown, transceiver module 2 can also verify JTAG slave devices, such as by verifying JTAG slave devices based on the read output data.

[0142] Optionally, such as Figure 7As shown, transceiver module 2 can send status data bit by bit through the TMS line between itself and the JTAG slave device, send input data bit by bit through the TDI line, and acquire output data bit by bit through the TDO line.

[0143] In some embodiments, such as Figure 7 As shown, transceiver module 2, while sending status data and input data bit by bit to the JTAG slave device, can also generate and send a clock signal, such as... Figure 7 The clock signal is sent via the TCK line between the JTAG slave device and the JTAG slave device. This provides a clock reference for the JTAG slave device, ensuring that all JTAG signals (such as TMS and TDI signals) are sampled and processed simultaneously on the JTAG slave device side. Specifically, it ensures that all signals are sampled and processed by the JTAG slave device on the same clock edge (such as the rising edge of the TCK), thus maintaining precise synchronization in the processing of each signal.

[0144] In some embodiments, the storage method of the transceiver module 2 for storing the aforementioned status data, output data, and input data can be flexibly selected based on actual usage requirements. For example, the transceiver module 2 may include one or more data registers to cache status data, output data, and / or input data. Alternatively, the transceiver module 2 may also include (or be connected to) one or more memories to store the status data, output data, and / or input data.

[0145] For example, the transceiver module 2 may include a first data register, a second data register, and a third data register. The first data register is used to buffer input data from the processing module 1; the second data register is used to buffer output data from the JTAG slave device; and the third data register is used to buffer status data from the processing module 1.

[0146] As another example, the transceiver module 2 may include a first memory, a second memory, and a third memory. The first memory is used to store input data from the processing module 1, the second memory is used to store output data from the JTAG slave device, and the third memory is used to store status data from the processing module 1.

[0147] In some embodiments, the processing module 1 may send input data to the transceiver module 2 based on the input data storage status of the transceiver module 2.

[0148] The input data storage status is used to indicate the status of the input data stored by the transceiver module 2.

[0149] For example, such as Figure 8As shown, the transceiver module 2 may include a first data register, which is used to buffer input data from the processing module 1. When the first data register can normally receive input data, the transceiver module 2 can set the input data storage status to a normal state. When the input data status is in a normal state, the processing module 1 sends the input data to the transceiver module 2.

[0150] If the first data register cannot receive input data normally, the transceiver module 2 can set the input data status to an abnormal state. If the input data storage status is abnormal, the processing module 1 will no longer send input data to the transceiver module 2 until the input data storage status is restored to normal.

[0151] The size of the first data register can be flexibly selected based on actual usage requirements; for example, the first data register can be a 32-bit register. In this scenario, processing module 1 can send 32 bits of input data to the first data register at once. Transceiver module 2 can set the input data storage status to a normal state when the 32 bits of data have been completely sent, indicating that input data can be received normally; and set the input data storage status to an abnormal state when the 32 bits of data have not been completely sent, indicating that the data in the register has not been completely sent and input data cannot be received.

[0152] Optionally, the first data register can be a TDI register, i.e., a register used to buffer data transmitted through the TDI line.

[0153] In some embodiments, the processing module 1 can read output data from the transceiver module 2 based on the output data storage status of the transceiver module 2.

[0154] The output data storage status is used to indicate the status of the output data stored by the transceiver module 2.

[0155] For example, such as Figure 8 As shown, the transceiver module 2 may include a second data register, which is used to buffer output data from the JTAG slave device. When the second data register can transmit output data normally, the transceiver module 2 can set the output data storage status to a normal state. When the output data status is in a normal state, the processing module 1 reads the output data from the transceiver module 2.

[0156] If the second data register fails to send output data normally, the transceiver module 2 can set the output data status to an abnormal state. If the output data storage status is abnormal, the processing module 1 will no longer read output data from the transceiver module 2 until the output data storage status is restored to normal.

[0157] The size of the second data register can be flexibly selected based on actual usage requirements; for example, the second data register can be a 32-bit register. In this scenario, the transceiver module 2 can accumulate and store 32 bits of output data in the second data register. When the second data register buffers 32 bits of output data, the transceiver module 2 can set the output data storage status to a normal state to indicate that output data can be sent normally; when the second data register is not full of 32 bits of output data, the output data storage status can be set to an abnormal state to indicate that the register is not full and output data cannot be sent.

[0158] Optionally, the second data register can be a TDO register, which is a register used to buffer data transmitted through the TDO line.

[0159] In some embodiments, the processing module 1 may send status data to the transceiver module 2 based on the status data storage status of the transceiver module 2.

[0160] The status data storage status is used to indicate the status of the status data stored by the transceiver module 2.

[0161] For example, such as Figure 8 As shown, the transceiver module 2 may include a third data register, which is used to buffer status data from the processing module 1. When the third data register can normally receive status data, the transceiver module 2 can set the status data storage status to a normal state. When the status data status is normal, the processing module 1 sends the status data to the transceiver module 2.

[0162] If the third data register cannot receive status data normally, the transceiver module 2 can set the status data status to an abnormal state. If the status data storage status is abnormal, the processing module 1 will no longer send status data to the transceiver module 2 until the status data storage status is restored to the normal state.

[0163] The size of the third data register can be flexibly selected based on actual usage requirements; for example, the third data register can be a 32-bit register. In this scenario, processing module 1 can send 32 bits of status data to the third data register at once. Transceiver module 2 can set the status data storage status to a normal state when the 32 bits of data have been completely sent, indicating that status data can be received normally; and set the status data storage status to an abnormal state when the 32 bits of data have not been completely sent, indicating that the data in the register has not been completely sent and status data cannot be received.

[0164] Optionally, the third data register can be a TMS register, i.e., a register used to buffer data transmitted through the TMS line.

[0165] In some embodiments, the first data register, the second data register, and the third data register may be the same data register or different data registers, and can be flexibly set according to actual usage requirements.

[0166] In some embodiments, such as Figure 9 As shown, the transceiver module 2 may include a status register, which is used to indicate the input data storage status, output data storage status and / or status data storage status of the transceiver module 2.

[0167] Processing module 1 can determine the input data storage status, output data storage status, and / or status data storage status of transceiver module 2 based on the status register area.

[0168] Optionally, the status register can be flexibly configured based on actual usage requirements, such as data transmission requirements.

[0169] Taking the need to transmit status data, input data, and output data between a data transmission device and a JTAG slave device as an example, the status register can include a 3-bit signal, wherein the first bit signal is used to indicate the input data storage status, the second bit signal is used to indicate the output data storage status, and the third bit signal is used to indicate the status data storage status.

[0170] When the first signal is high, it indicates that the transceiver module 2 can receive status data from the processing module 1 normally. At this time, the processing module 1 can send status data to ensure that the status data can be accurately received by the transceiver module 2.

[0171] When the second signal is high, it indicates that the transceiver module 2 can normally receive input data from the processing module 1. At this time, the processing module 1 can send input data to ensure that the input data can be accurately received by the transceiver module 2.

[0172] When the third signal is high, it indicates that the transceiver module 2 can send output data to the processing module 1 normally. At this time, the processing module 1 can read the output data from the transceiver module 2 to ensure that the output data can be accurately read by the processing module 1.

[0173] The embodiments of this application are illustrated below with reference to specific application scenarios. Taking the boundary scanning of a JTAG slave device based on input data as an example, the data transmission device can perform boundary scanning of a JTAG slave device through the following steps:

[0174] (1) Data transmission

[0175] Processing module 1 sends multiple status data and input data to transceiver module 2. Transceiver module 2 stores the status data in the TMS register and sends it bit by bit to make the TAP state machine enter the corresponding state. Transceiver module 2 stores the input data in the TDI register and sends it bit by bit to realize boundary detection of JTAG slave device.

[0176] (2) TAP reset state machine

[0177] Transceiver module 2 sets TMS=1 and sends multiple TCK pulses to reset the TAP state machine to the Test-Logic-Reset state.

[0178] (3) Enter IDLE state

[0179] In the Test-Logic-Reset state, transceiver module 2 sets TMS=0 and sends a TCK pulse, causing the TAP state machine to enter the Run-Test / Idle state.

[0180] (4) Select IR scan path

[0181] In Run-Test / Idle state, transceiver module 2 sets TMS=1 and sends a TCK pulse, causing the TAP state machine to enter the Select-IR-Scan state.

[0182] In Select-IR-Scan state, transceiver module 2 sets TMS=0 and sends a TCK pulse to cause the TAP state machine to enter Capture-IR state.

[0183] (5) Shift IR

[0184] In Capture-IR state, transceiver module 2 sets TMS=0 and sends a TCK pulse to cause the TAP state machine to enter Shift-IR state.

[0185] In Shift-IR mode, transceiver module 2 sends instruction data (i.e., input data) bit by bit from the TDI register to the instruction register of the JTAG slave device via the TDI pin. In each clock cycle (TCK cycle), one bit of data is shifted into the instruction register of the JTAG slave device; one bit of data is shifted from the instruction register of the JTAG slave device to the TDO pin and sent to the TDO register of transceiver module 2 via the TDO line.

[0186] (6) Update IR

[0187] In the Shift-IR state, if the transceiver module 2 completes the shift of the instruction data, the transceiver module 2 sets TMS=1 and sends a TCK pulse to cause the TAP state machine to enter the Exit1-IR state.

[0188] In the Exit1-IR state, transceiver module 2 sends TMS=1 and sends a TCK pulse to cause the TAP state machine to enter the Update-IR state and load the boundary scan instruction.

[0189] (7) Select DR scan path

[0190] In the Update-IR state, transceiver module 2 sets TMS=1 and sends a TCK pulse to cause the TAP state machine to enter the Select-DR-Scan state.

[0191] In Select-DR-Scan state, transceiver module 2 sets TMS=0 and sends a TCK pulse to cause the TAP state machine to enter Capture-DR state.

[0192] (8) Shift DR

[0193] In the Capture-DR state, transceiver module 2 sets TMS=0 and sends a TCK pulse to cause the TAP state machine to enter the Shift-DR state.

[0194] In Shift-DR mode, transceiver module 2 sends test data (i.e., input data) bit by bit from the TDI register to the data register of the JTAG slave device via the TDI pin, controlling the I / O pin status of the JTAG slave device. Each clock cycle (TCK cycle), one bit of data is shifted into the JTAG slave device's data register; the shifted data is then shifted from the JTAG data register to the TDO pin and sent to the TDO register of transceiver module 2 via the TDO line.

[0195] (9) Update DR

[0196] In the Shift-DR state, transceiver module 2 sets TMS=1 and sends a TCK pulse to cause the TAP state machine to enter the Exit1-DR state.

[0197] In the Exit1-DR state, transceiver module 2 sets TMS=0 and sends a TCK pulse to cause the TAP state machine to enter the Update-DR state and complete the data loading.

[0198] (10) Perform the test

[0199] In the Update-DR state, transceiver module 2 sets TMS=0 and sends a TCK pulse to cause the TAP state machine to enter the Run-Test / Idle state.

[0200] In the Run-Test / Idle state, transceiver module 2 sets TMS=0 and sends multiple TCK pulses to keep the TAP state machine in the Run-Test / Idle state, waiting for the test to complete.

[0201] While the TAP state machine remains in the Run-Test / Idle state, the JTAG slave device's boundary scan register controls the state of the I / O pins based on the instructions sent by transceiver module 2 and stores the state response.

[0202] (11) Read the test results

[0203] In Run-Test / Idle state, transceiver module 2 sets the TMS signal, causing the TAP state machine to re-enter the Shift-DR state. It reads the I / O pin status of the JTAG slave device bit by bit through the TDO pin and stores it in the TDO register.

[0204] For example, in the Run-Test / Idle state, transceiver module 2 sets TMS=1 and sends a TCK pulse to cause the TAP state machine to enter the Select-DR-Scan state; in the Select-DR-Scan state, transceiver module 2 sets TMS=0 and sends a TCK pulse to cause the TAP state machine to enter the Capture-DR state; in the Capture-DR state, transceiver module 2 sets TMS=0 and sends a TCK pulse to cause the TAP state machine to enter the Shift-DR state.

[0205] (12) Completion and Verification

[0206] The transceiver module 2 stores the test results returned from the JTAG slave device. The processing module 1 reads these test results to confirm whether the test was successfully executed and performs necessary verification. If an error occurs, the processing module 1 can take corrective measures, such as resending the command or reporting the problem.

[0207] In the above embodiments, processing module 1 can acquire multiple status data and input data at once and send them to transceiver module 2; transceiver module 2 sends the status data and input data bit by bit, thereby realizing the testing of JTAG slave device; and transceiver module 2 acquires and stores the test results from JTAG slave device bit by bit; when processing module 1 needs to verify the test results, it directly reads the test results from transceiver module 2 for verification, thereby improving the data transmission efficiency between the processor and the JTAG slave device, and thus improving the testing efficiency of the JTAG slave device.

[0208] Based on the same inventive concept, embodiments of this application also provide a data transmission system. Figure 10 This is a schematic diagram of the architecture of a data transmission system provided in an embodiment of this application, such as... Figure 10 As shown, the system includes a data transmission device 1001 and a JTAG slave device 1002. The data transmission device 1001 can be the data transmission device 300 described above.

[0209] Optionally, the JTAG slave device can be an FPGA device.

[0210] Optionally, for a more detailed description of the data transmission device 1001, please refer to the relevant description of the data transmission device 300 above, which will not be repeated here.

[0211] Based on the same inventive concept, this application also provides a data transmission method. Figure 11 This is a flowchart illustrating a data transmission method provided in an embodiment of this application. This method can be applied to the aforementioned data transmission system. Please refer to... Figure 11 The method includes the following steps:

[0212] S1101: The processing module sends input data to the transceiver module.

[0213] The input data consists of data that needs to be sent to the JTAG slave device of the Joint Working Test Group.

[0214] Optionally, the processing module can send input data to the transceiver module based on the input data storage status of the transceiver module, whereby the input data storage status indicates the state in which the transceiver module stores the input data.

[0215] S1102: The transceiver module stores input data and sends input data to the JTAG slave device.

[0216] In some embodiments, the transceiver module can store output data from the JTAG slave device. The output data is obtained by the JTAG slave device based on the input data. The processing module can read the output data from the transceiver module.

[0217] Optionally, the processing module can read output data from the transceiver module based on the output data storage status of the transceiver module, whereby the output data storage status indicates the state in which the transceiver module stores the output data.

[0218] In some embodiments, the processing module can send status data to the transceiver module. This status data is used to control the operating status of the JTAG slave device. The transceiver module can store the status data and send it to the JTAG slave device.

[0219] Optionally, the processing module can send status data to the transceiver module based on the status data storage status of the transceiver module, whereby the status data storage status is used to indicate the status of the transceiver module storing status data.

[0220] In some embodiments, the transceiver module includes a status register, which is used to indicate the input data storage status, output data storage status, and / or status data storage status of the transceiver module.

[0221] The processing module can determine the input data storage status, output data storage status, and / or status data storage status of the transceiver module based on the status register area.

[0222] Optionally, for a more detailed description of the actions performed by the above-mentioned processing module and transceiver module, please refer to the above-mentioned description of the data transmission device 300, which will not be repeated here.

[0223] It should be understood that, in the embodiments of this application, for a technical feature, the technical features in that technical feature are distinguished by "first", "second" and "third", and there is no order of precedence or size among the technical features described by "first", "second" and "third".

[0224] Furthermore, the term "and / or" in this application is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship. The term "at least one" in this application can represent "one" and "two or more." For example, A, B, and C can represent: A existing alone, B existing alone, C existing alone, A and B existing simultaneously, A and C existing simultaneously, C and B existing simultaneously, and A, B, and C existing simultaneously.

[0225] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0226] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0227] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0228] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0229] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0230] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0231] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A data transmission apparatus, characterized by comprising: include: The processing module and the transceiver module are connected to each other. The processing module is used to send input data to the transceiver module, wherein the input data is data that needs to be sent to the JTAG slave device of the Joint Working Test Group; The transceiver module is used to store the input data and send the input data to the JTAG slave device.

2. The data transmission device of claim 1, wherein The transceiver module is also used to store output data from the JTAG slave device, the output data being obtained by the JTAG slave device based on the input data; The processing module is also used to read the output data from the transceiver module.

3. The apparatus of claim 1 or 2, wherein, The processing module is also used to send status data to the transceiver module, and the status data is used to control the working status of the JTAG slave device. The transceiver module is also used to store the status data and send the status data to the JTAG slave device.

4. The apparatus of claim 1, wherein, The processing module is specifically used for: Based on the input data storage status of the transceiver module, the input data is sent to the transceiver module, and the input data storage status is used to indicate the state in which the transceiver module stores the input data.

5. The apparatus of claim 2, wherein, The processing module is specifically used for: Based on the output data storage status of the transceiver module, the output data is read from the transceiver module, and the output data storage status is used to indicate the state in which the transceiver module stores the output data.

6. The apparatus of claim 3, wherein, The processing module is specifically used for: Based on the status data storage status of the transceiver module, the status data is sent to the transceiver module, and the status data storage status is used to indicate the status of the transceiver module storing the status data.

7. The device of any one of claims 4-6, wherein, The transceiver module includes a status register, which is used to indicate the input data storage status, output data storage status, and / or status data storage status of the transceiver module. The processing module is further configured to determine the input data storage status, output data storage status, and / or status data storage status of the transceiver module based on the status register area.

8. The device of any one of claims 1-3, wherein, The transceiver module includes a data register; The data register is used to store the input data, output data, and / or status data.

9. The apparatus of claim 1, wherein, The transceiver module is a JTAG controller.

10. A data transmission system, characterized by Includes the data transmission device as described in any one of claims 1-9 and the JTAG slave device.

11. A data transmission method, characterized by, Applied to the system of claim 10, comprising: The processing module sends input data to the transceiver module, which is the data that needs to be sent to the JTAG slave device of the Joint Working Test Group; The transceiver module stores the input data and sends the input data to the JTAG slave device.

12. The method of claim 10, wherein, The method further includes: The transceiver module stores output data from the JTAG slave device, which is obtained by the JTAG slave device based on the input data. The processing module reads the output data from the transceiver module.

13. The method according to claim 10 or 12, characterized in that, The method further includes: The processing module sends status data to the transceiver module, and the status data is used to control the working status of the JTAG slave device. The transceiver module stores the status data and sends the status data to the JTAG slave device.

14. The method of claim 10, wherein, The processing module sends input data to the transceiver module, including: The processing module sends the input data to the transceiver module based on the input data storage status of the transceiver module. The input data storage status is used to indicate the state in which the transceiver module stores the input data.

15. The method of claim 12, wherein, The processing module reads the output data from the transceiver module, including: The processing module reads the output data from the transceiver module based on the output data storage status of the transceiver module. The output data storage status is used to indicate the state in which the transceiver module stores the output data.

16. The method of claim 13, wherein, The processing module sends status data to the transceiver module, including: The processing module sends the status data to the transceiver module based on the status data storage status of the transceiver module. The status data storage status is used to indicate the status of the transceiver module storing the status data.

17. The method according to any one of claims 14-16, characterized in that, The transceiver module includes a status register, which indicates the input data storage status, output data storage status, and / or status data storage status of the transceiver module; the method further includes: The processing module determines the input data storage status, output data storage status, and / or status data storage status of the transceiver module based on the status register area.

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