A quantum circuit compiling method and system

Abstract

This disclosure provides a quantum circuit compilation method and system. The method includes: based on a target quantum algorithm, sequentially performing high-dimensional unitary gate and / or two-bit gate renormalization processing on the quantum logic circuit to be compiled to obtain a first optimized circuit; determining a sub-topology structure for executing the first optimized circuit; establishing an initial mapping between the logical bits of the first optimized circuit and the physical bits of the sub-topology structure; dynamically adjusting the mapping relationship between the logical bits and physical bits through insertion swapping gates, so that the physical bits corresponding to the logical bits of the first circuit are adjacent in the sub-topology structure during execution, to obtain a second optimized circuit; and sequentially performing single-bit gate renormalization and gate sequence temporal rearrangement. This not only improves the comprehensiveness and accuracy of the compilation process but also significantly enhances the executability of quantum circuits on resource-constrained hardware, effectively reducing circuit depth and the number of gates, lowering the processing difficulty for subsequent mapping and routing, and effectively reducing overall hardware resource overhead.

Description

Technical Field

[0001] This disclosure relates to the field of quantum computing, and in particular to a quantum circuit compilation method and system. Background Technology

[0002] Quantum computing, a cutting-edge information technology, is gradually breaking through the limits of traditional computing power, bringing unprecedented hope for solving complex problems in fields such as chemical simulation, optimization, and cryptography. However, quantum algorithms still face core challenges in the deployment of real quantum hardware, including high-precision gate decomposition, hardware topology adaptation, and noise accumulation suppression. Existing quantum compilation technologies are limited by gate-level error accumulation, deep redundancy of circuits, and timing scheduling deviations. On the one hand, this results in algorithm fidelity and efficiency far below theoretical limits; on the other hand, it requires significant resource overhead. Both of these factors severely restrict the practical application of complex quantum algorithms. Summary of the Invention

[0003] To address the aforementioned problems with existing quantum compilation technologies, a quantum circuit compilation method and system are provided.

[0004] Firstly, this disclosure provides a quantum circuit compilation method, including the following steps: Based on the target quantum algorithm, the quantum logic circuit to be compiled is sequentially subjected to high-dimensional unitary gate and / or two-qubit gate renormalization processes to obtain the first optimized circuit. Based on the number of qubits in the quantum logic circuit and the topology of the target quantum hardware, a sub-topology for executing the first optimized circuit is determined; an initial mapping is established between the logic bits of the first optimized circuit and the physical bits of the sub-topology; based on the initial mapping, the mapping relationship between the logic bits and the physical bits is dynamically adjusted by inserting a switching gate, so that the physical bits corresponding to the logic bits of the first circuit are adjacent to each other on the sub-topology during execution, thus obtaining the second optimized circuit; for the second optimized circuit, single-bit gate renormalization and gate sequence time rearrangement are performed sequentially.

[0005] In some possible embodiments, the step of performing high-dimensional unitary gate and / or two-qubit gate renormalization processing on the quantum logic circuit to be compiled based on the target quantum algorithm to obtain a first optimized circuit includes: determining whether the quantum logic circuit to be compiled contains the high-dimensional unitary gate; if so, performing renormalization processing on the high-dimensional unitary gate to obtain native single-qubit and two-qubit quantum gates supporting the target quantum hardware, as the output of the first optimized circuit; if not, directly performing renormalization processing on the two-qubit gate to obtain native single-qubit and two-qubit quantum gates supporting the target quantum hardware, as the output of the first optimized circuit.

[0006] In some possible embodiments, determining the sub-topology for executing the first optimized circuit based on the number of qubits of the quantum logic circuit and the topology of the target quantum hardware includes: determining the logic circuit topology of the quantum logic circuit based on the number of qubits of the quantum logic circuit; and selecting the subset of physical bits that best matches the topology of the quantum logic circuit as the sub-topology based on the physical topology of the target quantum hardware.

[0007] In some possible embodiments, establishing an initial mapping between the logical bits of the first optimized line and the physical bits of the sub-topology includes: binding the logical bits of the first optimized line and the physical bits of the sub-topology using any one of the SABRE algorithm, BFS algorithm, or DFS search algorithm to form an initial mapping between the logical bits and the physical bits.

[0008] In some possible embodiments, the step of dynamically adjusting bit positions based on the initial mapping through switching gates so that the physical bits corresponding to the logical bits of the first line are adjacent to each other on the sub-topology during execution, to obtain a second optimized line, includes: based on the initial mapping; determining the number of switching gates and the line depth through path planning or gate sequence rearrangement; and dynamically adjusting the mapping relationship between the logical bits and the physical bits through the determined switching gates so that the physical bits corresponding to the logical bits of the first line are adjacent to each other on the sub-topology during execution, to obtain a second optimized line.

[0009] In some possible embodiments, performing single-bit gate renormalization sequentially on the second optimized line includes: merging and then decomposing adjacent single-bit gates on the second optimized line to complete the single-bit gate renormalization process.

[0010] In some possible embodiments, the time-series rearrangement of the gate sequence after the single-qubit gate renormalization process includes: rearranging the quantum gates after the single-qubit gate renormalization process according to the hardware timing constraints of the target quantum hardware.

[0011] In some possible embodiments, the renormalization of the high-dimensional unitary gate includes decomposing any high-dimensional unitary gate into a sequence of basic quantum gates supported by the target quantum hardware, the sequence of basic quantum gates including native single-qubit and two-qubit quantum gates supporting the target quantum hardware; and / or the renormalization of the two-qubit gate includes decomposing any two-qubit gate into a combination of two-qubit entangled gates and single-qubit gates supported by the target quantum hardware; and / or the renormalization of the single-qubit gate includes decomposing any single-qubit gate into a basic rotation gate supported by the target quantum hardware.

[0012] Secondly, this disclosure also includes a quantum circuit compilation system comprising: a quantum circuit renormalization module, used to sequentially perform high-dimensional unitary gate and / or two-qubit gate renormalization processing on the quantum logic circuit to be compiled based on the target quantum algorithm to obtain a first optimized circuit; a quantum physical bit selection module, used to determine a sub-topology for executing the first optimized circuit based on the number of qubits of the quantum logic circuit and the topology of the target quantum hardware; a quantum circuit initial mapping module, used to establish an initial mapping between the logic bits of the first optimized circuit and the physical bits of the sub-topology; a quantum bit routing optimization module, based on the initial mapping, dynamically adjusting the bit positions through quantum switching gates so that the physical bits corresponding to the logic bits of the first circuit are adjacent to each other on the sub-topology during execution, to obtain a second optimized circuit; and a quantum circuit timing reordering module, used to perform gate sequence timing reordering after the quantum circuit renormalization module performs single-qubit gate renormalization on the second optimized circuit.

[0013] In some possible embodiments, the quantum circuit compilation system further includes: The module includes a standard gate library for storing parameters of various logic gates supported by quantum algorithms and the target quantum hardware; a quantum circuit management module for outputting corresponding quantum logic circuits based on quantum circuits; a quantum gate decomposition algorithm module for decomposing any quantum gate into a sequence of basic gates supported by the target quantum hardware; a quantum circuit compilation module for building a complete compilation pipeline to generate quantum programs executable by the target quantum hardware; and an auxiliary function module for providing the target quantum hardware interface and execution configuration.

[0014] The above technical solution has the following advantages or beneficial effects: By decomposing the compilation task into multiple subtasks in a multidimensional way and executing them synchronously or sequentially, not only can the comprehensiveness and accuracy of the compilation process be improved, but the executability of quantum circuits on resource-constrained hardware can also be significantly improved. This effectively reduces the circuit depth and the number of gates, making subsequent mapping and routing less difficult and reducing the overall hardware resource overhead. At the same time, based on the flexible adjustment of the compilation process, it can not only adapt to the characteristics of different hardware platforms, but also better output quantum circuits that are adapted to the hardware and meet the requirements of low noise and high efficiency. Attached Figure Description

[0015] Embodiments of this disclosure will be described more fully with reference to the accompanying drawings. However, the accompanying drawings are for illustration and explanation only and do not constitute a limitation on the scope of this disclosure.

[0016] Figure 1 This is a flowchart illustrating an embodiment of a quantum circuit compilation method disclosed herein; Figure 2 This is a schematic diagram illustrating the process of logic gate execution for a quantum logic circuit in an embodiment of a quantum circuit compilation method disclosed herein. Figure 3 This is a schematic diagram illustrating the implementation of a quantum circuit compilation system disclosed herein.

[0017] The reference numerals in the attached figures indicate: 1. Standard gate library module; 2. Quantum circuit management module; 3. Quantum gate decomposition algorithm module; 4. Quantum circuit renormalization module; 5. Quantum physics bit selection module; 6. Quantum circuit initial mapping module; 7. Quantum bit routing optimization module; 8. Quantum circuit timing reordering module; 9. Quantum circuit compilation function module; 10. Auxiliary function module. Detailed Implementation

[0018] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0019] It should be noted that, unless otherwise specified, the embodiments and features described in this disclosure can be combined with each other.

[0020] The present disclosure will be further described below with reference to the accompanying drawings and specific embodiments, but this should not be construed as limiting the present disclosure.

[0021] Existing sub-circuit compilation technologies mainly include the following two directions: Firstly, independent algorithm design is carried out for specific sub-problems in the compilation process (such as mapping or optimization). Although this design approach can solve specific sub-problems, from the perspective of the entire compilation process, it still has problems such as gate-level error accumulation and line depth redundancy, which make the overall compilation require more hardware resource overhead or have limitations in hardware execution. Secondly, by proposing a macroscopic framework, it is found that macroscopic-level compilation frameworks, while guiding the compilation of quantum circuits with high specific complexity, are difficult to support the development of efficient and standardized quantum software toolchains, resulting in low overall development efficiency.

[0022] Accordingly, this embodiment provides a quantum circuit compilation method to solve the above problems. The specific quantum circuit compilation method includes the following steps: Based on the target quantum algorithm, the quantum logic circuit to be compiled is sequentially subjected to high-dimensional unitary gate and / or two-qubit gate renormalization processing to obtain a first optimized circuit; based on the number of qubits of the quantum logic circuit and the topology of the target quantum hardware, a sub-topology structure for executing the first optimized circuit is determined; an initial mapping is established between the logical bits of the first optimized circuit and the physical bits of the sub-topology structure; based on the initial mapping, the mapping relationship between the logical bits and physical bits is dynamically adjusted by inserting a swap gate (such as a SWAP gate), so that the physical bits corresponding to the logical bits of the first circuit are adjacent to each other in the sub-topology structure during execution, resulting in a second optimized circuit; for the second optimized circuit, single-qubit gate renormalization and gate sequence time reordering are sequentially performed. In this embodiment, the quantum circuit compilation task can be decomposed as follows: the quantum circuit consists of... 1 logical qubit and A quantum gate The description states that the quantum gate can be any single-bit gate, two-bit gate, or higher-order unitary gate.

[0023] The quantum chip in the target quantum hardware has One physical quantum bit Its executable native gate set typically consists of a finite set of single-bit gates. and double-bit gate set The structure, for example, the native gate set of a superconducting quantum computer might include As a single-bit gate As a two-qubit gate, the actual target quantum hardware topology is usually not fully connected (such as a chain or lattice structure), so the two-qubit gate can only be executed between adjacent physical bits. The specific compilation steps are as follows... Figure 1 As shown, it includes: S1. Based on the target quantum algorithm, the quantum logic circuit to be compiled is sequentially subjected to high-dimensional unitary gate and / or two-qubit gate renormalization processing to obtain the first optimized circuit; so as to decompose the non-native gate into a sequence of native gates supported by the target quantum hardware; S2. Based on the number of qubits in the quantum logic circuit and the topology of the target quantum hardware, determine the sub-topology for executing the first optimized circuit; in order to select a suitable sub-topology from the chip; S3. Establish an initial mapping between the logical bits of the first optimized line and the physical bits of the sub-topology; to achieve the initial binding of logical bits and physical bits; S4. Based on the initial mapping, the mapping relationship between logical bits and physical bits is dynamically adjusted by inserting a switching gate, so that the physical bits corresponding to the logical bits of the first line are adjacent to each other in the sub-topology during execution, thus obtaining the second optimized line; so as to ensure that all two-bit gates satisfy the nearest neighbor constraint in the hardware (sub-topology). S5. For the second optimized circuit, perform single-bit gate renormalization and gate sequence timing rearrangement sequentially. Gate sequence timing rearrangement involves dividing parallel-operable gates into the same time interval to optimize the scheduling efficiency of the measurement and control system. Specifically, such as... Virtual phase gates, such as those with phase parameters, are often superimposed on the operations of other gates during waveform compilation. Therefore, their timing needs to be coordinated with other gates, rather than being compiled independently. Through steps S1-S5, the entire compilation task is broken down into subtasks in multiple dimensions. This ensures that the compilation process remains orderly while significantly improving the executability of quantum circuits on resource-constrained hardware. Furthermore, a multi-level logic gate (high-dimensional unitary gates, two-bit gates, and single-bit gates) renormalization strategy effectively reduces circuit depth and the number of gates, laying the foundation for subsequent mapping and routing optimization (adding insertion gate operations) and lowering overall resource overhead. It should be noted that steps S1-S5 do not necessarily impose a sequential execution constraint. For example, steps S1 and S2 can be processed in parallel or distributed during the compilation task, allowing for a better balance based on the platform's hardware resources to achieve comprehensive compilation.

[0024] In some possible embodiments, the process of sequentially performing high-dimensional unitary gate and / or two-bit gate renormalization on the quantum logic circuit to be compiled based on the target quantum algorithm to obtain a first optimized circuit includes: determining whether the quantum logic circuit to be compiled contains high-dimensional unitary gates; if so, renormalizing the high-dimensional unitary gates to obtain native single-bit and two-bit quantum gates supporting the target quantum hardware. The renormalization of the high-dimensional unitary gates mainly involves extracting the high-dimensional unitary gates from the quantum circuit and decomposing them into circuits composed of basic two-bit and single-bit gates, reducing the difficulty of subsequent optimization, and outputting this as the first optimized circuit. If not, directly performing renormalization on the two-bit gates to obtain native single-bit and two-bit quantum gates supporting the target quantum hardware, and outputting this as the first optimized circuit. The renormalization of the two-bit gates mainly involves synthesizing and then decomposing two-bit gate sub-blocks with consecutive identical active bits in the quantum circuit, thereby optimizing the two-bit gate sequence to reduce redundant operations, reduce the number of two-bit gates in the circuit, reduce the number of operations for quantum circuit mapping and bit routing, and improve parallel execution efficiency. In this embodiment, the specific steps include, as follows: Figure 2As shown: S11, determine whether the quantum logic circuit to be compiled contains high-dimensional unitary gates; if yes, proceed to step S12; if no, proceed to step S13; S12, then renormalize the high-dimensional unitary gates to obtain native single-bit and two-bit quantum gates supporting the target quantum hardware, as the first optimized circuit output; S13, directly renormalize the two-bit gates to obtain native single-bit and two-bit quantum gates supporting the target quantum hardware, as the first optimized circuit output. Through the above steps S11-S13, non-native gates are decomposed into a sequence of native gates supported by the hardware, effectively reducing the circuit depth and the number of gates, reducing the processing difficulty for subsequent mapping and routing, and reducing the overall resource overhead.

[0025] Furthermore, the high-dimensional unitary gates undergo renormalization. Optionally, this renormalization process includes decomposing any high-dimensional unitary gate into a sequence of fundamental quantum gates supported by the target quantum hardware. This sequence includes native single-qubit and two-qubit quantum gates supporting the target quantum hardware. Specifically, arbitrary high-dimensional unitary gate decomposition involves decomposing the high-dimensional unitary gate into a sequence of fundamental quantum gates supported by the target quantum hardware (e.g., for a superconducting quantum computer). This process is implemented through algorithms (such as QR decomposition) to ensure the universality of quantum circuits and provide structured input for subsequent compilation steps. Its core objective is to transform abstract quantum operations into executable hardware primitives, reducing the complexity of high-dimensional operations.

[0026] Furthermore, renormalization of two-bit gates can optionally include decomposing any two-bit gate into a combination of a two-bit entangled gate and a single-bit gate supported by the target quantum hardware; and / or renormalizing a single-bit gate includes decomposing any single-bit gate into a basic rotation gate supported by the target quantum hardware. Specifically, any two-bit gate (such as a universal controlled gate) is decomposed into a two-bit entangled gate supported by the target quantum hardware (such as...). or A combination of two-bit gates and single-bit gates. Implemented using matrix synthesis algorithms (such as KAK decomposition), ensuring the feasibility of two-bit operations while minimizing the number of gates and circuit depth after decomposition.

[0027] In some embodiments, performing single-bit gate renormalization sequentially on the second optimized circuit includes: merging and decomposing adjacent single-bit gates on the second optimized circuit to complete the single-bit gate renormalization process. In this embodiment, after inserting the swap gate, merging and decomposing adjacent single-bit gates reduces the number of single-bit gates to be executed, decreases the circuit depth, and reduces the running time, effectively reducing hardware resource overhead. Specifically, merging and decomposing adjacent single-bit gates includes decomposing any single-bit gate (such as any rotation gate) into a basic rotation gate supported by the target quantum hardware (such as...). and The combination of these methods, using Euler angle decomposition or rotation gate synthesis strategies, ensures the accurate implementation of single-bit gates. This step is fundamental to the low-level compilation of quantum circuits, guaranteeing the compatibility and accuracy of single-bit operations.

[0028] In some embodiments, the time-series rearrangement of the gate sequence after single-qubit gate renormalization includes: rearranging the quantum gates after single-qubit gate renormalization according to the hardware timing constraints of the target quantum hardware. In this embodiment, the time-series rearrangement of the gate sequence specifically considers factors such as... Leveraging the characteristics of virtual phase gates such as quantum gates, their phases are superimposed on the operations of other quantum gates for co-compilation, rather than being compiled independently into waveforms. Based on the hardware execution time of each type of gate, the circuitry is layered, with each layer corresponding to a set of operations that can be executed in parallel within the same time interval, thereby minimizing the total execution time.

[0029] In some embodiments, determining the sub-topology for executing the first optimized circuit based on the number of qubits in the quantum logic circuit and the topology of the target quantum hardware includes: determining the logical circuit topology of the quantum logic circuit based on the number of qubits in the quantum logic circuit; and selecting the subset of physical bits that best matches the topology of the quantum logic circuit as the sub-topology based on the physical topology of the target quantum hardware. In this embodiment, the selection of the sub-topology is based on the physical topology of the quantum processor (such as a mesh or a custom connection graph), selecting the subset of physical bits that best matches the logical circuit topology. During the selection process, graph isomorphic matching or heuristic search algorithms are used to ensure that connection conflicts during circuit mapping are minimized, while maximizing the utilization of hardware resources.

[0030] In some embodiments, establishing an initial mapping between the logical bits of the first optimized circuit and the physical bits of the sub-topology includes: binding the logical bits of the first optimized circuit to the physical bits of the sub-topology using any one of the SABRE algorithm, BFS algorithm, or DFS search algorithm, thus forming an initial mapping between logical bits and physical bits. In this embodiment, by initially binding logical qubits to physical bits, the connectivity constraints of the target quantum hardware for the two-qubit gate can be satisfied. The algorithms used are implemented through graph embedding or path planning techniques (such as the SABRE algorithm, BFS / DFS search) to ensure that the connectivity of the logical circuit is feasible on the target quantum hardware (physical hardware), while minimizing the overhead of subsequent bit routing.

[0031] In some possible embodiments, based on the initial mapping, the bit positions are dynamically adjusted through switching gates so that the physical bits corresponding to the logical bits of the first line are adjacent in the sub-topology during execution, resulting in a second optimized line. This includes: based on the initial mapping; determining the number of switching gates and the line depth through path planning or gate sequence rearrangement; and dynamically adjusting the mapping relationship between logical bits and physical bits through the determined switching gates so that the physical bits corresponding to the logical bits of the first line are adjacent in the sub-topology during execution, resulting in a second optimized line. After the initial mapping, bit discontinuities due to hardware connection limitations may still exist in the line. In this embodiment, based on the initial mapping, the positions of physical bits are dynamically adjusted by inserting switching gates (such as SWAP gates) to solve the bit discontinuity problem caused by hardware connection limitations in the line. Specific algorithms can minimize the number of switching gates and the line depth through path planning (such as based on the A* algorithm) or gate sequence rearrangement to ensure the efficiency of bit routing.

[0032] On the other hand, this disclosure also provides a quantum circuit compilation system, as shown in Figure 3, which includes: The quantum circuit renormalization module 4 is used to sequentially perform high-dimensional unitary gate and / or two-qubit gate renormalization processes on the quantum logic circuit to be compiled based on the target quantum algorithm to obtain the first optimized circuit. Specifically, the quantum circuit renormalization module 4 undertakes multi-level optimization tasks for the quantum circuit, aiming to transform the input circuit into an equivalent form with lower resource overhead and higher hardware execution efficiency through a series of gate merging, decomposition, and replacement rules. The quantum circuit renormalization module 4 sequentially performs optimization operations including high-dimensional unitary gate renormalization, two-qubit gate renormalization, and single-qubit gate renormalization.

[0033] The quantum physics bit selection module 5 is used to determine the sub-topology for executing the first optimized circuit based on the number of qubits in the quantum logic circuit and the topology of the target quantum hardware. Specifically, the quantum physics bit selection module 5 selects a suitable physical bit layout scheme according to the hardware topology and the number of bits required by the quantum logic circuit. The inputs of the quantum physics bit selection module 5 include hardware topology information such as the connectivity of the quantum chip and the number of bits to be selected. The output is the physical bit selection scheme, providing physical layer layout support for the initial mapping module and the bit routing module.

[0034] The quantum circuit initial mapping module 6 is used to establish an initial mapping between the logical bits of the first optimized circuit and the physical bits of the sub-topology. Specifically, the quantum circuit initial mapping module 6 maps the logical circuit to the selected physical bits, establishing an initial binding relationship between the logical bits and the physical bits. The quantum circuit initial mapping module 6 receives the layout scheme (sub-topology) of the first optimized circuit from the linear quantum circuit renormalization module 4 and the quantum physical bit selection module 5, outputs the initial mapping result, and sends it to the quantum bit routing optimization module 7 for subsequent communication optimization.

[0035] The qubit routing optimization module 7, based on the initial mapping, dynamically adjusts the bit positions through quantum swap gates, ensuring that the physical bits corresponding to the logical bits of the first path are adjacent in the sub-topology during execution, thus obtaining a second optimized path. Specifically, the qubit routing optimization module 7 optimizes the path by inserting SWAP gates, making all two-bit gates executable in the hardware topology and reducing the communication overhead between physical bits. Based on the initial mapping result and hardware topology information, the qubit routing optimization module 7 outputs a physical path with lower communication costs and passes it to the timing reordering module 8.

[0036] The quantum circuit timing reordering module 8 is used to perform gate sequence timing reordering on the second optimized circuit after the quantum circuit renormalization module 4 performs single-qubit gate renormalization. Specifically, the quantum circuit timing reordering module 8 adjusts the execution order of the gates according to the target quantum hardware timing constraints (such as gate delay and parallel execution requirements), and performs layering and scheduling of the circuit. This quantum circuit timing reordering module 8 receives the circuit after route optimization and single-qubit gate renormalization, outputs the final circuit that meets the hardware timing requirements, and outputs it to the real machine waveform compilation interface to ensure optimal execution efficiency.

[0037] In this embodiment, the aforementioned modules are integrated into system software. Each module performs sequential or iterative optimization (including multiple mappings and renormalizations), ultimately outputting a hardware-adaptive, low-noise, and high-efficiency quantum circuit. This integrated model needs to support dynamic adjustment of the optimization weights of each module to adapt to the characteristics of different hardware platforms.

[0038] In some implementations, the quantum circuit compilation system also includes a standard gate set library module 1, which stores various logic gate parameters, including those supported by quantum algorithms and target quantum hardware. It should be noted that the standard gate set library module 1 primarily provides the basic gate definitions for commonly used quantum algorithms and hardware support, serving as a reference standard for gate operations and decomposition across all modules of the system. This standard gate set library module 1 outputs a standard gate set (including gate definitions, parameters, etc.) to the quantum circuit management module 2, providing a unified gate operation benchmark for modules involved in gate decomposition and hardware adaptation.

[0039] In some implementations, the quantum circuit compilation system also includes a quantum circuit management module 2, which outputs corresponding quantum logic circuits based on the quantum circuits. It should be noted that the quantum circuit management module 2 is primarily responsible for parsing user-input quantum circuits (such as manually added circuits or QASM format files) and storing, standardizing, and outputting the circuits. This quantum circuit management module 2 converts the original quantum circuits into standardized data containing information such as logic gate sequences and logic bit numbers, and outputs it to multiple downstream modules (including quantum gate decomposition algorithm module 3, quantum circuit renormalization module 4, quantum circuit initial mapping module 6, quantum bit routing optimization module 7, and quantum circuit timing reordering module 8) for gate decomposition, circuit renormalization, initial mapping, bit routing, timing reordering, and compilation functions, serving as the starting point and data hub of the entire compilation process.

[0040] In some implementations, the quantum circuit compilation system also includes a quantum gate decomposition algorithm module 3, used to decompose any quantum gate into a basic gate sequence supported by the target quantum hardware. It should be noted that the quantum gate decomposition algorithm module 3 is used to implement the decomposition of any quantum gate into a basic gate sequence supported by the hardware. This quantum gate decomposition algorithm module 3 covers decomposition algorithms for arbitrary high-dimensional unitary gates, special high-dimensional unitary gates, arbitrary two-qubit gates, and arbitrary one-qubit gates, supporting methods based on KAK decomposition, QR decomposition, etc. Its input includes logic circuits and gate definitions from the standard gate set library of the quantum circuit management module 2, and its output is the decomposed basic gate sequence (e.g., decomposing a multi-qubit gate into a combination of one / two-qubit gates), which is then passed to the quantum circuit renormalization module 4 to provide a basic gate-level representation for subsequent optimization.

[0041] In some implementations, the quantum circuit compilation system also includes a quantum circuit compilation function module 9, which serves as the core coordination module. Based on the input quantum circuit, it calls upon various function modules to construct a complete compilation pipeline, generating a quantum program executable by the target hardware. This module receives the raw circuit from the quantum circuit management module 2, integrates the processing results from each stage, and outputs the final quantum program that can be delivered to a real machine for execution. In some implementations, the quantum circuit compilation system also includes an auxiliary function module 10, which provides general support functions for the system, including hardware interface adaptation, parameter configuration, error detection, and logging. This auxiliary function module 10 can receive inputs such as hardware description files and user configuration parameters, and provide global configuration support and low-level services to other modules in the system.

[0042] In one specific implementation, the quantum circuit compilation system includes: a standard gate library module 1, a quantum circuit management module 2, a quantum gate decomposition algorithm module 3, a quantum circuit renormalization module 4, a quantum physics bit selection module 5, a quantum circuit initial mapping module 6, a quantum bit routing optimization module 7, a quantum circuit timing reordering module 8, a quantum circuit compilation function module 9, and an auxiliary function module 10. The standard gate library module 1 provides gate definition standards; the quantum circuit management module 2 serves as a data hub for resolving, storing, and outputting circuits; and the quantum gate decomposition algorithm module 3 decomposes arbitrary quantum gates. The system comprises: a basic gate sequence; a quantum circuit renormalization module 4, which performs hierarchical renormalization optimization of high-dimensional unitary gates, two-qubit gates, and single-qubit gates; a quantum physical bit selection module 5, responsible for selecting the physical bit layout; a quantum circuit initial mapping module 6, which establishes the initial binding of logical-physical bits; a quantum bit routing optimization module 7, which optimizes communication by inserting SWAP gates; a quantum circuit timing reordering module 8, which adjusts the gate execution order according to hardware timing constraints; a quantum circuit compilation function module 9, which serves as the core coordination module to build a complete compilation pipeline; and an auxiliary function module 10, which provides global support such as hardware interfaces and configuration. The entire system integrates gate decomposition, mapping, routing optimization, and timing reordering functions through modular combination, supports dynamic adjustment of the optimization weights of each module, can adapt to the characteristics of different hardware platforms, and outputs hardware-adaptive, low-noise, and high-efficiency quantum circuits, improving compilation flexibility and overall performance.

[0043] The above description is only a preferred embodiment of this disclosure and does not limit the implementation method and protection scope of this disclosure. Those skilled in the art should realize that any equivalent substitutions and obvious changes made using the description and illustrations of this disclosure should be included within the protection scope of this disclosure.

Claims

1. A quantum circuit compilation method, characterized by, Includes the following steps: Based on the target quantum algorithm, the quantum logic circuit to be compiled is sequentially subjected to high-dimensional unitary gate and / or two-qubit gate renormalization processes to obtain the first optimized circuit. Based on the number of qubits of the quantum logic circuit and the topology of the target quantum hardware, a sub-topology for executing the first optimized circuit is determined. Establish an initial mapping between the logical bits of the first optimized line and the physical bits of the sub-topology; Based on the initial mapping, by inserting a switching gate, the mapping relationship between the logical bits and the physical bits is dynamically adjusted so that the physical bits corresponding to the logical bits of the first line are adjacent to each other on the sub-topology during execution, thus obtaining the second optimized line. For the second optimized circuit, single-bit gate renormalization and gate sequence time-order rearrangement are performed sequentially.

2. The method of claim 1, wherein, The quantum logic circuit to be compiled based on the target quantum algorithm, through sequential high-dimensional unitary gate and / or two-qubit gate renormalization processing to obtain the first optimized circuit, includes: Determine whether the quantum logic circuit to be compiled contains the high-dimensional unitary gate; If so, the high-dimensional unitary gate is renormalized to obtain a native single-bit and two-bit quantum gate that supports the target quantum hardware, which is then used as the output of the first optimized circuit. If not, directly perform renormalization on the two-bit gate to obtain native single-bit and two-bit quantum gates that support the target quantum hardware, and use them as the output of the first optimized circuit.

3. The method of claim 1, wherein, The determination of the sub-topology for executing the first optimized circuit, based on the number of qubits of the quantum logic circuit and the topology of the target quantum hardware, includes: Based on the number of qubits in the quantum logic circuit, the logic circuit topology of the quantum logic circuit is determined; Based on the physical topology of the target quantum hardware, the subset of physical bits that best matches the topology of the quantum logic circuit is selected as the sub-topology.

4. The method of claim 1, wherein, The step of establishing an initial mapping between the logical bits of the first optimized line and the physical bits of the sub-topology includes: Using any one of the SABRE algorithm, BFS algorithm, or DFS search algorithm, the logical bits of the first optimized line are bound to the physical bits of the sub-topology to form an initial mapping between the logical bits and the physical bits.

5. The method of claim 1, wherein, Based on the initial mapping, the mapping relationship between the logical bits and the physical bits is dynamically adjusted through a switching gate, so that the physical bits corresponding to the logical bits of the first line are adjacent to each other on the sub-topology during execution, resulting in the second optimized line, including: Based on the initial mapping; The number of switching gates and the line depth are determined by path planning or gate sequence rearrangement. The mapping relationship between the logical bits and the physical bits is dynamically adjusted by the determined switching gates, so that the physical bits corresponding to the logical bits of the first line are adjacent to each other in the sub-topology during execution, thus obtaining the second optimized line.

6. The method of claim 1, wherein, The step of performing single-bit gate renormalization on the second optimized line includes: On the second optimized line, adjacent single-bit gates are merged and then decomposed to complete the single-bit gate renormalization process.

7. The method of claim 1, wherein, The time-series rearrangement of the gate sequence after the single-bit gate renormalization process includes: Based on the hardware timing constraints of the target quantum hardware, the quantum gates after single-qubit gate renormalization are rearranged.

8. The method of claim 2, wherein, The renormalization process of the high-dimensional unitary gate includes decomposing any high-dimensional unitary gate into a sequence of basic quantum gates supported by the target quantum hardware. The sequence of basic quantum gates includes native single-qubit and two-qubit quantum gates supporting the target quantum hardware; and / or The renormalization process performed on the two-bit gate includes decomposing any two-bit gate into a combination of a two-bit entangled gate and a single-bit gate supported by the target quantum hardware; and / or The single-bit gate renormalization process includes arbitrary single-bit gate decomposition to decompose the arbitrary single-bit gate into a basic rotation gate supported by the target quantum hardware.

9. A quantum circuit compiling system, characterized by, include: The quantum circuit renormalization module is used to sequentially perform high-dimensional unitary gate and / or two-qubit gate renormalization processes on the quantum logic circuit to be compiled based on the target quantum algorithm to obtain the first optimized circuit. A quantum physics bit selection module is used to determine a sub-topology for executing the first optimized circuit based on the number of qubits of the quantum logic circuit and the topology of the target quantum hardware. The quantum circuit initial mapping module is used to establish an initial mapping between the logical bits of the first optimized circuit and the physical bits of the sub-topology; The quantum bit routing optimization module, based on the initial mapping, dynamically adjusts the bit positions through quantum switching gates so that the physical bits corresponding to the logical bits of the first line are adjacent to each other on the sub-topology during execution, thus obtaining a second optimized line; The quantum circuit timing reordering module is used to perform gate sequence timing reordering after the quantum circuit renormalization module performs single-bit gate renormalization on the second optimized circuit.

10. The system of claim 9, wherein, Also includes: The standard gate set library module is used to store various logic gate parameters, including those supported by quantum algorithms and target quantum hardware. and / or A quantum circuit management module is used to output the corresponding quantum logic circuit based on the quantum circuit output; and / or A quantum gate decomposition algorithm module is used to decompose any quantum gate into a basic sequence of gates supported by the target quantum hardware; and / or A quantum circuit compilation module is used to build a complete compilation pipeline to generate quantum programs executable by the target quantum hardware; and / or The auxiliary function module is used to provide the target quantum hardware interface and perform configuration.

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