Quantum error mitigation method based on clifford learning and related apparatus

Abstract

This application discloses a quantum error mitigation method and related apparatus based on Clifford learning. The method includes acquiring a raw quantum circuit used to calculate the Hamiltonian of the system. The Hamiltonian is expanded using the tensor product of multiple Pauli operators as a basis, with each basis corresponding to a weight. A training set is generated based on the raw quantum circuit, the multiple bases, and the weights corresponding to each base. The training set includes multiple training quantum circuits. Objective functions of the multiple bases are fitted based on the Clifford simulation results and real chip operation results of the training quantum circuits. Noise-free operation results of the raw quantum circuit are determined based on the real chip operation results and the objective functions of each base. By fitting the operation results under different bases separately, this application avoids the situation where the operation results of the training set cluster at 0, thereby reducing the noise in the quantum system to an acceptable order of magnitude.

Description

Technical Field

[0001] This invention relates to the field of quantum computing technology, and in particular to a quantum error mitigation method and related apparatus based on Clifford learning. Background Technology

[0002] Quantum error mitigation is a post-processing method that uses software to compensate for noise generated during computation. It verifies quantum computation results with a small number of qubits using classical simulations, mitigating errors in larger systems with a certain degree of confidence. Quantum error mitigation is another approach to achieving precise quantum computation because it does not require a large number of qubits, making it suitable for the current era of noisy intermediate-scale quantum (NISQ). Quantum algorithms, such as variational quantum solvers, choose quantum error mitigation techniques to suppress errors rather than correct them. This technique allows for acceptable computational accuracy with only moderate additional resources and has made some progress in both theory and experiment. Summary of the Invention

[0003] This application provides a quantum error mitigation method and related apparatus based on Clifford learning. By fitting the running results under different substrates, it can avoid the running results of the training set from clustering at 0, thereby reducing the noise in the quantum system to an acceptable order of magnitude.

[0004] The first aspect of this application provides a quantum error mitigation method based on Clifford learning, comprising:

[0005] Obtain the original quantum circuit, which is used to calculate the Hamiltonian of the system. The Hamiltonian is expanded based on the tensor product of multiple Pauli operators, and each basis corresponds to a weight.

[0006] A training set is generated based on the original quantum circuit, the plurality of said substrates, and the weights corresponding to each said substrate. The training set includes the plurality of training quantum circuits.

[0007] The objective functions of multiple bases are fitted based on the Clifford simulation results and the actual chip operation results of the trained quantum circuit. The objective functions are used to characterize the relationship between the noisy operation results and the noise-free operation results.

[0008] The noise-free operating results of the original quantum circuit are determined based on the actual chip operation results of the original quantum circuit and the objective function of each substrate.

[0009] Optionally, generating a training set based on the original quantum circuit and the plurality of said substrates and the weights corresponding to each said substrate includes:

[0010] Based on the weight corresponding to each of the bases, one base is randomly selected from the multiple bases as the target base;

[0011] The training quantum circuit is generated and the target basis is updated by traversing each logic gate in the original quantum circuit according to the basic logic gates in the Clifford gate set, the training quantum circuit being used to compute the target basis.

[0012] Determine whether the number of generated training quantum circuits is equal to the preset number;

[0013] If the number of generated training quantum circuits is less than the preset number, then the step of randomly selecting one base from multiple bases as the target base according to the weight corresponding to each base is executed;

[0014] If the number of generated training quantum circuits is equal to the preset number, then the preset number of training quantum circuits is used as the training set.

[0015] Optionally, the step of traversing each logic gate in the original quantum circuit to generate the training quantum circuit and update the target basis based on the basic logic gates in the Clifford gate set includes:

[0016] Starting from the first logic gate in the original quantum circuit, the basic quantum logic gate and the qubits acting on the basic quantum logic gate are determined from the Clifford gate set based on the logic gates traversed, and the target basis is updated, until all logic gates in the original quantum circuit have been traversed.

[0017] The training quantum circuit is generated and the basis of the training quantum circuit is updated based on the obtained basic quantum logic gate and the qubits acting on the basic quantum logic gate.

[0018] Optionally, determining the basic quantum logic gate and the qubit acting on the basic quantum logic gate from the Clifford gate set based on the traversed logic gates, and updating the target basis, includes:

[0019] If the logic gate encountered is a single gate, then a basic single gate is randomly selected from the Clifford gate set;

[0020] The basic single gate is randomly selected as the basic quantum logic gate, and the traversed single gate is replaced with the basic quantum logic gate, wherein the qubits acting on the basic quantum logic gate are the qubits acting on the traversed single gate.

[0021] The target Pauli operator in the target basis is determined based on the qubits acting on the basic quantum logic gate, and the target Pauli operator is updated according to the Clifford transformation table to obtain the updated target basis. The target Pauli operator and the basic quantum logic gate act on the same qubit. The Clifford transformation table is used to characterize the evolution of the Pauli operator in the target basis under the basic quantum logic gate.

[0022] Optionally, determining the basic quantum logic gate and the qubit acting on the basic quantum logic gate from the Clifford gate set based on the traversed logic gates, and updating the target basis, includes:

[0023] If the logic gate encountered is a double gate, then the two qubits that the double gate affects are determined.

[0024] Two target Pauli operators are determined from the target basis based on the two qubits of the double-gate action traversed;

[0025] Based on the types of the two target Pauli operators, determine the basic single gate corresponding to each target Pauli operator from the Clifford gate set, and update the target Pauli operators corresponding to the basic single gates to obtain the updated target basis;

[0026] The basic single gate and the traversed double gate corresponding to each target Pauli operator are taken as basic quantum logic gates, and the qubits operated by the basic quantum logic gates are the two qubits operated by the traversed double gates.

[0027] Optionally, if the two gates are CZ gates, then the step of determining the basic single gate corresponding to each target Pauli operator from the Clifford gate set according to the types of the two target Pauli operators, and updating the target Pauli operators corresponding to the basic single gates to obtain the updated target basis includes:

[0028] If either of the two target Pauli operators is of type X gate, then the basic single gate corresponding to either of the target Pauli operators is determined to be H gate from the Clifford gate set;

[0029] If either of the two target Pauli operators is of type Y, then the basic single gates corresponding to either of the target Pauli operators are determined from the Clifford gate set to be S gates and H gates.

[0030] The target Pauli operator corresponding to the basic single gate is updated to a Z-gate to obtain the updated target basis.

[0031] Optionally, if the two gates are CNOT gates, then the step of determining the basic single gate corresponding to each target Pauli operator from the Clifford gate set according to the types of the two target Pauli operators, and updating the target Pauli operators corresponding to the basic single gates to obtain the updated target basis includes:

[0032] If the type of the first target Pauli operator is X gate, then the basic single gate corresponding to the first target Pauli operator is determined to be H gate from the Clifford gate set; if the type of the first target Pauli operator is Y gate, then the basic single gate corresponding to the first target Pauli operator is determined to be S gate and H gate from the Clifford gate set; the target Pauli operator corresponding to the basic single gate is updated to Z gate to obtain the updated target basis;

[0033] If the type of the second target Pauli operator is Z gate, then the basic single gate corresponding to the second target Pauli operator is determined to be H gate from the Clifford gate set; if the type of the second target Pauli operator is Y gate, then the basic single gate corresponding to the second target Pauli operator is determined to be S gate from the Clifford gate set; the target Pauli operator corresponding to the basic single gate is updated to X gate to obtain the updated target basis.

[0034] Optionally, the step of generating a training set based on the original quantum circuit and the plurality of substrates and the weights corresponding to each substrate, wherein the training set includes a plurality of training quantum circuits, including:

[0035] A training set is generated based on the circuit architecture of the original quantum circuit and the multiple substrates and the weights corresponding to each substrate, wherein the circuit architecture is used to characterize the circuit topology of the quantum circuit;

[0036] Before generating the training set based on the circuit architecture of the original quantum circuit and the plurality of said substrates and the weights corresponding to each said substrate, the method further includes:

[0037] Iterate from the first logic gate in the original quantum circuit;

[0038] If the logic gate encountered is a double gate, then the double gate is stored directly;

[0039] If the logic gate encountered is a single gate, then the target element is stored, and the number of bytes occupied by the target element is less than the number of bytes occupied by the single gate.

[0040] The circuit architecture of the original quantum circuit is determined based on the stored dual gates and the target element after all logic gates in the original quantum circuit have been traversed.

[0041] A second aspect of this application provides a quantum error mitigation device based on Clifford learning, comprising:

[0042] The data acquisition unit is used to acquire the original quantum circuit, which is used to calculate the Hamiltonian of the system. The Hamiltonian is expanded based on the tensor product of multiple Pauli operators, and each basis corresponds to a weight.

[0043] A training set generation unit is configured to generate a training set based on the original quantum circuit, the plurality of said substrates, and the weights corresponding to each said substrate, wherein the training set includes the plurality of training quantum circuits;

[0044] The function fitting unit is used to fit multiple objective functions of the substrates based on the Clifford simulation results and the actual chip operation results of the trained quantum circuit. The objective functions are used to characterize the relationship between noisy operation results and noise-free operation results.

[0045] The result determination unit is used to determine the noise-free operating result of the original quantum circuit based on the actual chip operation result of the original quantum circuit and the objective function of each substrate.

[0046] A third aspect of this application provides an electronic device, including: a processor and a memory;

[0047] The processor is connected to a memory, wherein the memory is used to store computer programs and the processor is used to invoke the computer programs to execute the methods as described in the first aspect of the embodiments of this application.

[0048] A fourth aspect of this application provides a computer-readable storage medium storing a computer program, the computer program including program instructions, which, when executed by a processor, perform the method as described in the first aspect of this application.

[0049] In this embodiment, the test set generated by the original quantum circuit and multiple bases and their weights of the Hamiltonian of the system to be calculated are used to fit the Clifford simulation results and the actual chip operation results, respectively, to obtain the functional relationship between the noisy operation results and the noiseless operation results on different bases. Finally, the noiseless operation results of the original quantum circuit are inferred from the functional relationship of the multiple bases.

[0050] The expectation of a Clifford circuit for a given Pauli operator can be easily calculated theoretically and is always one of -1, 0, or 1. Therefore, Clifford circuits are widely used in classical simulation verification. Furthermore, since they contain only Clifford quantum gates, they can also operate well on real chips. Thus, by using Clifford circuits, the noise-free operating results of the original quantum circuit can be inferred by fitting the functional relationship between classical simulation results and real chip operating results, thereby reducing the noise in the quantum system to an acceptable order of magnitude for application in the current NISQ era. Secondly, this application fits Clifford simulation results and real chip operating results on different substrates to obtain functional relationships between noisy and noise-free operating results on different substrates. This prevents the situation where most theoretical expectation values ​​of the training quantum circuits in the randomly generated training set are 0, making it difficult to obtain the corresponding functional relationship. Attached Figure Description

[0051] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0052] Figure 1 An example system block diagram of quantum error mitigation based on Clifford learning provided in one embodiment of this application is shown;

[0053] Figure 2 A flowchart illustrating a Clifford learning-based quantum error mitigation method provided in one embodiment of this application is shown.

[0054] Figure 3 This paper shows a schematic diagram of the original quantum circuit and its circuit architecture provided in one embodiment of this application;

[0055] Figure 4 This paper shows a schematic diagram of the structure of a quantum error mitigation device based on Clifford learning provided in one embodiment of this application;

[0056] Figure 5 A schematic diagram of the structure of a computer device provided in one embodiment of this application is shown. Detailed Implementation

[0057] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0058] Classical computers use transistors to encode information in binary data, such as bits, where each bit can represent a value of 1 or 0. These 1s and 0s act as switches to drive the functions of a classical computer. If there are n bits of data, there are 2^n possible classical states, and one state is represented at a time.

[0059] Quantum computers use quantum processors that operate on data represented by qubits, also known as quantum bits. A single qubit can represent the classical binary states "0" or "1", or a superposition of "0" and "1". Because it can represent a superposition of "0" and "1", a qubit can represent both "0" and "1" states simultaneously. For example, if there are n bits of data, then 2^n qubits can represent n bits of data. n A quantum state can be represented simultaneously. Furthermore, qubits in a superposition can be correlated with each other, a phenomenon known as entanglement, where the state of one qubit (whether 1, 0, or both) depends on the state of another qubit, and more information can be encoded within two entangled qubits. Based on the principles of superposition and entanglement, qubits enable quantum computers to perform functions that might be relatively complex and time-consuming for classical computers.

[0060] Please refer to Figure 1 This illustration shows an example system block diagram of quantum error mitigation based on Clifford learning, provided in one embodiment of this application. System 100 may be a hybrid computing system comprising a combination of one or more quantum computers, quantum systems, and / or classical computers. Figure 1 In the example shown, system 100 may include a quantum system 110 and a classical computer 120. In one implementation, the quantum system 110 and the classical computer 120 may be configured to communicate via one or more wired and / or wireless connections (e.g., wireless networks). The quantum system 110 may include a quantum chipset consisting of one or more quantum chips, comprising various hardware components for processing data encoded in qubits. The quantum chipset may be a quantum computing core surrounded by infrastructure to protect the quantum chips from electromagnetic noise sources, mechanical vibration sources, heat sources, and other noise sources that can degrade the performance of the quantum chips. The classical computer 120 may be electronically integrated with the quantum system 110 via any suitable wired and / or wireless electronic connection.

[0061] exist Figure 1 In the example shown, quantum system 110 can be any suitable set of components capable of performing quantum operations on a physical system. Quantum operations, such as quantum gate operations, manipulate the quantum states of qubits to evolve and / or become entangled. Figure 1 In the illustrated example embodiment, the quantum system 110 may include a measurement and control unit 111, an interface 112, and a quantum chip 113. In some embodiments, all or part of each of the measurement and control unit 111, interface 112, and quantum chip 113 may be located in a cryogenic environment to facilitate the performance of quantum operations. The quantum chip 113 may be any hardware capable of processing information using quantum states. This hardware may include multiple qubits and means for coupling or entanglement of the qubits to process information using quantum states. Qubits may include, but are not limited to, charge qubits, flux qubits, phase qubits, spin qubits, and ion qubits. The quantum chip may include a set of quantum logic gates configured to perform quantum logic operations on the qubits stored in a quantum register. The quantum gates may include one or more single-qubit gates, two-qubit gates, and / or other multi-qubit gates.

[0062] The measurement and control unit 111 can be any combination of digital computing devices capable of performing quantum computing (e.g., executing quantum circuits) in conjunction with interface 112. This digital computing device may include a digital processor and memory for storing and executing quantum instructions using interface 112. The digital computing device may also include a communication protocol device for receiving instructions and sending the results of the performed quantum computing to a classical computer. Additionally, the digital computing device may include a communication interface having interface 112. In one embodiment, the measurement and control unit 111 may be configured to receive classical instructions (e.g., from classical computer 120) and convert these classical instructions into measurement and control instructions for interface 112. The measurement and control instructions provided by the measurement and control unit 111 to interface 112 may be, for example, digital signals indicating which quantum gates in a quantum gate array need to be applied to the qubits to perform a specific function. Interface 112 may be configured to convert these digital signals into analog signals (e.g., analog pulses of microwave pulses), which can be used to apply quantum gates to the qubits to manipulate the interactions between the qubits.

[0063] Interface 112 may be a classical-quantum interface, comprising a combination of devices capable of receiving instructions from the integrated measurement and control unit 111 and converting those instructions into a means for implementing quantum operations. In one embodiment, interface 112 may convert instructions from the integrated measurement and control unit 111 into drive signals capable of driving or manipulating qubits, and / or applying quantum gates to qubits. Additionally, interface 112 may be configured to convert signals received from the quantum chip 113 into digital signals capable of being processed and transmitted by the integrated measurement and control unit 111. Devices included in interface 112 may include, but are not limited to, digital-to-analog converters, analog-to-digital converters, waveform generators, attenuators, amplifiers, optical fibers, lasers, and filters. Interface 112 may further include circuitry configured to measure multiple qubits after the application of quantum gates, wherein the measurements may produce results represented in classical bits. Each measurement performed by interface 112 may be read out to a device connected to the quantum system 110, such as a classical computer 120. The multiple measurement results provided by interface 112 may represent probabilistic results.

[0064] The classical computer 120 can include hardware components such as a processor and storage devices (e.g., including memory devices and classical registers) for processing data encoded in classical bits. In one embodiment, the classical computer 120 can be configured to provide the quantum system 110 with various control signals, instructions, and data encoded in classical bits. Further, quantum states measured by the quantum system 110 can be read out by the classical computer 120, and the classical computer 120 can store the measured quantum states as classical bits in classical registers. In one embodiment, the classical computer 120 can be any suitable combination of computer-executable hardware and / or computer-executable software capable of executing the preparation module 121 to perform quantum computation using data stored in the data storage module 122 as part of the construction and computation. The data storage module 122 can be a repository for data to be analyzed using quantum computing algorithms and the results of that analysis. The preparation module 121 can be a program or module capable of preparing classical data from the data storage module 122 as part of a quantum circuit implementation. Preparation module 121 can be instantiated as part of a larger algorithm, such as an application programming interface (API) function call, or by resolving hybrid classical-quantum computing into aspects of quantum and classical computing. For example, preparation module 121 can generate instructions for creating quantum circuits using quantum gates. In an embodiment, such instructions can be stored by the measurement and control unit 111 and can be instantiated by components of interface 112 to execute, enabling quantum operations of quantum gates to be performed on quantum chip 113.

[0065] The classic computer 120 may be a laptop computer, desktop computer, vehicle-integrated computer, smart mobile device, tablet device, and / or any other suitable classic computing device. Additionally or alternatively, the classic computer 120 may also operate as part of a cloud computing service model, such as Software as a Service (SaaS), Platform as a Service (PaaS), or Infrastructure as a Service (IaaS). The classic computer 120 may also reside in a cloud computing deployment model, such as a private cloud, community cloud, public cloud, or hybrid cloud.

[0066] Please refer to Figure 2 This illustration shows a flowchart of a quantum error mitigation method based on Clifford learning provided in one embodiment of this application. The method can be applied to computer devices, which refer to electronic devices with data computation and processing capabilities. The method may include the following steps:

[0067] Step 201: Obtain the original quantum circuit, which is used to calculate the Hamiltonian of the system. The Hamiltonian is expanded based on the tensor product of multiple Pauli operators, and each basis corresponds to a weight.

[0068] For any system, its Hamiltonian can be written out. By performing a second quantization on the Hamiltonian, it can be expanded using the tensor product of multiple Pauli operators as a basis. For example, the expanded Hamiltonian can take the form:

[0069] H = ∑ k w k P k ,

[0070] Where H is the Hamiltonian, It is a combination of tensor products of four Pauli matrices, where n is the number of qubits in the original quantum circuit, and w k The weights for each basis.

[0071] For example, when n=4, the basis and weights of a certain Hamiltonian are as follows:

[0072] 'IIIZ': 0.320566575040919,

[0073] 'IIZZ': 0.023788838961453417,

[0074] 'IZIZ': 0.15231868113005043,

[0075] 'ZIIZ': 0.023792955376358407,

[0076] 'IIZI': -0.08807004000714162,

[0077] 'IZZI': 0.023792955376358407,

[0078] 'ZIZI': 0.12229113101750828,

[0079] 'IZII': 0.3205665750409189,

[0080] 'ZZII': 0.023788838961453417,

[0081] 'ZIII':-0.08807004000714164.

[0082] Step 202: Generate a training set based on the original quantum circuit, the plurality of substrates, and the weights corresponding to each substrate. The training set includes the plurality of training quantum circuits.

[0083] For example, a training circuit corresponding to each basis can be generated based on the original quantum circuit. Then, the expected value of each basis can be calculated based on the training circuit corresponding to each basis. By multiplying the multiple expected values ​​by their corresponding weights and summing them, the expected value of the Hamiltonian of the system can be obtained.

[0084] Step 203: Fit multiple objective functions of the substrates based on the Clifford simulation results and the actual chip operation results of the trained quantum circuit. The objective functions are used to characterize the relationship between the noisy operation results and the noise-free operation results.

[0085] Clifford circuits refer to quantum circuits containing only Clifford quantum gates. Single-gate Clifford circuits include X, Y, Z, H, and S gates, as well as combinations thereof (e.g., a SY gate can be a combination of S and H gates). Two-gate Clifford circuits include CNOT, CZ, and SWAP gates. The expectation of a Clifford circuit for a given Pauli operator can be easily calculated theoretically and is always one of -1, 0, or 1. Therefore, Clifford circuits are widely used in classical simulation verification. Clifford simulation refers to training a quantum circuit to be a Clifford circuit, i.e., containing only Clifford quantum gates, and then performing quantum simulation on a classical computer to obtain noise-free results. Real chip execution results are noise-injected results. The objective function can be a linear, quadratic, or exponential function; no specific limitation is made here.

[0086] For example, the Clifford simulation results are: {IZZI: [1,-1,0,1,0,0,1],'IIII': [1,1,1,1,1,1,1],'IZZZ': [1,0,0,0,-1,1,1]….} etc. The actual chip running results are: {IZZI: [[0.9,0.7,0.9],[-0.5,-0.7,-0.5],[0.2,-0.1,0.2],[0.8,0.7,0.9],[0.1,-0.1,0.3]],….}. Based on these training Clifford simulation results and actual chip running results, objective functions with different bases can be fitted respectively.

[0087] Step 204: Determine the noise-free operating results of the original quantum circuit based on the actual chip operation results of the original quantum circuit and the objective function of each substrate.

[0088] For example, the original quantum circuit is run multiple times on a real chip, and the expected value of different substrates is calculated. The result is then substituted into the objective function of the corresponding substrate to determine the noise-free running result on each substrate. The result is then reconstructed according to the corresponding weights to obtain the expected value of the Hamiltonian.

[0089] For example, the noisy expectation of each basis is {IZZI:[-0.44,-0.45,-0.55,-0.50],…}. If the objective function is a linear function y=kx+b, then substituting it into the linear function y=kx+b yields the noisy expectation, {IZZI:[-0.428,-0.44,-0.56,-0.5],…}. Finally, the average of each value is taken, and it is then calculated according to the corresponding w. k Sum the results to get the final outcome.

[0090] As can be seen, in this embodiment, the Clifford simulation results and the actual chip operation results are fitted to multiple bases and their weights of the Hamiltonian of the system to be calculated and the original quantum circuit to generate a test set, respectively, to obtain the functional relationship between the noisy operation results and the noiseless operation results on different bases. Finally, the noiseless operation results of the original quantum circuit are inferred from the functional relationship of the multiple bases.

[0091] The expectation of a Clifford circuit for a given Pauli operator can be easily calculated theoretically and is always one of -1, 0, or 1. Therefore, Clifford circuits are widely used in classical simulation verification. Furthermore, since they contain only Clifford quantum gates, they can also operate well on real chips. Thus, by using Clifford circuits, the noise-free operating results of the original quantum circuit can be inferred by fitting the functional relationship between classical simulation results and real chip operating results, thereby reducing the noise in the quantum system to an acceptable order of magnitude for application in the current NISQ era. Secondly, this application fits Clifford simulation results and real chip operating results on different substrates to obtain functional relationships between noisy and noise-free operating results on different substrates. This prevents the situation where most theoretical expectation values ​​of the training quantum circuits in the randomly generated training set are 0, making it difficult to obtain the corresponding functional relationship.

[0092] In one embodiment provided in this application, generating a training set based on the original quantum circuit, the plurality of said substrates, and the weights corresponding to each said substrate includes:

[0093] Based on the weight corresponding to each of the bases, one base is randomly selected from the multiple bases as the target base;

[0094] The training quantum circuit is generated and the target basis is updated by traversing each logic gate in the original quantum circuit according to the basic logic gates in the Clifford gate set, the training quantum circuit being used to compute the target basis.

[0095] Determine whether the number of generated training quantum circuits is equal to the preset number;

[0096] If the number of generated training quantum circuits is less than the preset number, then the step of randomly selecting one base from multiple bases as the target base according to the weight corresponding to each base is executed;

[0097] If the number of generated training quantum circuits is equal to the preset number, then the preset number of training quantum circuits is used as the training set.

[0098] For example, taking n=4 as an example, the basis and weights of a certain Hamiltonian are as follows:

[0099] 'IIIZ': 0.320566575040919,

[0100] 'IIZZ': 0.023788838961453417,

[0101] 'IZIZ': 0.15231868113005043,

[0102] 'ZIIZ': 0.023792955376358407,

[0103] 'IIZI': -0.08807004000714162,

[0104] 'IZZI': 0.023792955376358407,

[0105] 'ZIZI': 0.12229113101750828,

[0106] 'IZII': 0.3205665750409189,

[0107] 'ZZII': 0.023788838961453417,

[0108] 'ZIII':-0.08807004000714164.

[0109] The probability of each basis being selected is equal to its weight. Then, the traversal begins from the first logic gate in the original quantum circuit. If the original quantum circuit includes multiple logic gates in the same time sequence, the traversal order of these gates is not limited; any gate can be started from. The update method for the target basis is determined by the logic gates traversed.

[0110] As can be seen from the above embodiments, each basis includes n Pauli operators, and the order of each Pauli operator corresponds to the order of the qubits. The measurement basis selected by the current real chip is all measured in the Z direction. Therefore, after traversing all logic gates, it is necessary to identify the Pauli operators in the updated basis that are not Z or I, and transform them to Z, so that their corresponding qubits can be measured along the Z axis. The specific transformation method is as follows: if the corresponding position is X, add an H gate at the end of the circuit to transform X to Z; if the corresponding position is Y, add S and H at the end of the circuit to transform Y to Z. Finally, the measurement operation is applied. The number of training quantum circuits in the training set can be preset. If the preset number is not met, the above embodiments are repeated until the preset number of training quantum circuits is obtained.

[0111] In one embodiment provided in this application, the step of traversing each logic gate in the original quantum circuit to generate the training quantum circuit and update the target basis based on the basic logic gates in the Clifford gate set includes:

[0112] Starting from the first logic gate in the original quantum circuit, the basic quantum logic gate and the qubits acting on the basic quantum logic gate are determined from the Clifford gate set based on the logic gates traversed, and the target basis is updated, until all logic gates in the original quantum circuit have been traversed.

[0113] The training quantum circuit is generated and the basis of the training quantum circuit is updated based on the obtained basic quantum logic gate and the qubits acting on the basic quantum logic gate.

[0114] Clifford circuits include basic logic gates such as single gates (X, Y, Z, H, S) and their combinations (e.g., the SY gate can be combined with S and H); and dual gates such as CNOT, CZ, and SWAP. All of these basic logic gates are supported by real-world chips. For some dual gates that are not supported, such as those only supported by CZ gates in some chips, the CNOT gate can be obtained by transforming the CZ and X gates. Therefore, the original quantum circuit can be transformed before traversal.

[0115] In one embodiment provided in this application, determining the basic quantum logic gate and the qubit acting on the basic quantum logic gate from the Clifford gate set based on the traversed logic gates, and updating the target basis, includes:

[0116] If the logic gate encountered is a single gate, then a basic single gate is randomly selected from the Clifford gate set;

[0117] The basic single gate is randomly selected as the basic quantum logic gate, and the traversed single gate is replaced with the basic quantum logic gate, wherein the qubits acting on the basic quantum logic gate are the qubits acting on the traversed single gate.

[0118] The target Pauli operator in the target basis is determined based on the qubits acting on the basic quantum logic gate, and the target Pauli operator is updated according to the Clifford transformation table to obtain the updated target basis. The target Pauli operator and the basic quantum logic gate act on the same qubit. The Clifford transformation table is used to characterize the evolution of the Pauli operator in the target basis under the basic quantum logic gate.

[0119] Table 1 Clifford Transformation Table

[0120]

[0121]

[0122] For example, the target basis randomly selected from the ten basis sets mentioned above is 'IZZI'. If the logic gate encountered is an RX gate, which acts on the third qubit, then a basic gate is randomly selected from the Clifford gate set. For example, if the randomly selected gate is an H gate, then the H gate replaces the RX gate in acting on the third qubit. The third qubit corresponds to the target Pauli operator 'Z' in the target basis 'IZZI'. According to the Clifford transformation table mentioned above, for the H gate, when the input is Z, the output is X. Therefore, the updated target basis is 'IZXI'.

[0123] In one embodiment provided in this application, determining the basic quantum logic gate and the qubit acting on the basic quantum logic gate from the Clifford gate set based on the traversed logic gates, and updating the target basis, includes:

[0124] If the logic gate encountered is a double gate, then the two qubits that the double gate affects are determined.

[0125] Two target Pauli operators are determined from the target basis based on the two qubits of the double-gate action traversed;

[0126] Based on the types of the two target Pauli operators, determine the basic single gate corresponding to each target Pauli operator from the Clifford gate set, and update the target Pauli operators corresponding to the basic single gates to obtain the updated target basis;

[0127] The basic single gate and the traversed double gate corresponding to each target Pauli operator are taken as basic quantum logic gates, and the qubits operated by the basic quantum logic gates are the two qubits operated by the traversed double gates.

[0128] It should be noted that the basic double gates in Clifford are CNOT gates, CZ gates, SWAP gates, etc. Therefore, for non-Clifford basic double gates, they need to be transformed using the basic logic gates in Clifford.

[0129] Specifically, if the two gates are CZ gates, then the step of determining the basic single gate corresponding to each target Pauli operator from the Clifford gate set according to the types of the two target Pauli operators, and updating the target Pauli operators corresponding to the basic single gates to obtain the updated target basis includes:

[0130] If either of the two target Pauli operators is of type X gate, then the basic single gate corresponding to either of the target Pauli operators is determined to be H gate from the Clifford gate set;

[0131] If either of the two target Pauli operators is of type Y, then the basic single gates corresponding to either of the target Pauli operators are determined from the Clifford gate set to be S gates and H gates.

[0132] The target Pauli operator corresponding to the basic single gate is updated to a Z-gate to obtain the updated target basis.

[0133] For example, the CZ gates that are traversed are applied to the second and third qubits. The target basis obtained by the current update is 'IZXI'. The basis corresponding to the second qubit is 'Z', which does not need to be transformed. The basis corresponding to the third qubit is 'X', so an H gate needs to be applied to the third qubit to transform 'X' in the target basis 'IZXI' to 'Z'. Then the target basis obtained by the update is 'IZZI'.

[0134] Specifically, if the two gates are CNOT gates, then the step of determining the basic single gate corresponding to each target Pauli operator from the Clifford gate set according to the types of the two target Pauli operators, and updating the target Pauli operators corresponding to the basic single gates to obtain the updated target basis includes:

[0135] If the type of the first target Pauli operator is X gate, then the basic single gate corresponding to the first target Pauli operator is determined to be H gate from the Clifford gate set; if the type of the first target Pauli operator is Y gate, then the basic single gate corresponding to the first target Pauli operator is determined to be S gate and H gate from the Clifford gate set; the target Pauli operator corresponding to the basic single gate is updated to Z gate to obtain the updated target basis;

[0136] If the type of the second target Pauli operator is Z gate, then the basic single gate corresponding to the second target Pauli operator is determined to be H gate from the Clifford gate set; if the type of the second target Pauli operator is Y gate, then the basic single gate corresponding to the second target Pauli operator is determined to be S gate from the Clifford gate set; the target Pauli operator corresponding to the basic single gate is updated to X gate to obtain the updated target basis.

[0137] For example, if the CNOT gates encountered during the traversal act on the third and fourth qubits, and the target basis obtained from the current update is 'IZXY', the basis corresponding to the third qubit is 'X', and the basis corresponding to the fourth qubit is 'Y', then an H gate is acted on the third qubit, and an S gate and an H gate are acted on the fourth qubit, so that the target basis is updated from 'IZXY' to 'IZZZ'.

[0138] It should be noted that for single gates encountered in the original quantum circuit, they are directly replaced using the gates from the Clifford transformation table; however, for double gates encountered in the original quantum circuit, a new single gate is added before them, while the double gates encountered are still retained. Therefore, the generation of training quantum circuits does not focus on the specific types of single gates in the original quantum circuit, but only on the qubits that act on the single gates; that is, as long as the circuit architecture of the original quantum circuit is obtained, it is sufficient.

[0139] In one embodiment provided in this application, the step of generating a training set based on the original quantum circuit, a plurality of substrates, and weights corresponding to each substrate, wherein the training set includes a plurality of training quantum circuits, comprising:

[0140] A training set is generated based on the circuit architecture of the original quantum circuit and the multiple substrates and the weights corresponding to each substrate, wherein the circuit architecture is used to characterize the circuit topology of the quantum circuit;

[0141] Before generating the training set based on the circuit architecture of the original quantum circuit and the plurality of said substrates and the weights corresponding to each said substrate, the method further includes:

[0142] Iterate from the first logic gate in the original quantum circuit;

[0143] If the logic gate encountered is a double gate, then the double gate is stored directly;

[0144] If the logic gate encountered is a single gate, then the target element is stored, and the number of bytes occupied by the target element is less than the number of bytes occupied by the single gate.

[0145] The circuit architecture of the original quantum circuit is determined based on the stored dual gates and the target element after all logic gates in the original quantum circuit have been traversed.

[0146] like Figure 3 The diagram illustrates a schematic representation of the original quantum circuit and its circuit architecture provided in one embodiment of this application. Before generating the training set, the circuit architecture diagram is obtained, and then the circuit architecture is traversed. For specific implementation details, please refer to the above embodiment to generate the training quantum circuit. In this embodiment, since individual gates are not considered, target elements with small byte sizes are directly used for storage. Therefore, the complexity of traversal and memory saving can be reduced. Target elements can be, for example, placeholders or specific single gates. For instance, a rotation gate may require storing not only the logic gate type but also rotation parameters; therefore, H-gates and S-gates can be used instead of single gates to save memory. Similarly, placeholders require even fewer bytes, also achieving memory saving.

[0147] Figure 4 A schematic diagram of a quantum error mitigation device based on Clifford learning according to an embodiment of this application is shown. The device includes:

[0148] The data acquisition unit 401 is used to acquire the original quantum circuit, which is used to calculate the Hamiltonian of the system. The Hamiltonian is expanded based on the tensor product of multiple Pauli operators, and each basis corresponds to a weight.

[0149] The training set generation unit 402 is used to generate a training set based on the original quantum circuit, the plurality of said substrates, and the weights corresponding to each said substrate, wherein the training set includes the plurality of training quantum circuits;

[0150] The function fitting unit 403 is used to fit multiple objective functions of the substrates based on the Clifford simulation results and the actual chip operation results of the trained quantum circuit. The objective functions are used to characterize the relationship between noisy operation results and noise-free operation results.

[0151] The result determination unit 404 is used to determine the noise-free operating result of the original quantum circuit based on the actual chip operation result of the original quantum circuit and the objective function of each substrate. Figure 5 A schematic diagram of the structure of a computer device provided in one embodiment of this application is shown, including a memory and a processor. The memory stores a computer program, and the processor executes the computer program to implement the functions of the computer system based on the Clifford learning quantum error mitigation method in any of the above embodiments.

[0152] This application also provides a computer-readable storage medium storing a computer program thereon, which, when executed by a computer, causes the computer to perform the functions of the computer system based on the Clifford learning quantum error mitigation method in any of the above embodiments.

[0153] This application also provides a computer program product containing instructions that, when executed by a computer, cause the computer to perform the functions of the computer system based on the Clifford learning quantum error mitigation method in any of the above embodiments.

[0154] It is understood that the specific examples in this application are only intended to help those skilled in the art better understand the implementation methods of this application, and are not intended to limit the scope of the invention.

[0155] It is understood that in the various embodiments of this application, the sequence number of each process does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not limit the implementation process of the embodiments of this application in any way.

[0156] It is understood that the various implementation methods described in this application can be implemented individually or in combination, and the implementation methods in this application are not limited in this respect.

[0157] Unless otherwise stated, all technical and scientific terms used in the embodiments of this application have the same meaning as commonly understood by one of ordinary skill in the art. The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. The term "and / or" as used in this application includes any and all combinations of one or more of the associated listed items. The singular forms "a," "the," and "the" as used in the embodiments of this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0158] It is understood that the processor in the embodiments of this application can be an integrated circuit chip with signal processing capabilities. During implementation, each step of the above method embodiments can be completed by the integrated logic circuits in the processor's hardware or by instructions in software form. The processor can be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this application. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this application can be directly embodied in the execution of a hardware decoding processor, or executed by a combination of hardware and software modules in the decoding processor. The software modules can be located in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. This storage medium is located in memory; the processor reads information from the memory and, in conjunction with its hardware, completes the steps of the above method.

[0159] It is understood that the memory in the embodiments of this application may be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. Specifically, non-volatile memory may be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. Volatile memory may be random access memory (RAM). It should be noted that the memory in the systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0160] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0161] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the aforementioned method implementations, and will not be repeated here.

[0162] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0163] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment, depending on actual needs.

[0164] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0165] If a function is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0166] The above are merely specific embodiments of this application, but the scope of protection of this invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this invention should be determined by the scope of the claims.

Claims

1. A quantum error mitigation method based on clifford learning, characterized in that, include: Obtain the original quantum circuit, which is used to calculate the Hamiltonian of the system. The Hamiltonian is expanded based on the tensor product of multiple Pauli operators, and each basis corresponds to a weight. A training set is generated based on the original quantum circuit, the plurality of said substrates, and the weights corresponding to each said substrate, wherein the training set includes the plurality of training quantum circuits; The objective functions of multiple bases are fitted based on the Clifford simulation results and the actual chip operation results of the trained quantum circuit. The objective functions are used to characterize the relationship between the noisy operation results and the noise-free operation results. The noise-free operating results of the original quantum circuit are determined based on the actual chip operation results of the original quantum circuit and the objective function of each substrate.

2. The method of claim 1, wherein, The step of generating a training set based on the original quantum circuit, the multiple substrates, and the weights corresponding to each substrate includes: Based on the weight corresponding to each of the bases, one base is randomly selected from the multiple bases as the target base; Each logic gate in the original quantum circuit is traversed to generate the training quantum circuit and update the target basis based on the basic logic gates in the Clifford gate set, the training quantum circuit being used to compute the target basis; Determine whether the number of generated training quantum circuits is equal to the preset number; If the number of generated training quantum circuits is less than the preset number, then the step of randomly selecting one base from multiple bases as the target base according to the weight corresponding to each base is executed. If the number of generated training quantum circuits is equal to the preset number, then the preset number of training quantum circuits is used as the training set.

3. The method according to claim 2, characterized in that, The step of traversing each logic gate in the original quantum circuit to generate the training quantum circuit and update the target basis based on the basic logic gates in the Clifford gate set includes: Starting from the first logic gate in the original quantum circuit, the basic quantum logic gate and the qubits acting on the basic quantum logic gate are determined from the Clifford gate set based on the logic gates traversed, and the target basis is updated, until all logic gates in the original quantum circuit have been traversed. The training quantum circuit is generated and the basis of the training quantum circuit is updated based on the obtained basic quantum logic gate and the qubits acting on the basic quantum logic gate.

4. The method according to claim 3, characterized in that, The process of determining the basic quantum logic gate and the qubits acting on the basic quantum logic gate from the Clifford gate set based on the traversed logic gates, and updating the target basis, includes: If the logic gate encountered is a single gate, then a basic single gate is randomly selected from the Clifford gate set; Randomly selected basic gates are used as basic quantum logic gates, and the gates that are traversed are replaced with the basic quantum logic gates, wherein the qubits acting on the basic quantum logic gates are the qubits acting on the traversed gates. The target Pauli operator in the target basis is determined based on the qubits acting on the basic quantum logic gate, and the target Pauli operator is updated according to the Clifford transformation table to obtain the updated target basis. The target Pauli operator and the basic quantum logic gate act on the same qubit. The Clifford transformation table is used to characterize the evolution of the Pauli operator in the target basis under the basic quantum logic gate.

5. The method according to claim 3, characterized in that, The process of determining the basic quantum logic gate and the qubits acting on the basic quantum logic gate from the Clifford gate set based on the traversed logic gates, and updating the target basis, includes: If the logic gate encountered is a double gate, then the two qubits that the double gate affects are determined. Two target Pauli operators are determined from the target basis based on the two qubits of the double-gate action traversed; Based on the types of the two target Pauli operators, determine the basic single gate corresponding to each target Pauli operator from the Clifford gate set, and update the target Pauli operators corresponding to the basic single gates to obtain the updated target basis; The basic single gate and the traversed double gate corresponding to each target Pauli operator are taken as basic quantum logic gates, and the qubits operated by the basic quantum logic gates are the two qubits operated by the traversed double gates.

6. The method according to claim 5, characterized in that, If the two gates are CZ gates, then the step of determining the basic single gate corresponding to each target Pauli operator from the Clifford gate set according to the types of the two target Pauli operators, and updating the target Pauli operators corresponding to the basic single gates to obtain the updated target basis includes: If either of the two target Pauli operators is of type X gate, then the basic single gate corresponding to either of the target Pauli operators is determined to be H gate from the Clifford gate set; If either of the two target Pauli operators is of type Y, then the basic single gates corresponding to either of the target Pauli operators are determined from the Clifford gate set to be S gates and H gates. The target Pauli operator corresponding to the basic single gate is updated to a Z-gate to obtain the updated target basis.

7. The method according to claim 5, characterized in that, If the two gates are CNOT gates, then the step of determining the basic single gate corresponding to each target Pauli operator from the Clifford gate set according to the types of the two target Pauli operators, and updating the target Pauli operators corresponding to the basic single gates to obtain the updated target basis includes: If the type of the first target Pauli operator is X gate, then the basic single gate corresponding to the first target Pauli operator is determined to be H gate from the Clifford gate set; if the type of the first target Pauli operator is Y gate, then the basic single gate corresponding to the first target Pauli operator is determined to be S gate and H gate from the Clifford gate set; the target Pauli operator corresponding to the basic single gate is updated to Z gate to obtain the updated target basis; If the type of the second target Pauli operator is Z gate, then the basic single gate corresponding to the second target Pauli operator is determined to be H gate from the Clifford gate set; if the type of the second target Pauli operator is Y gate, then the basic single gate corresponding to the second target Pauli operator is determined to be S gate from the Clifford gate set; the target Pauli operator corresponding to the basic single gate is updated to X gate to obtain the updated target basis.

8. The method according to any one of claims 1-7, characterized in that, The step of generating a training set based on the original quantum circuit, multiple substrates, and weights corresponding to each substrate, wherein the training set includes multiple training quantum circuits, including: A training set is generated based on the circuit architecture of the original quantum circuit and the multiple substrates and the weights corresponding to each substrate, wherein the circuit architecture is used to characterize the circuit topology of the quantum circuit; Before generating the training set based on the circuit architecture of the original quantum circuit and the plurality of said substrates and the weights corresponding to each said substrate, the method further includes: Iterate from the first logic gate in the original quantum circuit; If the logic gate encountered is a double gate, then the double gate is stored directly; If the logic gate encountered is a single gate, then the target element is stored, and the number of bytes occupied by the target element is less than the number of bytes occupied by the single gate. The circuit architecture of the original quantum circuit is determined based on the stored dual gates and the target element after all logic gates in the original quantum circuit have been traversed.

9. A quantum error mitigation device based on Clifford learning, characterized in that, include: The data acquisition unit is used to acquire the original quantum circuit, which is used to calculate the Hamiltonian of the system. The Hamiltonian is expanded based on the tensor product of multiple Pauli operators, and each basis corresponds to a weight. A training set generation unit is configured to generate a training set based on the original quantum circuit, the plurality of said substrates, and the weights corresponding to each said substrate, wherein the training set includes the plurality of training quantum circuits; The function fitting unit is used to fit multiple objective functions of the substrates based on the Clifford simulation results and the actual chip operation results of the trained quantum circuit. The objective functions are used to characterize the relationship between noisy operation results and noise-free operation results. The result determination unit is used to determine the noise-free operating result of the original quantum circuit based on the actual chip operation result of the original quantum circuit and the objective function of each substrate.

10. An electronic device, characterized in that, include: Processor and memory; The processor is connected to a memory, wherein the memory is used to store a computer program, and the processor is used to invoke the computer program to perform the method as described in any one of claims 1-8.

11. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, the computer program including program instructions that, when executed by a processor, perform the method as described in any one of claims 1-8.

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