A financial flow privacy protection analysis terminal and method based on an edge computing gateway

Abstract

This invention discloses a privacy-preserving analysis terminal and method for financial transaction records based on an edge computing gateway. Addressing the lack of logical error correction and data leakage privacy risks in existing financial bill recognition systems, this invention leverages a general heterogeneous computing architecture to construct an integrated NPU and TEE, and performs hardware-software collaborative processing logic through a high-speed collaborative channel. The method includes: the NPU performing OCR to extract text; the TEE replacing sensitive entities with encryption masks and mapping the text to SMT constraint expressions for logical verification; if a verification conflict occurs, a logical penalty term is calculated, triggering an NPU interrupt via the collaborative channel to call the operator dynamic update interface. While preventing redundant calculation of visual context features, the penalty term is injected as a bias into the decoding layer, dynamically adjusting the decoding weights and reconstructing the recognition result; finally, the desensitized data, based on homomorphic encryption to maintain the topology structure, is transmitted to the cloud for risk analysis and then restored locally. This invention achieves a closed loop between perception and deterministic logic, significantly improving feature extraction accuracy while ensuring privacy data remains within the data domain.

Description

Technical Field

[0001] This invention relates to the fields of data security and intelligent computing technology, specifically to a financial transaction privacy protection analysis terminal and method based on an edge computing gateway. Background Technology

[0002] With the development of financial digitalization, bank transaction and document analysis plays a crucial role in scenarios such as credit approval and anti-money laundering. Existing technologies typically employ a separate architecture for processing such financial documents: initial perception and extraction on the client side, followed by semantic analysis using a large-scale cloud model. However, these existing technologies have the following technical shortcomings in practical applications:

[0003] First, cross-modal recognition errors and logical gaps: Traditional OCR technology is limited by image quality (such as blurring and creases), resulting in unstable recognition rates. Moreover, in the existing architecture, the perception layer (feature extraction) and the logic layer (business rules) are isolated from each other. Once the front-end OCR produces a digit recognition error, there is a lack of underlying logical mechanisms to force the reconstruction of the perception path, and it can usually only rely on back-end software rules to intercept or manual review.

[0004] Second, the probabilistic defects of generative models: existing general-purpose large language models are essentially probabilistic sequence generation models. When dealing with the strong numerical logic required for financial statements (such as loan balance and accounting identity), they are prone to inference biases that lack mathematical certainty, resulting in wasted computing power and difficulty in meeting the rigor requirements of financial-grade systems.

[0005] Third, the privacy risk of edge-cloud collaboration: If highly sensitive plaintext data, including customers' real identities and transaction amounts, is directly uploaded to the cloud for complex network or large model analysis, it is very easy to trigger unauthorized data access and privacy compliance risks; on the other hand, if the data is completely desensitized on the edge, it often destroys the topological characteristics of fund flow, causing the cloud risk control model to fail. Summary of the Invention

[0006] This invention aims to solve the technical problems in existing technologies for financial transaction and bill analysis, such as the lag in logical error correction caused by the split architecture, the probabilistic inference bias of large models, and the risk of data privacy leakage during edge-cloud collaboration. It provides a financial transaction privacy protection analysis terminal and method based on an edge computing gateway.

[0007] The first aspect of the present invention provides a method for privacy protection analysis of financial transaction records based on an edge computing gateway, characterized in that the edge computing gateway is configured with a neural network processing unit (NPU), a trusted execution environment (TEE), and a high-speed collaborative channel connecting the NPU and the TEE based on an underlying bus protocol, the method comprising:

[0008] Step S1: Receive the original financial transaction file, and extract the initial text data from the financial transaction file by running the layout analysis and optical character recognition (OCR) model through the NPU;

[0009] Step S2: Within the TEE, identify sensitive entities in the initial text data, replace the sensitive entities with encryption masks using an encryption algorithm, and generate desensitized feature data;

[0010] Step S3: Within the TEE, the initial text data is mapped to a Satisfiability Modulus Theory (SMT) constraint expression, and input into a preset constraint solver for logical consistency verification. When the constraint solver returns a logical consistency result, the current text data is determined to be valid, and the output lock is released. When the constraint solver returns a logical conflict result, a logical penalty term that violates the SMT constraint expression is calculated, and the logical penalty term is transmitted back to the NPU via the high-speed collaborative channel by calling the underlying driver interface. The NPU dynamically adjusts the candidate path weights of the corresponding recognition results in its decoding layer based on the logical penalty term, and regenerates the text data for verification until the constraint solver returns a logical consistency result.

[0011] Step S4: The desensitized feature data that has been unlocked is encrypted and transmitted to the cloud. The cloud identifies the fund flow structure based on the homomorphic topology graph, generates encrypted risk reasoning results, and returns them to the edge computing gateway.

[0012] Step S5: The edge computing gateway decrypts the risk reasoning result locally and reverses the encryption mask to restore the real plaintext data, generating a compliance analysis report.

[0013] A second aspect of the present invention provides a financial transaction privacy protection analysis terminal based on an edge computing gateway, characterized in that it comprises:

[0014] The communication interface unit is used to receive the original financial transaction files and to interact with the cloud with encrypted data.

[0015] The Neural Processing Unit (NPU) is used to run layout analysis and optical character recognition models to extract text data, and to receive logical penalty terms and dynamically adjust decoding weights to regenerate text data;

[0016] The Trusted Execution Environment (TEE) includes a desensitization module and a constraint solver. It is used to replace sensitive entities in the text data with encryption masks to generate desensitized feature data, and to map the text data to SMT constraint expressions for logical self-consistency verification, and to generate the logical penalty term when verification conflicts occur.

[0017] A high-speed collaborative channel, relying on the internal interconnection bus of the edge computing gateway, logically connects the NPU and the TEE, and is used to transmit the logical penalty item back to the NPU when a logical conflict is determined;

[0018] The Hardware Security Module (HSM) is used to manage encryption / decryption keys and signature verification.

[0019] The beneficial effects of this invention are:

[0020] By constructing a closed-loop system that integrates hardware and software, the accuracy of feature extraction is significantly improved. This invention breaks through the traditional "post-processing manual / rule verification" model and introduces a formal constraint-driven execution path control mechanism. Through the underlying feedback bus, the logical loss of higher-level components is directly converted into decoding weight adjustment signals for the underlying OCR model, forcing the NPU to activate logically compliant suboptimal paths. This underlying hardware-software collaborative error correction mechanism greatly reduces numerical recognition errors caused by fuzzy documents.

[0021] Overcoming the probabilistic limitations of AI and achieving strict business logic gating: This invention strongly couples probabilistic AI perception with deterministic SMT mathematical solutions. The output of the perception layer must meet hard business logic requirements such as financial identities and time series before it can be released, effectively avoiding inference biases in general large models under numerical calculation scenarios and meeting the rigor requirements of financial-grade applications.

[0022] Balancing privacy protection and cloud computing power to eliminate data leakage risks: This invention performs masking replacement of sensitive information within the TEE environment of an edge computing gateway, outputting only a homomorphic topology graph that maintains the risk semantic structure to the cloud. This enables cloud-based graph neural networks to perform complex anti-money laundering pattern recognition without accessing any plaintext identities, fundamentally ensuring the compliant and data-free movement of financial data while fully utilizing the powerful computing capabilities of the cloud. Attached Figure Description

[0023] Figure 1 This is a system architecture diagram provided in an embodiment of the present invention;

[0024] Figure 2 This is a block diagram of the edge computing gateway hardware module provided in an embodiment of the present invention;

[0025] Figure 3 This is a flowchart of the logic verification and perception model dynamic reconstruction provided in the embodiments of the present invention;

[0026] Figure 4 This is a diagram showing the entire lifecycle of privacy data provided in this embodiment of the invention;

[0027] Figure 5This is a flowchart of the execution of the underlying interrupt service routine (ISR) of the NPU controller in response to the TEE feedback signal, provided in Embodiment 5 of the present invention. Detailed Implementation

[0028] Terminology Definitions: To more clearly describe this invention, the following terminology definitions apply to this specification and the claims:

[0029] Verifiable Perceptual Computing Architecture (VPC): refers to a new computing paradigm that encapsulates perceptual reasoning (probabilistic) and logical verification (deterministic) into atomic operations, requiring all outputs to carry proofs of logical consistency.

[0030] Neural Symbolic AI: In this invention, it specifically refers to a closed-loop system that uses logical loss signals to guide the inference path of a neural network.

[0031] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0032] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments.

[0033] Example 1: System Overall Architecture

[0034] like Figure 1 As shown, this system mainly consists of a user local security domain 100, a privacy computing cloud platform 200, and a security isolation boundary 300. The user local security domain 100 includes an original credential collection device 101, a trusted edge computing gateway 102, and a local business terminal 103. After the original image stream is processed by the gateway 102, it outputs de-identified feature vectors and encrypted data to the encrypted data receiving gateway 201 of the cloud platform 200. The cloud-based risk graph inference engine 202 combines with the risk knowledge base 203 to perform inference, and the generated encrypted risk inference results are sent back to the gateway 102. Finally, a compliance report is generated on the local business terminal 103.

[0035] Example 2: Hardware Terminal Design

[0036] like Figure 2 As shown, the terminal includes a Verifiable Perceptual Computing Module (VPC Module), whose logical structure includes:

[0037] Perception Subsystem: NPU accelerator card, performs OCR.

[0038] Verification subsystem: TEE environment, deploying SMT solver as logic gate.

[0039] High-speed Collaboration Channel: Unlike traditional application-layer software message queues, the collaboration channel in this embodiment relies on the existing internal hardware interconnect architecture of general-purpose heterogeneous computing chips. It achieves hardware-software collaborative feedback by calling the underlying firmware interface and based on the AXI-Stream extension protocol. It contains two logical channels:

[0040] Forward Channel: Used to transmit the high-dimensional feature tensor and confidence matrix output by the NPU to the TEE memory area. The bandwidth is configured to 128-bit and supports DMA direct memory access to ensure that the sensed data enters the verification domain with zero copy.

[0041] Backward Channel: This is a low-latency control path used to transmit the logic gradient vector generated by the SMT solver. When the TEE issues a "reconstruction command," this channel triggers the NPU controller's interrupt service routine (ISR), directly modifying the neural network accelerator's register configuration (such as BeamWidth parameters or Attention Mask weights), thereby achieving millisecond-level dynamic model reconstruction.

[0042] Security Subsystem: Hardware Security Module (HSM), used to manage encryption / decryption keys and signature verification. To ensure data tamper-proofing during edge-cloud collaboration, the Hardware Security Module (HSM) performs hash digest generation and signature verification by calling the standard PKCS#11 interface, ensuring that the Locality Sensitive Hash (LSH) has tamper-proof characteristics in the encrypted state.

[0043] Example 3: Logical Verification and Privacy Protection Methods

[0044] This embodiment describes in detail the core VPC verification process (such as...). Figure 3 (as shown)

[0045] 1. Semantic extraction and formal mapping: The system extracts semantics through VLM and converts the text into SMT expressions based on the constraint template library.

[0046] Table 2. Financial Transaction Logical Constraint Template Library (Partial)

[0047] Constraint Type Business logic description SMT-LIB Expression Template Accounting identity Beginning balance + Revenue - Expenses = Ending balance Assert(Start + In - Out == End) Loan balance Total debits equals total credits Assert(Sum(Debit) == Sum(Credit))

[0048] 2. Constraint-driven dynamic reconstruction mechanism for perception models (core hardware closed loop)

[0049] During the SMT expression verification process described above, if the solver returns Unsat, hardware closed-loop correction is triggered. In a specific embodiment, the specific hardware and software co-computation mechanism and logic implementation steps for "dynamically adjusting the candidate path weights of the NPU decoding layer using logic loss signals" are as follows:

[0050] Logical Error Localization and Loss Quantization: When the SMT solver within the TEE determines that a logical constraint is not met (e.g., a conflict occurs due to an imbalance in amounts), the verification subsystem not only returns an Unsat, but also calculates the residual gap (G). This is done to convert the absolute value of G into a scalar weight that the neural network decoding layer can process. The verification subsystem constructs a residual penalty function based on a nonlinear saturation mapping. The specific calculation formula is as follows: ;

[0051] in, The preset sensitivity hyperparameter (taken as 0.85 in this embodiment); This is the average character confidence scalar of the local bounding box ID of the image extracted based on the financial semantic association table; This represents the current candidate decoding sequence that is causing the conflict.

[0052] Low-level interrupt and control instruction injection (sub-millisecond timing closed loop):

[0053] Upon detecting a conflict, the system executes the following strictly timed actions:

[0054] Status monitoring phase ( The constraint solver within the TEE calculates... Then, the target region ID and penalty item are packaged into a 32-bit control frame.

[0055] Interrupt triggering phase (sub-millisecond theoretical latency): The TEE sends an edge-triggered interrupt signal to the NPU controller by calling the underlying driver to configure a dedicated hardware IRQ pin (configured to the highest priority).

[0056] Register rewrite phase (within several system clock cycles): After the NPU's interrupt service routine (ISR) responds, for heterogeneous architectures that support computation graph dynamic graph execution mechanisms or operator-level overloading (such as commercial NPUs based on general-purpose neural network compilers), it directly maps the target region ID and penalty term to the allocated decoder weight-specific SRAM offset address by calling the underlying tensor operator dynamic update interface (such as the dynamic weight API). This process strictly distinguishes between the feature extraction unit (Encoder) and the decoding unit (Decoder), and forcibly retains the visual context cache generated by the feature extraction layer during the interrupt. Specifically, it writes instructions to the decoding control register to reset the decoding cursor and writes instructions to the penalty weight register. Parameters. This process effectively avoids the huge computational overhead of rerunning the entire convolution or Transformer backbone network, and completely eliminates the latency gaps in traditional inter-process communication (IPC).

[0057] This process is completed directly in the underlying hardware registers, without the need for host CPU and operating system kernel stack switching, thus completely eliminating the latency gaps in traditional inter-process communication (IPC).

[0058] (3) Beam Search Decoding Tree Probability Reshaping: After an NPU interrupt, instead of re-executing the energy-intensive CNN / Transformer image feature extraction, it directly reads the cached high-dimensional feature tensor of the target region from the local SRAM and re-executes Beam Search decoding. When calculating sequence probabilities, the NPU hardware decoder uses traditional acoustic / visual probability scores... Combined with logical penalty terms. Specifically, the first... Updated probability of candidate decoding paths Satisfy the following formula: ;

[0059] in, K is the preset logic guidance coefficient used to balance visual confidence and logical compliance; K is the beam size of the beam search.

[0060] Logical guidance coefficient in the above formula It is not a fixed value, but rather an adaptively dynamic calculation based on the probability distribution entropy of the current beam search. The calculation formula is as follows: ;

[0061] in, Base experience value (set to 2.0). This is a modulating factor. When the perceptual layer is extremely uncertain about image recognition (high probability distribution entropy, such as severely blurred tickets), Dynamic magnification forces the NPU to rely heavily on the logical mathematical constraints of the TEE to guide decoding; when the image is extremely clear (entropy value approaches 0), The decoding process is now primarily based on visual perception features. This adaptive mechanism effectively addresses the overfitting problem of fixed weights under different levels of ambiguity in tickets.

[0062] (4) Path deweighting and suboptimal path activation: Through the above mechanism, the Top-1 candidate paths that originally caused logical conflicts are subject to strong penalties. ,That The weights are exponentially suppressed. The NPU decoding layer automatically promotes the Top-2 or Top-3 alternative paths with slightly lower visual feature scores but exempt from logical penalties to the current optimal path, generates a new recognition sequence, and resubmits it to the TEE for incremental verification until... Return to zero, and finally unlock the output.

[0063] 3. Risk semantic preservation mapping and graph neural network training model

[0064] like Figure 4 As shown, in the cloud, this invention constructs a homomorphic topology graph. To ensure node identifier encryption and maintain edge connectivity, the edge gateway performs the following deterministic desensitization and semi-homomorphic encryption:

[0065] Node ID desensitization: For sensitive identifiers such as transaction accounts, deterministic pseudo-name calculation is performed using a keyed hash message authentication code (HMAC-SHA256). Because it's a deterministic algorithm, the same account can generate [data / resources] in multiple transactions. It remains unique, thus preserving the topological structure of fund flow.

[0066] Edge feature encryption: The transaction amount is encrypted using the Paillier additive homomorphic encryption algorithm. .

[0067] In the cloud, the GNN network (using the GraphSAGE architecture in this embodiment) utilizes the aforementioned homomorphic topological graph for both training and inference. Its joint loss function for model training... The calculation is as follows: ;

[0068] Among them, the former term is the cross-entropy classification loss, and the latter term is the penalty constraint on the amount of violation calculated based on the homomorphic ciphertext. The model training uses an enhanced dataset containing 200,000 synthetic financial transaction records and money laundering topology labels, enabling the cloud to accurately identify money laundering patterns without decrypting specific identities.

[0069] 4. Local Decryption and Integrity Verification Closed-Loop After the edge computing gateway receives the risk inference result returned by the cloud, the Hardware Security Module (HSM) calls the built-in hardware cryptographic algorithm engine to reverse the encrypted mask to the real plaintext data. At the same time, the HSM calculates the hash digest of the restored plaintext data by calling the aforementioned standard PKCS#11 interface and strictly compares it with the Locality-Sensitive Hashing (LSH) generated during the acquisition stage of the original financial transaction file. Only when the comparison is consistent, the integrity of the data throughout the end-to-cloud transfer lifecycle is confirmed, and a final compliance analysis report is generated.

[0070] Embodiment 4: Workflow Instance of the VPC Architecture in a Typical Financial Scenario

[0071] To further illustrate the processing logic of the "Verifiable Perception Computing Architecture (VPC)" proposed in this invention in actual business, this embodiment provides two specific case examples of fault recovery and logic correction.

[0072] Scenario 1: Correction of the "Decimal Point Drift" Error in a Blurred Bill (Numeric Logic Closed-Loop)

[0073] Problem Description: When processing a bank acceptance bill with poor scanning quality, the NPU perception subsystem misidentifies the amount "10,000.00" (Ten thousand yuan in full) as "100,000.0" (One hundred thousand yuan), resulting in the loss of the decimal point position.

[0074] VPC Processing Flow:

[0075] Atomization Verification (First Round): The logic gating unit in the TEE loads the constraint Assert(Upper_Case_Amount == Digital_Amount) (the upper case amount is equal to the lower case amount).

[0076] Conflict Detection: The solver calculates and finds that the value corresponding to the upper case "Ten thousand yuan" (10,000) does not match the lower case recognition result (100,000), and returns Unsat.

[0077] Hardware Feedback: The logic gating unit sends a logic loss signal (Logic Loss) through the collaborative channel. This signal contains the specific residual value Gap = 90,000.

[0078] Model Reconstruction: After receiving the signal, the perception subsystem does not directly modify the number, but reduces the weight of the current path with the decimal point in the last place and activates the alternative path in Beam Search (i.e., the decimal point is in the third to last place).

[0079] Reconstruction verification (second round): The new recognition result "10,000.00" is submitted to TEE again. At this time, Assert(10,000==10,000) is true, and Sat is returned.

[0080] Output unlock: The VPC unit is unlocked, and data flows to the cloud.

[0081] Technical benefits: Traditional "post-processing rules" usually directly report errors or forcibly correct to uppercase, which can easily mask real forgery risks (such as cases where uppercase letters have been altered). The VPC architecture, however, ensures dual consistency between image features and logical features by forcing the perception layer to "look" at the image again.

[0082] Scenario 2: Interception of violations based on "time sequence logic" in supply chain finance (closed-loop time logic)

[0083] Problem description: When reviewing a supply chain financing application, the user uploaded an invoice and the corresponding trade contract.

[0084] VPC Processing Flow

[0085] Multimodal constraint loading: VPC unit loading timing constraint Assert(Invoice_Date >= Contract_Sign_Date) (The invoice date must be later than or equal to the contract signing date)

[0086] Perception and execution: The OCR identified the contract signing date as 2023-12-01, but the invoice date was misidentified as 2023-11-01 (mistaking 12 for 11).

[0087] Gating interception: If the solver determines that the timing axiom is violated (signing the contract before issuing the invoice), it returns Unsat and logically intercepts the data packet, preventing it from being uploaded to the cloud risk control model and avoiding pollution of the cloud graph.

[0088] Feedback Correction: The system prompts "timing logic conflict" and automatically performs high-precision local resampling for the date range.

[0089] Final output: The invoice date has been corrected to 2023-12-01. The logic verification passed, and the invoice is released.

[0090] Example 5: Comparison of Evidence from Equipment Integration and Actual Experimental Data

[0091] To demonstrate the feasibility of the "algorithm + hardware" collaborative architecture of this invention, the underlying code was integrated and debugged on a general-purpose commercial heterogeneous computing development board (as a software and hardware co-simulation environment) equipped with an NPU and a secure TrustZone (as a TEE environment). The NPU driver layer of the development board opens a dynamic bias injection interface for the Beam Search decoding operator, allowing local tensor updates without resetting the lifecycle of the overall computation graph. The specific execution control flow of its core underlying interrupt service routine (ISR) is shown in Figure 5: / / Added note: The SRAM offset address in step 3 is pre-statically allocated by the NPU compiler during the model compilation stage to ensure that memory out-of-bounds access or read-write conflicts do not occur during DMA writes.

[0092] void __attribute__((interrupt)) NPU_Logic_Correction_ISR(void) {

[0093] / / 1. Read the logic penalty parameters transmitted by the TEE via the AXI bus

[0094] uint32_t target_box_id = AXI_READ(TEE_FEEDBACK_ADDR_BOX_ID);

[0095] float penalty_weight = AXI_READ_FLOAT(TEE_FEEDBACK_ADDR_PENALTY);

[0096] / / 2. Physically block the current NPU decoding output pipeline

[0097] HW_REG_WRITE32(NPU_CTRL_BASE + DECODE_PIPELINE_HALT, 0x01);

[0098] / / 3. Write the logical penalty term directly to the specific SRAM offset address of the target tensor decoding weight.

[0099] HW_REG_WRITE_FLOAT(NPU_WEIGHT_SRAM_BASE + (target_box_id * SRAM_OFFSET), penalty_weight);

[0100] / / 4. Trigger register-level Beam Search resampling instructions

[0101] HW_REG_WRITE32(NPU_CTRL_BASE + CMD_RESTART_DECODE_PHASE2, 0x01);

[0102] / / 5. Clear the interruption flag and restore the pipeline.

[0103] HW_REG_WRITE32(INT_CLEAR_REG, IRQ_LOGIC_FAULT_BIT);

[0104] }

[0105] The specific execution control flow of the aforementioned underlying interrupt service routine (ISR) is as follows: Figure 5 As shown.

[0106] A comparative test was conducted on a batch of 10,000 randomly sampled genuine bank acceptance bills and customs declarations, which contained interference from water stains and creases. The experimental verification data is shown in the table below:

[0107] Table 3: System Performance Comparison Test Data in Real-World Business Scenarios

[0108] Architecture type Average delay at the edge (ms / frame) Financial identity logic first-time pass rate Final accuracy of cloud-based risk control graph construction Core data outbound rate Traditional "device-side OCR + cloud-based rules" separation architecture 145 ms 82.3% 85.1% 100% (plain text) This invention is a verifiable perceptual computing architecture for VPCs. 162 ms 99.98% 97.6% 0% (Homomorphic Ciphertext)

[0109] Experimental data clearly shows that while this invention adds approximately 17ms of processing latency on the edge side due to hardware interrupt reconfiguration (which conforms to the theoretical value of sub-millisecond timing settings), it significantly increases the logic self-consistency rate to 99.98%, completely resolving the probabilistic errors of traditional architectures and achieving extremely high cloud-based analysis accuracy. (See attached manual.) Figure 5 A slice of the underlying C language driver code that implements the above interrupt refactoring process is given.

[0110] It should be noted that the "direct modification of memory-mapped control registers via firmware instructions" described in this embodiment can be implemented in commercial hardware by calling the underlying computation graph dynamic update API provided by a specific NPU vendor (such as the dynamic weight interface of TensorRT or the underlying interface of Ascend C operator), combined with a customized driver layer kernel module to achieve hardware-level interrupt response and parameter injection without changing the physical transistor architecture of the general-purpose chip.

[0111] The essence of this invention is not a specific business or financial rule calculation, but rather a low-level hardware control architecture for Neuro-Symbolic AI. The financial transaction records described herein are merely a specific implementation scenario for verifying the effectiveness of this general computing architecture in 'logic-driven perception reconstruction'.

[0112] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for privacy protection analysis of financial transaction records based on edge computing gateways, characterized in that, The edge computing gateway is configured with a neural network processing unit (NPU), a trusted execution environment (TEE), and a high-speed collaborative channel connecting the NPU and the TEE based on an underlying bus protocol. The method includes: Step S1: Receive the original financial transaction file, and extract the initial text data from the financial transaction file by running the layout analysis and optical character recognition (OCR) model through the NPU; Step S2: Within the TEE, identify sensitive entities in the initial text data, replace the sensitive entities with encryption masks using an encryption algorithm, and generate desensitized feature data; Step S3: Within the TEE, the initial text data is mapped into Satisfiability Modulus Theory (SMT) constraint expressions, and these expressions are input into a preset constraint solver for logical self-consistency verification. When the constraint solver returns a logically consistent result, the current text data is determined to be valid, and the output lock is released; When the constraint solver returns a logical conflict result, the residual of the financial value that violates the SMT constraint expression is extracted. A logical penalty term is calculated based on the mapping relationship between the financial value residual and the local character confidence. The NPU's interrupt service routine is triggered by calling the underlying driver interface through the high-speed collaborative channel. After the NPU responds to the interrupt, it retains the visual context cache tensor already generated by its feature extraction layer, calls only the underlying tensor operator dynamic update interface, injects the logical penalty term as a bias matrix, and dynamically adjusts the candidate path weights of the corresponding recognition results in its decoding layer. This allows the NPU to avoid repeatedly executing the time-consuming image feature extraction stage, and only regenerates the text data for verification until the constraint solver returns a logically consistent result. Step S4: Encrypt and transmit the desensitized feature data that has been unlocked to the cloud, so that the cloud can identify the fund flow structure based on the homomorphic topology graph and generate encrypted risk reasoning results, and receive the risk reasoning results returned by the cloud; Step S5: The edge computing gateway decrypts the risk reasoning result locally and reverses the encryption mask to restore the real plaintext data, generating a compliance analysis report.

2. The method according to claim 1, characterized in that, In step S1, the step of running the layout analysis and optical character recognition model through the NPU specifically includes: The NPU's built-in tensor acceleration engine calls a lightweight convolutional neural network to identify table borders in the original financial transaction file. Based on the NPU's direct memory access (DMA) channel, the original financial transaction file stored in the local SRAM is processed for pixel-level image correction, denoising, and watermark removal, generating a high-dimensional feature tensor to be decoded in a zero-copy manner.

3. The method according to claim 1, characterized in that, In step S3, the satisfiability modulus (SMT) constraint expression includes at least one of the following: Based on a pre-built financial constraint template library, the extracted plaintext values ​​are mapped into formalized accounting identity constraints, temporal logic constraints, and loan balance constraint equations; wherein, the temporal logic constraints are used in the solver to determine whether the dependencies between transaction time nodes result in mathematical inversion.

4. The method according to claim 1, characterized in that, In step S3, the calculation model and dynamic adjustment process of the logical penalty term specifically include: Let the residual of the financial value be G, and the average character confidence scalar of the local region of the image be... The sensitivity hyperparameter is The logical penalty term The calculation formula is: ； The NPU's decoder reads the feature tensor of the target region that caused the logical conflict from the local cache and re-executes the beam search decoding; when calculating the probability of the candidate sequence, it dynamically calculates the logical guidance coefficient based on the probability distribution entropy of the current beam search. The original visual probability score is combined with the logical penalty term to reduce the weight of the preferred candidate path that causes the logical conflict, and to activate the secondary candidate path that satisfies the logical self-consistency result.

5. The method according to claim 1, characterized in that, In step S5, the method further includes an integrity verification step: The hardware security module (HSM) within the edge computing gateway calls the built-in hardware cryptographic algorithm engine to calculate the hash digest of the restored plaintext data, and compares it with the Local Sensitive Hash (LSH) generated during the acquisition phase of the original financial transaction file to verify data integrity.

6. The method according to claim 1, characterized in that, In step S4, the identification of the fund flow structure by the cloud based on the homomorphic topology graph specifically includes: The transaction node identifiers in the de-identified feature data are subjected to deterministic pseudo-name calculation using a keyed hash message authentication code to generate encrypted nodes. The transaction amount is encrypted using the Paillier additive homomorphic encryption algorithm to generate plaintext edge weights, thereby constructing the homomorphic topology graph. The structure of the homomorphic topology graph is analyzed using a graph neural network (GNN) model that includes a joint loss function of cross-entropy loss and logical violation penalty term to identify abnormal fund flow patterns.

7. A financial transaction privacy protection analysis terminal based on an edge computing gateway, characterized in that, include: The communication interface unit is used to receive the original financial transaction files and to perform encrypted data interaction with the cloud. The Neural Processing Unit (NPU) is used to run layout analysis and optical character recognition models to extract text data. After responding to the interrupt service routine, it directly modifies its memory-mapped control register by calling the underlying firmware interface to inject logical penalty terms and dynamically adjusts the decoding weights to regenerate text data. The Trusted Execution Environment (TEE) includes a desensitization module and a constraint solver. It is used to replace sensitive entities in the text data with encryption masks to generate desensitized feature data, and to map the text data into SMT constraint expressions for logical self-consistency verification. When a verification conflict occurs, it extracts the financial value residuals that violate the SMT constraint expressions, and calculates the logical penalty term based on the mapping relationship between the financial value residuals and the local character confidence. A high-speed collaborative channel, relying on the internal interconnection bus of the edge computing gateway, logically connects the NPU and the TEE. When a logical conflict is determined, the logical penalty item is transmitted back to the NPU, and the interrupt service routine of the NPU is triggered. The Hardware Security Module (HSM) is used to manage encryption / decryption keys and signature verification.

8. The terminal according to claim 7, characterized in that, The terminal is configured to perform the financial transaction privacy protection analysis method based on an edge computing gateway as described in any one of claims 1 to 6.

9. The terminal according to claim 7, characterized in that, The TEE is configured to: open the data output port of the communication interface unit if and only if the constraint solver returns the logically consistent result; otherwise, send an edge-triggered interrupt signal to the NPU through the high-speed cooperative channel by calling the underlying driver, and pack the target region ID that caused the logical conflict and the logical penalty term into a specific logical memory address of the NPU to force the NPU to perform decoding and reshaping.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the program is executed by the processor, it implements the financial transaction privacy protection analysis method based on the edge computing gateway as described in any one of claims 1 to 6.

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