A multi-frequency reconfigurable all-digital transmitter chip

Abstract

The application discloses a multi-frequency reconfigurable all-digital transmitter chip, which comprises a multi-path baseband I / Q signal, a multi-frequency reconfigurable digital front-end processing module, a multi-frequency reconfigurable modulator module, a digital modulation output interface, a high-speed serial transmitter and a parameter configuration interface and control module; the multi-path baseband I / Q signal provides one or more paths of baseband I / Q data to be transmitted; the multi-frequency reconfigurable digital front-end processing module performs multi-phase interpolation and multi-phase up-conversion on the multi-path baseband I / Q data to form a multi-frequency composite digital signal; the multi-frequency reconfigurable modulator module is connected with the multi-frequency reconfigurable digital front-end processing module; the digital modulation output interface maps the multi-frequency digital modulation signal to a corresponding high-speed serial transmitter according to a transmission mode; the high-speed serial transmitter is connected with the digital modulation output interface to form a multi-frequency radio frequency signal; and the parameter configuration interface and control module are used for receiving external configuration data and controlling parameter configuration and starting timing of each module.

Description

Technical Field

[0001] This invention belongs to the field of wireless communication transmitter technology, specifically relating to a multi-frequency reconfigurable all-digital transmitter chip. Background Technology

[0002] With the rapid evolution of fifth-generation (5G) and future sixth-generation (6G) mobile communication technologies, the Internet of Things (IoT), and software-defined radio (SDR) technologies, wireless communication systems are increasingly demanding multi-band, multi-mode, and high-bandwidth concurrent transmission. Especially in application scenarios such as carrier aggregation, multi-service parallel transmission, and dynamic spectrum allocation, transmitters need to have high frequency reconfigurability and broadband signal processing capabilities.

[0003] Traditional radio frequency (RF) transmitters typically employ analog up-conversion, analog local oscillators, and linear power amplifiers to shift baseband or intermediate frequency (IF) signals to the RF band for power amplification and output. While widely used, this architecture often suffers from high power consumption, insufficient frequency configuration flexibility, complex analog circuit design, and limited system integration, making it difficult to meet the demands of next-generation wireless communication systems for flexible multi-frequency configuration and high integration. The all-digital transmitter (ADT) aims to reduce the bulky and difficult-to-reconfigure analog components in the transmitter and transfer baseband signal processing and modulation to the digital domain. Therefore, it offers greater reconfiguration flexibility and has the potential to reduce system power consumption when combined with high-efficiency switching power amplifiers, becoming an important direction in the evolution of wireless communication system architecture. With the development of CMOS technology, the chip implementation of all-digital transmitters has further achieved advantages such as high integration, small area, and low cost.

[0004] Currently, researchers both domestically and internationally have proposed various all-digital transmitter schemes, focusing on key technologies such as multi-band transmission, digital up-conversion, and quantization modulators. Delta Sigma modulators (DSMs) are a type of quantization modulation structure widely used in all-digital transmitters. These modulators convert high-resolution baseband or intermediate frequency digital signals into low-bit-width, high-speed digital modulation signals through oversampling and noise shaping to drive high-efficiency switching power amplifiers, thereby improving system efficiency. However, existing all-digital transmitter schemes still suffer from insufficient flexibility in switching the number of frequency bands, limited transmission frequency adjustment capabilities, and difficulties in balancing area and timing overhead during chip implementation. Especially in scenarios involving multi-frequency concurrent transmission and high oversampling rate quantization modulation, large-scale operations such as digital interpolation, digital up-conversion processing, and multi-core parallel modulation place higher demands on the timing, area, and resource overhead of digital circuits. Existing solutions typically use FPGAs or other programmable logic devices for prototype verification to facilitate rapid algorithm verification and system construction. However, they still have certain limitations in terms of resource scale, power consumption, integration, and engineering deployment capabilities, making it difficult to meet the demand for multi-frequency reconfigurable all-digital transmitters to achieve high integration, small area, and low power consumption on a chip-based basis.

[0005] Therefore, it is necessary to propose a multi-frequency reconfigurable all-digital transmitter chip structure, which coordinates the design of digital core circuits such as multi-frequency reconfigurable digital front-end processing and high-performance quantization modulation, and is equipped with an effective on-chip parameter configuration and control mechanism to meet the configurable requirements of different transmission protocols, different transmission frequencies and different transmission modes. This enables flexible reconfiguration of the number of multi-frequency transmission bands and transmission frequencies, while taking into account the area, power consumption, timing and integration requirements in chip implementation.

[0006] An existing tri-band digital transmitter based on concurrent multi-frequency Delta-Sigma modulation and feedforward noise cancellation (S. Chung, R. Ma, KH Teo) can achieve concurrent tri-band transmission at 710 MHz, 1750 MHz, and 2510 MHz. This scheme focuses on noise cancellation and efficiency improvement in fixed tri-band scenarios. Its transmission band number and center frequency are mainly based on a predetermined tri-band structure, lacking a configurable modulation structure with enable levels for the chip's digital core and a unified on-chip parameter configuration control mechanism, making it difficult to simultaneously achieve flexible reconfiguration of the transmission band number and transmission frequency. A parallel all-digital tri-band RF transmission architecture for FPGAs (A Real-time Architecture for Agile and FPGA-based Concurrent Triple-Band All-Digital RF Transmission) can achieve concurrent tri-band transmission and possesses a certain degree of frequency flexibility. This solution primarily targets FPGA real-time prototyping and system-level implementation. It lacks a digital core structure for dedicated chips, on-chip parameter registers, and startup timing control mechanisms. Furthermore, it doesn't incorporate a mode-based dynamic shutdown design for the output channel and high-speed serial transmission link to balance reconfigurability and power consumption optimization. A 28 nm CMOS all-digital transmitter (All-Digital LTE SAW-Less Transmitter With DSP-Based Programming of RX-Band Noise, E. Roverato, M. Kosunen, K. Cornelissens) achieves receiver band noise suppression through digital bandpass Delta Sigma modulation and mismatch shaping. While this solution is a chip implementation, its focus is on out-of-band noise shaping for a single transmit channel and SAW-less applications, rather than an integrated all-digital transmitter chip structure with reconfigurable frequency bands and multiple frequency reconfigurable capabilities for multi-frequency concurrent transmission. Summary of the Invention

[0007] This invention provides a multi-frequency reconfigurable all-digital transmitter chip, comprising: multiple baseband I / Q signals, a multi-frequency reconfigurable digital front-end processing module, a multi-frequency reconfigurable modulator module, a digital modulation output interface, a high-speed serial transmitter, and a parameter configuration interface and control module; the multiple baseband I / Q signals are used to provide one or more channels of baseband I / Q data to be transmitted; the multi-frequency reconfigurable digital front-end processing module is used to perform multi-phase interpolation and multi-phase up-conversion on one or more channels of baseband I / Q data, so that each interpolated baseband signal is up-converted to a configurable target frequency, forming a multi-frequency composite digital signal; the multi-frequency reconfigurable modulator module is connected to the multi-frequency reconfigurable digital front-end processing module, and uses... The system performs quantization modulation and noise shaping on multi-frequency composite digital signals to form multi-frequency digital modulated signals. The digital modulation output interface is used to map the multi-frequency digital modulated signals to the corresponding high-speed serial transmitters according to the transmission mode. The high-speed serial transmitter is connected to the digital modulation output interface and is used to transmit the digital modulated signals at high speed to form multi-frequency radio frequency signals. The parameter configuration interface and control module are respectively connected to the multi-channel baseband I / Q signals, the multi-frequency reconfigurable digital front-end processing module, the multi-frequency reconfigurable modulator module, the digital modulation output interface, and the high-speed serial transmitter. They are used to receive external configuration data and control the parameter configuration and startup timing of each module in the digital core of the all-digital transmitter.

[0008] The present invention is achieved by at least one of the following technical solutions.

[0009] A multi-frequency reconfigurable all-digital transmitter chip includes: multiple baseband I / Q signals, a multi-frequency reconfigurable digital front-end processing module, a multi-frequency reconfigurable modulator module, a digital modulation output interface, a high-speed serial transmitter, and a parameter configuration interface and control module. The multi-channel baseband I / Q signal is used to provide one or more channels of baseband I / Q data to be transmitted; The multi-frequency reconfigurable digital front-end processing module is used to perform multi-phase interpolation and multi-phase up-conversion on one or more baseband I / Q data, so that each interpolated baseband signal is up-converted to a configurable target frequency to form a multi-frequency composite digital signal. The multi-frequency reconfigurable modulator module is connected to the multi-frequency reconfigurable digital front-end processing module and is used to perform quantization modulation and noise shaping on the multi-frequency composite digital signal to form a multi-frequency digital modulation signal; the digital modulation output interface is used to map the multi-frequency digital modulation signal to the corresponding high-speed serial transmitter according to the transmission mode; the high-speed serial transmitter is connected to the digital modulation output interface and is used to perform high-speed serial transmission of the digital modulation signal to form a multi-frequency radio frequency signal; The parameter configuration interface and control module are respectively connected to the multi-channel baseband I / Q signal, the multi-frequency reconfigurable digital front-end processing module, the multi-frequency reconfigurable modulator module, the digital modulation output interface, and the high-speed serial transmitter. They are used to receive external configuration data and control the parameter configuration and startup sequence of each module of the all-digital transmitter digital core.

[0010] Furthermore, the multi-frequency reconfigurable digital front-end processing module includes a multi-phase interpolation module, a multi-phase up-conversion module, and a digital combining module; The multiphase interpolation module is used to perform multiphase interpolation filtering on multiple baseband I / Q signals to improve the baseband signal sampling rate. The multiphase upconversion module calculates the corresponding phase parameters according to the configured frequency control word, inputs the direct frequency synthesis lookup table to generate multiphase digital local oscillator signals, and performs multiplication and subtraction combination operations on the parallel baseband I / Q signals of the multiphase interpolation signals with multiphase sine and multiphase cosine signals to shift each baseband signal to the corresponding target frequency position, thereby obtaining multi-upconverted digital signals. The digital combiner module is used to perform digital addition and combining on the multi-upconverted signals to form a multi-frequency composite digital signal.

[0011] Furthermore, the parameter configuration interface and control module output multiple frequency control words to the multiphase upconversion module to achieve frequency reconstruction; the multiphase upconversion module uses the frequency control words and multiple direct frequency synthesis units to generate multiphase local oscillator signals, and performs digital upconversion operations on the multiphase local oscillator signals and the multiphase interpolation signals output by the multiphase interpolation module to achieve spectrum shifting and output upconverted signals for each phase.

[0012] Furthermore, the multi-frequency reconfigurable modulator module includes a deinterleaving module, a multi-core parallel modulator module, and an interleaving module; The deinterleaving module is used to rearrange the multi-frequency composite digital signal to meet the data continuity requirements of multi-core parallel modulation processing; the multi-core parallel modulator module is used to perform quantization modulation and noise shaping on the data rearranged by the deinterleaving module to form a low-bit-width multi-frequency digital modulation parallel signal; the interleaving module is used to reassemble the parallel modulation results output by the multi-core parallel modulator module to form a digital modulation signal for input to the subsequent digital modulation output interface.

[0013] Furthermore, the multi-core parallel modulator module includes multiple modulation units that operate in parallel.

[0014] Furthermore, each modulator unit is implemented using a multi-level configurable SMASH-DSM unit.

[0015] Furthermore, the multi-level configurable SMASH-DSM unit includes a multi-level DeltaSigma modulator cascaded in SMASH form, with configurable activation levels. The multi-frequency transmission characteristics of the modulator can be reconstructed by configuring the DSM loop parameters of each level. The parameter configuration interface and control module output level control signals and DSM loop parameters of each level to the multi-level configurable SMASH-DSM unit for configuring the activation level and DSM loop parameters of the unit, thereby achieving reconfigurable modulation output of the multi-frequency digital modulation signal to meet modulation requirements under different transmission bandwidth and frequency conditions.

[0016] Furthermore, the digital modulation output interface is used to select the corresponding output channel according to the transmission mode configured by the parameter configuration interface and the control module, and to map the multi-frequency digital modulation signal output by the multi-frequency reconfigurable modulator module to the corresponding number of high-speed serial transmitters; for output channels and high-speed serial transmitters that are not enabled, they are controlled to be turned off through the parameter configuration interface and the control module to reduce the dynamic power consumption of the transmitter in multi-frequency switching scenarios.

[0017] Furthermore, the parameter configuration interface and control module includes a serial peripheral interface, a parameter register module, and a fully digital transmitter state machine module; the serial peripheral interface is used to receive external configuration data and write the external configuration data into the parameter register module; the parameter register module is used to store configurable parameters during the operation of the fully digital transmitter chip.

[0018] Furthermore, the fully digital transmitter state machine module loads the configuration data in the control parameter register module into each module in the initial state of the transmitter. After the configuration of each parameter is completed, the fully digital transmitter state machine module receives the start command input from the serial peripheral interface and outputs the corresponding enable signals of each module according to the start timing of each module, thereby realizing the configuration of working parameters and timing control of each module of the digital core of the fully digital transmitter chip, effectively supporting the realization of multi-frequency reconfigurable function.

[0019] Compared with the prior art, the present invention has the following beneficial effects: (1) In the multi-frequency reconfigurable digital front-end processing module, the present invention employs multi-phase interpolation and multi-phase up-conversion processing to improve the equivalent sampling rate of signal processing. In the multi-frequency reconfigurable modulator module, a multi-core parallel modulation implementation structure is adopted, enabling the spectrum shifting of multiple baseband signals and the quantization modulation processing with high oversampling rate to be completed in parallel digital circuit mode. This implementation method helps to alleviate the high sampling rate requirement of single-channel modulator on the chip's operating clock frequency, and can give full play to the advantages of the speed improvement of digital circuits under advanced technology, further improving the modulator's operating speed, thereby improving the frequency range of multi-frequency signal modulation and the broadband baseband signal processing capability, which is conducive to realizing a higher performance multi-frequency reconfigurable all-digital transmitter chip.

[0020] (2) This invention employs a multi-level configurable SMASH-DSM unit in the multi-frequency reconfigurable modulator module. By configuring the number of enabled levels and the loop parameters of each DSM level, the number of transmission bands and the transmission frequency of the transmitter can be reconfigured without changing the hardware circuit. Compared with the modulator implementation with a fixed number of bands, this invention reduces chip power consumption in application scenarios with different numbers of transmission bands and frequency configurations by bypassing the inactive DSM modulation stages and shutting down the corresponding output channels in fewer band transmission modes, thereby optimizing the hardware utilization efficiency of the multi-frequency reconfigurable all-digital transmitter chip.

[0021] (3) This invention integrates a parameter configuration interface and a control module on-chip. Through the serial peripheral interface and parameter register module, it configures multiple baseband signal data, multiple frequency control words, and multiple frequency reconfigurable modulation parameters, providing a low-cost and easy-to-implement on-chip reconfiguration scheme for multi-frequency reconfigurable all-digital transmitter chips. This scheme can flexibly configure the number of transmission bands and the transmission frequency of each band to meet the transmission requirements of various signal standards and communication protocols, significantly improving the flexibility and adaptability of all-digital transmitter chips in complex communication scenarios with multi-frequency dynamic switching and enhancing their application value in software radio engineering. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of the multi-frequency reconfigurable all-digital transmitter chip structure for an embodiment.

[0023] Figure 2 This is a schematic diagram of the structure of the multi-frequency reconfigurable digital front-end processing module in an embodiment.

[0024] Figure 3 This is a schematic diagram of the multi-frequency reconfigurable modulator module structure in an embodiment.

[0025] Figure 4 This is a schematic diagram of the parameter configuration interface and control module structure for an embodiment.

[0026] Figure 5 The multi-frequency reconfigurable all-digital transmitter chip used in this embodiment outputs a spectrum diagram when switching between single-frequency / dual-frequency / triple-frequency transmission modes.

[0027] Figure 6 The frequency reconstruction output spectrum of the multi-frequency reconfigurable all-digital transmitter chip in the tri-frequency transmission mode is shown in the example. Detailed Implementation

[0028] The present invention will now be described in further detail with reference to the accompanying drawings. It should be understood that the following specific embodiments are for illustrative purposes only and are not intended to limit the scope of protection of the present invention.

[0029] like Figure 1 As shown, this embodiment of a multi-frequency reconfigurable all-digital transmitter chip includes a multi-channel baseband I / Q signal module 110, a multi-frequency reconfigurable digital front-end processing module 120, a multi-frequency reconfigurable modulator module 130, a digital modulation output interface 140, a high-speed serial transmitter 160, and a parameter configuration interface and control module 150. The multi-frequency reconfigurable digital front-end processing module 120, the multi-frequency reconfigurable modulator module 130, the digital modulation output interface 140, and the parameter configuration interface and control module 150 constitute the digital core of the all-digital transmitter chip.

[0030] In one embodiment, the multi-channel baseband I / Q signal module 110 is used to provide one or more channels of baseband I / Q data to be transmitted. The multi-channel baseband I / Q data can be baseband signal data of different bandwidths and different standards. The parameter configuration interface and control module 150 can select or configure the multi-channel baseband I / Q data to meet the signal input requirements of different multi-frequency transmission modes.

[0031] In one embodiment, a multi-frequency reconfigurable digital front-end processing module 120 performs multi-phase interpolation and multi-phase up-conversion on one or more baseband I / Q data streams, up-converting each interpolated baseband signal to a configurable target frequency to form a multi-frequency composite digital signal. A multi-frequency reconfigurable modulator module 130, connected to the multi-frequency reconfigurable digital front-end processing module 120, performs quantization modulation and noise shaping on the multi-frequency composite digital signal to form a low-bit-width multi-frequency digital modulated parallel signal. The multi-frequency reconfigurable modulator module 130 can configure the number of activation stages and modulation parameters for each stage according to control signals provided by the parameter configuration interface and the control module 150, thereby adapting to modulation requirements under different transmission bandwidth and frequency conditions.

[0032] In one embodiment, the parameter configuration interface and control module 150 are respectively connected to the multi-channel baseband I / Q signal module 110, the multi-frequency reconfigurable digital front-end processing module 120, the multi-frequency reconfigurable modulator module 130, the digital modulation output interface 140, and the high-speed serial transmitter 160. This interface receives external configuration data and controls the parameter configuration and startup timing of each module within the digital core of the all-digital transmitter chip. The digital modulation output interface 140 can map the low-bit-width multi-frequency digital modulation signal output from the digital core of the all-digital transmitter chip to the corresponding high-speed serial transmitter 160, depending on the enabled transmission mode and the subsequent output link format. Alternatively, it can be selectively mapped to a data format suitable for processing by a low-resolution digital-to-analog converter.

[0033] In one embodiment, the high-speed serial transmitter 160 is connected to the digital modulation output interface 140 for high-speed serial transmission of the digital modulation signal, which is then converted into a multi-frequency radio frequency signal via an optional combiner. In another embodiment, the number of activated high-speed serial transmitters 160 can correspond to the number of activated stages of the multi-frequency reconfigurable modulator module 130 and the output channels of the digital modulation output interface 140, thereby adapting to transmission requirements in single-frequency, dual-frequency, or multi-frequency transmission modes. For inactive transmission modes or output channels, the relevant output channels and the operating state of the high-speed serial transmitter 160 can be shut down through the parameter configuration interface and the control module 150, achieving dynamic power consumption optimization.

[0034] Through the above structure, this embodiment completes the front-end digital processing of multiple baseband signals, multi-frequency reconfigurable modulation, and digital modulation output organization in the chip's digital core, and realizes multi-frequency radio frequency signal transmission in conjunction with the high-speed serial transmitter 160. This structure can flexibly configure the number of transmission bands and transmission frequencies through the parameter configuration interface and control module 150 without changing the hardware circuit, thereby meeting the all-digital transmission requirements in multi-frequency dynamic switching scenarios.

[0035] like Figure 2 The multi-frequency reconfigurable digital front-end processing module shown is described. The multi-frequency reconfigurable digital front-end processing module 120 includes a multi-phase interpolation module 210, a multi-phase up-conversion module 220, and a digital combiner module 230.

[0036] In one implementation, the multiphase interpolation module 210 uses a multiphase parallel interpolation structure to perform interpolation filtering on each baseband I / Q signal to improve the baseband signal sampling rate and generate a multiphase interpolated signal. The multiphase upconversion module 220 calculates the corresponding phase parameters according to the configured frequency control word, inputs the Direct Digital Synthesizer (DDS) lookup table to generate a multiphase digital local oscillator signal, and performs multi- and subtraction combination operations on the parallel baseband I / Q signals of the multiphase interpolation signal with multiphase sine and multiphase cosine signals, thereby shifting each baseband signal to the corresponding target frequency position to obtain a multi-upconverted digital signal. The parameter configuration interface and control module 150 outputs multiple frequency control words to the multi-phase up-conversion module 220 to achieve frequency reconstruction. The digital combiner module 230 is used to add and combine the multi-up-converted digital signals to form a multi-frequency composite digital signal. Specifically, the multi-phase up-conversion module 220 uses the frequency control words and multiple direct frequency synthesis units to generate multi-phase local oscillator signals, and performs digital up-conversion operations on the multi-phase local oscillator signals and the multi-phase interpolation signals output by the multi-phase interpolation module 210 to achieve spectrum shifting and output the up-converted signals of each phase. The digital combiner module 230 is used to digitally add and combine the multi-up-converted signals to form a multi-frequency composite digital signal.

[0037] In this implementation, when the multiphase parallelism of multiphase interpolation and multiphase upconversion is set to P, the equivalent sampling rate of the multiphase interpolation signal is increased to P times that of the original baseband signal, and the size of the subsequent multiplexing and storage units will also increase accordingly. Therefore, the multiphase parallelism can be set according to the baseband sampling frequency and the transmitter's requirements for the radio frequency sampling frequency to balance transmitter performance and chip area overhead. At the same time, multiphase upconversion uses a direct frequency synthesis unit as a lookup table to generate multiphase local oscillators, which can generate any multiphase local oscillator signal within a specified carrier frequency range. This eliminates the need for digital circuits to directly implement nonlinear operations with large timing overhead, such as division or trigonometric functions, and enables efficient digital front-end processing of multi-frequency signals while taking into account chip area overhead and timing implementation difficulty.

[0038] like Figure 3 As shown, Figure 3This is a schematic diagram of the multi-frequency reconfigurable modulator module 130. The multi-frequency reconfigurable modulator module 130 includes a deinterleaving module 310, a multi-core parallel modulator module 320, and an interleaving module 330. The deinterleaving module 310 rearranges the multi-frequency composite digital signal to meet the data continuity requirements of multi-core parallel modulation processing. The multi-core parallel modulator module 320 performs quantization modulation and noise shaping on the rearranged data from the deinterleaving module 310 to form a low-bit-width multi-frequency digital modulation parallel signal. The interleaving module 330 reassembles the parallel modulation results output by the multi-core parallel modulator module 320 to form a digital modulation signal for input to the subsequent digital modulation output interface 140.

[0039] In one implementation, since multiple modulation units in the multi-core parallel modulator module 320 have feedback loops, each modulation unit has a requirement for the continuity of input data. Therefore, the deinterleaving module 310 is used to transpose the multi-phase parallel input data, so that the data entering each modulation unit has a certain time continuity. At the same time, the timing of data processing by each modulation unit's SMASH-DSM unit 340 is aligned by controlling the input delay chain of the modulation unit. The delay length of each path depends on the total number of parallel paths P and the position of the path. The first path does not need to go through a discrete delay unit to enter the first path's SMASH-DSM unit 340 for modulation, while the second path needs to go through a discrete delay unit z of length P. -p Only then can it enter the SMASH-DSM unit 340 of the second path for modulation, until the Pth path needs to pass through the discrete delay unit z of length PP-1. -p(p-1) Only then can the data enter the SMASH-DSM unit 340 of the P-th channel for modulation, so that the data entering each modulation unit can achieve timing alignment.

[0040] The multiple parallel modulation units in the multi-core parallel modulator module 320 are implemented using a multi-level configurable robust multi-level noise-shaping Delta Sigma modulation unit 340 (SMASH-DSM unit). Each modulation unit performs quantization modulation and noise shaping on the input data in a parallel structure to form a low-bit-width multi-frequency digital modulation parallel signal. The signal is then re-aligned and transposed through the output delay chain and interleaving module 330, restoring the multi-phase parallel data organization order of the multi-core parallel processing results for subsequent links to achieve serial transmission processing.

[0041] The multi-stage configurable robust multi-stage noise-shaping Delta Sigma modulation unit 340 (SMASH-DSM unit) includes a multi-stage Delta Sigma modulator (DSM) cascaded in the form of robust multi-stage noise shaping (SMASH). In this embodiment, the number of enabled stages of the Delta Sigma modulator (DSM) can be configured via control signals, and the loop parameters of each DSM can be configured independently. Since the multi-stage DSM adopts the SMASH cascading method, the frequency transmission characteristics of each modulation unit can work together to affect the overall modulator output through the cascading relationship, forming a multi-frequency transmission characteristic.

[0042] In one embodiment, the SMASH-DSM unit 340 includes N cascaded DSMs, wherein the input signal X is input to the first-stage DSM, and the output signal V1 of the first-stage DSM is the output signal V1; the structures of the DSMs from the first stage to the Nth stage are similar. The cascading of the N-stage SMASH involves inputting the quantization noise E1 of the first-stage DSM into the second stage for modulation, and the quantization noise E2 of the second stage into the third stage for modulation, up to the (N-1)th stage quantization noise E... N-1 The input to the Nth stage is quantized and modulated; simultaneously, the output of the Nth stage modulator is V. N Feedback to the (N-1)th stage, the output V3 of the third-stage modulator will be fed back to the second stage, and the output V2 of the second-stage modulator will be fed back to the first stage, forming the output V of the first-stage modulator. 1。 The loop parameter L of the first-stage loop filter 01 L 11 The noise shaping characteristics of the first-stage DSM and the loop parameters L of the second-stage loop filter are affected. 02 L 12 The noise shaping characteristics of the second-stage DSM, ..., the loop parameters L of the Nth-stage loop filter. 0N L 1N The noise shaping characteristics of the Nth-level DSM are affected. The noise shaping transmission characteristics of each level of DSM can collectively affect the overall SMASH-DSM unit 340 through a cascading relationship, forming multi-frequency transmission characteristics. By configuring the DSM of a specific number of levels and the corresponding loop parameters of each level of DSM through the parameter configuration interface and control module 150, the multiple frequency transmission characteristics of the SMASH-DSM unit 340 can be changed, forming a multi-frequency reconfigurable digital modulation signal.

[0043] The digital modulation output interface 140 is used to select the corresponding output channel according to the transmission mode configured by the parameter configuration interface and the control module 150, and to map the multi-frequency digital modulation signal output by the multi-frequency reconfigurable modulator module 130 to the corresponding number of high-speed serial transmitters 160; for the output channels and high-speed serial transmitters 160 that are not enabled, they are controlled to be turned off through the parameter configuration interface and the control module 150 to reduce the dynamic power consumption of the transmitter in the multi-frequency switching scenario.

[0044] like Figure 4 As shown, Figure 4 This is a schematic diagram of the parameter configuration interface and control module 150. The parameter configuration interface and control module 150 can flexibly configure multiple baseband signal data, multiple frequency control words, and multi-frequency reconfigurable modulator parameters according to different transmission protocol requirements, thereby realizing flexible configuration and reconfiguration of multiple baseband signals, the number of transmission bands, and multiple transmission frequencies of the all-digital transmitter chip. The parameter configuration interface and control module 150 includes a serial peripheral interface 510, an all-digital transmitter state machine module 520, and a parameter register module 530.

[0045] In this embodiment, the serial peripheral interface 510 communicates with the outside world via the standard SPI protocol, receives external configuration data, decodes externally sent instructions, and writes the external configuration data into the parameter register module 530. This enables the reading and writing of the parameter register module 530 and the startup and reset of the all-digital transmitter state machine module 520. The parameter register module 530 stores various configurable parameters required during the operation of the all-digital transmitter chip, including baseband configuration signals, multiple frequency control words, DSM loop parameters at each stage, and stage control signals. Based on different parameter types, the parameter register module 530 outputs corresponding configuration data to the multiple baseband I / Q signal module 110, the multi-frequency reconfigurable digital front-end processing module 120, and the multi-frequency reconfigurable modulator module 130, thereby completing the on-chip configuration of baseband data selection, up-conversion frequency control, and modulator parameters.

[0046] The all-digital transmitter state machine module 520 is used to control the startup and operation sequence of each module in the digital core of the all-digital transmitter chip. In this embodiment, the all-digital transmitter state machine module 520 loads the configuration data stored in the control parameter register module 530 in the initial state of the transmitter to each module of the transmitter. After the parameters are configured, the all-digital transmitter state machine module 520 receives the startup command input through the serial peripheral interface 510 and outputs the enable signals of each module in sequence according to the preset startup sequence. This ensures that the multi-channel baseband I / Q signal module 110, the multi-frequency reconfigurable digital front-end processing module 120, the multi-frequency reconfigurable modulator module 130, and the subsequent output related modules enter the working state in sequence, thereby realizing the configuration of working parameters and timing control of each module in the digital core of the all-digital transmitter chip, effectively supporting the realization of the multi-frequency reconfigurable function.

[0047] Through the above structure, the parameter configuration interface and control module 150 can realize unified parameter configuration and startup timing control of each module in the digital core of the multi-frequency reconfigurable all-digital transmitter chip on the chip, providing support for the chip's reconfigurable operation under different transmission protocols, transmission frequencies, and transmission modes. Due to the use of a control method combining serial peripheral interfaces, parameter registers, and state machines, this implementation can achieve multi-parameter configuration and multi-module collaborative control of the chip with low hardware overhead, making it suitable for the engineering implementation of multi-frequency reconfigurable all-digital transmitter chips.

[0048] like Figure 5 As shown, Figure 5 This is an output spectrum diagram of the multi-frequency reconfigurable all-digital transmitter chip of the present invention in single-frequency, dual-frequency, and tri-frequency transmission modes. In this embodiment, the number of activation levels of the multi-level configurable SMASH-DSM unit is configured through the parameter configuration interface and the control module 150, enabling the all-digital transmitter chip to operate in single-frequency, dual-frequency, and tri-frequency transmission modes respectively. Figure 5 In this context, N represents the number of stages of the configured SMASH-DSM unit 340. When N=1, the transmitter outputs a single target transmission band; when N=2, the transmitter outputs two target transmission bands; and when N=3, the transmitter outputs three target transmission bands. Figure 5 As can be seen, the number of transmission bands in the output spectrum changes accordingly when the activation level changes, indicating that the all-digital transmitter chip of the present invention can achieve reconfiguration of the number of transmission bands without changing the hardware circuit.

[0049] like Figure 6 As shown, Figure 6This is the frequency reconstruction output spectrum diagram of the multi-frequency reconfigurable all-digital transmitter chip of the present invention in tri-frequency transmission mode. In this embodiment, while maintaining the tri-frequency transmission mode unchanged, the DSM loop parameters of each level of the multi-level configurable SMASH-DSM unit are configured through the parameter configuration interface and control module 150, thereby reconstructing the multi-frequency transmission characteristics of the modulator. Figure 6 As can be seen, in the tri-frequency transmission mode, the center frequency position of each transmission band can change with the parameter configuration, indicating that the all-digital transmitter chip of the present invention can realize the reconfigurability of the transmission frequency without changing the hardware circuit, and can meet the needs of flexible configuration of the number of transmission bands and transmission frequency in multi-frequency transmission scenarios.

[0050] Although the invention has been described above in conjunction with the accompanying drawings, the invention is not limited to the specific embodiments described. The above embodiments are merely illustrative and not restrictive. Those skilled in the art can make many modifications without departing from the spirit of the invention, and all such modifications are within the scope of protection of the invention.

Claims

1. A multi-frequency reconfigurable all-digital transmitter chip, characterized in that, include: Multi-channel baseband I / Q signal (110), multi-frequency reconfigurable digital front-end processing module (120), multi-frequency reconfigurable modulator module (130), digital modulation output interface (140), high-speed serial transmitter (160), and parameter configuration interface and control module (150). The multi-channel baseband I / Q signal (110) is used to provide one or more channels of baseband I / Q data to be transmitted; The multi-frequency reconfigurable digital front-end processing module (120) is used to perform multi-phase interpolation and multi-phase up-conversion on one or more baseband I / Q data, so that each baseband signal after interpolation is up-converted to a configurable target frequency to form a multi-frequency composite digital signal. The multi-frequency reconfigurable modulator module (130) is connected to the multi-frequency reconfigurable digital front-end processing module (120) and is used to perform quantization modulation and noise shaping on the multi-frequency composite digital signal to form a multi-frequency digital modulation signal; the digital modulation output interface (140) is used to map the multi-frequency digital modulation signal to the corresponding high-speed serial transmitter (160) according to the transmission mode; the high-speed serial transmitter (160) is connected to the digital modulation output interface (140) and is used to perform high-speed serial transmission of the digital modulation signal to form a multi-frequency radio frequency signal; The parameter configuration interface and control module (150) are respectively connected to the multi-channel baseband I / Q signal (110), the multi-frequency reconfigurable digital front-end processing module (120), the multi-frequency reconfigurable modulator module (130), the digital modulation output interface (140), and the high-speed serial transmitter (160), and are used to receive external configuration data and control the parameter configuration and startup sequence of each module of the digital core of the all-digital transmitter.

2. The multi-frequency reconfigurable all-digital transmitter chip according to claim 1, characterized in that, The multi-frequency reconfigurable digital front-end processing module (120) includes a multi-phase interpolation module (210), a multi-phase up-conversion module (220), and a digital combiner module (230). The multiphase interpolation module (210) is used to perform multiphase interpolation filtering on multiple baseband I / Q signals (110) to improve the baseband signal sampling rate; the multiphase upconversion module (220) calculates the corresponding phase parameters according to the configured frequency control word, inputs the direct frequency synthesis lookup table to generate multiphase digital local oscillator signals, and performs multi- and subtraction combination operations on the parallel baseband I / Q signals of the multiphase interpolation signals with multiphase sine signals and multiphase cosine signals, thereby shifting each baseband signal to the corresponding target frequency position to obtain multi-upconverted digital signals; the digital combiner module (230) is used to perform digital addition and combining on the multi-upconverted signals to form a multi-frequency composite digital signal.

3. The multi-frequency reconfigurable all-digital transmitter chip according to claim 2, characterized in that, The parameter configuration interface and control module (150) outputs multiple frequency control words to the multiphase upconversion module (220) to achieve frequency reconstruction; the multiphase upconversion module (220) uses the frequency control words and multiple direct frequency synthesis units to generate multiphase local oscillator signals, and performs digital upconversion operations on the multiphase local oscillator signals and the multiphase interpolation signals output by the multiphase interpolation module (210) to achieve spectrum shift and output upconverted signals of each phase.

4. The multi-frequency reconfigurable all-digital transmitter chip according to claim 1, characterized in that, The multi-frequency reconfigurable modulator module (130) includes a deinterleaving module (310), a multi-core parallel modulator module (320), and an interleaving module (330). The deinterleaving module (310) is used to rearrange the data of the multi-frequency composite digital signal to meet the data continuity requirements of the multi-core parallel modulation processing; the multi-core parallel modulator module (320) is used to perform quantization modulation and noise shaping processing on the data rearranged by the deinterleaving module (310) to form a low-bit-width multi-frequency digital modulation parallel signal; the interleaving module (330) is used to reassemble the parallel modulation results output by the multi-core parallel modulator module (320) to form a digital modulation signal for input to the subsequent digital modulation output interface (140).

5. A multi-frequency reconfigurable all-digital transmitter chip according to claim 1, characterized in that, The multi-core parallel modulator module (320) includes multiple modulation units that operate in parallel.

6. A multi-frequency reconfigurable all-digital transmitter chip according to claim 5, characterized in that, Each modulator unit is implemented using a multi-level configurable SMASH-DSM unit (340).

7. A multi-frequency reconfigurable all-digital transmitter chip according to claim 6, characterized in that, The multi-level configurable SMASH-DSM unit (340) includes a multi-level Delta Sigma modulator cascaded in SMASH form. The number of its activation levels is configurable, and the multi-frequency transmission characteristics of the modulator can be reconstructed by configuring the DSM loop parameters of each level. The parameter configuration interface and control module (150) outputs level control signals and DSM loop parameters of each level to the multi-level configurable SMASH-DSM unit (340) to configure the number of activation levels and DSM loop parameters of each level, thereby realizing the reconstructable modulation output of the multi-frequency digital modulation signal to meet the modulation requirements under different transmission frequency bands and transmission frequency conditions.

8. A multi-frequency reconfigurable all-digital transmitter chip according to claim 1, characterized in that, The digital modulation output interface (140) is used to select the corresponding output channel according to the transmission mode configured by the parameter configuration interface and the control module (150), and to map the multi-frequency digital modulation signal output by the multi-frequency reconfigurable modulator module (130) to the corresponding number of high-speed serial transmitters (160); for the output channels and high-speed serial transmitters (160) that are not enabled, they are controlled to be turned off through the parameter configuration interface and the control module (150) to reduce the dynamic power consumption of the transmitter in the multi-frequency switching scenario.

9. A multi-frequency reconfigurable all-digital transmitter chip according to claim 1, characterized in that, The parameter configuration interface and control module (150) includes a serial peripheral interface (510), a parameter register module (530), and a fully digital transmitter state machine module (520); the serial peripheral interface (510) is used to receive external configuration data and write the external configuration data into the parameter register module (530); the parameter register module (530) is used to store configurable parameters during the operation of the fully digital transmitter chip.

10. A multi-frequency reconfigurable all-digital transmitter chip according to claim 9, characterized in that, The fully digital transmitter state machine module (520) loads the configuration data in the control parameter register module (530) to each module in the initial state of the transmitter. After the configuration of each parameter is completed, the fully digital transmitter state machine module (520) receives the start command input from the serial peripheral interface (510) and outputs the corresponding enable signal of each module according to the start timing of each module, thereby realizing the configuration of working parameters and timing control of each module of the digital core of the fully digital transmitter chip, effectively supporting the realization of multi-frequency reconfigurable function.

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