An edge-computing-based internet of things gateway data processing method

Abstract

This invention relates to the field of IoT data processing technology and discloses an IoT gateway data processing method based on edge computing. The method includes establishing an association model that defines the mapping relationship between device control commands, hardware acquisition strategies, and physical hysteresis characteristics; maintaining a circular buffer with historical backtracking capabilities in circular physical memory based on this model; generating time-aligned physical data fragments from the buffer based on the model when a change in control commands is detected; binding and encapsulating logical domain anchor headers, physical domain anchor headers, and data fragments to generate dual-headed anchored data packets; and executing data output operations based on a data scheduling strategy. This invention solves the problem of timing misalignment between control logic and physical response by establishing an association model and maintaining a circular buffer with historical backtracking capabilities, using backtracking to compensate for the time lag of physical responses, and ensuring that data fragments accurately correspond to the effective physical time window of command execution.

Description

Technical Field

[0001] This invention relates to the field of Internet of Things (IoT) data processing technology, specifically to an IoT gateway data processing method based on edge computing. Background Technology

[0002] In modern Industrial Internet of Things (IIoT) and edge computing architectures, edge gateways serve as the hub connecting industrial controllers and cloud platforms, undertaking the tasks of data acquisition, protocol conversion, and preliminary processing. Edge gateways typically need to receive device operation commands from the controller while simultaneously collecting physical operating status data of the device through sensor interfaces, such as vibration, temperature, or current signals. This architecture aims to achieve device status monitoring, fault diagnosis, and the construction of digital twin models by analyzing the physical behavior of the device when executing specific commands.

[0003] However, existing IoT gateway data processing methods typically employ a simple triggering mechanism based on the system clock, meaning data capture or tagging begins immediately upon detecting a control command. Due to the inertia and backlash of mechanical transmission components, the actual physical action often lags behind the issuance of the logical command. This processing method, which does not consider physical hysteresis, results in a timing misalignment between the acquired data segments and the physical window of the device's actual action, failing to accurately reflect the true physical state during command execution. Furthermore, existing data encapsulation methods often transmit or store high-frequency sensor data and low-frequency control commands separately, leading to a lack of control logic context during subsequent data analysis and making it difficult to trace the specific operational intent at the time of data generation. In addition, for the control of high-frequency sampling hardware, existing technologies mostly adopt either command-triggered immediate start or continuous operation throughout the entire period. The former results in data loss during the initial stage of action due to the time overhead of hardware power-on initialization, while the latter leads to increased power consumption and heat accumulation in edge devices.

[0004] Therefore, how to achieve precise timing alignment between control logic and physical response while ensuring the integrity of data context and the scheduling efficiency of acquisition hardware is a problem that needs to be solved by those skilled in the art. Summary of the Invention

[0005] To address the shortcomings of existing technologies, this invention provides an IoT gateway data processing method based on edge computing, which solves the problems of timing misalignment between device control logic and physical response, lack of logical context association in data acquisition, and inaccurate control of hardware activation timing in existing technologies.

[0006] To address the above problems, the present invention provides the following technical solution:

[0007] This invention provides a data processing method for IoT gateways based on edge computing, employing the following technical solution:

[0008] A data processing method for an IoT gateway based on edge computing includes the following steps:

[0009] A correlation model was established that defines the mapping relationship between device control commands, hardware acquisition strategies, and physical hysteresis characteristics.

[0010] The underlying data acquisition behavior is controlled based on the aforementioned association model, and a circular buffer with historical backtracking capability is maintained in the circular physical memory space.

[0011] When a change in control command is detected, time-aligned physical data fragments are generated from the circular buffer with historical backtracking capability based on the association model.

[0012] The logical domain anchor header describing the control logic context, the physical domain anchor header describing the hardware acquisition configuration, and the time-aligned physical data segment are bound and encapsulated to generate a dual-headed anchored data packet.

[0013] Based on a preset data scheduling strategy, a data output operation is performed on the dual-headed anchored data packet.

[0014] By adopting the above technical solution, and by establishing the correlation model that includes physical hysteresis characteristics and cooperating with the circular buffer with historical backtracking capabilities, this invention can solve the spatiotemporal misalignment problem of the time when industrial field control commands are issued and the actual response time of sensors. The system does not intercept data at the instant the command is issued, but rather backtracks through the buffer based on the physical hysteresis characteristics to capture data segments reflecting the physical response of the command. Simultaneously, the dual-head anchoring structure binds the control logic context to physical parameters, achieving alignment between the logical and physical domains of edge-side data, providing a time-aligned data foundation for subsequent digital twin construction or fault analysis.

[0015] Furthermore, the association model is an instruction policy mapping matrix, the hardware acquisition policy includes a sampling policy parameter set containing the sampling frequency, the gain value of the analog front-end circuit, and the quantization bit width of the analog-to-digital converter, and the physical hysteresis characteristics include mechanical hysteresis time and hardware warm-up time; the control of the underlying data acquisition behavior based on the association model includes: pre-parsing the instruction sequence in the controller buffer, determining the hardware start-up timing, generating a hardware warm-up control signal, and starting acquisition in response to the hardware warm-up control signal; the generation of time-aligned physical data segments includes: extracting transitional state data from the circular buffer with historical backtracking capability based on the mechanical hysteresis time, and concatenating it with the currently acquired steady-state data in the time domain; the data output operation includes: writing to local storage space or sending through a network transmission channel; the execution of the data output operation includes: performing hierarchical storage or transmission scheduling on the dual-headed anchored data packets according to the current network status and local storage space occupancy rate.

[0016] By employing the above technical solution, hardware resource management is achieved using the instruction strategy mapping matrix. Pre-parsing the instruction sequence to initiate hardware warm-up in advance avoids data loss in the initial stage caused by startup delays in high-frequency acquisition hardware. Simultaneously, concatenating the transitional state data with the steady-state data allows for the reproduction of the physical changes that occur when the device transitions from a static state to a dynamic state or during a change in operating condition. The hierarchical storage scheduling strategy ensures system stability under network fluctuations or storage constraints, guaranteeing the retention and transmission of core data.

[0017] Furthermore, determining the hardware activation timing includes: based on the current system time, accumulating the ratio of the physical path length of all instructions from the current instruction in the instruction sequence to the target instruction to be executed in the instruction sequence to the theoretical feed rate, and correcting the theoretical feed rate using a real-time feed rate factor to calculate the expected execution time of the target instruction to be executed; the triggering condition for generating the hardware preheating control signal is: the time difference between the expected execution time and the current system time is greater than zero and less than or equal to the hardware preheating time corresponding to the target instruction to be executed, and the sampling frequency required by the target instruction to be executed is higher than the sampling frequency currently running on the edge computing gateway hardware.

[0018] By adopting the above technical solution, the system can calculate and predict the expected execution time of the target instruction based on the physical path and feed rate of motion control. By introducing the real-time feed rate coefficient for correction, the prediction logic can adapt to dynamic changes in processing speed temporarily adjusted by on-site operators. Hardware preheating is triggered when the sampling frequency required by the target instruction increases and time is tight, achieving immediate activation to reduce the overall power consumption and thermal load of the edge gateway, and ensuring that the hardware is ready at the moment of instruction execution.

[0019] Furthermore, the physical length of the circular buffer with historical backtracking capability is determined based on the product of the maximum value of all mechanical hysteresis times in the instruction policy mapping matrix, the highest sampling frequency supported by the hardware, and the buffer safety redundancy coefficient; maintaining the circular buffer with historical backtracking capability includes: maintaining a write pointer indicating the current write memory address offset and a time anchor register. Whenever a new sampled data point arrives, the write pointer is updated and the current system time is written to the time anchor register. When the write pointer reaches the end of the circular buffer with historical backtracking capability, it automatically jumps back to the beginning address of the circular buffer with historical backtracking capability.

[0020] By adopting the above technical solution, the length design of the circular buffer takes into account the maximum physical latency faced by the system, ensuring that even lagging physical signals can find corresponding historical data in the buffer, avoiding data being overwritten by new data. By maintaining the write pointer and the time anchor register, the system achieves continuous recording and time indexing of streaming data with low memory overhead, providing underlying data structure support for subsequent backtracking reading.

[0021] Furthermore, the extraction of transitional state data includes: determining a physical effective time window, wherein the start time of the physical effective time window is the start time of instruction logic execution, and the end time of the physical effective time window is the completion time of instruction logic execution plus the mechanical hysteresis time.

[0022] By adopting the above technical solution, the concept of the physical effective time window is clarified, and the data extraction range is shifted backward on the time axis by one mechanical hysteresis time. This processing method corrects the deviation between the control domain time and the physical domain time, ensuring that the extracted data segments correspond to the time period during which the command takes physical action, eliminating invalid silent data, and retaining characteristic data containing mechanical aftershocks or delayed responses.

[0023] Furthermore, the generation of time-aligned physical data segments also includes: calculating the start and end read pointers in the circular buffer with historical backtracking capability based on the time difference between the value of the time anchor register and the start and end times of the physical effective time window, combined with the sampling frequency in the sampling strategy parameter set containing the sampling frequency; if the start read pointer is less than the end read pointer, then directly read the data block between the start read pointer and the end read pointer; if the start read pointer is greater than the end read pointer, then perform two read operations, respectively reading the data segment from the start read pointer to the end of the circular buffer with historical backtracking capability and the data segment from the start address of the circular buffer with historical backtracking capability to the end read pointer, and splicing the two data segments to form the time-aligned physical data segment.

[0024] By adopting the above technical solution, the time window is mapped to a memory address pointer, realizing the indexing from the time domain to the storage domain. For the case where the circular buffer spans both ends of the memory, segmented reading and concatenation logic is designed to ensure the logical continuity of physical data, allowing upper-layer applications to directly obtain time-aligned data streams without having to deal with underlying memory fragmentation.

[0025] Furthermore, the logic domain anchor header includes a unique type identifier for the control instruction, a set of target control parameters, the start time of instruction logic execution, the completion time of instruction logic execution, and an environment status code; the physical domain anchor header includes the sampling frequency, the physical effective start time, the total number of data points, the gain setting value, and the sensor physical channel identifier.

[0026] By adopting the above technical solution, the structure of the dual-headed anchored data packet distinguishes between control intent and configuration parameters. The logical domain anchor header records the control context, and the physical domain anchor header records the hardware acquisition configuration. This data encapsulation method makes each data packet an independent unit, reducing the difficulty of parsing data stored in the cloud and supporting the reconstruction of on-site operating conditions without the assistance of an external database.

[0027] Furthermore, the generation of the dual-headed anchored data packet also includes: performing a joint hash calculation on the logical domain anchor header, the physical domain anchor header, and the time-aligned physical data segment to generate a data packet integrity check code, and encapsulating the data packet integrity check code into the dual-headed anchored data packet.

[0028] By adopting the above technical solution, the logical domain anchor, the physical domain anchor, and the time-aligned physical data segments are calculated holistically at the data generation source. This means that tampering with instruction parameters, changes in physical configuration, or damage to data packets can be detected, ensuring the integrity of industrial data throughout its lifecycle.

[0029] Furthermore, the step of performing hierarchical storage or transmission scheduling on the dual-headed anchored data packets based on the current network status and local storage space occupancy rate includes: placing the dual-headed anchored data packets into a transmission queue and periodically calculating the local storage space occupancy rate; setting a high occupancy rate threshold and a low occupancy rate threshold; when the local storage space occupancy rate exceeds the high occupancy rate threshold, discarding the earliest generated but untransmitted dual-headed anchored data packets in chronological order starting from the head of the transmission queue, until the local storage space occupancy rate falls back below the low occupancy rate threshold.

[0030] By adopting the above technical solution, an adaptive mechanism based on storage pressure was established. When data backlog occurs due to edge gateway offline or network congestion, priority is given to ensuring system operation. By discarding old data, it is ensured that new, timely data is sent after the network is restored, thus avoiding obsolete data blocking the transmission channel.

[0031] Furthermore, the calibration method for the mechanical hysteresis time is as follows: the control device executes the calibration command and records the time when the calibration command logic is completed, continuously monitors the sensor amplitude signal, and when the sensor amplitude signal is lower than the noise threshold determined based on the environmental background noise and the duration reaches the judgment duration, records the physical stability time, and determines the difference between the physical stability time and the time when the calibration command logic is completed as the mechanical hysteresis time.

[0032] By employing the above technical solution, a method for measuring physical characteristics is provided. By monitoring the vibration decay process after the device executes a command, the termination time of the physical action is determined using the characteristic that the signal energy is below the noise threshold. This method quantifies the differences in mechanical hysteresis between different devices, thereby providing calibration parameters for the correlation model and ensuring the accuracy of the timing alignment algorithm on different physical devices.

[0033] This invention provides a data processing method for IoT gateways based on edge computing. It has the following beneficial effects:

[0034] 1. This invention establishes an association model that defines the mapping relationship between device control commands, hardware acquisition strategies, and physical hysteresis characteristics. It maintains a circular buffer with historical backtracking capability in the circular physical memory space. Based on the mechanical hysteresis time, it extracts transitional data from the circular buffer with historical backtracking capability to generate time-aligned physical data fragments. It uses historical backtracking capability to compensate for the time lag of physical device response relative to control commands, ensuring that the acquired physical data fragments accurately correspond to the physical effective time window of the actual execution of the command, thus solving the problem of misalignment between control logic time and physical response time in industrial fields.

[0035] 2. This invention generates a dual-headed anchored data packet by binding and encapsulating a logical domain anchor header describing the control logic context, a physical domain anchor header describing the hardware acquisition configuration, and a time-aligned physical data segment. Furthermore, it performs a joint hash calculation on the logical domain anchor header, the physical domain anchor header, and the time-aligned physical data segment, thereby forcibly establishing a connection between the control intent and the physical reality. This ensures that each data packet independently contains complete logical context and hardware configuration information to achieve data self-description, avoiding the loss of data semantics due to the separation of data and metadata, and guaranteeing the overall integrity of the logical and physical domain data.

[0036] 3. This invention pre-parses the instruction sequence to calculate the expected execution time of the target instruction to be executed, and generates a hardware warm-up control signal when the time difference between this time and the current system time is less than the hardware warm-up time. This enables forward-looking control of the underlying data acquisition behavior, ensuring that the hardware startup is completed before the high sampling frequency requirement arrives. This eliminates the initial stage data loss caused by hardware startup delay, and avoids continuous high-load operation of the hardware while ensuring the integrity of data acquisition. Attached Figure Description

[0037] Figure 1 This is a flowchart of an IoT gateway data processing method based on edge computing according to an embodiment of the present invention;

[0038] Figure 2 This is a flowchart of data fragmentation and backtracking splicing based on a relative time sequence according to an embodiment of the present invention;

[0039] Figure 3 This is a schematic diagram of a dual-headed anchored data packet structure according to an embodiment of the present invention;

[0040] Figure 4 This is a comparison diagram of the hardware preheating control effect according to an embodiment of the present invention;

[0041] Figure 5 This is a comparison diagram of data fragmentation and backtracking stitching effects according to an embodiment of the present invention;

[0042] Figure 6 This is a schematic diagram of a cache management strategy based on storage level according to an embodiment of the present invention. Detailed Implementation

[0043] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0044] See attached document Figure 1 This invention provides a data processing method for an IoT gateway based on edge computing, comprising the following steps:

[0045] S100. Construct a spatiotemporal three-dimensional mapping matrix for the instruction strategy. Load the preset configuration file during the gateway initialization phase to define the mapping relationship between device control instructions and data processing strategies, including control instruction characteristics, sampling strategy parameter set, mechanical hysteresis time, and hardware warm-up time.

[0046] S200 executes hardware preheating control based on instruction prefetching. It reads the controller instruction buffer in real time through the fieldbus, calculates the expected execution time of the instruction to be executed, and triggers a hardware preheating interrupt when the preheating time condition is met and the hardware performance requirement is higher than the current state.

[0047] S300 operates a full-speed circular buffer and inertia retention strategy. The gateway's underlying module maintains a fixed-length circular buffer, continuously writing sensor data into the buffer at the highest fundamental frequency allowed by the hardware, and executing automatic overwrite rules to retain the original physical data within the most recent time period.

[0048] S400: Performs data slicing and backtracking splicing based on relative timing. When a control command switch is detected, the transition state slice is extracted from the ring buffer using the mechanical hysteresis parameter. The sampling frequency is adjusted according to the new command strategy to collect steady-state action slices. All sampling point timestamps are converted into relative timestamps.

[0049] S500: Construct a dual-headed anchored data packet, encapsulating the transition state slice and steady-state action slice into an action slice packet containing a globally unique identifier, working condition code and absolute start time;

[0050] S600 performs slice upload and cache management, puts the encapsulated data packets into the sending queue, and determines whether to temporarily store the data packets in the local storage area or use the idle bandwidth to upload them to the server in batches based on the current acquisition mode.

[0051] The above steps will be explained in detail below with reference to specific embodiments.

[0052] In step S100, a spatiotemporal mapping matrix for the instruction strategy is constructed. During system initialization, the edge computing gateway reads the configuration file stored in local non-volatile memory and constructs a multi-dimensional correlation model in memory. This model is built upon the principle that the physical response of industrial equipment inherently misaligns with control instructions in a spatiotemporal manner. By pre-constructing a static knowledge base, the system can translate abstract logical instructions into specific underlying hardware control parameters and timing compensation parameters, thereby achieving hardware-software collaboration at the edge. This step specifically includes the following sub-steps:

[0053] S101, The system defines a mapping set containing the correspondence between control commands and physical sampling behaviors. Its expression is as follows:

[0054] ;

[0055] in, This is the instruction index number, and its value is a positive integer. Indicates the first Class control command characteristics, which correspond to specific opcodes or status words parsed from industrial fieldbus protocols; Indicates when the device is in the first position The set of sampling strategy parameters that the gateway's underlying data acquisition module should execute under the operating conditions defined by the class control command characteristics; Indicates the first Mechanical hysteresis time corresponding to the characteristics of class control commands; Indicates the first Hardware warm-up time corresponding to the characteristics of class control instructions.

[0056] S102, Define the sampling strategy parameter set. It is defined as a vector containing multiple hardware configuration parameters:

[0057] ;

[0058] in, This indicates the sampling frequency of the analog-to-digital converter when implementing this strategy; This indicates the gain value of the programmable gain amplifier in the analog front-end circuit, used to adapt to the dynamic range of the signal under different operating conditions; This indicates the quantization bit width of the analog-to-digital converter, used to balance data precision and transmission bandwidth. For example, in the strategy corresponding to finishing instructions, It is set to a high frequency to capture minute vibration characteristics, while in the strategy corresponding to the standby command, Set to low frequency or zero to reduce power consumption and data redundancy.

[0059] S103, calibrate mechanical hysteresis time. (Regarding mechanical hysteresis time...) This parameter is used to quantify the time difference between receiving a logical stop command and the complete cessation of physical and mechanical movement or the decay of vibration energy to the level of ambient noise. The calibration method for this parameter is as follows: During the equipment commissioning phase, the control equipment executes the... The instruction corresponding to the control instruction characteristic records the time when the calibration instruction logic is completed. Simultaneously, the amplitude signal output by the sensor is continuously monitored. When the amplitude signal is below the noise threshold and the duration reaches the determination time, this moment is recorded as the physical stability moment. The noise threshold is determined by multiplying the root mean square value of the ambient background noise when the device is completely stationary by a coefficient of 3 to 5 to filter out environmental interference. The judgment duration is set to be no less than twice the period of the device's lowest natural frequency to prevent misjudgment due to transient fluctuations. Mechanical hysteresis time. The calculation is as follows:

[0060] ;

[0061] in, Indicates the first Mechanical hysteresis time corresponding to the characteristics of class control commands; Indicates the moment when the body is physically stable; This indicates the time when the calibration command logic is completed.

[0062] S104, determine the hardware warm-up time. (Regarding the hardware warm-up time...) It is used to quantify the switching of data acquisition hardware from a low-power sleep state or a low-precision state to a sampling strategy parameter set. The setup time required for the high-precision operating state. This time includes the settling time of the internal reference voltage source of the analog-to-digital converter, the clock locking time of the phase-locked loop circuit, and the charging time of the analog filter capacitors. To ensure the reliability of the engineering implementation, the actual hardware warm-up time is also considered. Based on the theoretical establishment time And increase the preheating safety redundancy factor. Sure:

[0063] ;

[0064] in, Indicates the first Hardware warm-up time corresponding to the characteristics of class control instructions; Indicates the theoretical setup time of the data acquisition hardware; This represents the preheating safety redundancy factor, with a value ranging from 0.05 to 0.1. This parameter ensures that in the first... The moment the instruction corresponding to the control instruction characteristic officially begins execution, the data acquisition hardware has reached the nominal measurement accuracy, avoiding the initial data drift error caused by initialization.

[0065] In step S200, hardware warm-up control based on instruction prefetching is performed. The core principle of this process is to utilize the logic lead characteristic of the digital control system to compensate for the response lag characteristic of the analog physical system. Since high-precision analog-to-digital converters and analog front-end circuits need to overcome physical setup time when switching from sleep or low-performance mode to high-performance mode, by pre-analyzing future instruction sequences, the system can accurately calculate the latest time when the hardware must be activated, thereby minimizing the duration of high-power states while ensuring data acquisition accuracy. This step specifically includes the following sub-steps:

[0066] S201, Obtain the queue of instructions to be executed. The edge computing gateway reads the instruction buffer inside the controller in real time through the fieldbus interface using a circular memory mapping or periodic polling mechanism to obtain the queue of instructions to be executed. The queue of instructions to be executed contains several instructions to be executed in order of execution. For each instruction to be executed in the queue, the gateway retrieves its corresponding hardware warm-up time and sampling strategy parameter set according to the mapping set constructed in step S100.

[0067] S202, Estimate the expected execution time of the instruction. The gateway estimates the expected start time of the instruction to be executed based on the current feed rate, spindle speed, and path length of the instruction to be executed. To improve the robustness of the estimation under actual operating conditions, a real-time feed rate factor is introduced into the estimation process. Make corrections. Read from the controller's real-time status register to reflect real-time operator intervention in equipment speed. Revised estimated start time of execution. The calculation logic is as follows:

[0068] ;

[0069] in, Indicates the first The expected start time for the execution of the pending instructions; Indicates the current system time; This represents the summation index, with values ​​ranging from 1 to... Integers; Indicates the number of elements in the queue. The physical path length corresponding to each instruction; Indicates the first The theoretical feed rate set by the instruction; This indicates the real-time feed rate factor.

[0070] S203, determine the preheating trigger condition. The gateway calculates the number of steps in real time. The time difference between the pending instruction and its execution. A hardware warm-up interrupt signal is generated when the system simultaneously meets both the time window condition and the performance improvement condition. The time window condition is expressed as:

[0071] ;

[0072] The performance improvement requirements are expressed as follows:

[0073] ;

[0074] in, Indicates the first The expected start time for the execution of the pending instructions; Indicates the current system time; Indicates the first Hardware warm-up time for each instruction to be executed; Indicates the first The sampling frequency specified in the sampling strategy parameter set corresponding to each instruction to be executed; This indicates the sampling frequency at which the gateway hardware is actually operating at the current moment.

[0075] The above-mentioned decision logic ensures that the warm-up operation is triggered only when a future instruction is about to be executed, the hardware sampling performance required by the instruction is higher than the current hardware state, and the time difference between the current moment and the execution of the instruction has entered the physical setup time window required by the hardware. This avoids the ineffective power consumption caused by premature warm-up and the signal distortion caused by late warm-up.

[0076] S204 performs hardware warm-up and data stabilization. Once the hardware warm-up interrupt signal is triggered, the gateway immediately controls the underlying analog-to-digital converter and analog front-end circuitry to enter a ready state. This state switching action specifically includes adjusting the crystal oscillator's multiplication factor to match the target sampling frequency, adjusting the bias current of the analog front-end operational amplifier to meet the bandwidth requirements at the target gain, and activating the output switch of the high-precision reference voltage source. During this warm-up phase, although the analog-to-digital converter has already begun data conversion to stabilize the internal capacitor charge and phase-locked loop state, the gateway's data processing unit does not write this data to the storage medium but discards it directly until the system reaches its ready state. Alternatively, it may receive a switching signal from the controller. This mechanism eliminates transient distortion in the header of valid data segments caused by hardware performance switching lag.

[0077] In step S300, a full-speed circular buffer and inertia retention strategy are executed. The core principle of this step is to construct a low-level physical data channel independent of upper-level logic judgments, using a full-time-domain coverage mechanism to solve the problem of missing header data in traditional trigger-based acquisition. Regardless of whether a control command has been triggered or what operating condition is currently in place, the low-level acquisition unit always operates continuously at the highest base frequency allowed by the hardware or the currently set strategy frequency, mapping the continuous state of the physical world to a discrete sequence in memory, thereby ensuring that the original physical state of the device over a past period can be obtained without loss at any time. This step specifically includes the following sub-steps:

[0078] S301, the gateway allocates a contiguous physical memory space in random access memory as a circular buffer. To ensure this buffer can cover the mechanical hysteresis backtracking requirements under harsh system operating conditions, the length of the circular buffer is... The length of the circular buffer is defined as the product of the system's maximum mechanical hysteresis time and the hardware's highest sampling capability. The calculation formula is as follows:

[0079] ;

[0080] in, This indicates the length of the circular buffer, expressed in the number of data points. This represents the maximum value among all mechanical hysteresis times within the mapping set; This indicates the highest sampling frequency supported by the data acquisition hardware; This represents the buffer safety redundancy factor, with a value ranging from 0.2 to 0.5. This indicates a round-up operation. Buffer safety redundancy factor. The allocation of physical memory in bytes is determined by the operating system's maximum interrupt response latency and the system clock's maximum drift rate. Its physical significance lies in reserving sufficient buffer space to absorb read lag caused by scheduling jitter in a non-real-time operating system, preventing data overflow and overwriting before it is retrieved by upper-layer applications. The product of the maximum quantization bit width of the analog-to-digital converter is used to determine this.

[0081] S302, the data acquisition module writes the discrete digital signal output from the analog-to-digital converter into a circular buffer in real time. The system maintains a current write pointer position. This indicates the memory address offset where the current data is written, and also maintains a time anchor register that is updated synchronously with the write pointer. Whenever a new sampled data point arrives, the system performs a write operation and updates the write pointer. The current write pointer position... The update logic follows the modulo operation rules:

[0082] ;

[0083] in, Indicates the current position of the write pointer; Indicates the position of the write pointer at the previous moment; This indicates the length of the circular buffer. Simultaneously, the system writes the absolute system time of the current sampling moment to the time anchor register. This is determined by the current write pointer position. The strict binding with the time anchor register establishes a bijective relationship between the buffer space index and the time dimension, providing a time reference for subsequent data backtracking. The write process is executed atomically, ensuring no bus contention or data tearing occurs when the upper-level processor reads the pointer position. Through this mechanism, when the write pointer reaches the end of the buffer, it automatically jumps back to the beginning address of the buffer, automatically overwriting the oldest data.

[0084] S303, implement inertial data retention. This strategy means that after a change or cessation of logical instructions, the physical data stream does not immediately stop or change its recording strategy, but continues to run in the current hardware state until the entire mechanical hysteresis time window is covered. The write logic always unconditionally stores all conversion results into the buffer. This strategy is based on the energy decay characteristics of the physical system, that is, the cessation of mechanical motion lags behind the cessation of electrical instructions. Through continuous recording, it is ensured that the decay process of physical vibration of the device during the transition from motion to rest, or from high speed to low speed, is completely recorded in the circular buffer, providing a complete data foundation for the backtracking stitching in the subsequent step S400.

[0085] See attached document Figure 2 In step S400, data fragmentation and backtracking splicing based on relative time sequence are performed. This step utilizes the full-time-domain circular buffer constructed in step S300, combined with the mechanical hysteresis time calibrated in step S100, to segment the continuous unstructured physical data stream into structured data segments that strictly correspond to control commands. This process employs an asynchronous backtracking mechanism, meaning it does not rely on the real-time response at the moment the trigger signal arrives to intercept data. Instead, it utilizes the historical memory characteristics of the circular buffer, calculating the physical state of a specific time period from historical data already written to memory through timestamp indexing. This mechanism eliminates data time-domain alignment errors caused by communication interruption response delays and operating system task scheduling delays. This step specifically includes the following sub-steps:

[0086] S401, Determine the physical effective time window. When the controller completes the execution of an instruction or the edge computing gateway detects a change in the instruction's state, the gateway immediately obtains the start time of the instruction's logical-level record. End of recording The gateway determines the command based on its corresponding command index number. From the mapping set Retrieving mechanical hysteresis time To fully capture the physical process including the residual mechanical response, the system calculates the effective physical start time. With physical effective termination time The calculation formula is as follows:

[0087] ;

[0088] ;

[0089] in, Indicates the effective start time of the physical event; Indicates the effective termination time of the physical event; Indicates the time when the instruction logic begins execution; Indicates the time when the instruction logic execution is completed; Indicates the first The mechanical hysteresis time corresponding to the characteristics of the control command. Here, the physical effective termination time is extended by one mechanical hysteresis time. The aim is to cover the physical attenuation vibration data of the device due to inertia after the logical command stops, so as to ensure the physical integrity of the data sample.

[0090] S402, calculate the buffer mapping index. The gateway reads the write pointer position maintained in real time in step S302. With time anchor register value Based on the principle of relative timing, the physical time window is mapped to a memory address index in a circular buffer. To ensure the accuracy of the mapping calculation, this step is performed immediately after instruction execution, at which point the sampling frequency is maintained at [a certain value]. And no changes have occurred. First, calculate the number of sampling points for the time deviation between the current time and the physical effective start time. Number of sampling points relative to the time deviation from the physical effective termination time :

[0091] ;

[0092] ;

[0093] Then, the start read pointer in the circular buffer is calculated. With the terminating read pointer :

[0094] ;

[0095] ;

[0096] in, This represents the number of sampling points with respect to the time deviation relative to the physical effective start time. This represents the number of sampling points representing the time deviation relative to the physical effective termination time. This indicates the value of the time anchor register; Indicates the effective start time of the physical event; Indicates the effective termination time of the physical event; Indicates the sampling frequency; Indicates the starting read pointer; This indicates that the read pointer has been terminated; Indicates the current position of the write pointer; Indicates the length of the circular buffer; To ensure that the minuend is any positive integer; This indicates a floor operation. The above calculation, by tracing back the time difference between the current moment and the target moment, pinpoints the physical location of historical data in memory.

[0097] S403 performs backtracking concatenation and linearization output. Due to the contiguous nature of the circular buffer, physically continuous time segments may experience address breaks in memory, meaning they may wrap back from the end of the buffer to the beginning. The gateway reads the data based on the starting pointer. With the terminating read pointer Based on the relative positions of the elements, perform memory copy and join operations. If This indicates that no data rollback occurred, and the gateway directly reads the pointer from the beginning. Initially, the continuous read length is... The data block. If This indicates that data rollback has occurred, and the gateway performed two read operations: the first read starts from the beginning of the pointer. The data segment up to the end of the buffer; the second read from the beginning of the buffer to the end of the buffer. The first data segment is then concatenated with the second data segment to form a linearly continuous one-dimensional data vector in the time dimension. Ultimately, the gateway will convert the one-dimensional data vector... With instruction characteristics Physical effective start time and sampling frequency The data is packaged to generate a structured dataset containing the complete physical response process, which is then stored in a non-volatile database for subsequent analysis. Through this step, the system achieves slicing of an infinite time stream with limited storage resources.

[0098] See attached document Figure 3 In step S500, the operation of constructing a dual-headed anchoring data packet is performed. The core principle of this step is to construct a self-describing data container to solve the problem of heterogeneous control logic and sensor sampling in industrial data acquisition, which makes it difficult to maintain long-term correlation. By introducing a dual-headed anchoring mechanism, the system binds the control intent and physical response at the source of data generation, thereby generating structured samples that can be used for supervised learning without subsequent manual annotation. This step specifically includes the following sub-steps:

[0099] S501, The gateway generates a logical field anchor header describing the logical attributes of the data packet based on the current instruction context. This header information is used to explicitly state the logical truth value of the data. Logical Field Anchor Header The data structure is defined as follows:

[0100] ;

[0101] in, A unique type identifier representing a control instruction, corresponding to the instruction index number. , used to indicate the prediction target of subsequent classification models; It represents the set of target control parameters, specifically a multi-dimensional feature vector containing velocity, position coordinates, or torque setpoints, used to quantify the strength of the control intent; Indicates the time when the instruction logic begins execution; Indicates the time when the instruction logic execution is completed; This indicates the environment status code. Through the logical field anchor header, data packets are anchored within the business logic flow of the control system.

[0102] S502, the gateway generates a physical domain anchor header describing the physical attributes of the data packet based on the actual configuration of the data acquisition hardware and the slicing parameters in step S400. This header information is used to clarify the physical source of the data, providing not only the necessary parameters for signal reconstruction but also recording the spatiotemporal range of the physical tracing. Physical Domain Anchor Header The data structure is defined as follows:

[0103] ;

[0104] in, This indicates the sampling frequency, which is used to subsequently reconstruct the time-domain waveform from the discrete points. It indicates the effective start time of the physical waveform and serves as the zero-point reference for the physical waveform. Represents a one-dimensional data vector The total number of data points included, which is equal to the product of the physical effective time window length and the sampling frequency; This represents the gain setting value, used to restore quantized values ​​to standard physical dimensions; Indicates the physical channel identifier of the sensor.

[0105] S503 generates integrity check codes and encapsulates data. To ensure the binding relationship between logical information and physical data during transmission and storage, and to prevent tag and data mismatch due to transmission errors or storage errors, the system anchors the logical field header. Physical domain anchor head and one-dimensional data vectors Perform joint hash calculation to generate a unique data packet integrity check code. The calculation formula is as follows:

[0106] ;

[0107] in, Indicates a data packet integrity check code; Represents a hash function; Represents a one-dimensional data vector; This indicates a data concatenation operation. The checksum is used to detect whether logical tags or physical data within the data packet have been modified. Finally, the gateway assembles the above parts into the final dual-headed anchored data packet. :

[0108] ;

[0109] The double-headed anchored data packet It is transmitted over the network in the form of a binary stream to a host computer or cloud database for persistent storage.

[0110] In step S600, slice uploading and cache management are performed. This step resolves the conflict between limited storage resources at the edge and fluctuating network bandwidth, ensuring data persistence in weak or offline environments and achieving data synchronization after network recovery. The system adopts a producer-consumer model, decoupling the data generation and transmission processes, and introduces an adaptive eviction mechanism based on storage watermarks. This step specifically includes the following sub-steps:

[0111] S601 pushes the generated double-headed anchored data packet into the send queue. The gateway maintains a first-in-first-out queue in its local non-volatile storage space. Each time a new dual-headed anchored data packet is generated in step S500... At that time, the system detects the first-in, first-out queue. The current write status. If the queue is not locked, the system will store the double-headed anchored packet. The data is appended to the tail of the queue, and the queue tail pointer is updated. This process is implemented in the local file system by appending to a log, ensuring that data packets already in the queue are not lost in the event of a power outage.

[0112] S602 implements an asynchronous transmission and acknowledgment mechanism. The gateway starts an independent sending thread and continuously monitors the first-in-first-out queue. The status and network connection quality. When a network connection is detected to be available and the queue is not empty, the sending thread reads the earliest double-headed anchored packet from the head of the queue. The data packet is then sent to the cloud server via an encrypted transmission channel. The system employs an application-layer handshake confirmation mechanism to ensure transmission reliability; that is, the data packet is only sent after receiving a verification code from the cloud server. Only after receiving the confirmation receipt will the gateway enter the first-in-first-out queue. The system marks the data packet as transmitted and performs a physical deletion operation.

[0113] S603 implements a cache management strategy based on storage watermarks. This strategy incorporates hysteresis control principles, using intervald high and low thresholds to prevent frequent erase-write oscillations in critical states, thereby extending the lifespan of the storage media and reducing I / O load. To prevent local storage space overflow due to prolonged network interruptions, the system periodically calculates the local storage space occupancy rate. The occupancy rate calculation formula is as follows:

[0114] ;

[0115] in, Indicates storage space utilization; Indicates the current queue The total number of data packets remaining in the middle; Indicates the first The number of bytes occupied by each data packet; This indicates the maximum storage capacity, which is set to 70% to 80% of the total capacity of the disk partition. The system has a preset high-water mark threshold. The value ranges from 0.85 to 0.95, and there is a low water level threshold. The value ranges from 0.50 to 0.70. When the calculated storage space utilization rate... Exceeding the high water level threshold When this happens, the system triggers a cache eviction policy. The eviction policy proceeds chronologically, starting from the head of the queue, forcibly discarding the earliest generated untransmitted data packets until storage space is fully utilized. Falling back to the low water level threshold The following is the amount of storage space that needs to be freed. The calculation is as follows:

[0116] ;

[0117] in, Indicates the amount of storage space that needs to be freed; Indicates storage space utilization; Indicates the low water level threshold; This indicates the maximum storage capacity. This is achieved by maintaining a high watermark threshold. With low water level threshold The system uses a buffer zone to ensure that each cleanup operation releases sufficient write headroom, avoiding frequent write and delete operations. This strategy ensures that, under limited storage conditions, the system always retains physical data that is most recent to the current system time and has high diagnostic value.

[0118] Specific application examples:

[0119] To better understand the technical solution of this invention, the following detailed description is provided in conjunction with specific application scenarios and accompanying drawings. This specific application embodiment is built on a tool condition monitoring system of a CNC machine tool. The edge computing gateway is responsible for collecting spindle vibration data.

[0120] During the system initialization phase, the edge computing gateway needs to execute step S301 to determine the physical size of the circular buffer. The parameters are set as follows: based on the maximum mechanical hysteresis time calibrated in step S100. The maximum sampling frequency supported by the hardware is 0.5s. 20000Hz, buffer safety redundancy factor The value is 0.2. The edge computing gateway substitutes the values ​​into the formula in step S301 to calculate the length of the circular buffer. :

[0121] ;

[0122] The numerical calculation process is as follows:

[0123] ;

[0124] The calculation results show that the edge computing gateway opens a circular buffer with a length of 12,000 data points in memory, which ensures that the system can backtrack a sufficiently long amount of historical data to meet the operation requirements of the full-speed circular buffer in step S300.

[0125] The edge computing gateway reads the instruction queue in real time according to step S200 and determines the ADC activation time. Parameter settings are as follows: current system time. The execution time is 10.0s, and the first instruction in the queue is yet to be executed (i.e., Physical path length The theoretical feed rate is set to 200mm in the first instruction. 100mm / s, real-time feed rate factor The value is 0.8. The edge computing gateway substitutes the values ​​into the formula in step S202 to calculate the expected start time of the first instruction to be executed. (Summation index at this point) Take only 1):

[0126] ;

[0127] The numerical calculation process is as follows:

[0128] ;

[0129] The calculation shows that the first instruction to be executed is expected to begin execution at 12.5s. This is based on the hardware warm-up time defined in step S100. ( The timeout is 0.1s, and the edge computing gateway will trigger a hardware warm-up interrupt at 12.4s.

[0130] See attached document Figure 4 In the graph, the horizontal axis represents time, and the vertical axis represents the amplitude of the sensor signal. The command start time marked in the graph corresponds to... (i.e., time 0 on the time axis). The dashed line in the diagram represents the traditional method, which lacks the pre-reading mechanism in step S200. It only powers on and starts data acquisition at time 0, resulting in significant voltage drift in the first 0.05 seconds. The signal amplitude slowly climbs from around 0.5V to a stable operating point of 1.5V, which is a transient distortion in the header of the valid data segment in step S204. The solid line in the diagram represents the method of this invention, which performs hardware preheating. The physical setup process is completed before time 0, so at the start of the command, the sensor signal amplitude is already in a stable sine wave state with an amplitude of around 3.5V. This result verifies that the preheating control strategy effectively ensures the validity of the data in the initial stage of the action.

[0131] See attached document Figure 5 After the instruction execution is completed, the edge computing gateway performs data fragmentation and backtracking stitching in step S400. In the figure, the horizontal axis represents time, and the vertical axis represents the sensor signal amplitude. The shaded area on the left side of the figure represents the instruction execution interval. to During this period, the machine operates in a steady state, and the dashed line in the diagram coincides with the solid line. At time 2.0s, the instruction logic execution is complete. In the diagram, the dashed line represents the traditional method, which immediately stops data acquisition and returns the value to zero. The solid line represents the physical effective termination time calculated according to step S401 in the method of this invention. The backtracking mechanism extends the acquisition window to cover the mechanical hysteresis time period marked in the figure (i.e., The damped oscillation process, in which the amplitude gradually decays from 1.5V to 0V, was fully recorded. This result verifies that the ring buffer and backtracking strategy ensures the completeness of the physical domain anchoring data in step S502.

[0132] When local storage space is insufficient, the edge computing gateway executes the cache management strategy in step S603. The parameters are set as follows: maximum storage capacity. 100GB, high water level threshold The threshold value is 0.90, representing a low water level. The current storage space utilization rate is 0.60. The value is 0.92. The edge computing gateway is substituted into the formula in step S603 to calculate the amount of space that needs to be released. :

[0133] ;

[0134] The numerical calculation process is as follows:

[0135] ;

[0136] The edge computing gateway will remove the oldest packets starting from the head of the queue until at least 32GB of space is freed up, reducing the occupancy rate back to 60%.

[0137] See attached document Figure 6 In the graph, the horizontal axis represents runtime, and the vertical axis represents storage space utilization. The data shows that storage utilization exhibits a sawtooth wave shape over time. As can be seen from the graph, the storage utilization curve rises linearly, reaching the 90% high-water mark (marked on the graph). When the line is dashed, the edge computing gateway immediately triggers a cleanup operation, causing the occupancy rate to drop vertically to the 60% low-water threshold marked in the diagram at the same time. The line initially dipped, then began to rise slowly again. This result verifies that the hysteresis control logic based on high and low water level thresholds avoids frequent erase / write oscillations near the storage critical point, which aligns with the design objective of step S603.

Claims

1. An edge-computing-based Internet of Things gateway data processing method, characterized in that, Includes the following steps: A correlation model was established that defines the mapping relationship between device control commands, hardware acquisition strategies, and physical hysteresis characteristics. The underlying data acquisition behavior is controlled based on the aforementioned association model, and a circular buffer with historical backtracking capability is maintained in the circular physical memory space. When a change in control command is detected, time-aligned physical data fragments are generated from the circular buffer with historical backtracking capability based on the association model. The logical domain anchor header describing the control logic context, the physical domain anchor header describing the hardware acquisition configuration, and the time-aligned physical data segment are bound and encapsulated to generate a dual-headed anchored data packet. Based on a preset data scheduling strategy, a data output operation is performed on the dual-headed anchored data packet. 2.The edge computing based Internet of Things gateway data processing method of claim 1, wherein, The association model is an instruction strategy mapping matrix, the hardware acquisition strategy includes a sampling strategy parameter set containing the sampling frequency, the gain value of the analog front-end circuit and the quantization bit width of the analog-to-digital converter, and the physical hysteresis characteristics include mechanical hysteresis time and hardware warm-up time. Controlling the underlying data acquisition behavior based on the aforementioned correlation model includes: pre-parsing the instruction sequence in the controller buffer, determining the hardware start-up timing, generating a hardware preheating control signal, and starting acquisition in response to the hardware preheating control signal; The generation of time-aligned physical data segments includes: extracting transitional state data from the circular buffer with historical backtracking capability based on the mechanical hysteresis time, and splicing it in the time domain with the currently acquired steady-state data; The data output operation includes: writing to local storage space or sending via a network transmission channel; The data output operation includes: performing hierarchical storage or transmission scheduling on the dual-headed anchored data packets according to the current network status and local storage space occupancy rate.

3. The IoT gateway data processing method based on edge computing according to claim 2, characterized in that, The determination of when to enable the hardware includes: Based on the current system time, the ratio of the physical path length of all instructions from the current instruction in the instruction sequence to the target instruction to be executed in the instruction sequence to the theoretical feed rate is accumulated, and the theoretical feed rate is corrected using the real-time feed rate factor to calculate the expected execution time of the target instruction to be executed; The triggering condition for generating the hardware preheating control signal is: the time difference between the expected execution time and the current system time is greater than zero and less than or equal to the hardware preheating time corresponding to the target instruction to be executed, and the sampling frequency required by the target instruction to be executed is higher than the sampling frequency currently running on the edge computing gateway hardware.

4. The IoT gateway data processing method based on edge computing according to claim 2, characterized in that, The physical length of the circular buffer with historical backtracking capability is determined based on the product of the maximum value of all mechanical hysteresis times in the instruction policy mapping matrix, the highest sampling frequency supported by the hardware, and the buffer safety redundancy coefficient. The maintenance of the circular buffer with historical backtracking capability includes: maintaining a write pointer indicating the current write memory address offset and a time anchor register. Whenever a new sampled data point arrives, the write pointer is updated and the current system time is written to the time anchor register. When the write pointer reaches the end of the circular buffer with historical backtracking capability, it automatically jumps back to the beginning address of the circular buffer with historical backtracking capability.

5. The IoT gateway data processing method based on edge computing according to claim 4, characterized in that, The extraction of transition state data includes: A physical effective time window is determined, wherein the start time of the physical effective time window is the time when the instruction logic begins execution, and the end time of the physical effective time window is the time when the instruction logic completes execution plus the mechanical hysteresis time.

6. The IoT gateway data processing method based on edge computing according to claim 5, characterized in that, The generation of time-aligned physical data fragments also includes: Based on the time difference between the value of the time anchor register and the start and end times of the physical effective time window, the start and end read pointers in the circular buffer with historical backtracking capability are calculated in conjunction with the sampling frequency in the sampling strategy parameter set containing the sampling frequency. If the starting read pointer is less than the ending read pointer, then the data block between the starting read pointer and the ending read pointer is read directly; If the starting read pointer is greater than the ending read pointer, then two read operations are performed to read the data segment from the starting read pointer to the end of the circular buffer with historical backtracking capability and the data segment from the beginning address of the circular buffer with historical backtracking capability to the ending read pointer, and then the two data segments are spliced ​​together to form the time-aligned physical data segment.

7. The IoT gateway data processing method based on edge computing according to claim 2, characterized in that, The logical domain anchor header contains a unique type identifier for the control instruction, a set of target control parameters, the start time of instruction logic execution, the completion time of instruction logic execution, and an environment status code. The physical domain anchor head includes the sampling frequency, physical valid start time, total number of data points, gain setting value, and sensor physical channel identifier.

8. The IoT gateway data processing method based on edge computing according to claim 7, characterized in that, The generation of the dual-headed anchored data packet also includes: A joint hash calculation is performed on the logical domain anchor header, the physical domain anchor header, and the time-aligned physical data segment to generate a data packet integrity check code, and the data packet integrity check code is encapsulated into the dual-headed anchored data packet.

9. The IoT gateway data processing method based on edge computing according to claim 2, characterized in that, The step of performing hierarchical storage or transmission scheduling on the dual-headed anchored data packets based on the current network status and local storage space occupancy includes: The dual-headed anchored data packet is placed into the sending queue, and the local storage space occupancy rate is calculated periodically; A high occupancy rate threshold and a low occupancy rate threshold are set. When the local storage space occupancy rate exceeds the high occupancy rate threshold, the earliest generated but untransmitted double-headed anchored data packets are discarded in chronological order, starting from the head of the sending queue, until the local storage space occupancy rate falls back below the low occupancy rate threshold.

10. The IoT gateway data processing method based on edge computing according to claim 2, characterized in that, The method for calibrating the mechanical hysteresis time is as follows: The control device executes calibration instructions and records the time when the calibration instruction logic is completed. It continuously monitors the sensor amplitude signal. When the sensor amplitude signal is lower than the noise threshold determined based on the ambient background noise and the duration reaches the judgment duration, it records the physical stability time. The difference between the physical stability time and the time when the calibration instruction logic is completed is determined as the mechanical hysteresis time.

Images