Solar cells and their fabrication methods, tandem cells and photovoltaic modules

Abstract

This application relates to the photovoltaic field, providing a solar cell and its fabrication method, a tandem solar cell, and a photovoltaic module. The solar cell includes a substrate; a tunneling dielectric layer located on the surface of the substrate; a doped conductive layer located on the surface of the tunneling dielectric layer; a fluorinated silicon oxide layer located on the surface of the doped conductive layer, the fluorinated silicon oxide layer having a mesoporous structure; a passivation layer located on the surface of the fluorinated silicon oxide layer; and an electrode electrically connected to the doped conductive layer. The solar cell, its fabrication method, the tandem solar cell, and the photovoltaic module provided by this application can at least improve the PID (Potential Influence of Processing) problem.

Description

Technical Field

[0001] This application relates to the photovoltaic field, and in particular to a solar cell and its preparation method, a tandem cell, and a photovoltaic module. Background Technology

[0002] Currently, with the gradual depletion of fossil fuels, solar cells are becoming increasingly widely used as a new energy alternative. A solar cell is a device that converts sunlight into electrical energy. Solar cells utilize the photovoltaic principle to generate charge carriers, which are then extracted using electrodes, thus facilitating the efficient utilization of electrical energy.

[0003] Current solar cells mainly include IBC cells (Interdigitated Back Contact), TOPCON (Tunnel Oxide Passivated Contact) cells, PERC cells (Passivated emitter and rear cell), and heterojunction cells. Different film layer configurations and functional limitations are used to reduce optical losses and decrease photogenerated carrier recombination on and within the silicon substrate, thereby improving the photoelectric conversion efficiency of solar cells.

[0004] However, current solar cells have some problems that result in poor photoelectric conversion efficiency, such as PID (Potential Induced Degradation) or the integrity of the passivation layer. Summary of the Invention

[0005] This application provides a solar cell and its preparation method, a tandem cell and a photovoltaic module, which at least helps to solve the PID problem of solar cells.

[0006] This application provides a solar cell comprising: a substrate; a tunneling dielectric layer located on the surface of the substrate; a doped conductive layer located on the surface of the tunneling dielectric layer; a fluorinated silicon oxide layer located on the surface of the doped conductive layer, the fluorinated silicon oxide layer having a mesoporous structure; a passivation layer located on the surface of the fluorinated silicon oxide layer; and an electrode electrically connected to the doped conductive layer.

[0007] Optionally, the porosity of the fluorine-doped silicon oxide layer is greater than or equal to 30%.

[0008] Optionally, the thickness of the fluorine-doped silicon oxide layer is 0.8 nm to 2 nm.

[0009] Optionally, the fluorine content in the fluorine-doped silicon oxide layer ranges from 3 at.% to 12 at.%.

[0010] Optionally, the substrate adjacent to the substrate surface has an amorphous silicon layer, and the tunneling dielectric layer is located on the amorphous silicon layer.

[0011] Optionally, the surface of the amorphous silicon layer has a textured structure, the size of which is on the submicron scale.

[0012] Optionally, the thickness of the amorphous silicon layer ranges from 5 nm to 8 nm.

[0013] A second aspect of this application also provides a method for fabricating a solar cell, comprising: providing a substrate; forming a tunneling dielectric layer located on the surface of the substrate; forming an intrinsic semiconductor film located on the surface of the tunneling dielectric layer; doping the intrinsic semiconductor film and forming a doped conductive layer and a doped silicon glass layer located on the surface of the doped conductive layer; performing a dry plasma etching process on the doped silicon glass layer to convert the doped silicon glass layer into a fluorine-doped silicon oxide layer, the fluorine-doped silicon oxide layer having a mesoporous structure; forming a passivation layer located on the fluorine-doped silicon oxide layer; and forming an electrode electrically connected to the doped conductive layer.

[0014] Optionally, the process parameters of the dry plasma etching process include: using an NF3 / N2O mixed gas with a volume ratio of (2%~5%):(95%~98%), a reaction pressure of 0.5 Torr~1.0 Torr, a radio frequency power of 300W~500W, and a reaction time of 20s~40s.

[0015] Optionally, the doped silicon glass layer includes: a first doped silicon glass layer formed on a first surface of the substrate and a second doped silicon glass layer formed on the doped conductive layer; after forming the doped silicon glass layer, the process further includes: performing the dry plasma etching process on the first doped silicon glass layer; forming a mask layer located on the surface of the second doped silicon glass layer; removing the first doped silicon glass layer; or forming a mask layer located on the surface of the second doped silicon glass layer; removing the first doped silicon glass layer; and performing the dry plasma etching process on the remaining second doped silicon glass layer.

[0016] Optionally, after forming the fluorine-doped silicon oxide layer, the method further includes: using an ion implantation process to modify the substrate, thereby converting a portion of the substrate into an amorphous silicon layer.

[0017] A third aspect of this application also provides a tandem solar cell, comprising: a bottom cell, which is a solar cell as described in any of the above examples or a solar cell prepared by any of the above examples; and a top cell located on one side of the bottom cell.

[0018] A fourth aspect of this application also provides a photovoltaic module, comprising: a battery string, formed by connecting a plurality of solar cells as described in any one of the above examples, solar cells prepared by any one of the above examples, or stacked cells as described in the above examples; an encapsulating film for covering the surface of the battery string; and a cover plate for covering the surface of the encapsulating film facing away from the battery string.

[0019] The technical solution provided in this application has at least the following advantages: This application provides a solar cell in which a fluorine-doped silicon oxide layer is positioned on a doped conductive layer. The strong polarity and high bond energy of the Si-OF bonds in SiOF form a dense "ion sieve" structure, significantly improving the Na+ content derived from the glass. + K + The migration barrier; F in the fluorine-doped silicon oxide layer - With Na migrating to the interface + K + The combination of NaF and KF forms stable NaF and KF, preventing further disruption of the passivation state on the battery surface. Secondly, the mesoporous structure of the fluorine-doped silicon oxide layer provides tunneling channels for charge carriers between the electrode and the doped conductive layer, but the pore size is much smaller than that of NaF. + K + The critical size for cation migration is determined by the Si-OF network on the pore walls, which forms a continuous barrier interface to prevent metal ions and Na from entering the electrode. + K + Cations undergo "penetrating migration". Attached Figure Description

[0020] One or more embodiments are illustrated by way of example with reference to the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the drawings in the accompanying drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this application or in the conventional art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This is a schematic diagram of a solar cell provided in an embodiment of this application; Figure 2 for Figure 1 A magnified view of a section at point A in the middle; Figure 3 for Figure 1 A top view of a fluorine-doped silicon oxide layer; Figure 4 This is a schematic diagram of another structure of a solar cell provided in an embodiment of this application; Figure 5 for Figure 4 A magnified view of a section at point B in the middle; Figure 6 This is a schematic diagram of a solar cell provided in another embodiment of this application; Figure 7 A schematic diagram of a solar cell provided in another embodiment of this application; Figure 8 This is a schematic diagram of the structure of a solar cell corresponding to a substrate in a method for fabricating a solar cell according to an embodiment of this application; Figure 9 This is a schematic diagram of the structure of a solar cell corresponding to the emitter in a method for fabricating a solar cell according to an embodiment of this application; Figure 10 This is a schematic diagram of the structure of a solar cell corresponding to the formation of a tunneling dielectric layer in a method for fabricating a solar cell according to an embodiment of this application; Figure 11 This is a schematic diagram of the structure of a solar cell corresponding to the formation of a doped conductive layer in a method for fabricating a solar cell according to an embodiment of this application; Figure 12 This is a schematic diagram of the structure of a solar cell corresponding to the formation of a fluorine-doped silicon oxide layer in a method for fabricating a solar cell according to an embodiment of this application. Figure 13 This is a schematic diagram of the first structure of a solar cell corresponding to the formation of a mask layer in a method for fabricating a solar cell according to an embodiment of this application; Figure 14 This is a schematic diagram of a second structure of a solar cell corresponding to the formation of a mask layer in a method for fabricating a solar cell according to an embodiment of this application; Figure 15 This is a schematic diagram of the structure of a solar cell corresponding to the removal of the first doped silicon glass layer in a method for fabricating a solar cell according to an embodiment of this application. Figure 16 This is a schematic diagram of the structure of a solar cell corresponding to the formation of an amorphous silicon layer in a method for fabricating a solar cell according to an embodiment of this application; Figure 17 This application provides a schematic diagram of the structure of a stacked battery in another embodiment. Figure 18 This is a schematic diagram of a photovoltaic module provided in another embodiment of this application.

[0022] Explanation of reference numerals in the attached figures: 10. Substrate; 101. First surface; 102. Second surface; 103. Doped silicon glass layer; 1031. First doped silicon glass layer; 1032. Second doped silicon glass layer; 104. Fluorine-doped silicon oxide layer; 106. Front passivation layer; 107. Passivation layer; 108. Front electrode; 109. Electrode; 110. Emitter; 111. Mask layer; 112. Amorphous silicon layer; 113. Textured structure; 120. Mesoporous structure; 131. First film layer; 132. Tunneling dielectric layer; 133. Doped conductive layer; 136. Intrinsic semiconductor film; 20. Substrate; 201. First surface; 202. Second surface; 204. Fluorine-doped silicon oxide layer; 205. Doped semiconductor layer; 206. Front passivation layer; 207. Passivation layer; 208. Front electrode; 209. Electrode; 210. Emitter; 30. Substrate; 301. First surface; 302. Second surface; 304. Fluorine-doped silicon oxide layer; 307. Passivation layer; 309. Electrode; 310. Emitter; 332. Tunneling dielectric layer; 333. Doped conductive layer; 334. Back passivation layer; 335. Back electrode; 150. Bottom cell; 180. Top cell; 181. Interface layer; 182. First transport layer; 183. Perovskite substrate; 184. Second transport layer; 185. First transparent conductive layer; 186. First grid line; 01. Solar cell; 21. Encapsulating film; 22. Cover plate; 28. Connecting components. Detailed Implementation

[0023] As can be seen from the background technology, the PID problem in current solar cells is quite serious, which further affects the photoelectric conversion efficiency of solar cells.

[0024] This application provides a solar cell by forming a fluorine-doped silicon oxide layer on the surface of the solar cell. Based on the performance of the fluorine-doped silicon oxide layer, it can block the migration of ions in the glass layer or combine with them to form a more stable NaF or KF, preventing them from further damaging the passivation state of the passivation layer.

[0025] In the description of the embodiments of this application, technical terms such as "first" and "second" are used only to distinguish different objects and should not be construed as indicating or implying relative importance or implicitly specifying the number, specific order, or primary and secondary relationship of the indicated technical features. In the description of the embodiments of this application, "multiple" means two or more, unless otherwise explicitly defined.

[0026] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0027] In the description of the embodiments in this application, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent three cases: A exists, A and B exist simultaneously, and B exists. In addition, the character " / " in this document generally indicates that the related objects before and after it have an "or" relationship.

[0028] In the description of the embodiments of this application, the term "multiple" refers to two or more (including two), similarly, "multiple sets" refers to two or more (including two sets), and "multiple pieces" refers to two or more (including two pieces).

[0029] In the description of the embodiments of this application, the technical terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing the embodiments of this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the embodiments of this application.

[0030] In the description of the embodiments of this application, unless otherwise expressly specified and limited, the technical terms such as "installation," "connection," "joining," and "fixing" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. For those skilled in the art, the specific meaning of the above terms in the embodiments of this application can be understood according to the specific circumstances.

[0031] In the description of the embodiments of this application, "electrically connected to one component" means that both components are made of conductive materials, and the two components are in direct contact and connected or connected via other conductive materials. Therefore, when the photovoltaic module is generating electricity, there is current transfer between the two components. "Electrically contacting one component to another" means that the two components are not only in contact, but also, because both components are made of conductive materials, there is current transfer between the two components when the photovoltaic module is generating electricity.

[0032] In the accompanying drawings corresponding to the embodiments of this application, the thickness and / or area of ​​layers, films, panels, regions, etc., are enlarged for better understanding and ease of description. Throughout the specification, the same reference numerals denote the same elements. It should be understood that when describing a component (such as a layer, film, region, or substrate) on or on the surface of another component, the component may be "directly" located on the surface of the other component, or there may be an intermediate component between the two components. Conversely, when describing a component on the surface of another component, or a component "directly" on another component, or a component surface on which another component is formed or disposed, it indicates that there is no intermediate component between the two components. Furthermore, when describing a component as "generally" formed on another component, it means that the component is not formed on the entire surface (or front surface) of the other component, nor is it formed on a portion of the edge of the entire surface.

[0033] In the description of the embodiments of this application, when a component "includes" another component, other components are not excluded unless otherwise stated, and other components may be further included. Furthermore, when a component such as a layer, film, region, or plate is referred to as being "on / located" on another component, it can be "directly on" the other component (i.e., located on the surface of the other component with no other components between them), or another component may be present therein. Moreover, when a component such as a layer, film, region, or plate is "directly located" on another component, or when a component such as a layer, film, region, or plate is located on the surface of another component, it indicates that no other components are located therein.

[0034] The embodiments of this application will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this application to facilitate a better understanding of the application. However, the technical solutions claimed in this application can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0035] According to some embodiments of this application, one aspect of this application provides a solar cell for improving PID problems.

[0036] A solar cell includes: a substrate; a tunneling dielectric layer located on the surface of the substrate; a doped conductive layer located on the surface of the tunneling dielectric layer; a fluorinated silicon oxide layer located on the surface of the doped conductive layer, the fluorinated silicon oxide layer having a mesoporous structure; a passivation layer located on the surface of the fluorinated silicon oxide layer; and an electrode electrically connected to the doped conductive layer.

[0037] This application provides a solar cell in which a fluorine-doped silicon oxide layer is located on a doped conductive layer. The strong polarity and high bond energy of the Si-OF bonds in SiOF form a dense "ion sieve" structure, significantly improving the performance of Na+. + K + The migration barrier; F in the fluorine-doped silicon oxide layer - With Na migrating to the interface + K + The combination of NaF and KF forms stable NaF and KF, preventing further disruption of the passivation state on the battery surface. Secondly, the mesoporous structure of the fluorine-doped silicon oxide layer provides tunneling channels for charge carriers between the electrode and the doped conductive layer, but the pore size is much smaller than that of NaF. + K + The critical size for cation migration is determined by the Si-OF network on the pore walls, which forms a continuous barrier interface to prevent metal ions and Na from entering the electrode. + K + Cations undergo "penetrating migration".

[0038] The solar cells provided in the above embodiments will be described in detail below with reference to the accompanying drawings.

[0039] Figure 1 This is a schematic diagram of a solar cell provided in an embodiment of this application; Figure 2 for Figure 1 A magnified view of a section at point A in the middle; Figure 3 for Figure 1 A top view of a fluorine-doped silicon oxide layer.

[0040] refer to Figure 1 The solar cell includes a substrate 10 having a first surface 101 and a second surface 102 facing each other.

[0041] The substrate 10 is used to receive light and generate photogenerated carriers. In some embodiments, the substrate 10 may be a semiconductor substrate.

[0042] In some embodiments, the material of the substrate 10 may be an elemental semiconductor material. Specifically, the elemental semiconductor material is composed of a single element, such as silicon or germanium. The elemental semiconductor material may be monocrystalline, polycrystalline, amorphous, or microcrystalline (a state simultaneously possessing both monocrystalline and amorphous states is called microcrystalline). For example, silicon may be at least one of monocrystalline silicon, polycrystalline silicon, amorphous silicon, and microcrystalline silicon.

[0043] In some embodiments, the substrate 10 may also be a compound semiconductor material. Common compound semiconductor materials include, but are not limited to, silicon germanide, silicon carbide, gallium arsenide, indium gallium arsenide, perovskite, cadmium telluride, copper indium selenide, etc.

[0044] The substrate 10 can also be a sapphire substrate, a silicon substrate on an insulator, or a germanium substrate on an insulator.

[0045] The substrate 10 can be an N-type semiconductor substrate or a P-type semiconductor substrate. The N-type semiconductor substrate is doped with an N-type dopant element, which can be at least one of group V elements such as phosphorus (P), bismuth (Bi), antimony (Sb), or arsenic (As). The P-type semiconductor substrate is doped with a P-type dopant element, which can be at least one of group III elements such as boron (B), aluminum (Al), gallium (Ga), or indium (In).

[0046] In some embodiments, the cells used in single-glass photovoltaic modules are considered single-sided cells, in which case the first side 101 can serve as the light-receiving surface for receiving sunlight, and the second side 102 serves as the backlighting surface. In some embodiments, the cells used in double-glass or bifacial modules are considered bifacial cells, in which case both the first side 101 and the second side 102 can serve as light-receiving surfaces and can both be used to receive sunlight. It is understood that the backlighting surface referred to in the embodiments of this application can also receive sunlight, but the degree of sunlight reception is weaker than that of the light-receiving surface, and therefore it is defined as a backlighting surface.

[0047] It should be noted that, Figure 1 And the following Figure 4 , Figure 6 as well as Figure 7 The side facing the top is the illuminated side, and the side facing the bottom is the shaded side. Taking the first side as the illuminated side and the second side as the shaded side as an example.

[0048] The first surface 101 of the substrate 10 has a textured surface (not shown). The textured surface can improve the internal reflectivity of incident light, thereby improving the photoelectric conversion efficiency. The textured surface may include multiple protrusions, which may be arranged adjacently or spaced apart, or stacked or partially overlapped. This application does not limit the number, arrangement, or shape of the protrusions.

[0049] In other embodiments, the second surface 102 is a polished surface. A polished surface refers to a surface that has been smooth or has low roughness by removing the textured surface, rough layer, damaged layer, or oxide layer of the material surface through methods such as mechanical grinding, chemical polishing (e.g., acid / alkali solution etching), or chemical-mechanical polishing (CMP). Polished surfaces can optimize optical and electrical properties by improving surface smoothness.

[0050] The solar cell includes an emitter 110 located within the substrate 10 adjacent to the first surface 101.

[0051] Emitter 110 is used to generate a built-in electric field and selectively collect charge carriers. The built-in electric field drives the separation of photogenerated electron-hole pairs, with electrons moving towards the n-region (emitter 110 or base region) and holes moving towards the p-region, forming a photocurrent.

[0052] Emitter 110 is doped with a first dopant element, the doping type of which differs from that of the dopant element in the substrate 10. In one example, the substrate 10 is doped with an N-type dopant element, and the emitter 110 is doped with a P-type dopant element. In another example, the substrate 10 is doped with a P-type dopant element, and the emitter 110 is doped with an N-type dopant element.

[0053] It should be noted that the emitter 110 is part of the substrate 10. An original substrate 10 is subjected to doping or diffusion treatment to convert a portion of the substrate 10 into the emitter 110. The first surface 101 of the substrate 10 can be the surface of the emitter 110. In other embodiments, the emitter 110 can be a separate film layer, with the undoped or undiffused substrate 10 serving as the substrate, and the emitter 110 located on the substrate.

[0054] The solar cell includes: a tunneling dielectric layer 132 located on the second surface 102 of a substrate 10; and a doped conductive layer 133 located on the surface of the tunneling dielectric layer 132. The doped conductive layer 133 and the tunneling dielectric layer 132 together form a passivated contact structure.

[0055] The tunneling dielectric layer 132 and the doped conductive layer 133 form a passivation contact structure. Due to the special band structure of the passivation contact structure, the doped conductive layer 133 and the substrate 10 are in electrical contact, causing the energy band of the substrate 10 to bend downward, which reduces the electron transport barrier. Therefore, the ultrathin tunneling dielectric layer 132 can allow majority carriers to tunnel through while blocking minority carriers from passing through, thereby separating electrons and holes, reducing recombination, and lowering the recombination rate.

[0056] In some embodiments, the thickness of the tunneling dielectric layer 132 is 0.5 nm to 10 nm. The thickness range of the tunneling dielectric layer 132 is 0.5 nm to 1.3 nm, 1.3 nm to 4.6 nm, 4.6 nm to 6.1 nm, or 6.1 nm to 10 nm. The thickness of the tunneling dielectric layer 132 is 0.5 nm, 2 nm, 2.5 nm, 4 nm, 6 nm, or 10 nm. When the thickness of the tunneling dielectric layer 132 is within any of the above ranges, the thickness of the tunneling dielectric layer 132 is relatively thin, allowing majority carriers to easily tunnel through the tunneling dielectric layer for quantum tunneling, while minority carriers have difficulty passing through the tunneling dielectric layer 132, thus achieving selective carrier transport.

[0057] In some embodiments, the material of the tunneling dielectric layer 132 includes at least one of silicon oxide, amorphous silicon, microcrystalline silicon, nanocrystalline silicon, or silicon carbide.

[0058] The doped conductive layer 133 includes at least one of a doped amorphous silicon layer, a doped polycrystalline silicon layer, a doped microcrystalline silicon layer, a doped silicon carbide layer, or a doped crystalline silicon layer.

[0059] In some embodiments, the dopant elements in the doped conductive layer 133 have the same conductivity type as the dopant elements in the substrate 10. For example, the substrate 10 has N-type dopant elements, and the doped conductive layer 133 has N-type dopant elements; or the substrate 10 has P-type dopant elements, and the doped conductive layer 133 has P-type dopant elements. In this way, the doped conductive layer 133 and the substrate 10 have dopant elements of the same conductivity type. By setting the concentration of dopant elements in the doped conductive layer 133 to be greater than the concentration of dopant elements in the substrate 10, a high-low junction is formed between the substrate 10 and the doped conductive layer 133. Under the action of the built-in electric field constructed by the high-low junction, charge carriers can quickly migrate from the substrate 10 to the doped conductive layer 133 and be collected by the electrode 109.

[0060] The solar cell includes a fluorine-doped silicon oxide layer 104, which is located on the surface of the doped conductive layer 133.

[0061] The strong polarity and high bond energy of the Si-OF bonds in the fluorine-doped silicon oxide layer 104 can form a dense "ion sieve" structure, significantly improving the performance of Na+. + K + The migration barrier; F in the fluorine-doped silicon oxide layer 104- Respectively with Na that migrated to the interface + K + The combination forms stable NaF and KF, preventing them from further disrupting the passivation state of the battery surface. Secondly, the mesoporous structure 120 of the fluorine-doped silicon oxide layer 104 can provide tunneling channels for charge carriers between the electrode 109 and the doped conductive layer 133, but the pore size is much smaller than that of NaF. + K + The critical size for cation migration is determined by the Si-OF network on the pore walls, which forms a continuous barrier interface to prevent metal ions and Na from entering the electrode. + K + Cations undergo "penetrating migration".

[0062] In some embodiments, the fluorine-doped silicon oxide layer 104 has a mesoporous structure 120, which refers to pores with a pore size ranging from 5 nm to 20 nm. When the pore walls are SiOF, the pores are in a gas phase / vacuum (the size of the material of the subsequently formed film layer is larger than the size of this mesoporous structure 120, therefore the mesoporous structure 120 is in a gas phase / vacuum). It should be noted that when forming the fluorine-doped silicon oxide layer 104, during dry plasma etching of the original film layer, the plasma bombards the original film layer, thereby forming multiple pores. Then, fluorine ions pass through these pores and the internal microstructure of the original film layer to form the fluorine-doped silicon oxide layer 104. The fluorine content at the pore walls is higher than the fluorine content in other areas.

[0063] It should be noted that the mesoporous structure 120 is not a through-hole. That is, the mesoporous structure 120 is a blind hole / sponge-like hole with an open surface and a closed / semi-connected interior, and is not a through hole that penetrates the entire fluorine-doped silicon oxide layer 104. Figure 2 as well as Figure 3 The mesoporous structures 120 in the image have inconsistent lateral dimensions and are dispersed, and their depths along the vertical direction are also inconsistent, but they do not penetrate the thickness of the fluorine-doped silicon oxide layer 104 (in extreme cases, a small portion of the mesoporous structures 120 penetrate the thickness of the fluorine-doped silicon oxide layer 104). That is, the embodiments of this application do not limit the size, depth, shape, or distribution of the mesoporous structures 120. Figure 2 and Figure 3 The dimensions, depth, shape, and distribution of the mesoporous structure 120 in the figure are for illustrative purposes only.

[0064] Among them, the pore size testing methods for mesoporous structure 120 can be gas adsorption method, mercury porosimetry, bubble pressure method, scanning electron microscopy method, etc.; and can be tested using fully automatic specific surface area and porosity analyzer or scanning electron microscope.

[0065] In some embodiments, the thickness of the fluorine-doped silicon oxide layer 104 is 0.8 nm to 2 nm. The thickness range of the fluorine-doped silicon oxide layer 104 is 0.8 nm to 1.0 nm, 1.0 nm to 1.3 nm, 1.3 nm to 1.6 nm, or 1.6 nm to 2 nm. The thickness of the fluorine-doped silicon oxide layer 104 is 0.8 nm, 0.9 nm, 1 nm, 1.1 nm, 1.2 nm, 1.3 nm, 1.4 nm, 1.5 nm, 1.6 nm, 1.7 nm, 1.8 nm, 1.9 nm, or 2 nm. When the thickness of the fluorine-doped silicon oxide layer 104 falls within any of the above ranges, it is moderate, serving both as a passivation layer to passivate the doped semiconductor layer and the substrate, and allowing some charge carriers to tunnel through the mesoporous structure 120 into the electrode 109.

[0066] In some embodiments, the porosity of the fluorine-doped silicon oxide layer 104 is greater than or equal to 30%. The porosity of the fluorine-doped silicon oxide layer 104 is less than or equal to 50%. For example, the porosity of the fluorine-doped silicon oxide layer 104 can be any value within or between any two values ​​of 30%, 31%, 32%, 33%, 34%, 35%, 36%, 37%, 38%, 39%, 40%, 41%, 42%, 43%, 44%, 45%, 46%, 47%, 48%, 49%, or 50%. When the porosity of the fluorine-doped silicon oxide layer 104 is within the above range, it can have a large number of mesoporous structures 120, allowing majority carriers to tunnel through, thereby improving the photoelectric conversion efficiency of the solar cell. Furthermore, the fluorine-doped silicon oxide layer 104 has good density, forming a barrier layer to block the migration of sodium or potassium ions, exhibiting good anti-PID performance and passivation properties.

[0067] It should also be noted that, compared to the entire solar cell / photovoltaic module, the specific surface area of ​​the mesoporous structures 120 in the fluorinated silicon oxide layer 104 is very small and the number of mesoporous structures 120 is very large. Therefore, it is impossible to exhaustively measure all mesoporous structures 120 in the entire fluorinated silicon oxide layer 104. Instead, several sampling points are selected at different locations in the fluorinated silicon oxide layer 104, and the average value of the ratio of the total specific surface area of ​​the mesoporous structures 120 at these sampling points to the area of ​​the sampling point is calculated to obtain the porosity of the fluorinated silicon oxide layer 104. That is, the average porosity of the fluorinated silicon oxide layer 104 can be measured by sampling. For example, the average value of the ratio of the total specific surface area of ​​the mesoporous structures 120 at 5 sampling points in the fluorinated silicon oxide layer 104 to the area of ​​the sampling point can be used as the average porosity of the fluorinated silicon oxide layer 104.

[0068] In addition, the specific surface area of ​​the mesoporous structure 120 of the fluorine-doped silicon oxide layer 104 can be measured using fully automated specific surface area and porosity analyzers or scanning electron microscopes.

[0069] In some embodiments, the fluorine content in the fluorine-doped silicon oxide layer 104 ranges from 3 at.% to 12 at.%. The fluorine content in the fluorine-doped silicon oxide layer 104 can be any value within or between any two values ​​of 3 at.%, 4 at.%, 5 at.%, 6 at.%, 7 at.%, 8 at.%, 9 at.%, 10 at.%, 11 at.%, or 12 at.%. Within this range, the fluorine content in the fluorine-doped silicon oxide layer 104 allows for a sufficient number of fluorine atoms to form Si-F bonds with silicon atoms, thereby improving hydrophobicity and ion barrier properties, and resisting Na+. + K + It has high migration ability, thus exhibiting good anti-PID performance. In addition, the number of fluorine atoms is also appropriate, without disrupting the original silica network, and the density between silica atoms can provide good passivation and anti-PID properties.

[0070] It should also be noted that the fluorine content in the fluorine-doped silicon oxide layer 104 can be measured by sampling. For example, the average fluorine content in the fluorine-doped silicon oxide layer 104 at five sampling points can be measured and calculated as the fluorine content in the fluorine-doped silicon oxide layer 104.

[0071] Correspondingly, elemental analysis methods such as atomic absorption spectrometry, atomic fluorescence spectrometry, inductively coupled plasma atomic emission spectrometry, inductively coupled plasma mass spectrometry, X-ray fluorescence spectrometry, and nuclear magnetic resonance can be used to determine the fluorine content in the fluorine-doped silicon oxide layer 104. Testing equipment may include an X-ray photoelectron spectrometer (XPS). XPS (Extreme Photoelectron Spectrometer) and Energy Dispersive X-ray Spectrometer ray spectrometer (EDS / EDX), scanning electron microscope, or time-of-flight secondary ion mass spectrometer (Time-of-flight secondary ion mass spectrometer). of Flight Secondary IonMass Spectrometry, TOF SIMS).

[0072] The solar cell includes: a front passivation layer 106, which is located on the surface of the emitter 110 and on the first surface 101 of the substrate 10.

[0073] In some embodiments, the front passivation layer 106 can be a single-layer structure or a stacked structure, and the material of the front passivation layer 106 can be one or more of the following materials: silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, titanium oxide, hafnium oxide, or aluminum oxide.

[0074] The solar cell includes a passivation layer 107 located on the surface of a fluorine-doped silicon oxide layer 104. The passivation layer 107 covers the surface of a mesoporous structure 120. Because the pores in the mesoporous structure 120 are small, the passivation layer 107 does not fill the mesoporous structure 120, thus the passivation layer 107 simply covers the surface of the mesoporous structure 120.

[0075] In some embodiments, the passivation layer 107 can be a single-layer structure or a stacked structure, and the material of the passivation layer 107 can be one or more of the following materials: silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, titanium oxide, hafnium oxide, or aluminum oxide.

[0076] The solar cell includes: a front electrode 108, which is located on a front passivation layer 106 and is electrically connected to an emitter 110.

[0077] In some embodiments, the front electrode 108 may be sintered from a burn-through metal paste or from a LECO (Laser-enhanced contact optimization) paste, wherein the metal paste and the LECO paste may include at least one of silver, aluminum, copper, tin, gold, lead or nickel.

[0078] The solar cell includes an electrode 109, which is located on a passivation layer 107 and is electrically connected to a doped conductive layer 133.

[0079] In some embodiments, the electrode 109 may be sintered from a burn-through metal paste or from a LECO paste, wherein the metal paste and the LECO paste may include at least one of silver, aluminum, copper, tin, gold, lead or nickel.

[0080] It should be noted that, Figure 1 and Figure 4 The front electrode 108, as shown, penetrates the front passivation layer 106 and makes an electrical contact with the emitter 110, and the electrode 109 penetrates the passivation layer 107 and makes an electrical contact with the doped conductive layer 133, and so on. Figure 6 The front electrode 208, as shown, penetrates the front passivation layer 206 and makes an electrical contact with the emitter 210, and the electrode 209 penetrates the passivation layer 207 and makes an electrical contact with the doped semiconductor layer 205. Figure 7The electrode 309, which penetrates the passivation layer 307 and makes an electrical contact with the emitter 310, and the back electrode 335, which penetrates the back passivation layer 334 and makes an electrical contact with the doped conductive layer 133, shown are merely examples. In actual solar cells, the connection between the front electrode 108 and the emitter 110, the front electrode 208 and the emitter 210, and the electrode 109 and the emitter 310 can be a contact connection or an indirect connection through conductive particles; the connection between the electrode 109 and the doped conductive layer 133, the electrode 209 and the doped semiconductor layer 205, and the back electrode 335 and the doped conductive layer 333 can be a contact connection or an indirect connection through conductive particles. The conductive particles can be silver crystals, silver aggregates, silver particles, or other conductive metal particles.

[0081] The solar cell provided in this application embodiment has a fluorine-doped silicon oxide layer 104 located on the surface of the doped conductive layer 133. The strong polarity and high bond energy of the Si-OF bonds in the fluorine-doped silicon oxide layer 104 can form a dense "ion sieve" structure, significantly improving the Na+ conductivity. + K + The migration barrier; F in the fluorine-doped silicon oxide layer 104 - With Na migrating to the interface + K + The combination forms stable NaF and KF, preventing them from further disrupting the passivation state of the battery surface. Secondly, the mesoporous structure 120 of the fluorine-doped silicon oxide layer 104 can provide tunneling channels for charge carriers between the electrode 109 and the doped conductive layer 133, but the pore size is much smaller than that of NaF. + K + The critical size for cation migration is determined by the Si-OF network on the pore walls, which forms a continuous barrier interface to prevent metal ions and Na from entering the electrode. + K + Cations undergo "penetrating migration".

[0082] Figure 4 This is a schematic diagram of another structure of a solar cell provided in an embodiment of this application; Figure 5 for Figure 4 A magnified view of a section at point B in the middle. Figure 4 Solar cells in Figure 1 Based on this, an additional amorphous silicon layer is added. The amorphous silicon layer is located within the substrate adjacent to the second surface of the substrate 10. The following will combine... Figure 4 and Figure 5 for Figure 1 The different parts of a solar cell and their corresponding films will be explained in detail; other details will not be elaborated upon.

[0083] It should be noted that, Figure 4The amorphous silicon layer is needed as the interface between the amorphous silicon layer and the silicon layer, but this does not mean that there is a clear film layer interface between the silicon layer and the amorphous silicon layer in the actual substrate. The amorphous silicon layer is actually a portion of the silicon material in the substrate that has been transformed into amorphous silicon material.

[0084] refer to Figure 4 An amorphous silicon layer 112 is located within the substrate 10 adjacent to its surface, and a tunneling dielectric layer 132 is situated on the amorphous silicon layer 112. A second surface 102 adjacent to the substrate 10 also has an amorphous silicon layer 112. This forms an amorphous silicon / silicon oxide composite tunneling passivation structure, enabling efficient and selective tunneling of majority carriers while maintaining high layer resistivity through synergistic control of the tunneling barrier and thickness. The amorphous silicon layer 112 and the tunneling dielectric layer 132 form a bilayer ion barrier system, significantly hindering the migration of mobile ions such as sodium and potassium ions under high temperature, high humidity, and high pressure conditions, thus greatly improving the battery's anti-PID performance.

[0085] In some embodiments, the thickness of the amorphous silicon layer 112 ranges from 5 nm to 8 nm. The thickness of the amorphous silicon layer 112 is any value within the range of any two values ​​of 5 nm, 5.2 nm, 5.5 nm, 5.8 nm, 6 nm, 6.2 nm, 6.5 nm, 6.7 nm, 7 nm, 7.3 nm, 7.5 nm, 7.8 nm, or 8 nm, or any value within that range. A thickness of the amorphous silicon layer 112 within the above range can provide a good passivation effect to improve passivation performance without causing excessive resistance loss to the electrical performance of the substrate 10, thereby improving the photoelectric conversion efficiency of the solar cell.

[0086] In some embodiments, reference Figure 5 The amorphous silicon layer 112 has a textured surface 113; the cone angle α of the textured surface 113 is 70°~85°. Thus, the textured surface 113 can improve the internal reflectivity of the second surface 102, thereby reducing optical losses and improving the photoelectric conversion efficiency of the solar cell.

[0087] It should be noted that the textured structure formed by the amorphous silicon layer 112 is a surface structure formed by partial etching of the surface of the substrate 10. The length L of the overall surface formed by the surface structure is at the submicron level, and the size of the textured structure is simply referred to as a submicron textured structure. The fluorine-doped silicon oxide layer 104 exhibits two structures, one of which is... Figure 4 The first example shows a doped silicon oxide layer located on a submicron textured structure, forming a vacuum-like region between them. The second example shows a submicron textured structure where the corresponding fluorinated silicon oxide layer 104 is removed, meaning there is no complete fluorinated silicon oxide layer 104 on the submicron textured structure. Here, "submicron" refers to a textured structure with a size of 200 nm to 600 nm. The size can be the average side length of the pyramid base constituting the textured structure or the distance between two opposite corners of the pyramid base.

[0088] This application provides a solar cell in which a fluorine-doped silicon oxide layer 104 is disposed on a doped conductive layer 133. The fluorine-doped silicon oxide layer 104 can block the migration of sodium and potassium ions, thereby resisting the PID effect. The fluorine-doped silicon oxide layer 104 has a mesoporous structure 120, which can provide tunneling channels for charge carriers between the electrode 109 and the doped conductive layer 133, but the pore size is much smaller than that of sodium ions. + K + The critical size for cation migration is determined by the Si-OF network on the pore walls, which forms a continuous barrier interface to prevent metal ions and Na from entering the electrode. + K + The amorphous silicon layer 112 and the tunneling dielectric layer 132 can form a composite tunneling passivation structure. By synergistically controlling the tunneling barrier and thickness, efficient and selective tunneling of majority carriers is achieved while maintaining high layer resistivity. The amorphous silicon layer 112 and the tunneling dielectric layer 132 form a bilayer ion barrier system, which significantly hinders the migration of mobile ions such as sodium and potassium ions under high temperature, high humidity, and high pressure conditions, greatly improving the battery's anti-PID performance.

[0089] Figure 6 This is a schematic diagram of a solar cell provided in another embodiment of this application. Figure 6 The provided solar cells and Figure 1 The difference is that, Figure 1 The fluorine-doped silicon oxide layer is located on the doped conductive layer. Figure 6 The provided fluorine-doped silicon oxide layer is located on the substrate and has the same or corresponding features as in the above embodiments, which will not be described in detail here.

[0090] refer to Figure 6 The solar cell includes: a substrate 20; a fluorine-doped silicon oxide layer 204 located on the substrate 20, the fluorine-doped silicon oxide layer 204 having a mesoporous structure; a doped semiconductor layer 205 located on the surface of the fluorine-doped silicon oxide layer 204; a passivation layer 207 located on the surface of the doped semiconductor layer 205; and an electrode 209 electrically connected to the doped semiconductor layer 205.

[0091] refer to Figure 6 The solar cell includes a substrate 20 having a first surface 201 and a second surface 202. The first surface 201 of the substrate 20 has a textured surface. The solar cell includes an emitter 210 located within the substrate 20 adjacent to the first surface 201.

[0092] The solar cell includes a fluorine-doped silicon oxide layer 204, which is located on the surface of the substrate 20.

[0093] The fluorine-doped silicon oxide layer 204 has a mesoporous structure. The SiOF layer is locally thinner at this mesoporous structure, forming a low-barrier microregion. Charge carriers preferentially tunnel through this mesoporous structure, thus enabling the charge carriers to conduct current through this mesoporous structure. The equivalent barrier when charge carriers pass through the fluorine-doped silicon oxide layer 204 is low, further increasing the tunneling probability.

[0094] Furthermore, the small size of the mesoporous structure does not affect the insulation and passivation properties of the fluorine-doped silicon oxide layer 204. In other words, the fluorine-doped silicon oxide layer 204 has weak lateral transport capability and does not form leakage channels. The size of the mesoporous structure is smaller than that of metal ions, thus it can block sodium and potassium ions and has good resistance to PID effects.

[0095] In some embodiments, the thickness of the fluorine-doped silicon oxide layer 204 is 0.8 nm to 2 nm. The thickness range of the fluorine-doped silicon oxide layer 204 is 0.8 nm to 1.0 nm, 1.0 nm to 1.3 nm, 1.3 nm to 1.6 nm, or 1.6 nm to 2 nm. The thickness of the fluorine-doped silicon oxide layer 204 is 0.8 nm, 0.9 nm, 1 nm, 1.1 nm, 1.2 nm, 1.3 nm, 1.4 nm, 1.5 nm, 1.6 nm, 1.7 nm, 1.8 nm, 1.9 nm, or 2 nm. When the thickness of the fluorine-doped silicon oxide layer 204 falls within any of the above ranges, the thickness is moderate, serving both as a passivation layer to passivate the doped semiconductor layer and the substrate, and allowing some charge carriers to tunnel into the electrode 109 through the mesoporous structure.

[0096] It should be noted that in some embodiments, the thickness of the fluorine-doped silicon oxide layer 204 is not limited to 0.8 nm to 2 nm, and the fluorine-doped silicon oxide layer 204 can still have tunneling capabilities, with majority carriers tunneling through thinning at the mesoporous structure. In other embodiments, when the thickness of the fluorine-doped silicon oxide layer 204 is between 0.8 nm and 2 nm, majority carrier tunneling includes direct tunneling and tunneling through thinning at the mesoporous structure.

[0097] The solar cell includes a doped semiconductor layer 205, which is located on the surface of a fluorine-doped silicon oxide layer 204 and between the fluorine-doped silicon oxide layer 204 and a passivation layer 207. The doped semiconductor layer 205 and the fluorine-doped silicon oxide layer 204 together form a passivation contact structure.

[0098] The doped semiconductor layer 205 provides a field passivation effect. Specifically, an electrostatic field pointing inwards from the substrate 20 is formed on the surface of the substrate 20, causing minority carriers to escape from the interface, thereby reducing the minority carrier concentration and decreasing the carrier recombination rate at the interface of the substrate 20. This increases the open-circuit voltage, short-circuit current, and fill factor of the solar cell, thereby improving the photoelectric conversion efficiency of the solar cell.

[0099] In some embodiments, the doped semiconductor layer 205 includes at least one of a doped amorphous silicon layer, a doped polycrystalline silicon layer, a doped microcrystalline silicon layer, a doped silicon carbide layer, or a doped crystalline silicon layer.

[0100] In some embodiments, the dopant elements in the doped semiconductor layer 205 have the same conductivity type as the dopant elements in the substrate 20. For example, the substrate 20 has N-type dopant elements, and the doped semiconductor layer 205 has N-type dopant elements; or the substrate 20 has P-type dopant elements, and the doped semiconductor layer 205 has P-type dopant elements. In this way, the doped semiconductor layer 205 and the substrate 20 have dopant elements of the same conductivity type. By setting the concentration of dopant elements in the doped semiconductor layer 205 to be greater than the concentration of dopant elements in the substrate 10, a high-low junction is formed between the substrate 20 and the doped semiconductor layer 205. Under the action of the built-in electric field constructed by the high-low junction, charge carriers can quickly migrate from the substrate 20 to the doped semiconductor layer 205 and be collected by the electrode 209.

[0101] In some embodiments, the fluorine content in the fluorine-doped silicon oxide layer 204 ranges from 3 at.% to 12 at.%. The effect obtained can be referred to the effect of the fluorine content range in the fluorine-doped silicon oxide layer 104 in the above embodiments, and will not be repeated here.

[0102] The solar cell includes a passivation layer 207, which is located on the surface of the doped semiconductor layer 205.

[0103] The solar cell includes a front passivation layer 206, which is located on the surface of the emitter 210.

[0104] The solar cell includes an electrode 209, which is located on a passivation layer 207 and is electrically connected to a doped semiconductor layer 205.

[0105] The solar cell includes a front electrode 208, which is located on a front passivation layer 206 and is electrically connected to an emitter 210.

[0106] This application provides a solar cell in which a fluorine-doped silicon oxide layer 204 is disposed on a substrate 20. The strong polarity and high bond energy of the Si-OF bonds in SiOF form a dense "ion sieve" structure, significantly improving the performance of Na+. +K + The migration barrier; F in the fluorine-doped silicon oxide layer 204 - With Na migrating to the interface + K + The combination of NaF and KF (low solubility, high chemical stability) prevents further damage to the passivation state of the battery surface. Secondly, while the mesoporous structure of the fluorine-doped silicon oxide layer 204 provides tunneling channels for charge carriers, the pore size is much smaller than the critical size for cation migration, and the Si-OF network on the pore walls forms a continuous barrier interface, preventing "through-migration" of ions. The mesoporous structure within the fluorine-doped silicon oxide layer 204, with locally thinner SiOF layers at these mesoporous locations, creates low-barrier microregions. Charge carriers preferentially tunnel through these mesoporous structures, allowing more carriers to conduct current. Furthermore, with SiOF as the pore walls, the pores are in a gas phase / vacuum, resulting in a lower equivalent barrier for charge carriers traversing the fluorine-doped silicon oxide layer 204, further increasing the tunneling probability.

[0107] Figure 7 This is a schematic diagram of a solar cell provided in another embodiment of this application. Figure 7 The provided solar cells and Figure 1 The difference is that, Figure 1 The fluorine-doped silicon oxide layer is located on the doped conductive layer. Figure 6 The provided fluorine-doped silicon oxide layer is located on the emitter and has the same or corresponding features as in the above embodiments, which will not be elaborated here.

[0108] refer to Figure 7 The solar cell includes a substrate 30 having a first surface 301 and a second surface 302. The first surface 301 of the substrate 30 has a textured surface. The solar cell includes an emitter 310 located within the substrate 30 adjacent to the first surface 301.

[0109] The solar cell includes a fluorine-doped silicon oxide layer 304, which is located on the first surface 301 of the substrate 30. The fluorine-doped silicon oxide layer 304 is located on the surface of the emitter 310. The strong polarity and high bond energy of the Si-OF bonds in the fluorine-doped silicon oxide layer 304 can form a dense "ion sieve" structure, significantly improving the performance of Na+ solar cells. + K + The migration barrier; F in the fluorine-doped silicon oxide layer 304 - With Na migrating to the interface + K + The combination forms stable NaF and KF, preventing further damage to the passivation state of the battery surface. At this point, the fluorine-doped silicon oxide layer 304 acts as a barrier against Na... + K + A barrier layer is used to improve resistance to PID effects.

[0110] In some embodiments, the thickness of the fluorine-doped silicon oxide layer 304 is 0.8 nm to 5 nm. The thickness range of the fluorine-doped silicon oxide layer 304 is 0.8 nm to 2.0 nm, 2.0 nm to 3.0 nm, 3.0 nm to 4.0 nm, or 4.0 nm to 5 nm. The thickness of the fluorine-doped silicon oxide layer 304 is 0.8 nm, 1 nm, 1.5 nm, 1.8 nm, 2.3 nm, 2.7 nm, 3.1 nm, 3.5 nm, 3.7 nm, 4.3 nm, 4.8 nm, or 5 nm. The thickness of the fluorine-doped silicon oxide layer 304 ensures that it has better passivation performance and resistance to PID effects.

[0111] In some embodiments, the fluorine content in the fluorine-doped silicon oxide layer 304 ranges from 3 at.% to 12 at.%. The resulting effect can be referred to the effect of the fluorine content range in the fluorine-doped silicon oxide layer 304 in the above embodiments, and will not be repeated here.

[0112] The solar cell includes: a tunneling dielectric layer 332 located on the second surface 302 of a substrate 30; and a doped conductive layer 333 located on the surface of the tunneling dielectric layer 332. The doped conductive layer 333 and the tunneling dielectric layer 332 together form a passivated contact structure.

[0113] The tunneling dielectric layer 332 and the doped conductive layer 333 form a passivation contact structure. Due to the special band structure of the passivation contact structure, the doped conductive layer 333 and the substrate 30 are in electrical contact, causing the energy band of the substrate 30 to bend downward, which reduces the electron transport barrier. Therefore, the ultrathin tunneling dielectric layer 332 can allow majority carriers to tunnel through while blocking minority carriers from passing through, thereby separating electrons and holes, reducing recombination, and lowering the recombination rate.

[0114] In some embodiments, the thickness of the tunneling dielectric layer 332 is 0.5 nm to 30 nm. The thickness range of the tunneling dielectric layer 332 is 0.5 nm to 1.3 nm, 1.3 nm to 4.6 nm, 4.6 nm to 6.1 nm, or 6.1 nm to 30 nm. The thickness of the tunneling dielectric layer 332 is 0.5 nm, 2 nm, 2.5 nm, 4 nm, 6 nm, or 30 nm. When the thickness of the tunneling dielectric layer 332 is within any of the above ranges, the thickness of the tunneling dielectric layer 332 is relatively thin, allowing majority carriers to easily tunnel through the tunneling dielectric layer 332, while making it difficult for minority carriers to pass through, thus achieving selective carrier transport.

[0115] In some embodiments, the material of the tunneling dielectric layer 332 includes at least one of silicon oxide, amorphous silicon, microcrystalline silicon, nanocrystalline silicon, or silicon carbide.

[0116] The doped conductive layer 333 includes at least one of amorphous silicon doped layer, polycrystalline silicon doped layer, microcrystalline silicon doped layer, silicon carbide doped layer, or crystalline silicon doped layer.

[0117] In some embodiments, the dopant elements in the doped conductive layer 333 have the same conductivity type as the dopant elements in the substrate 30. For example, the substrate 30 has N-type dopant elements, and the doped conductive layer 333 has N-type dopant elements; or the substrate 30 has P-type dopant elements, and the doped conductive layer 333 has P-type dopant elements. In this way, the doped conductive layer 333 and the substrate 30 have dopant elements of the same conductivity type. By setting the concentration of dopant elements in the doped conductive layer 333 to be greater than the concentration of dopant elements in the substrate 30, a high-low junction is formed between the substrate 30 and the doped conductive layer 333. Under the action of the built-in electric field constructed by the high-low junction, charge carriers can quickly migrate from the substrate 30 to the doped conductive layer 333 and be collected by the electrode 309.

[0118] The solar cell includes a passivation layer 307, which is located on the surface of a fluorine-doped silicon oxide layer 304.

[0119] The solar cell includes a back passivation layer 334, which is located on the surface of the doped conductive layer 333.

[0120] The solar cell includes an electrode 309, which is located on a passivation layer 307 and is electrically connected to a substrate 30 (specifically, an emitter 310).

[0121] The solar cell includes a back electrode 335, which is located on a back passivation layer 334 and is electrically connected to a doped conductive layer 333.

[0122] This application provides a solar cell in which a fluorine-doped silicon oxide layer 304 is disposed on a substrate 30. The strong polarity and high bond energy of the Si-OF bonds in SiOF form a dense "ion sieve" structure, significantly improving the performance of Na+. + K + The migration barrier; F in the fluorine-doped silicon oxide layer 304 - With Na migrating to the interface + K + The combination forms stable NaF and KF (low solubility, high chemical stability), preventing them from further damaging the passivation state of the battery surface. Secondly, although the mesoporous structure 120 of the fluorine-doped silicon oxide layer 304 provides tunneling channels for charge carriers, the pore size is much smaller than the critical size for cation migration, and the Si-OF network on the pore walls forms a continuous barrier interface, avoiding "penetrating migration" of ions.

[0123] Accordingly, another aspect of this application provides a method for preparing a solar cell, which is used to prepare the solar cell provided in the above embodiments. The same or corresponding technical features as those in the above embodiments will not be described in detail here.

[0124] refer to Figure 8 A method for preparing a solar cell includes: providing a substrate 10 having a first surface 101 and a second surface 102 opposite to each other.

[0125] The first surface 101 of the substrate 10 is texturized. Texturing includes chemical etching, for example, cleaning the substrate 10 with a mixed solution of potassium hydroxide and hydrogen peroxide. Specifically, the desired texturized structure can be formed by controlling the concentration ratio of potassium hydroxide and hydrogen peroxide solutions. In some embodiments, the texturized structure can also be formed using laser etching, mechanical methods, or plasma etching. In laser etching, the laser process parameters are controlled to obtain a texturized structure with the desired morphology. The texturized structure includes multiple pyramidal structures.

[0126] refer to Figure 9 The first surface 101 of the substrate 10 is doped to convert a portion of the substrate 10 into an emitter 110, and a first film layer 131 is formed on the surface of the emitter 110 and the second surface of the substrate. The first film layer 131 is a silicon glass layer formed by doping the emitter and contains the doping elements of the emitter.

[0127] refer to Figure 10 Remove the first film layer 131.

[0128] Continue to refer to Figure 10 A tunneling dielectric layer 132 is formed, which is located on the surface of the substrate 10. The tunneling dielectric layer 132 is located on the surface of the emitter 110 and the second surface 102 of the substrate 10.

[0129] Continue to refer to Figure 10 An intrinsic semiconductor film 136 is formed, which is located on the surface of the tunneling dielectric layer 132.

[0130] refer to Figure 11 The intrinsic semiconductor film 136 is doped to form a doped conductive layer 133 and a doped silicon glass layer 103, with the doped silicon glass layer 103 located on the surface of the doped conductive layer 133.

[0131] The doped silicon glass layer 103 includes a first doped silicon glass layer 1031 formed on the first surface 101 of the substrate 10 and a second doped silicon glass layer 1032 formed on the surface of the doped conductive layer 133.

[0132] refer to Figure 12 as well as Figure 2 A dry plasma etching process is performed on the doped silicon glass layer to transform it into a fluorine-doped silicon oxide layer 104, which has a mesoporous structure 120.

[0133] Specifically, the second doped silicon glass layer 1032 is subjected to a dry plasma etching process to transform the second doped silicon glass layer 1032 into a fluorine-doped silicon oxide layer 104.

[0134] The process parameters for dry plasma etching include: using an NF3 / N2O mixed gas with a volume ratio of (2%~5%):(95%~98%), a reaction pressure of 0.5 Torr~1.0 Torr, an RF power of 300W~500W, and a reaction time of 20s~40s.

[0135] The mechanism by which the dry plasma etching process transforms the doped silicon glass layer 103 into the fluorinated silicon oxide layer 104 is as follows: F radicals attack Si-O bonds to generate SiF4 (volatile), preferentially etching regions rich in doped elements (the doped elements formed by the emitter 110) and network defects, forming initial micropores. O radicals / NO radicals oxidize and etch the remaining Si and doped elements, while simultaneously inserting O atoms and repairing part of the network, but the etching rate > reconstruction rate, forming a mesoporous structure 120; F replaces some O to form Si-OF bonds, reducing network density and stabilizing the porous structure.

[0136] refer to Figure 1 Remove the first doped silicon glass layer 1031.

[0137] Continue to refer to Figure 1 A passivation layer 107 is formed on the surface of the doped conductive layer 133; an electrode 109 is formed and electrically connected to the doped conductive layer 133. The method also includes: forming a front passivation layer 106 on the surface of the emitter 110; forming a front electrode 108 on the front passivation layer 106; and the front passivation layer 106 being electrically connected to the emitter 110.

[0138] In other embodiments, after the formation of the fluorine-doped silicon oxide layer 104 and before the removal of the first doped silicon glass layer 1031, i.e. Figure 12 and Figure 1 Add a step to form a mask layer, refer to Figure 13 A mask layer 111 is formed, which is located on the surface of the fluorine-doped silicon oxide layer 104.

[0139] In some embodiments, the mask layer 111 is perfluorooctyltrimethoxysilane, forming an ultrathin, dense, highly selective, and highly resistant to plasma etching fluorocarbon self-assembled monolayer (SAM), achieving gentle NF3 / N2O plasma etching to create pores, precisely controlling the pore size, porosity, and pore depth of the porous SiOF, while protecting the underlying substrate 10 (or the amorphous silicon layer 112 in subsequent steps) from etching damage.

[0140] In some embodiments, the thickness of the mask layer 111 is 0.2 nm to 0.5 nm. The relatively thin mask layer 111 can be easily removed in subsequent removal steps, and the removal will not compromise the dimensional control of the 0.8 nm to 2.0 nm ultrathin fluorine-doped silicon oxide layer 104.

[0141] The first doped silicon glass layer 1031 was removed by vapor phase etching; the reaction temperature of the vapor phase etching process was -20℃ to -10℃.

[0142] The process parameters for removing the first doped silicon glass layer 1031 by vapor phase etching include using a ClF3 / He mixed gas with a volume ratio of (0.5%~1.5%):(98.5%~99.5%), a reaction pressure of 10mTorr~20mTorr, and a reaction time of 40s~60s.

[0143] Continue to refer to Figure 13 Mask layer 111 is removed by thermal decomposition at a temperature of approximately 200 degrees Celsius.

[0144] In some other embodiments, after forming the second doped silicon glass layer 1032 and before forming the fluorine-doped silicon oxide layer 104, a step of forming a mask layer is added, see reference. Figure 14 A mask layer 111 is formed, which is located on the surface of the second doped silicon glass layer 1032; Reference Figure 15 Remove the first doped silicon glass layer 1031; perform dry plasma etching on the remaining second doped silicon glass layer 1032.

[0145] In some other embodiments, Figure 12 and Figure 1 Add a step to form an amorphous silicon layer, refer to Figure 16 An ion implantation process is used to modify the substrate 10, thereby converting part of the substrate 10 into an amorphous silicon layer 112.

[0146] The ions used in the ion implantation process include boron-doped ions or argon-doped ions. The process parameters for ion implantation include: implantation energy of 5 keV to 10 keV and implantation dose of 1 × 10⁻⁶. 14 ions / cm 2 ~5×10 14ions / cm 2 .

[0147] The doped silicon glass layer includes a first doped silicon glass layer 1031 formed on a first surface 101 of the substrate 10 and a second doped silicon glass layer 1032 formed on a second surface 102; the second doped silicon glass layer 1032 is also located on an amorphous silicon layer 112, and during the removal of the second doped silicon glass layer 1032, a submicron textured structure is formed on the surface of the amorphous silicon layer 112.

[0148] In some embodiments, the above-described embodiments involve a doped silicon glass layer formed during the formation of a doped conductive layer. The doped silicon glass layer is formed on both the emitter surface and the surface of the doped conductive layer, and contains the same doping elements as the doped conductive layer. A dry plasma etching process is then performed on the doped silicon glass layer on the emitter surface to form a layer as shown in the image. Figure 7 The solar cell shown is formed by dry plasma etching of the doped silicon glass layer on the second side of the substrate, as shown. Figure 1 The solar cell shown is illustrated. In some embodiments, during the process of forming the emitter, a doped silicon glass layer is formed on the emitter surface and the second surface. The doped silicon glass layer contains the same doping elements as the emitter. A dry plasma etching process is then performed on the doped silicon glass layer on the second surface of the substrate to form a structure as shown. Figure 6 The solar cells shown can be specifically described using the preparation methods provided in the above embodiments, which will not be elaborated upon here.

[0149] Accordingly, this application also provides a tandem battery and a photovoltaic module, which include the solar cell provided in the above embodiments.

[0150] Figure 17 This is a schematic diagram of a stacked battery provided in another embodiment of this application.

[0151] refer to Figure 17 The tandem solar cell includes: a bottom cell 150, which is a solar cell prepared by any of the above embodiments or by any of the above embodiments; and a top cell 180, which is located on one side of the bottom cell.

[0152] In some embodiments, the top cell is a perovskite cell located on the bottom cell 150.

[0153] In some embodiments, the tandem solar cell has a first grid line 186 of a first polarity and a second grid line of a second polarity. The first grid line 186 is in electrical contact with the perovskite solar cell, and the second grid line is in electrical contact with the bottom solar cell 150. The second grid line serves as an electrode of the bottom solar cell.

[0154] In some embodiments, an interface layer 181 is provided between the top battery and the bottom battery.

[0155] It is worth noting that the stacked battery in this application embodiment only illustrates two layers of solar cells. Those skilled in the art can set up three layers of solar cells or more than three layers of multi-layer stacked solar cells according to actual needs.

[0156] The mainstream methods for tandem solar cells are the 2T (two-terminal series / two-terminal stacked) structure and the 4T (four-terminal series / four-terminal stacked) structure; there is also the 3T structure, which is mainly used for three-terminal tandem solar cells made by combining BC cells with perovskites, but it will produce three electrodes.

[0157] The two sub-cells of the four-terminal stacked cell are made independently, and they are only connected optically. Their circuits are independent of each other. It can be understood that the perovskite and crystalline silicon cells are just physically stacked, but in reality they still do their own thing and output independently. Therefore, the four-terminal stacked cell will have two positive electrodes and two negative electrodes.

[0158] In some embodiments, the perovskite solar cell includes: a first transport layer 182, a perovskite substrate 183, a second transport layer 184, a first transparent conductive layer 185, and an antireflection layer (not shown). The first transport layer is directly opposite the bottom cell.

[0159] In some embodiments, the first transport layer may be either an electron transport layer or a hole transport layer, and the second transport layer may be either an electron transport layer or a hole transport layer.

[0160] Figure 18 This is a schematic diagram of a photovoltaic module provided in another embodiment of this application.

[0161] It should be noted that, Figure 18 The photovoltaic module only shows 4 solar cells 01, and the solar cells 01 are electrically connected in pairs through the connecting component 28. However, in reality, the photovoltaic module can include multiple battery strings, and the battery strings can be connected in series or in parallel. A battery string includes multiple solar cells 01 connected by the connecting component 28.

[0162] refer to Figure 18 The photovoltaic module includes: a battery string, which is formed by connecting multiple solar cells 01 as described in any of the above embodiments, or solar cells 01 prepared by any of the above embodiments, or tandem cells as described in the above embodiments; an encapsulating film 21 for covering the surface of the battery string; and a cover plate 22 for covering the surface of the encapsulating film 21 facing away from the battery string.

[0163] Specifically, in some embodiments, multiple solar cells can be electrically connected to each other via a connecting member 28, which is electrically connected to the sub-busbars / main busbars on the solar cells.

[0164] In some embodiments, the encapsulating film 21 includes a first encapsulating layer and a second encapsulating layer. The first encapsulating layer covers one of the front or back sides of the solar cell, and the second encapsulating layer covers the other of the front or back sides of the solar cell. Specifically, at least one of the first or second encapsulating layer can be one or more organic encapsulating films such as polyvinyl butyral (PVB) film, ethylene-vinyl acetate copolymer (EVA) film, polyvinyl octene elastomer (POE) film, or polyethylene terephthalate (PET) film. For example, the encapsulating layer composed of multiple organic encapsulating films can be an EPE film, which is an EVA-POE-EVA three-layer composite film.

[0165] It is worth noting that the first encapsulation layer and the second encapsulation layer still have a dividing line before lamination. After lamination, the photovoltaic module will no longer have the concept of a first encapsulation layer and a second encapsulation layer. That is, the first encapsulation layer and the second encapsulation layer have formed an integral encapsulation film 21.

[0166] In some embodiments, the cover plate 22 can be a glass cover plate, a plastic cover plate, or other cover plate with light-transmitting function. Specifically, the surface of the cover plate 22 facing the encapsulating film 21 can be an uneven surface, thereby increasing the utilization rate of incident light. The cover plate 22 includes a first cover plate and a second cover plate, the first cover plate being opposite to the first encapsulation layer and the second cover plate being opposite to the second encapsulation layer; or the first cover plate being opposite to one side of the solar cell and the second cover plate being opposite to the other side of the solar cell.

[0167] Those skilled in the art will understand that the above-described embodiments are specific examples of implementing this application, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of this application. Any person skilled in the art can make their own modifications and alterations without departing from the spirit and scope of this application; therefore, the scope of protection of this application should be determined by the scope defined in the claims.

Claims

1. A solar cell, characterized by, include: Base; A tunneling medium layer, wherein the tunneling medium layer is located on the surface of the substrate; A doped conductive layer is located on the surface of the tunneling dielectric layer; A fluorine-doped silicon oxide layer is located on the surface of the doped conductive layer, and the fluorine-doped silicon oxide layer has a mesoporous structure. A passivation layer is located on the fluorine-doped silicon oxide layer; An electrode, which is electrically connected to the doped conductive layer.

2. The solar cell according to claim 1, characterized in that, The porosity of the fluorine-doped silicon oxide layer is greater than or equal to 30%.

3. The solar cell according to claim 1 or 2, characterized in that, The thickness of the fluorine-doped silicon oxide layer is 0.8 nm to 2 nm.

4. The solar cell according to claim 1, characterized in that, The fluorine content in the fluorine-doped silicon oxide layer ranges from 3 at.% to 12 at.%.

5. The solar cell according to claim 1, characterized in that, An amorphous silicon layer is present in the substrate adjacent to the substrate surface, and the tunneling dielectric layer is located on the amorphous silicon layer.

6. The solar cell according to claim 5, characterized in that, The surface of the amorphous silicon layer has a textured structure, and the size of the textured structure is on the submicron scale.

7. The solar cell according to claim 5, characterized in that, The thickness of the amorphous silicon layer ranges from 5 nm to 8 nm.

8. A method for preparing a solar cell, characterized in that, include: Provide a base; A tunneling medium layer is formed, the tunneling medium layer being located on the surface of the substrate; An intrinsic semiconductor film is formed, wherein the intrinsic semiconductor film is located on the surface of the tunneling dielectric layer; The intrinsic semiconductor film is doped to form a doped conductive layer and a doped silicon glass layer, wherein the doped silicon glass layer is located on the surface of the doped conductive layer. The doped silicon glass layer is subjected to a dry plasma etching process to transform the doped silicon glass layer into a fluorine-doped silicon oxide layer, wherein the fluorine-doped silicon oxide layer has a mesoporous structure. A passivation layer is formed on the fluorine-doped silicon oxide layer; An electrode is formed, which is electrically connected to the doped conductive layer.

9. The method for preparing a solar cell according to claim 8, characterized in that, The process parameters of the dry plasma etching process include: using an NF3 / N2O mixed gas with a volume ratio of (2%~5%):(95%~98%), a reaction pressure of 0.5 Torr~1.0 Torr, an RF power of 300W~500W, and a reaction time of 20s~40s.

10. The method for preparing a solar cell according to claim 8, characterized in that, The doped silicon glass layer includes: a first doped silicon glass layer formed on a first surface of the substrate and a second doped silicon glass layer formed on the doped conductive layer; after forming the doped silicon glass layer, it further includes: The dry plasma etching process is performed on the second doped silicon glass layer; a mask layer is formed on the surface of the second doped silicon glass layer; the first doped silicon glass layer is removed; or... A mask layer is formed on the surface of the second doped silicon glass layer; the first doped silicon glass layer is removed; and the remaining second doped silicon glass layer is subjected to the dry plasma etching process.

11. The method for preparing a solar cell according to claim 8, characterized in that, After forming the fluorine-doped silicon oxide layer, the method further includes: using an ion implantation process to modify the substrate, thereby converting a portion of the substrate into an amorphous silicon layer.

12. A stacked battery, characterized in that, include: The bottom cell is a solar cell as described in any one of claims 1 to 7 or a solar cell prepared by the preparation method as described in any one of claims 8 to 11; A top battery, located on one side of the bottom battery.

13. A photovoltaic module, characterized in that, include: A battery string is formed by connecting multiple solar cells as described in any one of claims 1 to 7, solar cells prepared by the preparation method as described in any one of claims 8 to 11, or tandem cells as described in claim 12. An encapsulating film is used to cover the surface of the battery string; A cover plate is used to cover the surface of the encapsulating film that faces away from the battery string.

Images