Display device, method of manufacturing the same, and display apparatus

Abstract

This invention provides a display device and its manufacturing method, as well as a display apparatus, relating to the field of display technology, and is used to solve the problem of decreased luminous efficiency in miniaturized display devices. The display device includes: a substrate and a pixel structure disposed on the substrate. The pixel structure includes a plurality of nanopillar light-emitting units, each nanopillar light-emitting unit having a groove around its periphery. The display device also includes a lens structure located on the side of the plurality of nanopillar light-emitting units facing away from the substrate. The lens structure includes a plurality of lens units, the orthographic projection of each lens unit onto the substrate covering the orthographic projection of the corresponding nanopillar light-emitting unit onto the substrate, and at least a portion of each lens unit being located within the groove around the corresponding nanopillar light-emitting unit.

Description

Technical Field

[0001] This invention relates to the field of display technology, and in particular to a display device, its manufacturing method, and a display apparatus. Background Technology

[0002] With the continuous development of display technology, the application fields of display devices are becoming increasingly widespread. To meet the needs of more application areas, it is necessary to manufacture miniaturized display devices with smaller dimensions. Taking light-emitting diode (LED) display devices as an example, in the process of miniaturizing LED display devices, when the size of LED display devices is reduced from the commonly used 250μm or more to about 100μm, there are not many technical challenges. However, when the size of LED display devices is further reduced to below 100μm, many problems that cannot be ignored arise, such as: increased surface defects of LED display devices, current congestion, sidewall effect, mass chip (i.e., LED display device) transfer, mass chip repair, etc. These problems all lead to a decrease in the luminous efficiency of display devices, which seriously limits the large-scale application of Micro-LED in the field of micro-displays. Summary of the Invention

[0003] The purpose of this invention is to provide a display device and its manufacturing method, as well as a display apparatus, to solve the problem of decreased luminous efficiency in miniaturized display devices.

[0004] To achieve the above objectives, the present invention provides the following technical solution:

[0005] A first aspect of the present invention provides a display device, comprising: a substrate and a pixel structure disposed on the substrate, the pixel structure comprising a plurality of nanopillar light-emitting units, each nanopillar light-emitting unit having a groove around its periphery; the display device further comprising a lens structure located on the side of the plurality of nanopillar light-emitting units facing away from the substrate, the lens structure comprising a plurality of lens units, the orthographic projection of the lens units on the substrate covering the orthographic projection of the corresponding nanopillar light-emitting unit on the substrate, at least a portion of the lens units being located within the groove around the corresponding nanopillar light-emitting unit.

[0006] Optionally, the nanopillar light-emitting unit includes a first semiconductor layer, a quantum well film layer, a second semiconductor layer, and a second electrode layer sequentially stacked along a direction away from the substrate; the pixel structure further includes:

[0007] A dielectric layer is located in the trenches surrounding each nanopillar light-emitting unit, and the dielectric layer at least covers the side surface of the first semiconductor layer and the side surface of the quantum well film layer;

[0008] A common electrode layer is coupled to the second electrode layer in each of the nanopillar light-emitting units, and at least a portion of the common electrode layer is located in the trench around each nanopillar light-emitting unit.

[0009] The dielectric layer, the common electrode layer, and the lens unit are stacked sequentially in a direction away from the substrate.

[0010] Optionally, the distance between the trench surface and the portion of the common electrode layer located at the bottom of the trench is less than the thickness of the second semiconductor layer; at least a portion of the side surface of the second semiconductor layer is in contact with the common electrode layer.

[0011] Optionally, the dielectric layer continues the morphology of the trench walls and bottom, and the dielectric layer covers the side surface of the second semiconductor layer; the portion of the common electrode layer located within the trench continues the morphology of the dielectric layer; the distance between the trench surface and the portion of the common electrode layer located at the bottom of the trench is greater than the sum of the thicknesses of the quantum well film layer and the second semiconductor layer.

[0012] Optionally, the display device further includes a distributed Bragg reflector located on the side of the lens structure facing away from the substrate.

[0013] Optionally, the distributed Bragg reflector includes a first material layer and a second material layer stacked together, the first material layer and the second material layer having different refractive indices.

[0014] Optionally, the first material layer includes a SiN film layer and the second material layer includes a SiO2 film layer; or, the first material layer includes a Nb2O5 film layer and the second material layer includes a SiO2 film layer; or, the first material layer includes a TiO2 film layer and the second material layer includes a SiO2 film layer.

[0015] Based on the technical solution of the above-described display device, a second aspect of the present invention provides a display apparatus including the above-described display device.

[0016] Based on the above-described display device technical solution, a third aspect of the present invention provides a method for manufacturing a display device, used to manufacture the above-described display device; the manufacturing method includes:

[0017] A pixel structure is fabricated on a substrate, the pixel structure comprising multiple nanopillar light-emitting units, each nanopillar light-emitting unit having a groove around its periphery;

[0018] A lens structure is fabricated on the side of the plurality of nanopillar light-emitting units facing away from the substrate. The lens structure includes a plurality of lens units, the orthographic projection of the lens unit on the substrate covering the orthographic projection of the corresponding nanopillar light-emitting unit on the substrate, and at least a portion of the lens unit is located in a groove around the corresponding nanopillar light-emitting unit.

[0019] Optionally, the steps for creating the pixel structure on the substrate specifically include:

[0020] Multiple nanopillar light-emitting units are fabricated, each nanopillar light-emitting unit comprising a first semiconductor layer, a quantum well film layer, a second semiconductor layer, and a second electrode layer sequentially stacked along a direction away from the substrate;

[0021] A dielectric layer is fabricated, which is located in the trenches around each nanopillar light-emitting unit, and the dielectric layer at least covers the side surface of the first semiconductor layer and the side surface of the quantum well film layer;

[0022] A common electrode layer is fabricated, which is coupled to the second electrode layer in each of the nanopillar light-emitting units. At least a portion of the common electrode layer is located in the trenches surrounding each nanopillar light-emitting unit. The dielectric layer, the common electrode layer, and the lens unit are stacked sequentially in a direction away from the substrate.

[0023] The steps for fabricating the lens structure specifically include:

[0024] A lens material layer is fabricated, wherein the orthographic projection of the lens material layer onto the substrate covers the orthographic projection of the pixel structure onto the substrate;

[0025] The lens material layer is patterned to form the lens structure.

[0026] In the technical solution provided by this invention, a single pixel structure is divided into multiple nanopillar light-emitting units. Grooves are formed around each nanopillar light-emitting unit, and a lens structure is provided on the light-emitting side of each nanopillar light-emitting unit. Each lens unit in the lens structure can cover the corresponding nanopillar light-emitting unit and can be at least partially located within the grooves surrounding the corresponding nanopillar light-emitting unit, thus achieving wrapping around the side surface of the nanopillar light-emitting unit. Therefore, in the technical solution provided by this invention, the lens units can wrap around the top and side surfaces of the nanopillar light-emitting units, increasing the light emission from the top surface of each nanopillar light-emitting unit while also effectively extracting the light emission from the side surfaces, thereby effectively improving the luminous efficiency of the display device.

[0027] Therefore, for miniaturized display devices with a size of less than 100μm, and miniaturized display devices including arrayed light-emitting units of a few micrometers, the technical solution provided by the present invention can effectively solve the problem of reduced luminous efficiency and reduce the power consumption of miniaturized display devices. Attached Figure Description

[0028] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings:

[0029] Figures 1 to 8 A process flow diagram for manufacturing a display device provided in an embodiment of the present invention;

[0030] Figure 9 This is a schematic diagram of a first cross-section of a medium layer formed in a trench, provided by an embodiment of the present invention.

[0031] Figure 10 In order to be in Figure 9 A schematic diagram of the lens structure formed in the middle;

[0032] Figure 11 This is a schematic diagram of a second cross-section of a medium layer formed in a trench, provided by an embodiment of the present invention;

[0033] Figure 12 In order to be in Figure 11 A schematic diagram of the lens structure formed in the middle;

[0034] Figure 13 This is a schematic diagram of forming a distributed Bragg reflector in a display device according to an embodiment of the present invention. Detailed Implementation

[0035] To further illustrate the display device and its manufacturing method, as well as the display apparatus provided in the embodiments of the present invention, a detailed description is provided below with reference to the accompanying drawings.

[0036] Please see Figures 1 to 12 This invention provides a display device, including: a substrate 10 and a pixel structure disposed on the substrate 10, the pixel structure including a plurality of nanopillar light-emitting units 20, each nanopillar light-emitting unit 20 having a groove 30 around its periphery; the display device further includes a lens structure 40, the lens structure 40 including a plurality of lens units 401, the lens units 401 covering the corresponding nanopillar light-emitting units 20, at least a portion of the lens units 401 being located within the groove 30 around the corresponding nanopillar light-emitting unit 20.

[0037] For example, the lens structure 40 is located on the side of the plurality of nanopillar light-emitting units 20 facing away from the substrate 10. The lens structure 40 includes a plurality of lens units 401, and the orthogonal projection of the lens unit 401 on the substrate 10 covers the orthogonal projection of the corresponding nanopillar light-emitting unit 20 on the substrate 10.

[0038] For example, the pixel structure includes a plurality of nanopillar light-emitting units 20 arranged in an array, the plurality of nanopillar light-emitting units 20 emitting light of the same color.

[0039] For example, each nanopillar light-emitting unit 20 has a groove 30 around its periphery. The groove 30 is formed due to the step difference between each nanopillar light-emitting unit 20 and other surrounding structures. It should be noted that the periphery of the nanopillar light-emitting unit 20 refers to the peripheral region immediately adjacent to the nanopillar light-emitting unit 20. This peripheral region may surround the nanopillar light-emitting unit 20 or at least partially surround it.

[0040] For example, the display device further includes a lens structure 40 located on the side of the pixel structure facing away from the substrate 10. The lens structure 40 includes a plurality of lens units 401 arranged in an array. The lens units 401 cover the corresponding nanopillar light-emitting units 20, and at least a portion of the lens units 401 are located in the grooves 30 around the corresponding nanopillar light-emitting units 20, thereby wrapping at least a portion of the side of the nanopillar light-emitting units 20.

[0041] For example, the nanopillar light-emitting unit 20 is patterned by using nanoimprinting and etching processes. By adjusting the diameter and height of the nanopillar light-emitting unit 20, the shape of the lens unit 401 can be adjusted.

[0042] As can be seen from the specific structure of the display device described above, in the display device provided by the embodiments of the present invention, a single pixel structure is divided into multiple nanopillar light-emitting units 20, a groove 30 is formed around each nanopillar light-emitting unit 20, and a lens structure 40 is provided on the light-emitting side of the nanopillar light-emitting unit 20, so that each lens unit 401 in the lens structure 40 can cover the corresponding nanopillar light-emitting unit 20 and can be at least partially located in the groove 30 around the corresponding nanopillar light-emitting unit 20, thereby achieving the wrapping of the side of the nanopillar light-emitting unit 20. Therefore, in the display device provided by the embodiments of the present invention, the lens unit 401 can wrap the light-emitting top surface and side surface of the nanopillar light-emitting unit 20, which not only increases the light emission from the top surface of each nanopillar light-emitting unit 20, but also effectively extracts the light emission from the side surface of each nanopillar light-emitting unit 20, thereby effectively improving the luminous efficiency of the display device.

[0043] Therefore, for miniaturized display devices with a size of less than 100μm, and miniaturized display devices including arrayed light-emitting units of a few micrometers, the technical solution provided by the embodiments of the present invention can effectively solve the problem of reduced luminous efficiency and effectively reduce the power consumption of miniaturized display devices.

[0044] Please see Figures 1 to 12 In some embodiments, the nanopillar light-emitting unit 20 includes a first semiconductor layer 202, a quantum well film layer 203, a second semiconductor layer 204, and a second electrode layer 205 sequentially stacked along a direction away from the substrate 10; the pixel structure further includes:

[0045] A dielectric layer 50 is located in the trench 30 surrounding each nanopillar light-emitting unit 20. The dielectric layer 50 covers at least the side surface of the first semiconductor layer 202 and the side surface of the quantum well film layer 203. It should be noted that the film layer includes a bottom surface facing the substrate and a top surface facing away from the substrate. The film layer also includes a side surface that connects the bottom surface and the top surface, respectively.

[0046] A common electrode layer 60 is coupled to the second electrode layer 205 in each of the nanopillar light-emitting units 20, and at least a portion of the common electrode layer 60 is located in the trench 30 around each nanopillar light-emitting unit 20.

[0047] The dielectric layer 50, the common electrode layer 60, and the lens unit 401 are stacked sequentially in a direction away from the substrate 10.

[0048] For example, the first semiconductor layer 202 includes an N-type GaN film, the second semiconductor layer 204 includes a P-type GaN film, and the quantum well film 203 is made of a variety of materials, such as InGaN, GaN, etc., but not limited to these.

[0049] For example, the pixel structure further includes a buffer layer 70, which may include, but is not limited to, a GaN buffer layer. The buffer layer 70 is located between the plurality of nanopillar light-emitting units 20 and the substrate 10, and the buffer layer 70 is in contact with the first semiconductor layer 202 in each nanopillar light-emitting unit 20.

[0050] For example, the bottom of the trench 30 is the buffer layer 70, and the trench wall of the trench 30 includes the buffer layer 70, the first semiconductor layer 202, the quantum well film layer 203, the second semiconductor layer 204, and the second electrode layer 205.

[0051] For example, the nanopillar light-emitting unit 20 is formed as a columnar structure, and the light emission color of the nanopillar light-emitting unit 20 can be controlled by changing the diameter of the nanopillar light-emitting unit 20.

[0052] For example, the dielectric layer 50 includes an insulating layer that fills the trench 30 surrounding each nanopillar light-emitting unit 20, and the dielectric layer 50 is in contact with the side surface of the first semiconductor layer 202 and the side surface of the quantum well film layer 203.

[0053] The dielectric layer 50 described above fills the trench 30, which not only fills the step difference formed by the nanopillar light-emitting unit 20, ensuring the stability and yield of each nanopillar light-emitting unit 20, but also indirectly adjusts the shape of the upper lens unit 401 by changing the morphology of the dielectric layer 50, thereby improving the light extraction efficiency of the display device.

[0054] The above-mentioned common electrode layer 60 is coupled to the second electrode layer 205 in each of the nanopillar light-emitting units 20, which not only ensures that the second electrode layer 205 in each of the nanopillar light-emitting units 20 can stably receive electrode signals, but also helps to simplify the structural complexity of the display device and reduce the manufacturing difficulty of the display device.

[0055] The above configuration ensures that after the dielectric layer 50 and the common electrode layer 60 are formed, there is still a certain step difference between the nanopillar light-emitting unit 20 and its surroundings. That is, the trench 30 around the nanopillar light-emitting unit 20 is not filled by the dielectric layer 50 and the common electrode layer 60. Based on this, a lens unit 401 is formed above the common electrode layer 60. At least a portion of the lens unit 401 is located in the trench 30, so that the lens unit 401 can cover at least a portion of the side surface of the nanopillar light-emitting unit 20, thereby effectively improving the lateral light extraction efficiency of the nanopillar light-emitting unit 20 and improving the overall light extraction efficiency of the display device.

[0056] like Figure 9 and Figure 10 As shown, in some embodiments, after the trench 30 is filled by the dielectric layer 50 and the common electrode layer 60, the depth of the trench 30 is less than the thickness of the second semiconductor layer 204; at least a portion of the side surface of the second semiconductor layer 204 is in contact with the common electrode layer 60.

[0057] For example, the distance between the trench surface and the portion of the common electrode layer 60 located at the bottom of the trench is less than the thickness of the second semiconductor layer 204. It should be noted that the trench surface refers to the surface of the trench wall at the edge of the trench opening that faces away from the substrate.

[0058] For example, the dielectric layer 50 covers the sides of the first semiconductor layer 202 and the sides of the quantum well film layer 203. The dielectric layer 50 does not cover the sides of the second semiconductor layer 204, or the dielectric layer 50 covers the sides of the second semiconductor layer 204 near a portion of the substrate 10.

[0059] For example, the dielectric layer 50 can fill the step gap formed by the first semiconductor layer 202 and the quantum well film layer 203.

[0060] The above arrangement results in a shallow remaining accommodating space in the trench 30 after the dielectric layer 50 and the common electrode layer 60 are filled in the trench 30, thereby making the volume of the lens unit 401 subsequently fabricated in the trench 30 smaller.

[0061] like Figure 11 and Figure 12 As shown, in some embodiments, the dielectric layer 50 continues the morphology of the trench walls and bottom of the trench 30, and the dielectric layer 50 covers the side of the second semiconductor layer 204; the portion of the common electrode layer 60 located within the trench 30 continues the morphology of the dielectric layer 50; after the trench 30 is filled by the dielectric layer 50 and the common electrode layer 60, the depth of the trench 30 is greater than the sum of the thicknesses of the quantum well film layer 203 and the second semiconductor layer 204.

[0062] For example, the distance between the trench surface and the portion of the common electrode layer 60 located at the bottom of the trench is greater than the sum of the thicknesses of the quantum well film layer 203 and the second semiconductor layer 204.

[0063] For example, the dielectric layer 50 is a thinner layer that continues the morphology of the trench walls and bottom of the trench 30. The dielectric layer 50 covers the side of the first semiconductor layer 202, the side of the quantum well film layer 203, the side of the second semiconductor layer 204, and the side of the second electrode layer 205.

[0064] The above configuration results in a deeper remaining space in the trench 30 after the dielectric layer 50 and the common electrode layer 60 are filled in the trench 30. This allows the lens unit 401 to be filled in the trench 30 in a larger volume, so that the side of the nanopillar light-emitting unit 20 can correspond to the curved surface of the lens unit 401 with a larger area. This allows more side-emitting light rays to be emitted from the corresponding curved surface of the lens unit 401, thereby achieving more efficient side light extraction.

[0065] In the display device provided in the above embodiments, by setting the dielectric layer 50 to have different morphologies, the morphology of the lens unit 401 can be adjusted, thereby adjusting the degree of encapsulation of the lens unit 401 on the nanopillar light-emitting unit 20, achieving different lateral light extraction efficiencies, and thus achieving the light extraction efficiency that meets the requirements.

[0066] like Figure 13 As shown, in some embodiments, the display device further includes a distributed Bragg reflector (DBR) located on the side of the lens structure 40 facing away from the substrate 10.

[0067] For example, the distributed Bragg reflector (DBR) covers the lens structure 40, and the distributed Bragg reflector (DBR) continues the appearance of the lens structure 40, but is not limited thereto.

[0068] The above configuration further improves the light extraction efficiency of the display device.

[0069] In some embodiments, the distributed Bragg reflector (DBR) includes a first material layer and a second material layer stacked together, the first material layer and the second material layer having different refractive indices.

[0070] For example, the distributed Bragg reflector (DBR) includes multiple first material layers and multiple second material layers, with the first and second material layers arranged alternately, but is not limited to this.

[0071] For example, the refractive index difference between the first material layer and the second material layer is greater than 0.4, but is not limited to this.

[0072] For example, the refractive index of the first material layer is greater than that of the second material layer, and the first material layer is located between the second material layer and the substrate 10, but is not limited thereto.

[0073] For example, the thickness of a single film of the first material layer and the second material layer is less than 100 nm, but it is not limited to this.

[0074] For example, the first material layer includes a SiN film layer and the second material layer includes a SiO2 film layer; or, the first material layer includes an Nb2O5 film layer and the second material layer includes a SiO2 film layer; or, the first material layer includes a TiO2 film layer and the second material layer includes SiO2. Wherein, the SiN film layer, Nb2O5 film layer, and TiO2 film layer are high refractive index films, and the SiO2 film layer is a low refractive index film layer.

[0075] In the display device provided in the above embodiments, by setting the distributed Bragg reflector (DBR) to include a first material layer and a second material layer with different refractive indices stacked together, and by adjusting the thickness of the first material layer and the second material layer, the light extraction efficiency of the display device is further improved.

[0076] This invention also provides a display device, including the display device provided in the above embodiments.

[0077] For example, the display device includes a Micro LED display device, but is not limited to this.

[0078] It should be noted that the display device can be any product or component with display function, such as a television, monitor, digital photo frame, mobile phone, or tablet computer. The display device also includes flexible circuit boards, printed circuit boards, and backplanes.

[0079] In the display device provided in the above embodiments, a single pixel structure is divided into multiple nanopillar light-emitting units 20. A groove 30 is formed around each nanopillar light-emitting unit 20, and a lens structure 40 is provided on the light-emitting side of each nanopillar light-emitting unit 20. Each lens unit 401 in the lens structure 40 can cover the corresponding nanopillar light-emitting unit 20 and can be at least partially located within the groove 30 around the corresponding nanopillar light-emitting unit 20, thus achieving wrapping around the side surface of the nanopillar light-emitting unit 20. Therefore, in the display device provided in the above embodiments, the lens unit 401 can wrap around the light-emitting top surface and side surface of the nanopillar light-emitting unit 20, increasing the light emission from the top surface of each nanopillar light-emitting unit 20 while also effectively extracting the light emission from the side surface of each nanopillar light-emitting unit 20, thereby effectively improving the luminous efficiency of the display device. Therefore, for miniaturized display devices with a size less than 100 μm, and miniaturized display devices including arrayed light-emitting units of a few micrometers, the technical solution provided in the above embodiments can effectively solve the problem of decreased luminous efficiency and effectively reduce the power consumption of miniaturized display devices.

[0080] The display device provided in the embodiments of the present invention, when including the above-described display device, also has the above-described beneficial effects, which will not be repeated here.

[0081] This invention also provides a method for manufacturing a display device, used to manufacture the display device provided in the above embodiments; the manufacturing method includes:

[0082] A pixel structure is fabricated on a substrate 10, the pixel structure including a plurality of nanopillar light-emitting units 20, each nanopillar light-emitting unit 20 having a groove 30 around its periphery;

[0083] A lens structure 40 is fabricated, comprising a plurality of lens units 401. Each lens unit 401 covers a corresponding nanopillar light-emitting unit 20, and at least a portion of each lens unit 401 is located within a groove 30 surrounding the corresponding nanopillar light-emitting unit 20. For example, the lens structure 40 is located on the side of the plurality of nanopillar light-emitting units 20 facing away from the substrate, and the orthographic projection of each lens unit 401 onto the substrate 10 overlaps the orthographic projection of the corresponding nanopillar light-emitting unit 20 onto the substrate 10.

[0084] In the display device fabricated using the method provided in this embodiment of the invention, a single pixel structure is divided into multiple nanopillar light-emitting units 20. A groove 30 is formed around each nanopillar light-emitting unit 20, and a lens structure 40 is provided on the light-emitting side of each nanopillar light-emitting unit 20. Each lens unit 401 in the lens structure 40 can cover the corresponding nanopillar light-emitting unit 20 and can be at least partially located within the groove 30 surrounding the corresponding nanopillar light-emitting unit 20, thus achieving the wrapping of the side surface of the nanopillar light-emitting unit 20. Therefore, in the display device fabricated using the method provided in this embodiment of the invention, the lens unit 401 can wrap the top and side surfaces of the nanopillar light-emitting unit 20, increasing the light emission from the top surface of each nanopillar light-emitting unit 20 while also effectively extracting the light emission from the side surfaces of each nanopillar light-emitting unit 20, thereby effectively improving the luminous efficiency of the display device. Therefore, for miniaturized display devices with a size of less than 100 μm, and miniaturized display devices including arrayed light-emitting units of a few micrometers, the display devices fabricated using the manufacturing method provided in the embodiments of the present invention can effectively solve the problem of reduced luminous efficiency and effectively reduce the power consumption of miniaturized display devices.

[0085] In some embodiments, the step of fabricating the pixel structure on the substrate 10 specifically includes:

[0086] Multiple nanopillar light-emitting units 20 are fabricated. Each nanopillar light-emitting unit 20 includes a first semiconductor layer 202, a quantum well film layer 203, a second semiconductor layer 204, and a second electrode layer 205, which are sequentially stacked along a direction away from the substrate 10.

[0087] A dielectric layer 50 is fabricated, which is located in the trench 30 around each nanopillar light-emitting unit 20. The dielectric layer 50 covers at least the side surface of the first semiconductor layer 202 and the side surface of the quantum well film layer 203.

[0088] A common electrode layer 60 is fabricated, which is coupled to the second electrode layer 205 in each of the nanopillar light-emitting units 20. At least a portion of the common electrode layer 60 is located in the trench 30 around each nanopillar light-emitting unit 20. The dielectric layer 50, the common electrode layer 60 and the lens unit 401 are stacked sequentially in a direction away from the substrate 10.

[0089] The steps for fabricating the lens structure 40 specifically include:

[0090] A lens material layer is fabricated, which covers the pixel structure; for example, the orthographic projection of the lens material layer on the substrate covers the orthographic projection of the pixel structure on the substrate.

[0091] The lens material layer is patterned to form the lens structure 40.

[0092] like Figures 1 to 8 As shown, to more clearly illustrate the manufacturing process of display devices, a detailed manufacturing process is provided below as an example:

[0093] Provides a 4-inch sapphire substrate 10.

[0094] A buffer material layer 70a, a first semiconductor material layer 202a, a quantum well material layer 203a, a second semiconductor material layer 204a, and a second electrode material layer 205a are epitaxially grown sequentially on the substrate 10. The buffer material layer 70a includes a GaN film, the first semiconductor material layer 202a includes an N-type GaN film, the quantum well material layer 203a includes an InGaN film, the second semiconductor material layer 204a includes a P-type GaN film, and the second electrode material layer 205a includes an ITO (indium tin oxide) film. The thickness of the quantum well material layer is approximately 100 nm, and the thickness of the second semiconductor material layer is approximately 100 nm.

[0095] SiO2 material was deposited using plasma-enhanced chemical vapor deposition (PECVD) to form a mask material layer with a thickness ranging from 100 nm to 300 nm.

[0096] Nanoimprinting technology is used to imprint a mask material layer using a nanopillar template; the diameter of the nanopillar template can range from 300 nm to 1000 nm.

[0097] like Figure 2 As shown, inductively coupled plasma (ICP) etching technology is used, and F (fluorine)-based ions are used to etch the mask material layer to form a hard mask pattern 80.

[0098] like Figure 3As shown, using a hard mask pattern as a mask, ICP etching technology is employed, with Cl-based ions used as the gas to etch and form nanopillar light-emitting units 20. Grooves 30 are formed around each nanopillar light-emitting unit 20, with an etching depth in the range of 300nm to 1000nm, which can etch part of the buffer material layer.

[0099] like Figure 4 As shown, a dielectric material layer is formed, which fills the trenches 30 surrounding each nanopillar light-emitting unit 20 and covers the second electrode layer 205. Then, the dielectric material layer is etched using ICP etching technology to expose the second electrode layer 205, forming the dielectric layer 50. For example, the thickness of the dielectric layer 50 is controlled within the range of 100 nm to 200 nm, but is not limited to this.

[0100] like Figure 4 As shown, ITO material is deposited on the entire surface to form the common electrode layer 60. To ensure good current spreading performance, the thickness of the common electrode layer 60 can be set to be greater than 100 nm.

[0101] like Figure 5 As shown, a high refractive index (e.g., refractive index > 1.7) lens material layer is formed by spin coating. Lens structure 40 is formed by adjusting exposure and ICP etching. More specifically, the lens material layer completely covers the pixel structure; a photoresist layer is formed on the side of the lens material layer facing away from the substrate 10; the photoresist layer is exposed and developed to form a photoresist pattern; the lens material layer is patterned using the photoresist pattern as a mask to form the lens structure 40.

[0102] like Figure 6 As shown, a first electrode layer 201 is fabricated using a lift-off technique. The first electrode layer 201 is located on the surface of the buffer layer 70 facing away from the substrate 10. The first electrode layer 201 includes multiple sub-film layers stacked together, such as: the first electrode layer 201 includes a Ti sub-film layer, an Al sub-film layer, a Ni sub-film layer, and an Au sub-film layer stacked sequentially, with the thickness of the Ti sub-film layer between 15nm and 30nm, the thickness of the Al sub-film layer between 50nm and 200nm, the thickness of the Ni sub-film layer between 20nm and 50nm, and the thickness of the Au sub-film layer between 50nm and 350nm; or the first electrode layer 201 includes a Cr sub-film layer, a Pt sub-film layer, and an Au sub-film layer stacked sequentially, with the thickness of the Cr sub-film layer being 50nm, the thickness of the Pt sub-film layer being 20nm, and the thickness of the Au sub-film layer being 250nm.

[0103] like Figure 7As shown, a passivation layer PVX is fabricated, wherein the passivation layer PVX has vias exposing the first electrode layer 201 and vias exposing the common electrode layer 60.

[0104] like Figure 8 As shown, a first conductive pad Pad1 and a second conductive pad Pad2 are fabricated. The first conductive pad Pad1 is coupled to the common electrode layer 60, and the second conductive pad Pad2 is coupled to the first electrode layer 201.

[0105] It is worth noting that all the technical solutions provided in the embodiments of the present invention are applicable not only to display devices (i.e., chips) with flip-chip structures, but also to display devices with upright structures.

[0106] It should be noted that, in the embodiments of the present invention, "same layer" can refer to film layers located on the same structural layer. Alternatively, for example, film layers located on the same layer can be layer structures formed by using the same film deposition process to form a specific pattern, and then patterning the film layer using the same photomask through a single patterning process. Depending on the specific pattern, the single patterning process may include multiple exposure, development, or etching processes, and the specific pattern in the formed layer structure can be continuous or discontinuous. These specific patterns may also be at different heights or have different thicknesses.

[0107] In the various method embodiments of the present invention, the sequence numbers of each step are not intended to limit the order of the steps. For those skilled in the art, any changes in the order of the steps without creative effort are also within the scope of protection of the present invention.

[0108] It should be noted that the various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the method embodiments are basically similar to the product embodiments, so the description is relatively simple, and the relevant parts can be referred to the description of the product embodiments.

[0109] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this invention pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connection,” “coupled,” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships; these relative positional relationships may change accordingly when the absolute position of the described object changes.

[0110] It is understandable that when a component such as a layer, film, region, or substrate is referred to as being "above" or "below" another component, the component may be "directly" located "above" or "below" the other component, or there may be intermediate components present.

[0111] In the description of the above embodiments, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0112] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A display device, characterized in that, include: The display device includes a substrate and a pixel structure disposed on the substrate, the pixel structure comprising a plurality of nanopillar light-emitting units, each nanopillar light-emitting unit having a groove around its periphery; the display device further includes a lens structure located on the side of the plurality of nanopillar light-emitting units facing away from the substrate, the lens structure comprising a plurality of lens units, the orthographic projection of the lens unit on the substrate covering the orthographic projection of the corresponding nanopillar light-emitting unit on the substrate, at least a portion of the lens unit being located within the groove around the corresponding nanopillar light-emitting unit.

2. A display device according to claim 1, characterised in that The nanopillar light-emitting unit includes a first semiconductor layer, a quantum well film layer, a second semiconductor layer, and a second electrode layer sequentially stacked along a direction away from the substrate; the pixel structure further includes: A dielectric layer is located in the trenches surrounding each nanopillar light-emitting unit, and the dielectric layer at least covers the side surface of the first semiconductor layer and the side surface of the quantum well film layer; A common electrode layer is coupled to the second electrode layer in each of the nanopillar light-emitting units, and at least a portion of the common electrode layer is located in the trenches surrounding each nanopillar light-emitting unit; the dielectric layer, the common electrode layer and the lens unit are stacked sequentially in a direction away from the substrate.

3. The display device according to claim 2, characterized in that, The distance between the trench surface and the portion of the common electrode layer located at the bottom of the trench is less than the thickness of the second semiconductor layer; at least a portion of the side surface of the second semiconductor layer is in contact with the common electrode layer.

4. The display device according to claim 2, characterized in that, The dielectric layer continues the shape of the trench walls and bottom, and the dielectric layer covers the side of the second semiconductor layer; the portion of the common electrode layer located within the trench continues the shape of the dielectric layer. The distance between the trench surface and the portion of the common electrode layer located at the bottom of the trench is greater than the sum of the thicknesses of the quantum well film and the second semiconductor layer.

5. The display device according to any one of claims 1 to 4, characterized in that, The display device further includes a distributed Bragg reflector located on the side of the lens structure facing away from the substrate.

6. The display device according to claim 5, characterized in that, The distributed Bragg reflector includes a first material layer and a second material layer stacked together, the first material layer and the second material layer having different refractive indices.

7. The display device according to claim 5, characterized in that, The first material layer includes a SiN film layer and the second material layer includes a SiO2 film layer; or, the first material layer includes a Nb2O5 film layer and the second material layer includes a SiO2 film layer; or, the first material layer includes a TiO2 film layer and the second material layer includes a SiO2 film layer.

8. A display device, characterized in that, Includes the display device as described in any one of claims 1 to 7.

9. A method for manufacturing a display device, characterized in that, Used to manufacture a display device as described in any one of claims 1 to 7; the manufacturing method includes: A pixel structure is fabricated on a substrate, the pixel structure comprising multiple nanopillar light-emitting units, each nanopillar light-emitting unit having a groove around its periphery; A lens structure is fabricated on the side of the plurality of nanopillar light-emitting units facing away from the substrate. The lens structure includes a plurality of lens units, the orthographic projection of the lens unit on the substrate covering the orthographic projection of the corresponding nanopillar light-emitting unit on the substrate, and at least a portion of the lens unit is located in a groove around the corresponding nanopillar light-emitting unit.

10. The method for manufacturing a display device according to claim 9, characterized in that, The specific steps involved in creating a pixel structure on a substrate include: Multiple nanopillar light-emitting units are fabricated, each nanopillar light-emitting unit comprising a first semiconductor layer, a quantum well film layer, a second semiconductor layer, and a second electrode layer sequentially stacked along a direction away from the substrate; A dielectric layer is fabricated, which is located in the trenches around each nanopillar light-emitting unit, and the dielectric layer at least covers the side surface of the first semiconductor layer and the side surface of the quantum well film layer; A common electrode layer is fabricated, which is coupled to the second electrode layer in each of the nanopillar light-emitting units. At least a portion of the common electrode layer is located in the trenches surrounding each nanopillar light-emitting unit. The dielectric layer, the common electrode layer, and the lens unit are stacked sequentially in a direction away from the substrate. The steps for fabricating the lens structure specifically include: A lens material layer is fabricated, wherein the orthographic projection of the lens material layer onto the substrate covers the orthographic projection of the pixel structure onto the substrate; The lens material layer is patterned to form the lens structure.

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