Display device and electronic device including the same

Abstract

A display device and an electronic apparatus including the same are provided. The display device includes a pixel and a first scan driver that provides a first scan signal to the pixel. The first scan driver can include a first inverter that inverts a first clock signal and outputs the inverted first clock signal, a first node controller that controls a voltage level of a first node and a voltage level of a second node to have levels different from each other in response to a first input signal, the first clock signal, and an output signal of the first inverter, a first output buffer that outputs the first scan signal in response to a voltage level of a third node and a voltage level of a fourth node, and a second inverter that inverts the voltage level of the fourth node and provides the inverted voltage level of the fourth node to the third node. The second node can be connected to the fourth node through the first inverter.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2025-0001442, filed on January 6, 2025, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates herein to display devices and electronic devices including display devices. Background Technology

[0003] Typically, electronic devices that provide images to users, such as smartphones, digital cameras, laptops, navigation systems, and smart TVs, include display devices for displaying images. The display device generates images and provides the generated images to the user via a screen.

[0004] The display device includes a plurality of pixels for generating an image, a scan driver for applying a scan signal to the pixels, a data driver for applying a data voltage to the pixels, and a transmit driver for applying a transmit signal to the pixels. The pixels receive the data voltage in response to the scan signal. The pixels display the image by emitting light with a brightness corresponding to the data voltage in response to the transmit signal. Summary of the Invention

[0005] This disclosure provides a display device capable of rapidly charging a scan signal to a target level while reducing power consumption, as well as an electronic device including the display device.

[0006] According to an embodiment of the present invention, a display device includes: a pixel; and a first scan driver configured to provide a first scan signal to the pixel. The first scan driver includes: a first inverter configured to invert a first clock signal and output the inverted first clock signal; a first node controller configured to control the voltage levels of a first node and a second node to have different levels in response to a first input signal, the first clock signal, and the output signal of the first inverter; a first output buffer configured to output the first scan signal in response to the voltage levels of a third node and a fourth node; and a second inverter configured to invert the voltage level of the fourth node and provide the inverted voltage level of the fourth node to the third node. The second node is connected to the fourth node via the first inverter.

[0007] In an embodiment of the present invention, the electronic device includes: a display device configured to display an image based on data received from a processor; and a processor electrically connected to the display device and configured to control the operation of the display device. The display device includes: pixels; and a first scan driver configured to provide a first scan signal to the pixels. The first scan driver includes: a first inverter configured to invert a first clock signal and output the inverted first clock signal; a first node controller configured to control the voltage levels of a first node and a second node to have different levels in response to a first input signal, the first clock signal, and the output signal of the first inverter; a first output buffer configured to output the first scan signal in response to the voltage levels of a third node and a fourth node; and a second inverter configured to invert the voltage level of the fourth node and provide the inverted voltage level of the fourth node to the third node. The second node is connected to the fourth node via the first inverter. Attached Figure Description

[0008] The accompanying drawings are included to provide a further understanding of the inventive concept, and together with the description, embodiments of the inventive concept are illustrated to explain its features.

[0009] Figure 1 This is a block diagram of an electronic device according to an embodiment of the concept of the present invention.

[0010] Figure 2 Schematic diagrams of electronic devices according to various embodiments are shown.

[0011] Figure 3 A cross-section of a display device according to an embodiment of the present invention is shown.

[0012] Figure 4 It shows Figure 3 The image shows a cross-section of the display panel.

[0013] Figure 5 This is a block diagram of a display device according to an embodiment of the present invention.

[0014] Figure 6 It shows Figure 5 The equivalent circuit of a pixel among the multiple pixels shown in the figure.

[0015] Figure 7 It is used to describe Figure 6 The timing diagram of the scanning and transmitting signals for the operation of the pixels is shown in the figure.

[0016] Figure 8 Is included Figure 5 A block diagram of the first scan driver in the scan driver is shown.

[0017] Figure 9 It shows Figure 8 The circuit configuration of the first stage of the first scan driver is shown in the figure.

[0018] Figure 10A Is applied to Figure 8 The timing diagram of the signals of the first stage and the second stage of the first scan driver is shown in the figure.

[0019] Figure 10B Is applied to Figure 8 The timing diagram of the signals of the third and fourth stages of the first scan driver is shown in the figure.

[0020] Figure 11A , Figure 11B and Figure 11C The first stage of the first scan driver is shown. Figure 10A The operation of the first, second, and third time periods is shown in the figure.

[0021] Figure 12 It shows the way Figure 9 The charging state of the first write scan signal output from the output terminal is shown in the figure.

[0022] Figure 13 The circuit configuration of the first stage of the first scan driver according to an embodiment of the present invention is shown.

[0023] Figure 14 Is applied to Figure 13 The timing diagram of the signals of the first stage of the first scan driver is shown in the figure.

[0024] Figure 15A and Figure 15B The first stage of the first scan driver is shown. Figure 14 The operation of the first and second time periods is shown in the figure.

[0025] Figure 16 Is included Figure 5 A block diagram of the second scan driver in the scan driver is shown.

[0026] Figure 17 It shows Figure 16 The circuit configuration of the first stage of the second scan driver is shown in the figure.

[0027] Figure 18 Is applied to Figure 16 The timing diagram of the signals of the first and second stages of the second scan driver is shown in the figure.

[0028] Figure 19A and Figure 19B The first stage of the second scan driver is shown. Figure 18 The operation of the first and second time periods is shown in the figure.

[0029] Figure 20 It is a timing diagram of the signals applied to the first and second stages of the third scan driver.

[0030] Figure 21A The first stage of the third scan driver is shown. Figure 20 The operation during the second time period is shown in the figure.

[0031] Figure 21B The first stage of the third scan driver is shown. Figure 20 The operation during the first time period is shown in the figure. Detailed Implementation

[0032] In this specification, it will be understood that when an element (or region, layer, or portion, etc.) is referred to as being "on" another element, "connected to" or "attached to" another element, the element may be directly on, directly connected to or attached to the other element, or may be indirectly on, indirectly connected to or attached to the other element, wherein an intermediary element is between the element and the other element.

[0033] Throughout this specification, the same reference numerals or symbols refer to the same elements. In the drawings, the thickness, scale, and dimensions of elements are exaggerated in order to effectively depict the technical features of the inventive concept. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0034] It will be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, components, regions, layers, or portions, these elements, components, regions, layers, or portions should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, or portion from another. For example, the first element, component, region, layer, or portion discussed below may be referred to as the second element, component, region, layer, or portion without departing from the scope of the inventive concept. Similarly, the second element, component, region, layer, or portion may also be referred to as the first element, component, region, layer, or portion. In this specification, the singular expressions “a” and “the (described)” are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0035] Additionally, terms such as "below," "under," "on the lower side," "above," "above," or "on the upper side" can be used to describe the spatial relationship between the elements shown in the accompanying drawings. These terms are relative concepts and are described based on the directions indicated in the drawings.

[0036] It will be further understood that, when used in this specification, the terms “comprising,” “including,” “containing,” and / or “having” indicate the presence of the stated features, quantities, steps, operations, elements, components, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, quantities, steps, operations, elements, components, and / or combinations thereof.

[0037] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which the inventive concept pertains. It will be further understood that terms such as those defined in commonly used dictionaries shall be interpreted as having a meaning consistent with their meaning in the context of the relevant field, and unless expressly defined herein, these terms shall not be interpreted in an idealized or overly formal sense.

[0038] In the following description, embodiments of the inventive concept are illustrated with reference to the accompanying drawings.

[0039] Figure 1 This is a block diagram of an electronic device according to an embodiment of the concept of the present invention.

[0040] refer to Figure 1 An electronic device ED according to an embodiment may include a display device DD for providing images to a user, and may further include modules or devices having additional functions besides providing images to a user like the display device DD. For example, an electronic device ED according to an embodiment may include a processor 12, a memory 13, a power module 14, and a display module 11 included in the display device DD.

[0041] The processor 12 may include at least one of a central processing unit (CPU), an application processor (AP), a graphics processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller.

[0042] Processor 12 can process image signals and provide the processed image signals to display device DD. For example, processor 12 can process image signals and provide the processed image signals to display module 11. Processor 12 can be connected to display device DD via a flexible circuit board or connector, etc. Display device DD can display images based on signals (e.g., data) received from processor 12. For example, display module 11 can display images based on data received from processor 12.

[0043] In an embodiment, from a functional or structural perspective, processor 12 may be divided into two or more blocks. For example, processor 12 may include a main processor in the form of a first driver chip containing a central processing unit and an auxiliary processor in the form of a second driver chip containing a controller (which receives image signals from the main processor and processes the image signals to conform to the interface specifications of display module 11).

[0044] The memory 13 can store the data information required for the operation of the processor 12 or the display module 11. When the processor 12 runs the application stored in the memory 13, input image signals and / or input control signals can be transmitted to the display module 11, and the display module 11 can process the received signals and output image information through the display screen.

[0045] The power module 14 may include a power supply module such as a power adapter or battery cell, and a power conversion module that converts the power supplied from the power supply module to generate the power required for the operation of the electronic device ED.

[0046] At least one of the individual components of the aforementioned electronic device ED can be included within the display device DD according to an embodiment of the present invention. Furthermore, in terms of function, some of the aforementioned modules can be included within the display device DD, while others can be provided separately from the display device DD. For example, although the display device DD may include a display module 11, a processor 12, and a memory 13, the power module 14 can be provided as a device separate from the display device DD but included within the electronic device ED.

[0047] Figure 2 Schematic diagrams of electronic devices according to various embodiments are shown.

[0048] refer to Figure 2 The display device DD according to embodiments of the present invention can be applied to various electronic devices. For example, various electronic devices that apply the display device DD according to the embodiments may include electronic devices such as smartphones 10_1a, tablet PCs 10_1b, laptop computers 10_1c, TVs 10_1d, or monitors 10_1e for desktop computers for displaying images.

[0049] Additionally, various electronic devices using the display device DD according to the embodiments may include wearable electronic devices such as smart glasses 10_2a, head-mounted displays 10_2b, or smartwatches 10_2c. Furthermore, various electronic devices using the display device DD according to the embodiments may include vehicle-specific electronic devices 10_3, such as a vehicle dashboard, center console, central information display (CID) located on the dashboard, or interior mirror display.

[0050] Figure 3 A cross-section of a display device according to an embodiment of the present invention is shown.

[0051] refer to Figure 3 The display device DD may include a display panel DP, an input sensing unit ISP, an anti-reflective layer RPL, a window WIN, a panel protective film PPF, and a first adhesive layer AL1 and a second adhesive layer AL2. For example... Figure 3 As shown, the aforementioned display module 11 may include a display panel DP, an input sensing unit ISP, an anti-reflective layer RPL, and a panel protective film PPF.

[0052] The display panel DP according to embodiments of the present invention can be an emissive display panel. For example, the display panel DP can be an organic emissive display panel or an inorganic emissive display panel. The light-emitting layer of an organic emissive display panel can include organic light-emitting materials. The light-emitting layer of an inorganic emissive display panel can include quantum dots or quantum rods, etc. Hereinafter, for ease of description, the display panel DP will be described as an organic emissive display panel.

[0053] The input sensing unit ISP can be disposed on the display panel DP. The input sensing unit ISP may include multiple sensing units (not shown) for capacitively sensing external input. The input sensing unit ISP can be directly manufactured on the display panel DP during the manufacturing of the display device DD. However, embodiments of the present invention are not limited thereto, and the input sensing unit ISP can be manufactured separately from the display panel DP and can be attached to the display panel DP using an adhesive layer.

[0054] An anti-reflective layer RPL can be disposed on the input sensing unit ISP. The anti-reflective layer RPL can be directly fabricated on the input sensing unit ISP during the manufacturing of the display device DD. However, embodiments of the present invention are not limited thereto, and the anti-reflective layer RPL can be fabricated separately and can be attached to the input sensing unit ISP using an adhesive layer.

[0055] An anti-reflective layer (RPL) can be defined as an anti-reflective film against external light. The RPL reduces the reflectivity of external light incident from above the display device (DD) towards the display panel (DP). Due to the RPL, the user cannot perceive external light reflected from the display device (DD).

[0056] When external light traveling toward the display panel DP is reflected back to the user, the user may perceive the display panel DP as a mirror due to the reflected light. To prevent this phenomenon, for example, the anti-reflective layer RPL may include multiple color filters that emit the same color as the light emitted by the pixels arranged in the display panel DP.

[0057] A color filter can filter external light to produce the same color as the light emitted by a pixel. In this case, the external light may be invisible to the user. However, embodiments of the inventive concept are not limited to this, and the anti-reflective layer RPL may include a retarder and / or a polarizer to reduce the reflectivity of external light.

[0058] The WIN window can be installed on the anti-reflective layer RPL. The WIN window can protect the display panel DP, input sensor ISP, and anti-reflective layer RPL from external impacts and scratches.

[0059] A panel protective film (PPF) can be applied beneath the display panel (DP). The PPF protects the lower portion of the display panel (DP). The PPF can comprise flexible plastic materials such as polyethylene terephthalate (PET).

[0060] The first adhesive layer AL1 can be disposed between the display panel DP and the panel protective film PPF, and the display panel DP and the panel protective film PPF can be bonded to each other through the first adhesive layer AL1. The second adhesive layer AL2 can be disposed between the window WIN and the anti-reflective layer RPL, and the window WIN and the anti-reflective layer RPL can be bonded to each other through the second adhesive layer AL2.

[0061] Figure 4 It shows Figure 3 The image shows a cross-section of the display panel.

[0062] refer to Figure 4 The display panel DP may include a substrate SUB, a circuit element layer DP-CL disposed on the substrate SUB, a display element layer DP-OLED disposed on the circuit element layer DP-CL, and a thin film encapsulation layer TFE disposed on the display element layer DP-OLED.

[0063] The substrate SUB may include a display area DA and a non-display area NDA surrounding the display area DA. The substrate SUB may include glass or a flexible plastic material such as polyimide (PI). The display element layer DP-OLED may be located within the display area DA.

[0064] Multiple pixels can be disposed in the circuit element layer DP-CL and the display element layer DP-OLED. Each pixel may include a transistor disposed in the circuit element layer DP-CL and a light-emitting element disposed in the display element layer DP-OLED and connected to the transistor.

[0065] A thin-film encapsulation layer (TFE) can be applied to the DP-CL circuit element layer to cover the DP-OLED display element layer. The TFE protects the pixels from moisture, oxygen, and external contaminants.

[0066] Figure 5 This is a block diagram of a display device according to an embodiment of the present invention.

[0067] refer to Figure 5 The display device DD may include a display panel DP, a timing controller TC, a data driver DDV, a scan driver SDV, a transmit driver EDV, and a voltage generator VG.

[0068] The display panel DP may include multiple scan lines GIL1 to GILn, GCL1 to GCLn, GWL1 to GWLn and GBL1 to GBLn, multiple emission lines EML1 to EMLn, multiple data lines DL1 to DLm, and multiple pixels PX. In this document, n and m can represent natural numbers greater than 0.

[0069] The planar area of ​​the display panel DP may include the display area DA and the non-display area NDA surrounding the display area DA. Pixels PX may be disposed in the display area DA. Pixels PX may be electrically connected to scan lines GIL1 to GILn, GCL1 to GCLn, GWL1 to GWLn and GBL1 to GBLn, emitter lines EML1 to EMLn and data lines DL1 to DLm.

[0070] Each pixel PX can be electrically connected to four corresponding scan lines and one corresponding emitter line. For example, a pixel PX in the j-th row can be connected to the j-th scan lines GILj, GCLj, GWLj, and GBLj, and the j-th emitter line EMLj. In this paper, j can represent a natural number greater than 0 and less than or equal to n.

[0071] Scan lines GIL1 to GILn, GCL1 to GCLn, GWL1 to GWLn, and GBL1 to GBLn may include multiple initialization scan lines GIL1 to GILn, multiple compensation scan lines GCL1 to GCLn, multiple write scan lines GWL1 to GWLn, and multiple bias scan lines GBL1 to GBLn.

[0072] Each pixel PX can be connected to a corresponding one of the initialization scan lines GIL1 to GILn, a corresponding one of the compensation scan lines GCL1 to GCLn, a corresponding one of the write scan lines GWL1 to GWLn, and a corresponding one of the bias scan lines GBL1 to GBLn.

[0073] The scan driver SDV can be positioned on the first side of the display panel DP. Scan lines GIL1 to GILn, GCL1 to GCLn, GWL1 to GWLn, and GBL1 to GBLn can extend from the scan driver SDV in the second direction DR2.

[0074] The transmitter driver EDV can be located on the second side of the display panel DP. Transmit lines EML1 to EMLn can extend from the transmitter driver EDV in a direction opposite to the second direction DR2. The first and second sides of the display panel DP can be opposite sides of the display panel DP in the second direction DR2.

[0075] exist Figure 5 In the embodiments shown, the scan driver SDV and the transmit driver EDV may be located on opposite sides, with the pixel PX between the scan driver SDV and the transmit driver EDV; however, embodiments of the inventive concept are not limited to this. For example, the scan driver SDV and the transmit driver EDV may be located on the same side (e.g., on the first or second side of the display panel DP). For example, the scan driver SDV and the transmit driver EDV may be implemented as a single circuit.

[0076] Scan lines GIL1 to GILn, GCL1 to GCLn, GWL1 to GWLn, and GBL1 to GBLn, as well as transmit lines EML1 to EMLn, can be arranged on the first direction DR1. Data lines DL1 to DLm can extend from the data driver DDV in the opposite direction to the first direction DR1 and can be arranged on the second direction DR2.

[0077] The timing controller TC can be derived from Figure 1 The processor 12 shown receives an input image signal RGB and an input control signal CTRL. The timing controller TC can convert the data format of the input image signal RGB to conform to the interface specification of the data driver DDV, and can generate an image data signal DS. The timing controller TC can output a scan control signal SCS, a data control signal DCS, and a transmit control signal ECS in response to the input control signal CTRL.

[0078] The data driver DDV receives data control signals DCS and image data signals DS from the timing controller TC. The data driver DDV converts the image data signal DS into a data signal and can output the data signal. The data signal can be defined as an analog voltage corresponding to the grayscale level of the image data signal DS. The data signal can be applied to pixel PX through data lines DL1 to DLm.

[0079] The voltage generator VG generates the voltages required for the operation of the display panel DP. The voltage generator VG generates a first drive voltage ELVDD, a second drive voltage ELVSS, a first initialization voltage VINT, and a second initialization voltage AINT. These voltages can be applied to pixels PX.

[0080] The scan driver SDV can receive scan control signals SCS from the timing controller TC. In response to the scan control signals SCS, the scan driver SDV can output scan signals to scan lines GIL1 to GILn, GCL1 to GCLn, GWL1 to GWLn, and GBL1 to GBLn. The scan signals can be applied to pixels PX through scan lines GIL1 to GILn, GCL1 to GCLn, GWL1 to GWLn, and GBL1 to GBLn.

[0081] The transmit driver EDV can receive the transmit control signal ECS from the timing controller TC. In response to the transmit control signal ECS, the transmit driver EDV can output a transmit signal to transmit lines EML1 to EMLn. The transmit signal can be applied to pixel PX through transmit lines EML1 to EMLn.

[0082] A pixel PX can receive data voltage in response to a scan signal. A pixel PX can display an image by emitting light with a brightness corresponding to the data voltage in response to a transmit signal.

[0083] Figure 6 It shows Figure 5 The equivalent circuit of a pixel among the multiple pixels shown in the figure.

[0084] For example, Figure 6 The pixel PXij is shown, which is connected to the i-th data line DLi, the j-th scan lines GWLj, GCLj, GILj, and GBLj, and the j-th emission line EMLj. In this paper, i can represent a natural number greater than 0 and less than or equal to m.

[0085] refer to Figure 6 The pixel PXij may include a pixel circuit PC and a light-emitting element OLED connected to the pixel circuit PC. The pixel circuit PC can drive the light-emitting element OLED.

[0086] The pixel circuit PC may include a capacitor CST and multiple transistors T1' to T8'. Transistors T1' to T8' and capacitor CST can control the amount of driving current flowing to the light-emitting element OLED. The light-emitting element OLED can produce light with a predetermined brightness corresponding to the amount of driving current.

[0087] The j-th write scan line GWLj can receive the j-th write scan signal GWj, and the j-th compensation scan line GCLj can receive the j-th compensation scan signal GCj. The j-th initialization scan line GILj can receive the j-th initialization scan signal GIj, and the j-th bias scan line GBLj can receive the j-th bias scan signal GBj. The j-th transmit line EMLj can receive the j-th transmit signal EMj.

[0088] Pixel PXij can be connected to the i-th data line DLi, the j-th write scan line GWLj, the j-th compensation scan line GCLj, the j-th initialization scan line GILj, the j-th bias scan line GBLj, the j-th emit line EMLj, the first initialization line VIL1, the second initialization line VIL2, the bias line VBL, and the first power line PL1 and the second power line PL2.

[0089] The first initialization line VIL1 can receive the first initialization voltage VINT, and the second initialization line VIL2 can receive the second initialization voltage AINT. The bias line VBL can receive the bias voltage VBIAS. The first power supply line PL1 can receive the first drive voltage ELVDD, and the second power supply line PL2 can receive the second drive voltage ELVSS.

[0090] Each of transistors T1' to T8' may include a source electrode, a drain electrode, and a gate electrode. In the following text, Figure 6 In this diagram, for ease of explanation, either the source electrode or the drain electrode is referred to as the first electrode, and the other of the source electrode and the drain electrode is referred to as the second electrode. Additionally, the gate electrode is referred to as the control electrode.

[0091] Transistors T1' to T8' may include first transistor T1' to eighth transistor T8'. First transistor T1', second transistor T2', and fifth transistor T5' to eighth transistor T8' may include (for example, are) PMOS transistors. Third transistor T3' and fourth transistor T4' may include (for example, are) NMOS transistors.

[0092] The first transistor T1' can be called the driving transistor, and the second transistor T2' can be called the switching transistor. The third transistor T3' can be called the compensation transistor. The fourth transistor T4' and the seventh transistor T7' can be called the initialization transistors. The fifth transistor T5' and the sixth transistor T6' can be called the emitter control transistors. The eighth transistor T8' can be called the bias transistor.

[0093] An OLED (Organic Light Emitting Device) can be referred to as an organic light-emitting device. An OLED can include an anode (AE) and a cathode (CE). The anode (AE) can be connected to a first power line PL1 that receives a first drive voltage ELVDD via a sixth transistor T6', a first transistor T1', and a fifth transistor T5'.

[0094] The cathode CE can be connected to a second power supply line PL2 that receives a second drive voltage ELVSS that has a lower level than the first drive voltage ELVDD.

[0095] The first transistor T1' can be positioned between the fifth transistor T5' and the sixth transistor T6', and can be connected to both the fifth transistor T5' and the sixth transistor T6'. The first transistor T1' can be connected to the first power supply line PL1 via the fifth transistor T5', and can be connected to the anode AE ​​via the sixth transistor T6'.

[0096] The first transistor T1' may include a first electrode connected to the first power line PL1 via the fifth transistor T5', a second electrode connected to the anode AE ​​via the sixth transistor T6', and a control electrode connected to the node ND.

[0097] The first electrode of the first transistor T1' can be connected to the fifth transistor T5', and the second electrode of the first transistor T1' can be connected to the sixth transistor T6'. The first transistor T1' can control the amount of driving current flowing to the light-emitting element OLED according to the voltage applied to the node ND of the control electrode of the first transistor T1'.

[0098] The second transistor T2' can be disposed between the first transistor T1' and the i-th data line DLi, and can be connected to the first transistor T1' and the i-th data line DLi. The second transistor T2' may include a first electrode connected to the i-th data line DLi, a second electrode connected to the first electrode of the first transistor T1', and a control electrode connected to the j-th write scan line GWLj.

[0099] The second transistor T2' can be turned on in response to the j-th write scan signal GWj applied through the j-th write scan line GWLj, and can electrically connect the i-th data line DLi to the first electrode of the first transistor T1'. The second transistor T2' can perform a switching operation to provide the data voltage VD (corresponding to the aforementioned data signal) applied through the i-th data line DLi to the first electrode of the first transistor T1'.

[0100] The third transistor T3' can be connected to the second electrode of the first transistor T1' and node ND. The third transistor T3' may include a first electrode connected to the second electrode of the first transistor T1', a second electrode connected to node ND, and a control electrode connected to the j-th compensation scan line GCLj.

[0101] The third transistor T3' can be turned on in response to the j-th compensation scan signal GCj applied through the j-th compensation scan line GCLj, and the second electrode of the first transistor T1' can be electrically connected to the control electrode of the first transistor T1'. When the third transistor T3' is turned on, the first transistor T1' can be connected in the form of a diode.

[0102] A fourth transistor T4' may be connected to node ND. The fourth transistor T4' may include a first electrode connected to node ND, a second electrode connected to the first initialization line VIL1, and a control electrode connected to the j-th initialization scan line GILj. The fourth transistor T4' may be turned on in response to the j-th initialization scan signal GIj applied through the j-th initialization scan line GILj, and may provide the first initialization voltage VINT applied through the first initialization line VIL1 to node ND.

[0103] The fifth transistor T5' may include a first electrode connected to the first power line PL1, a second electrode connected to the first electrode of the first transistor T1', and a control electrode connected to the j-th emitter line EMLj.

[0104] The sixth transistor T6' may include a first electrode connected to the second electrode of the first transistor T1', a second electrode connected to the anode AE, and a control electrode connected to the j-th emitter line EMLj.

[0105] The fifth transistor T5' and the sixth transistor T6' can be turned on in response to the j-th emission signal EMj applied through the j-th emission line EMLj. The first driving voltage ELVDD can be provided to the light-emitting element OLED through the turned-on fifth transistor T5' and sixth transistor T6', and therefore, driving current can flow to the light-emitting element OLED. Accordingly, the light-emitting element OLED can emit light.

[0106] The seventh transistor T7' may include a first electrode connected to the anode AE, a second electrode connected to the second initialization line VIL2, and a control electrode connected to the j-th bias scan line GBLj. The seventh transistor T7' may be turned on in response to the j-th bias scan signal GBj applied through the j-th bias scan line GBLj, and may provide the second initialization voltage AINT received through the second initialization line VIL2 to the anode AE ​​of the light-emitting element OLED.

[0107] although Figure 6 The pixel PXij includes a seventh transistor T7', but the inventive concept is not limited thereto. For example, the seventh transistor T7' can be omitted. In embodiments of the inventive concept, the second initialization voltage AINT can have a different level than the first initialization voltage VINT, but is not limited thereto, and the second initialization voltage AINT can have the same level as the first initialization voltage VINT.

[0108] The seventh transistor T7' can improve the black level performance of pixel PXij. When the seventh transistor T7' is turned on, the parasitic capacitor (not shown) of the OLED light-emitting element can be discharged. Accordingly, when achieving black brightness, the OLED light-emitting element can emit light without emitting light due to the leakage current of the first transistor T1', thereby improving the black level performance.

[0109] The capacitor CST may include a first electrode connected to the first power line PL1 and a second electrode connected to node ND. When the fifth transistor T5' and the sixth transistor T6' are turned on, the amount of current flowing to the first transistor T1' may depend on the voltage stored in the capacitor CST.

[0110] The eighth transistor T8' may include a first electrode connected to the bias line VBL, a second electrode connected to the first electrode of the first transistor T1', and a control electrode connected to the j-th bias scan line GBLj.

[0111] The eighth transistor T8' can be turned on in response to the j-th bias scan signal GBj, and can provide the bias voltage VBIAS to the first electrode of the first transistor T1'.

[0112] Figure 7 It is used to describe Figure 6 The timing diagram of the scanning and transmitting signals for the operation of the pixels is shown in the figure.

[0113] refer to Figure 6 and Figure 7 The j-th transmit signal EMj can be high during the non-transmit period NLP and low during the transmit period LP. The time period during which each of the j-th write scan signal GWj and the j-th bias scan signal GBj is low can be referred to as the activation period of the corresponding one of the j-th write scan signal GWj and the j-th bias scan signal GBj. The time period during which each of the j-th compensation scan signal GCj and the j-th initialization scan signal GIj is high can be referred to as the activation period of the corresponding one of the j-th compensation scan signal GCj and the j-th initialization scan signal GIj.

[0114] After the j-th initialization scan signal GIj is activated, the j-th compensation scan signal GCj and the j-th write scan signal GWj can be activated. Then, the j-th bias scan signal GBj can be activated.

[0115] During non-emission NLP, the j-th initialization scan signal GIj, the j-th compensation scan signal GCj, the j-th write scan signal GWj, and the j-th bias scan signal GBj, which are in an active state, can be applied to pixel PXij.

[0116] When the j-th initialization scan signal GIj is in the active period, a high-level j-th initialization scan signal GIj can be applied to the fourth transistor T4', and the fourth transistor T4' can be turned on. The first initialization voltage VINT can be provided to node ND through the turned-on fourth transistor T4'. Correspondingly, the first initialization voltage VINT can be applied to the control electrode of the first transistor T1', and the first transistor T1' can be initialized by the first initialization voltage VINT. Such an operation can be referred to as an initialization operation.

[0117] When the j-th write scan signal GWj is in the active period, the j-th write scan signal GWj with a low level can be applied to the second transistor T2', and the second transistor T2' can be turned on. Additionally, when the j-th compensation scan signal GCj is in the active period, the j-th compensation scan signal GCj with a high level can be applied to the third transistor T3', and the third transistor T3' can be turned on.

[0118] When the third transistor T3' is turned on, the first transistor T1' can be connected as a diode. In this case, a compensation voltage (VD-Vth) that reduces the threshold voltage (Vth) of the first transistor T1' from the data voltage VD provided through the i-th data line DLi can be applied to the control electrode of the first transistor T1'. Such an operation can be referred to as a write operation (or programming operation) and a compensation operation.

[0119] A first driving voltage ELVDD and a compensation voltage (VD-Vth) can be applied to the first and second electrodes of capacitor CST, respectively. In capacitor CST, a charge corresponding to the voltage difference between the voltage at the first electrode and the voltage at the second electrode of capacitor CST can be stored.

[0120] Subsequently, when the j-th bias scan signal GBj is in the active period, the j-th bias scan signal GBj with a low level can be applied to the seventh transistor T7' and the eighth transistor T8', and the seventh transistor T7' and the eighth transistor T8' can be turned on. The second initialization voltage AINT can be provided to the anode AE ​​through the turned-on seventh transistor T7', and the voltage of the anode AE ​​can be initialized to the second initialization voltage AINT. The bias voltage VBIAS can be applied to the first electrode of the first transistor T1' through the turned-on eighth transistor T8'.

[0121] Subsequently, during the transmission period LP, a low-level j-th transmission signal EMj can be applied to the fifth transistor T5' and the sixth transistor T6' through the j-th transmission line EMLj, and thus, the fifth transistor T5' and the sixth transistor T6' can be turned on. In this case, a drive current (Id) corresponding to the voltage difference between the first drive voltage ELVDD and the voltage of the control electrode of the first transistor T1' can be generated. The drive current (Id) can be provided to the light-emitting element OLED through the sixth transistor T6', and thus, the light-emitting element OLED can emit light.

[0122] During the emission period LP, the gate-source voltage (Vgs) of the first transistor T1' can be maintained by the capacitor CST, and the gate-source voltage (Vgs) of the first transistor T1' can be expressed as Vgs = ELVDD - (VD - Vth). The relationship between the current and voltage of the first transistor T1' can be defined as Id = (1 / 2)μCox(W / L)(Vgs - Vth). 2 This expression represents the relationship between current and voltage in a typical transistor.

[0123] When Vgs is substituted into the relationship between current and voltage, the threshold voltage (Vth) is eliminated, and the drive current (Id) can be expressed as the square of the value obtained by subtracting the data voltage VD from the first drive voltage ELVDD (i.e., (ELVDD-VD)). 2 The drive current (Id) is proportional to the threshold voltage (Vth) of the first transistor T1'. Accordingly, the drive current (Id) can be determined regardless of the threshold voltage (Vth) of the first transistor T1'. Such an operation can be called threshold voltage compensation operation.

[0124] After the threshold voltage (Vth) of the first transistor T1' is compensated and before the OLED emits light, a bias voltage VBIAS can be applied to the first electrode of the first transistor T1' through the turned-on eighth transistor T8'. The shift in the hysteresis curve of the first transistor T1' can be reduced by the bias voltage VBIAS. Such an operation can be called bias operation.

[0125] Figure 8 Is included Figure 5 A block diagram of the first scan driver in the scan driver is shown.

[0126] refer to Figure 5 and Figure 8 The scan driver SDV may include a first scan driver SDV1. The first scan driver SDV1 may include a plurality of stages ST1 to STn connected sequentially and consecutively. Stages ST1 to STn may include a first stage ST1 to an nth stage STn.

[0127] The stages ST1 to STn of the first scan driver SDV1 can generate and output write scan signals GW1 to GWn. The write scan signals GW1 to GWn can be... Figure 5 The write scan lines GWL1 to GWLn shown are output and can be provided to pixel PX.

[0128] The stages ST1 to STn of the first scan driver SDV1 can receive a first input signal IN1, a first voltage VGH, a second voltage VGL, and multiple first clock signals CK1. The aforementioned scan control signal SCS may include the first input signal IN1 and the first clock signals CK1. The first voltage VGH and the second voltage VGL can be... Figure 5 The voltage is generated in the voltage generator VG shown and can be provided to the first scan driver SDV1. The second voltage VGL can have a lower level than the first voltage VGH.

[0129] The first clock signal CK1 may include clock signal CK1-1 (1-1), clock signal CK1-2 (1-2), clock signal CK1-3 (1-3), and clock signal CK1-4 (1-4). Clock signal CK1-1 (1-1), clock signal CK1-2 (1-2), clock signal CK1-3 (1-3), and clock signal CK1-4 (1-4) may be clock signals that are shifted sequentially.

[0130] Clock signal CK1-1 (1-1) can be applied to level 4h-3. Here, h can represent a natural number greater than 0. Clock signal CK1-2 (1-2) can be applied to level 4h-2. Clock signal CK1-3 (1-3) can be applied to level 4h-1. Clock signal CK1-4 (1-4) can be applied to level 4h.

[0131] For example, clock signal CK1-1 (1-1) can be applied to stage 1 ST1, stage 5 ST5, ..., and stage (n-3) STn-3. Clock signal CK1-2 (1-2) can be applied to stage 2 ST2, stage 6 ST6, ..., and stage (n-2) STn-2. Clock signal CK1-3 (1-3) can be applied to stage 3 ST3, stage 7 ST7, ..., and stage (n-1) STn-1. Clock signal CK1-4 (1-4) can be applied to stage 4 ST4, stage 8 ST8, ..., and stage (n) STn.

[0132] The first input signal IN1 can be applied to the first stage ST1. The (h+1)th stage can receive the write scan signal output from the h-th stage. For example, as... Figure 8As shown, the second stage ST2 can receive the first write scan signal GW1 output from the first stage ST1. In the following text, the write scan signal output from the h-th stage and input to the h+1-th stage, like the first input signal IN1 applied to the first stage ST1, can be referred to as the first input signal.

[0133] The h-th stage can receive the write scan signal output from the h+1-th stage. For example, the first stage ST1 can receive the second write scan signal GW2 output from the second stage ST2.

[0134] The first scan driver SDV1 may further include a dummy stage DST disposed after and connected to the nth stage STn. The dummy stage DST may receive a first-to-first clock signal CK1-1, an nth write scan signal GWn output from the nth stage STn, and a first voltage VGH and a second voltage VGL.

[0135] The first stage ST1 can be activated by the first input signal IN1. The (h+1)th stage can be activated by receiving the write scan signal output from the h-th stage. For example, the second stage ST2 can be activated by receiving the first write scan signal GW1 output from the first stage ST1.

[0136] The activated stages ST1 to STn can generate write scan signals GW1 to GWn using a first clock signal CK1, a first voltage VGH, and a second voltage VGL. The activated stages ST1 to STn can apply the write scan signals GW1 to GWn to the pixel PX. For example, the write scan signals GW1 to GWn output from stages ST1 to STn of the first scan driver SDV1 can be referred to as the first scan signal.

[0137] The dummy level DST can be activated by receiving the nth write scan signal GWn output from the nth level STn. The dummy level DST can generate the dummy write scan signal DGW using the 1-1 clock signal CK1-1, the first voltage VGH, and the second voltage VGL. The dummy write scan signal DGW may not be applied to the pixel PX.

[0138] The h-th stage can receive the write scan signal output from the h+1-th stage, and can use the write scan signal output from the h+1-th stage to initialize the h-th stage (as shown below). Figure 9 (As shown in the diagram) The fourth node N4. For example, the first stage ST1 can receive the second write scan signal GW2 output from the second stage ST2, and can use the second write scan signal GW2 to initialize the fourth node N4 of the first stage ST1. See later... Figure 11C Let's describe the initialization operation of the fourth node N4 in detail.

[0139] The nth stage STn can receive the dummy write scan signal DGW output from the dummy stage DST, and can initialize the fourth node N4 of the nth stage STn.

[0140] Figure 9 It shows Figure 8 The circuit configuration of the first stage of the first scan driver is shown in the figure.

[0141] Although not shown, the second stage ST2 to the nth stage STn and the dummy stage DST can also have the same circuit configuration as the first stage ST1.

[0142] refer to Figure 9 The first stage ST1 of the first scan driver SDV1 can receive the first input signal IN1, the first clock signal CK1-1, the first voltage VGH, the second voltage VGL, and the second write scan signal GW2 through the input terminal IT. The first stage ST1 can output the first write scan signal GW1 through the output terminal OT.

[0143] The first stage ST1 may include a first node controller NCT1, a first inverter INV1, a second inverter INV2, and a first output buffer OBP1. The first inverter INV1 and the second inverter INV2 can invert the phase or voltage level of the input signal and can output the inverted input signal.

[0144] The first inverter INV1 can be connected to the first node controller NCT1. The first inverter INV1 can receive the first voltage VGH and the first-1 clock signal CK1-1. The first inverter INV1 can invert the first-1 clock signal CK1-1 and output the inverted first-1 clock signal CK1-1.

[0145] The first node controller NCT1 can be connected to the first node N1 and the second node N2. The first node controller NCT1 can receive the first input signal IN1, the first voltage VGH, the second voltage VGL, and the first clock signal CK1-1. In addition, the first node controller NCT1 can receive the output signal of the first inverter INV1.

[0146] The first node controller NCT1 can control the voltage level of the first node N1 and the voltage level of the second node N2 in response to the first input signal IN1, the first voltage VGH, the second voltage VGL, the first clock signal CK1-1, and the output signal of the first inverter INV1. The first node controller NCT1 can control the voltage level of the first node N1 and the voltage level of the second node N2 to have different levels from each other.

[0147] The first output buffer OBP1 can be connected to the third node N3 and the fourth node N4. The first output buffer OBP1 can receive a first voltage VGH and a second voltage VGL. The first output buffer OBP1 can output a first write scan signal GW1 in response to the voltage levels of the third node N3 and the fourth node N4.

[0148] The second inverter INV2 can be connected to the third node N3 and the fourth node N4. The second inverter INV2 can receive the first voltage VGH and the second voltage VGL. The second inverter INV2 can invert the voltage level of the fourth node N4 and provide the inverted voltage level to the third node N3.

[0149] The first inverter INV1 can be connected to the second node N2 and the fourth node N4. Accordingly, the second node N2 can be connected to the fourth node N4 through the first inverter INV1. The voltage of the second node N2 can be applied to the fourth node N4 through the first inverter INV1.

[0150] Please refer to later Figure 10A The timing diagram shown in the figure and Figures 11A to 11C The operation states of the first stage ST1 in each time period are shown to describe in detail the specific operations of the first node controller NCT1, the first inverter INV1, the second inverter INV2 and the first output buffer OBP1.

[0151] In the following text, with Figure 6 Similar, in Figure 9 In each of the transistors T1 to T10, RT1 and RT2 shown, either the source electrode or the drain electrode is referred to as the first electrode, and the other of the source electrode and the drain electrode is referred to as the second electrode. Additionally, the gate electrode is defined as the control electrode.

[0152] The first node controller NCT1 may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, and a first capacitor C1. The first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 may include (for example, be) PMOS transistors.

[0153] The first transistor T1 may include a first electrode receiving a first voltage VGH, a second electrode connected to a first node N1, and a control electrode receiving a first input signal IN1. The first transistor T1 may be turned on or off in response to the first input signal IN1.

[0154] The second transistor T2 may include a first electrode connected to the second node N2, a second electrode receiving a second voltage VGL, and a control electrode receiving a first input signal IN1. The second transistor T2 may be turned on or off in response to the first input signal IN1.

[0155] The third transistor T3 may include a first electrode receiving a first voltage VGH, a second electrode connected to a first node N1, and a control electrode receiving a first-1 clock signal CK1-1. The third transistor T3 may be turned on or off in response to the first-1 clock signal CK1-1.

[0156] The fourth transistor T4 may include a first electrode connected to the first node N1, a second electrode receiving a second voltage VGL, and a control electrode connected to the fourth node N4. The fourth transistor T4 can be turned on or off in response to the voltage at the fourth node N4.

[0157] The first capacitor C1 may include a first electrode connected to a first node N1 and a second electrode connected to a second node N2.

[0158] The first inverter INV1 may include a fifth transistor T5 and a sixth transistor T6. The fifth transistor T5 may include (for example, be) a PMOS transistor, and the sixth transistor T6 may include (for example, be) an NMOS transistor.

[0159] The fifth transistor T5 may include a first electrode receiving a first voltage VGH, a second electrode connected to the fourth node N4, and a control electrode receiving a first-1 clock signal CK1-1. The fifth transistor T5 may be turned on or off in response to the first-1 clock signal CK1-1.

[0160] The sixth transistor T6 may include a first electrode connected to the second node N2, a second electrode connected to the fourth node N4, and a control electrode that receives the first-1 clock signal CK1-1. The sixth transistor T6 may be turned on or off in response to the first-1 clock signal CK1-1.

[0161] The second inverter INV2 may include a seventh transistor T7 and an eighth transistor T8. The seventh transistor T7 may include (for example, is) a PMOS transistor, and the eighth transistor T8 may include (for example, is) an NMOS transistor.

[0162] The seventh transistor T7 may include a first electrode receiving a first voltage VGH, a second electrode connected to a third node N3, and a control electrode connected to a fourth node N4. The seventh transistor T7 may be turned on or off in response to the voltage at the fourth node N4.

[0163] The eighth transistor T8 may include a first electrode receiving the second voltage VGL, a second electrode connected to the third node N3, and a control electrode connected to the fourth node N4. The eighth transistor T8 may be turned on or off in response to the voltage at the fourth node N4.

[0164] The first output buffer OBP1 may include a ninth transistor T9 and a tenth transistor T10. The ninth transistor T9 and the tenth transistor T10 may include (for example,) PMOS transistors.

[0165] The ninth transistor T9 may include a first electrode receiving a first voltage VGH, a second electrode connected to an output terminal OT that outputs a first write scan signal GW1, and a control electrode connected to a third node N3. The ninth transistor T9 may be turned on or off in response to the voltage of the third node N3.

[0166] The tenth transistor T10 may include a first electrode connected to the output terminal OT, a second electrode receiving a second voltage VGL, and a control electrode connected to the fourth node N4. The tenth transistor T10 may be turned on or off in response to the voltage at the fourth node N4.

[0167] The first stage ST1 may further include a reset unit RTP connected to the second node N2. The first stage ST1 may further receive a reset signal ESR via an input terminal IT. The reset signal ESR may be applied to the reset unit RTP. For example, the reset signal ESR in... Figure 8 The information in the text is omitted. The reset signal ESR can be a signal that is activated at a low level when the display device DD is powered on or reset.

[0168] The reset unit RTP may include a first reset transistor RT1 and a second reset transistor RT2. The first reset transistor RT1 and the second reset transistor RT2 may include (for example,) PMOS transistors.

[0169] The first reset transistor RT1 may include a first electrode connected to the second node N2, a second electrode receiving a first voltage VGH, and a control electrode receiving a second write scan signal GW2. The first reset transistor RT1 may be turned on or off in response to the second write scan signal GW2. The second write scan signal GW2 applied to the first stage ST1 may be a shift signal of the first write scan signal GW1 and may be referred to as the first reset signal.

[0170] The second reset transistor RT2 may include a first electrode connected to the second node N2, a second electrode receiving a first voltage VGH, and a control electrode receiving a reset signal ESR. The second reset transistor RT2 may be turned on or off in response to the reset signal ESR. When the second write scan signal GW2 is referred to as the first reset signal, the reset signal ESR may be referred to as the second reset signal.

[0171] Figure 10A Is applied to Figure 8 The timing diagram of the signals of the first stage and the second stage of the first scan driver is shown in the figure. Figure 10B Is applied to Figure 8 The timing diagram of the signals of the third and fourth stages of the first scan driver is shown in the figure.

[0172] exist Figure 10A and Figure 10B In the brackets [], the numbers written in parentheses indicate the order of the levels.

[0173] refer to Figure 10A and Figure 10B The first-1 clock signal CK1-1, the first-2 clock signal CK1-2, the first-3 clock signal CK1-3, and the first-4 clock signal CK1-4 can be clock signals that are shifted sequentially.

[0174] For example, in Figure 10B In order to compare the timing of clock signals CK1-3 and CK1-4 with the timing of clock signals CK1-1 and CK1-2, a pulse of each of clock signals CK1-1 and CK1-2 is plotted as a dashed line at the time point preceding any pulse of the corresponding one of clock signals CK1-3 and CK1-4.

[0175] The low level L can be a level lower than the high level H. The first voltage VGH can be defined as a voltage with a high level H, and the second voltage VGL can be defined as a voltage with a low level L. When the first write scan signal GW1 to the fourth write scan signal GW4 are activated, the first write scan signal GW1 to the fourth write scan signal GW4 can have a low level L (the low level L can correspond to the voltage level of the second voltage VGL).

[0176] When the high-level H clock signal CK1-1 is applied to the first stage ST1, which is activated in response to the low-level L first input signal IN1, the first write scan signal GW1 with the second voltage VGL can be output.

[0177] When the high-level H first-second clock signal CK1-2 is applied to the second stage ST2, which is activated in response to the low-level L first write scan signal GW1, a second write scan signal GW2 with a second voltage VGL can be output.

[0178] When the high-level H clock signal CK1-3 is applied to the third stage ST3, which is activated in response to the low-level L second write scan signal GW2, a third write scan signal GW3 with a second voltage VGL can be output.

[0179] When the high-level H clock signals CK1-4 are applied to the fourth stage ST4, which is activated in response to the low-level L third write scan signal GW3, the fourth write scan signal GW4 with the second voltage VGL can be output.

[0180] Since the operations of levels ST1 through STn are essentially the same, reference will be made below. Figure 10A The timing diagram shown in the figure refers to the signal applied to the first stage ST1 to describe the operation of the first stage ST1.

[0181] Figure 11A , Figure 11B and Figure 11C The first stage of the first scan driver is shown. Figure 10A The operation of the first, second, and third time periods is shown in the figure.

[0182] In the following text, Figures 11A to 11C In the diagram, transistors that are off are indicated by slashes.

[0183] refer to Figure 10A and Figure 11A During the first time period t1, a first input signal IN1 with a low level L can be applied to the first stage ST1. The first transistor T1 and the second transistor T2 can be turned on in response to the first input signal IN1 with a low level L.

[0184] During the first time period t1, a low-level clock signal CK1-1 can be applied to the third transistor T3, the fifth transistor T5, and the sixth transistor T6. The third transistor T3 and the fifth transistor T5 can be turned on in response to the low-level clock signal CK1-1, and the sixth transistor T6 can be turned off in response to the low-level clock signal CK1-1.

[0185] A first voltage VGH can be applied to the first node N1 through a conducting first transistor T1 and a conducting third transistor T3, and therefore, the first node N1 can be set to the first voltage VGH. A second voltage VGL can be applied to the second node N2 through a conducting second transistor T2, and therefore, the second node N2 can be set to the second voltage VGL. A first capacitor C1 connected between the first node N1 and the second node N2 can store a charge corresponding to the voltage difference between the first voltage VGH and the second voltage VGL.

[0186] A first voltage VGH can be applied to the fourth node N4 through the conducting fifth transistor T5, and therefore, the fourth node N4 can be set to the first voltage VGH. Since the fourth node N4 has the first voltage VGH, the first voltage VGH of the fourth node N4 can be applied to the fourth transistor T4, and the fourth transistor T4 can be turned off.

[0187] Through the above operations, during the first time period t1, the first inverter INV1 can output a first voltage VGH in response to the first-1 clock signal CK1-1. The first inverter INV1 can invert the first-1 clock signal CK1-1, which has a low level L, and can output a first voltage VGH, which has a high level H. The first inverter INV1 can provide the first voltage VGH to the first node controller NCT1 and the fourth node N4.

[0188] Furthermore, when the first inverter INV1 outputs the first voltage VGH in response to the first clock signal CK1-1, the first node controller NCT1 can set the voltage of the first node N1 to the first voltage VGH and the voltage of the second node N2 to the second voltage VGL in response to the first input signal IN1. In other words, the first node controller NCT1 can control the voltage levels of the first node N1 and the second node N2 to have different levels from each other.

[0189] A first voltage VGH at node N4 can be applied to the seventh transistor T7 and the eighth transistor T8. In response to the first voltage VGH at node N4, the seventh transistor T7 can be turned off and the eighth transistor T8 can be turned on. A second voltage VGL can be applied to node N3 through the turned-on eighth transistor T8, and therefore, node N3 can be set to the second voltage VGL.

[0190] Through the above operations, the second inverter INV2 can invert the first voltage VGH, which has a high level H, and output a second voltage VGL, which has a low level L. The second inverter INV2 can then provide the second voltage VGL to the third node N3.

[0191] The second voltage VGL of the third node N3 can be applied to the ninth transistor T9, and the first voltage VGH of the fourth node N4 can be applied to the tenth transistor T10. The ninth transistor T9 can be turned on in response to the second voltage VGL of the third node N3, and the tenth transistor T10 can be turned off in response to the first voltage VGH of the fourth node N4. The first voltage VGH can be provided to the output terminal OT through the turned-on ninth transistor T9. Accordingly, a first write scan signal GW1 with a high level H can be output through the output terminal OT.

[0192] Through the above operations, the first output buffer OBP1 can output a first write scan signal GW1 with a high level H in response to the voltage of the third node N3 and the fourth node N4.

[0193] refer to Figure 10A and Figure 11B In the second time period t2 following the first time period t1, the first input signal IN1 with a high level H and the first clock signal CK1-1 with a high level H can be applied to the first stage ST1.

[0194] The first transistor T1 and the second transistor T2 can be turned off in response to the first input signal IN1 having a high level H. In response to the first clock signal CK1-1 having a high level H, the third transistor T3 and the fifth transistor T5 can be turned off and the sixth transistor T6 can be turned on.

[0195] The second voltage VGL of the second node N2 can be applied to the fourth transistor T4 through the conducting sixth transistor T6. The fourth transistor T4 can be turned on in response to the second voltage VGL of the second node N2 having a low level L. The second voltage VGL can be applied to the first node N1 through the conducting fourth transistor T4. Accordingly, the first node N1 can be set to the second voltage VGL. The voltage of the first node N1 can be changed from the first voltage VGH having a high level H to the second voltage VGL having a low level L.

[0196] When the voltage level of the first node N1 changes from high level H to low level L, the voltage of the second node N2 can be changed from the second voltage VGL to a third voltage VL1, which has a lower level than the second voltage VGL, through the coupling operation of the first capacitor C1. In other words, the voltage of the second node N2 can be changed from the second voltage VGL to the third voltage VL1 through the first capacitor C1. Accordingly, the second node N2 can be set to the third voltage VL1.

[0197] For example, the third voltage VL1 can have a low level 2L that is lower than the low level L. The voltage difference ΔV1 between the first voltage VGH and the third voltage VL1 can be twice the voltage difference ΔV2 between the first voltage VGH and the second voltage VGL.

[0198] The third voltage VL1 of the second node N2 can be supplied to the fourth node N4 through the conducting sixth transistor T6. That is, the third voltage VL1 of the second node N2 can be supplied to the fourth node N4 through the first inverter INV1.

[0199] Through the above operations, during the second time period t2, the first inverter INV1 can output the voltage of the second node N2 in response to the first-1 clock signal CK1-1. The first inverter INV1 can provide the voltage of the second node N2 (e.g., the second voltage VGL and the third voltage VL1) to the first node controller NCT1 and the fourth node N4.

[0200] Furthermore, when the first inverter INV1 outputs the second voltage VGL of the second node N2 according to the first clock signal CK1-1, in response to the output signal of the first inverter INV1, the first node controller NCT1 can set the voltage of the first node N1 to the second voltage VGL and can set the voltage of the second node N2 to the third voltage VL1. That is, the first node controller NCT1 can control the voltage level of the first node N1 and the voltage level of the second node N2 to have different levels from each other.

[0201] Accordingly, in the first time period t1 and the second time period t2, in response to the output signals of the first input signal IN1 and the first inverter INV1, the first node controller NCT1 can set the voltage of the first node N1 to the first voltage VGH or the second voltage VGL, and can set the voltage of the second node N2 to the second voltage VGL or the third voltage VL1.

[0202] The third voltage VL1 of the fourth node N4 can be applied to the seventh transistor T7 and the eighth transistor T8. In response to the third voltage VL1 of the fourth node N4, the seventh transistor T7 can be turned on and the eighth transistor T8 can be turned off. The first voltage VGH can be applied to the third node N3 through the turned-on seventh transistor T7, and therefore, the third node N3 can be set to the first voltage VGH.

[0203] The first voltage VGH of the third node N3 can be applied to the ninth transistor T9, and the third voltage VL1 of the fourth node N4 can be applied to the tenth transistor T10. The ninth transistor T9 can be turned off in response to the first voltage VGH of the third node N3, and the tenth transistor T10 can be turned on in response to the third voltage VL1 of the fourth node N4. The second voltage VGL can be provided to the output terminal OT through the turned-on tenth transistor T10. Accordingly, a first write scan signal GW1 with a low level L can be output through the output terminal OT.

[0204] Through the above operations, in the second time period t2, the first output buffer OBP1 can output a first write scan signal GW1 with a low level L in response to the voltage of the third node N3 and the fourth node N4.

[0205] The first reset transistor RT1 and the second reset transistor RT2 can remain off during the first time period t1 and the second time period t2.

[0206] refer to Figure 10A and Figure 11C In the third time period t3 following the second time period t2, the first input signal IN1 with a high level H, the first clock signal CK1-1 with a low level L, and the second write scan signal GW2 with a low level L can be applied to the first stage ST1.

[0207] The first transistor T1 and the second transistor T2 can be turned off in response to the first input signal IN1 having a high level H. In response to the first clock signal CK1-1 having a low level L, the third transistor T3 and the fifth transistor T5 can be turned on, and the sixth transistor T6 can be turned off. The first reset transistor RT1 can be turned on in response to the second write scan signal GW2 having a low level L.

[0208] A first voltage VGH can be applied to the first node N1 through the conducting third transistor T3. The first voltage VGH can be applied to the second node N2 through the conducting first reset transistor RT1. The first voltage VGH can be applied to the fourth node N4 through the conducting fifth transistor T5. The first voltage VGH can be applied to the fourth node N4, and the fourth node N4 can be initialized.

[0209] When the first voltage VGH is applied to the fourth node N4, the first output buffer OBP1 can output the first write scan signal GW1 with a high level H, just like the first time period t1.

[0210] When the display device DD is powered on or reset, a reset signal ESR activated at a low level L can be applied to the first stage ST1. When the reset signal ESR activated at a low level L is applied to the second reset transistor RT2, the same operation as when the second write scan signal GW2 with a low level L is applied to the first reset transistor RT1 can be performed.

[0211] refer to Figure 8 , Figure 9 as well as Figures 11A to 11C In embodiments of the present invention, a single clock signal can be applied to each of stages ST1 to STn, instead of applying two clock signals with opposite phases to each of stages ST1 to STn. For example, one of clock signals CK1-1 (first clock signal), CK1-2 (first clock signal), CK1-3 (first clock signal), and CK1-4 (first clock signal), can be applied to each stage of ST1 to STn. Power consumption can be reduced when a single clock signal is applied to each of stages ST1 to STn instead of using two clock signals.

[0212] Figure 12 It shows the way Figure 9 The charging state of the first write scan signal output from the output terminal is shown in the figure.

[0213] refer to Figure 11B and Figure 12 A voltage with a low level L can be applied to the first output buffer OBP1, and a first write scan signal GW1 with a low level L can be output through the output terminal OT. That is, based on the voltage of the fourth node N4, the first write scan signal GW1 can be set to a target low level L and can be output through the output terminal OT.

[0214] When the fourth node N4 has a second voltage VGL (which has a low level L), as shown by the dashed line, the level of the first write scan signal GW1 may charge slowly and insufficiently to the low level L. However, according to an embodiment of the present invention, since the fourth node N4 has a third voltage VL1 (which has a low level 2L lower than the low level L), as shown by the solid line, the level of the first write scan signal GW1 can charge quickly and sufficiently to the low level L.

[0215] In an embodiment of the present invention, the first write scan signal GW1 can be rapidly and sufficiently charged to a target level (e.g., a low level) using a third voltage VL1 of the fourth node N4, which is lower than the second voltage VGL. Accordingly, a number of write scan signals with sufficiently low levels can be provided to the pixel PX.

[0216] Figure 13 The circuit configuration of the first stage of the first scan driver according to an embodiment of the present invention is shown.

[0217] In the following text, Figure 13 The components of the first stage ST1-1 shown in the figure will be concentrated with Figure 9 The components shown are described as different parts.

[0218] refer to Figure 13 The first-level ST1-1 may further include a second node controller NCT2. The second node controller NCT2 may be connected to the first node controller NCT1 and the fourth node N4.

[0219] The second node controller NCT2 can be connected to the fifth node N5 and the sixth node N6. The second electrode of the fourth transistor T4 can be connected to the fifth node N5. The second node controller NCT2 can be connected to the first node controller NCT1 through the fifth node N5. The second node controller NCT2 can receive the first input signal IN1, the first voltage VGH, the second voltage VGL, and the first clock signal CK1-1.

[0220] The second node controller NCT2 can control the voltage levels of the fifth node N5 and the sixth node N6 in response to the first input signal IN1, the first voltage VGH, the second voltage VGL, the first clock signal CK1-1, and the voltage of the fourth node N4. The second node controller NCT2 can control the voltage levels of the fifth node N5 and the sixth node N6 to have different levels from each other.

[0221] The second node controller NCT2 may include an eleventh transistor T11, a twelfth transistor T12, a thirteenth transistor T13, and a second capacitor C2. The eleventh transistor T11, the twelfth transistor T12, and the thirteenth transistor T13 may include (for example, be) PMOS transistors.

[0222] The eleventh transistor T11 may include a first electrode connected to the fifth node N5, a second electrode receiving a second voltage VGL, and a control electrode receiving a first input signal IN1. The eleventh transistor T11 may be turned on or off in response to the first input signal IN1.

[0223] The twelfth transistor T12 may include a first electrode connected to the sixth node N6, a second electrode receiving the second voltage VGL, and a control electrode connected to the fourth node N4. The twelfth transistor T12 can be turned on or off in response to the voltage at the fourth node N4.

[0224] The thirteenth transistor T13 may include a first electrode receiving a first voltage VGH, a second electrode connected to the sixth node N6, and a control electrode receiving a first-1 clock signal CK1-1. The thirteenth transistor T13 may be turned on or off in response to the first-1 clock signal CK1-1.

[0225] The second capacitor C2 may include a first electrode connected to the fifth node N5 and a second electrode connected to the sixth node N6.

[0226] Figure 14 Is applied to Figure 13 The timing diagram of the signals of the first stage of the first scan driver is shown in the figure. Figure 15A and Figure 15B The first stage of the first scan driver is shown. Figure 14 The operation of the first and second time periods is shown in the figure.

[0227] Figure 14 The first time period t1, the second time period t2, and the third time period t3 shown can be respectively compared with... Figure 10A The first time period t1, the second time period t2, and the third time period t3 shown correspond to each other. The operation of the second node controller NCT2 will be primarily described below, with a brief description of other components.

[0228] refer to Figure 14 and Figure 15A In the first time period t1, such as Figure 11A As shown, the first node N1 can be set to the first voltage VGH, and the second node N2 can be set to the second voltage VGL.

[0229] During the first time period t1, a first input signal IN1 with a low level L can be applied to the eleventh transistor T11. Additionally, a first-to-one clock signal CK1-1 with a low level L can be applied to the thirteenth transistor T13. The eleventh transistor T11 can be turned on in response to the first input signal IN1 with a low level L, and the thirteenth transistor T13 can be turned on in response to the first-to-one clock signal CK1-1 with a low level L.

[0230] A second voltage VGL with a low level L can be applied to the fifth node N5 through the eleventh transistor T11, which is turned on. A first voltage VGH with a high level H can be applied to the sixth node N6 through the thirteenth transistor T13, which is turned on. Accordingly, the fifth node N5 can be set to the second voltage VGL, and the sixth node N6 can be set to the first voltage VGH.

[0231] The second node controller NCT2 can set the voltage of the fifth node N5 to the second voltage VGL and the voltage of the sixth node N6 to the first voltage VGH in response to the first input signal IN1 and the first clock signal CK1-1. The charge corresponding to the voltage difference between the first voltage VGH and the second voltage VGL can be stored in the second capacitor C2.

[0232] The first voltage VGH of the fourth node N4 can be applied to the twelfth transistor T12. The twelfth transistor T12 can be turned off in response to the first voltage VGH of the fourth node N4.

[0233] refer to Figure 14 and Figure 15B During the second time period t2, the second voltage VGL of the second node N2 can be output through the first inverter INV1 and applied to the fourth transistor T4 and the twelfth transistor T12. The fourth transistor T4 and the twelfth transistor T12 can be turned on in response to the second voltage VGL of the second node N2 having a low level L.

[0234] The second voltage VGL at the fifth node N5 can be supplied to the first node N1 through the conducting fourth transistor T4. Accordingly, as... Figure 11B As shown, the voltage of the first node N1 can be changed from a first voltage VGH with a high level H to a second voltage VGL with a low level L, and the voltage of the second node N2 can be changed from a first capacitor C1 to a third voltage VL1 with a low level 2L.

[0235] The second voltage VGL can be applied to the sixth node N6 through the turned-on twelfth transistor T12. Accordingly, the voltage at the sixth node N6 can be switched from the first voltage VGH with a high level H to the second voltage VGL with a low level L.

[0236] When the voltage level of the sixth node N6 changes from high level H to low level L, the voltage of the fifth node N5 can be changed from the second voltage VGL to the third voltage VL1 with a low level 2L through the coupling operation of the second capacitor C2. The voltage of the fifth node N5 can be changed from the second voltage VGL to the third voltage VL1 through the second capacitor C2.

[0237] The third voltage VL1 of the fifth node N5 can be applied to the first node N1. Accordingly, the voltage of the first node N1 can be converted from the second voltage VGL to the third voltage VL1 with a low level 2L.

[0238] When the voltage of the first node N1 changes from low level L to low level 2L, the voltage of the second node N2 can change from the third voltage VL1 to the fourth voltage VL2 through the coupling operation of the first capacitor C1. The fourth voltage VL2 can have a low level 3L. Accordingly, the first node N1 can be set to the third voltage VL1, and the second node N2 can be set to the fourth voltage VL2.

[0239] Through the above operations, when the second node controller NCT2 provides the third voltage VL1 to the first node N1, the first node controller NCT1 can set the voltage of the first node N1 to the third voltage VL1, and can set the voltage of the second node N2 to the fourth voltage VL2.

[0240] The voltage difference ΔV3 between the first voltage VGH and the fourth voltage VL2 can be three times the voltage difference ΔV2 between the first voltage VGH and the second voltage VGL.

[0241] The fourth voltage VL2 of the second node N2 can be supplied to the fourth node N4 through the first inverter INV1. Since the fourth node N4 has a low level 3L, the first write scan signal GW1 can be charged to the low level L more quickly and can be output through the output terminal OT.

[0242] Due to the operation and reference of the first level ST1-1 in the third time period t3. Figure 11C The operation of the first-level ST1 described is the same in the third time period t3, so its description is omitted.

[0243] Figure 16 Is included Figure 5 A block diagram of the second scan driver in the scan driver is shown.

[0244] refer to Figure 5 and Figure 16 The scan driver SDV may further include a second scan driver SDV2. The second scan driver SDV2 may include a plurality of stages ST1' to STn' connected sequentially and consecutively. Stages ST1' to STn' may include a first stage ST1' to an nth stage STn'.

[0245] Stages ST1' to STn' can generate and output bias scan signals GB1 to GBn. The bias scan signals GB1 to GBn can be... Figure 5 The bias scan lines GBL1 to GBLn shown are output and can be provided to pixel PX.

[0246] Stages ST1' to STn' can receive a second input signal IN2, a first voltage VGH, a second voltage VGL, and multiple second clock signals CK2. The aforementioned scan control signal SCS may include the second input signal IN2 and the second clock signals CK2.

[0247] The second clock signal CK2 may include the second-1st clock signal CK2-1, the second-2nd clock signal CK2-2, the second-3rd clock signal CK2-3, and the second-4th clock signal CK2-4. The second-1st clock signal CK2-1, the second-2nd clock signal CK2-2, the second-3rd clock signal CK2-3, and the second-4th clock signal CK2-4 may be clock signals that are shifted sequentially.

[0248] Clock signal CK2-1 (2-1) can be applied to level 4h-3. Clock signal CK2-2 (2-2) can be applied to level 4h-2. Clock signal CK2-3 (2-3) can be applied to level 4h-1. Clock signal CK2-4 (2-4) can be applied to level 4h.

[0249] The second input signal IN2 can be applied to the first stage ST1'. The (h+1)th stage can receive the bias scan signal output from the h-th stage. Like the second input signal IN2, the bias scan signal output from the h-th stage and provided to the (h+1)th stage can be referred to as the second input signal.

[0250] The first stage ST1' can be activated by the second input signal IN2. The (h+1)th stage can be activated by receiving the bias scan signal output from the h-th stage.

[0251] The activated stages ST1' to STn' can generate bias scan signals GB1 to GBn using a second clock signal CK2, a first voltage VGH, and a second voltage VGL. The bias scan signals GB1 to GBn can be applied to pixel PX. For example, the bias scan signals GB1 to GBn output from stages ST1' to STn' of the second scan driver SDV2 can be referred to as the second scan signals.

[0252] Figure 17 It shows Figure 16 The circuit configuration of the first stage of the second scan driver is shown in the figure.

[0253] Although not shown, the second stage ST2' to the nth stage STn' can have the same circuit configuration as the first stage ST1'.

[0254] refer to Figure 17The first stage ST1' can receive the second input signal IN2, the second-to-first clock signal CK2-1, the first voltage VGH, and the second voltage VGL through the input terminal IT'. The first stage ST1' can output the first bias scan signal GB1 through the output terminal OT'.

[0255] The first stage ST1' may include the first-1 node controller NCT1-1, the first-1 inverter INV1-1, the second-1 inverter INV2-1, and the second output buffer OBP2.

[0256] Inverter INV1-1 (1-1) can receive a first voltage VGH and can be connected to input node IND, node N2-1 (2-1), and node N4-1 (4-1). Inverter INV1-1 can be connected to controller NCT1-1 (1-1) via input node IND and node N2-1. Inverter INV1-1 can invert the second input signal IN2 provided by input node IND and output the inverted second input signal IN2.

[0257] Node 2-1 N2-1 can be connected to node 4-1 N4-1 via inverter INV1-1. Accordingly, similar to the first stage ST1 of the first scan driver SDV1, the voltage of node 2-1 N2-1 can be supplied to node 4-1 N4-1 via inverter INV1-1.

[0258] Node 1-1 controller NCT1-1 can be connected to input node IND, node 1-1 N1-1, and node 2-1 N2-1. Node 1-1 controller NCT1-1 can receive a second input signal IN2, a first voltage VGH, a second voltage VGL, and a second clock signal CK2-1. Node 1-1 controller NCT1-1 can provide the second input signal IN2 to input node IND in response to the second clock signal CK2-1.

[0259] The first-1 node controller NCT1-1 can control the voltage levels of the first-1 node N1-1 and the second-1 node N2-1 to have different levels in response to the second input signal IN2, the first voltage VGH, the second voltage VGL, the second-1 clock signal CK2-1, and the output signal of the first-1 inverter INV1-1.

[0260] The second output buffer OBP2 can be connected to nodes 3-1 N3-1 and 4-1 N4-1, and can receive a first voltage VGH and a second voltage VGL. The second output buffer OBP2 can output a first bias scan signal GB1 in response to the voltage levels of nodes 3-1 N3-1 and 4-1 N4-1.

[0261] Inverter INV2-1 (2-1) can be connected to nodes N3-1 (3-1) and N4-1 (4-1), and can receive a first voltage VGH and a second voltage VGL. Inverter INV2-1 can invert the voltage level of node N4-1 (4-1) and provide the inverted voltage level to node N3-1 (3-1).

[0262] The first-1 node controller NCT1-1 may include a first-1 transistor T1-1, a second-1 transistor T2-1, a third-1 transistor T3-1, a fourth-1 transistor T4-1, and a first-1 capacitor C1-1. The first-1 transistor T1-1, the second-1 transistor T2-1, the third-1 transistor T3-1, and the fourth-1 transistor T4-1 may include (for example, be) PMOS transistors.

[0263] Transistor T1-1 (1-1) may include a first electrode receiving the second input signal IN2, a second electrode connected to the input node IND, and a control electrode receiving the second clock signal CK2-1. Transistor T2-1 (2-1) may include a first electrode receiving the first voltage VGH, a second electrode connected to the first node N1-1, and a control electrode connected to the input node IND.

[0264] Transistor T3-1 (3-1) may include a first electrode connected to node N2-1 (2-1), a second electrode receiving a second voltage VGL, and a control electrode receiving a clock signal CK2-1 (2-1). Transistor T4-1 (4-1) may include a first electrode connected to node N1-1 (1-1), a second electrode receiving a second voltage VGL, and a control electrode connected to node N4-1 (4-1). Capacitor C1-1 (1-1) may include a first electrode connected to node N1-1 (1-1) and a second electrode connected to node N2-1 (2-1).

[0265] Inverter INV1-1 (1-1) may include transistor T5-1 (5-1), which is a PMOS transistor, and transistor T6-1 (6-1), which is an NMOS transistor. Transistor T5-1 (5-1) may include a first electrode receiving a first voltage VGH, a second electrode connected to node N4-1 (4-1), and a control electrode connected to the input node IND. Transistor T6-1 (6-1) may include a first electrode connected to node N2-1 (2-1), a second electrode connected to node N4-1 (4-1), and a control electrode connected to the input node IND.

[0266] Inverter INV2-1 (2-1) may include transistor T7-1 (7-1) and transistor T8-1 (8-1). The second output buffer OBP2 may include transistor T9-1 (9-1) and transistor T10-1 (10-1).

[0267] Due to the configuration of the first stage ST1' of the second scan driver SDV2, the inverter INV2-1 and the second output buffer OBP2 are... Figure 9 The configurations of the aforementioned second inverter INV2 and first output buffer OBP1 of the first stage ST1 of the first scan driver SDV1 shown are substantially the same, therefore the description of the configuration of the transistors in the second-1 inverter INV2-1 and the second output buffer OBP2 is omitted.

[0268] Figure 18 Is applied to Figure 16 The timing diagram of the signals of the first and second stages of the second scan driver is shown in the figure. Figure 19A and Figure 19B The first stage of the second scan driver is shown. Figure 18 The operation of the first and second time periods is shown in the figure.

[0269] refer to Figure 18 The second-second clock signal CK2-2 can be a shifted signal of the second-first clock signal CK2-1. Although not shown, similar to the first-third clock signal CK1-3 and the first-fourth clock signal CK1-4 mentioned above, the second-third clock signal CK2-3 can be a shifted signal of the second-second clock signal CK2-2, and the second-fourth clock signal CK2-4 can be a shifted signal of the second-third clock signal CK2-3.

[0270] The second clock signal CK2 can be a signal with a phase opposite to that of the first clock signal CK1. For example, the second-to-first clock signal CK2-1 can be... Figure 10A The first-1 clock signal CK1-1 shown is the phase-inverted signal. Additionally, the second-2 clock signal CK2-2 can be... Figure 10AThe phase-inverted signal of the first-second clock signal CK1-2 is shown in the figure.

[0271] Although not shown, the second-to-third clock signal CK2-3 could be... Figure 10B The first-to-third clock signal CK1-3 shown is the phase-inverted signal of the second-to-fourth clock signal CK2-4. Figure 10B The phase-inverted signals of clock signals CK1-4 shown in the figure are the first to fourth clock signals.

[0272] The consecutive first time period t1', second time period t2', and third time period t3' can be defined. Each of the first time period t1', second time period t2', and third time period t3' can be defined as one cycle of the 2-1 clock signal CK2-1, which changes from low level L to high level H.

[0273] refer to Figure 18 and Figure 19A During the first time period t1', when the second-first clock signal CK2-1 has a low level L, the first-first transistor T1-1 can be turned on. The second input signal IN2 with a low level L can be provided to the input node IND through the turned-on first-first transistor T1-1.

[0274] A signal with a low level L at input node IND can be applied to transistor T2-1, and transistor T2-1 can be turned on. A first voltage VGH can be applied to node N1-1 through the turned-on transistor T2-1. When the second-order clock signal CK2-1 has a low level L, transistor T3-1 can be turned on. A second voltage VGL can be applied to node N2-1 through the turned-on transistor T3-1.

[0275] Accordingly, during the first time period t1', the controller NCT1-1 of node 1-1 can set the voltage of node 1-1 N1-1 to the first voltage VGH, and can set the voltage of node 2-1 N2-1 to the second voltage VGL.

[0276] A low-level L signal at input node IND can be applied to transistors 5-1 T5-1 and 6-1 T6-1, causing transistor 5-1 T5-1 to be turned on and transistor 6-1 T6-1 to be turned off. Accordingly, a first voltage VGH can be applied to node 4-1 N4-1.

[0277] Reference Figure 11A The operation is similar, and when node 4-1 N4-1 is set to the first voltage VGH, the first bias scan signal GB1 with a high level H can be output through the output terminal OT'.

[0278] refer to Figure 18 and Figure 19B During the second time period t2', when the second-first clock signal CK2-1 has a low level L, the second input signal IN2 can have a high level H. The first-first transistor T1-1 can be turned on, and the second input signal IN2 with a high level H can be provided to the input node IND through the turned-on first-first transistor T1-1.

[0279] A high-level signal H at input node IND can be applied to transistors 5-1 T5-1 and 6-1 T6-1, causing transistor 5-1 T5-1 to be turned off and transistor 6-1 T6-1 to be turned on. Correspondingly, the second voltage VGL of node 2-1 N2-1 can be applied to transistor 4-1 T4-1.

[0280] Transistor T4-1 (4-1) can be turned on in response to a second voltage VGL having a low level L at node N2-1 (2-1). The second voltage VGL can be applied to node N1-1 (1-1) through the turned-on transistor T4-1. Accordingly, with reference... Figure 11B The operations described are similar; the voltage of node 1-1 N1-1 can be converted from a first voltage VGH to a second voltage VGL, and the voltage of node 2-1 N2-1 can be converted from the second voltage VGL to a third voltage VL1. Therefore, the voltage of node 1-1 N1-1 can have a low level L, and the voltage of node 2-1 N2-1 can have a low level 2L.

[0281] The third voltage VL1 at node 2-1 N2-1 can be supplied to node 4-1 N4-1 via inverter INV1-1 at node 1-1. Correspondingly, with reference... Figure 11B The operation is similar, with the first bias scan signal GB1 having a low level L being output through the output terminal OT'.

[0282] The level of the first bias scan signal GB1 output from the output terminal OT' can be rapidly charged to the target level (e.g., low level L) by a third voltage VL1 with a low level 2L at node 2-1 N2-1. Therefore, a larger number of bias scan signals with sufficiently low levels can be provided to pixel PX.

[0283] The operation of the first-level ST1' in the third time period t3' can be basically the same as the operation of the first-level ST1' in the first time period t1'.

[0284] Although not shown, the scan driver SDV may further include a third scan driver that generates an initial scan signal and a fourth scan driver that generates a compensation scan signal.

[0285] Figure 20 It is a timing diagram of the signals applied to the first and second stages of the third scan driver. Figure 21A The first stage of the third scan driver is shown. Figure 20 The operation during the second time period is shown in the figure. Figure 21B The first stage of the third scan driver is shown. Figure 20 The operation during the first time period is shown in the figure.

[0286] refer to Figure 20 The second input signal IN2' provided to the third scan driver can have Figure 18 The diagram shows the inverted level of the second input signal IN2 provided to the second scan driver SDV2. The timing of other signals can be compared with... Figure 18 The timing shown is basically the same.

[0287] exist Figure 18 In the second time period t2' shown, when the second-to-first clock signal CK2-1 has a low level L, the second input signal IN2 can have a high level H. However, in Figure 20 In the second time period t2'' shown, when the second-1 clock signal CK2-1 has a low level L, the second input signal IN2' can have a low level L.

[0288] refer to Figure 21A and Figure 21B The circuit configuration of the first stage ST1'' of the third scan driver SDV3 can be compared with... Figure 17 The circuit configuration of the first stage ST1' of the second scan driver SDV2 shown in the figure is basically the same.

[0289] refer to Figure 20 and Figure 21A During the second time period t2'', when the second-1 clock signal CK2-1 has a low level L, the second input signal IN2' can also have a low level L. Accordingly, the operation of the first stage ST1'' of the third scan driver SDV3 can be substantially the same as the operation of the first stage ST1' of the second scan driver SDV2 during the aforementioned first time period t1'.

[0290] refer to Figure 20 and Figure 21BDuring the first time period t1'', ​​when the second-to-first clock signal CK2-1 has a low level L, the second input signal IN2' can have a high level H. Accordingly, the operation of the first stage ST1'' of the third scan driver SDV3 can be substantially the same as the operation of the first stage ST1'' of the second scan driver SDV2 during the aforementioned second time period t2'. The operation of the first stage ST1'' in the third time period t3'' can be substantially the same as the operation of the first stage ST1'' in the first time period t1''.

[0291] refer to Figure 20 , Figure 21A and Figure 21B During the second time period t2'', the first stage ST1'' of the third scan driver SDV3 can output the first initialization scan signal GI1 with a high level H.

[0292] Although not shown, the fourth scan driver may also have a circuit configuration substantially the same as that of the second scan driver SDV2. Furthermore, the operating timing of the fourth scan driver may be similar to... Figure 20 The timing shown is essentially the same. Except that the high-level output timing of each of the compensation scan signals differs from the high-level output timing of each of the initialization scan signals, the fourth scan driver can also output a compensation scan signal with a high level H by operating similarly to the first stage ST1'' of the third scan driver SDV3.

[0293] Although not shown, the aforementioned transmit driver EDV can also have a circuit configuration substantially the same as that of the second scan driver SDV2. Furthermore, the operating timing of the transmit driver EDV can be similar to... Figure 20 The timing shown is essentially similar. Accordingly, by operating similarly to the first stage ST1'' of the third scan driver SDV3, the transmit driver EDV can also output a transmit signal with a high level H.

[0294] According to embodiments of the present invention, power consumption can be reduced because the scan signal is generated using a single clock signal instead of two clock signals with opposite phases.

[0295] In addition, the scan signal can be rapidly charged to the target level (e.g., low level) by a third voltage having a lower level than the second voltage, thereby providing more general scan signal to the pixel.

[0296] The embodiments of the present invention have been described above with reference to the present invention concept. However, those skilled in the art will understand that various modifications and changes can be made to the present invention concept, as long as such modifications and changes do not depart from the spirit and technical scope of the present invention concept set forth in the claims.

[0297] Therefore, the technical scope of the present invention should not be limited to the contents stated in the detailed description of the specification, but should be determined by the claims.

Claims

1. A display device, comprising: Pixel; as well as A first scan driver is configured to provide a first scan signal to the pixel. The first scan driver includes: The first inverter is configured to invert the first clock signal and output the inverted first clock signal; The first node controller is configured to control the voltage level of the first node and the voltage level of the second node to have different levels from each other in response to the first input signal, the first clock signal and the output signal of the first inverter. A first output buffer is configured to output the first scan signal in response to the voltage levels of the third node and the fourth node; and The second inverter is configured to invert the voltage level of the fourth node and provide the inverted voltage level of the fourth node to the third node. The second node is connected to the fourth node via the first inverter.

2. The display device according to claim 1, wherein, The first inverter receives a first voltage and, in response to the first clock signal, provides the first voltage or the voltage of the second node to the first node controller and the fourth node.

3. The display device according to claim 2, wherein, The first node controller receives the first voltage and a second voltage having a level lower than the first voltage, and The first node controller, in response to the first input signal and the output signal of the first inverter, sets the voltage of the first node to the first voltage or the second voltage, and sets the voltage of the second node to the second voltage or a third voltage having a level lower than the second voltage.

4. The display device according to claim 3, wherein, When the first inverter outputs the first voltage in response to the first clock signal, the first node controller sets the voltage of the first node to the first voltage and the voltage of the second node to the second voltage in response to the first input signal.

5. The display device according to claim 4, wherein, The first inverter provides the first voltage to the fourth node.

6. The display device according to claim 3, wherein, When the first inverter outputs the second voltage of the second node in response to the first clock signal, the first node controller sets the voltage of the first node to the second voltage and sets the voltage of the second node to the third voltage in response to the output signal of the first inverter.

7. The display device according to claim 6, wherein, The third voltage of the second node is provided to the fourth node through the first inverter.

8. The display device according to claim 3, wherein, The voltage difference between the first voltage and the third voltage is twice the voltage difference between the first voltage and the second voltage.

9. The display device according to claim 3, further comprising: The second node controller is connected to the first node controller and the fourth node. Specifically, when the first inverter outputs the second voltage of the second node in response to the first clock signal, the second node controller provides the third voltage to the first node, and The first node controller sets the voltage of the first node to the third voltage and sets the voltage of the second node to a fourth voltage having a level lower than the third voltage.

10. The display device according to claim 9, wherein, The voltage difference between the first voltage and the fourth voltage is three times the voltage difference between the first voltage and the second voltage.

11. The display device according to claim 1, wherein, The first node controller includes: The first transistor includes a first electrode configured to receive a first voltage, a second electrode connected to the first node, and a control electrode configured to receive the first input signal; The second transistor includes a first electrode connected to the second node, a second electrode configured to receive a second voltage having a level lower than the first voltage, and a control electrode configured to receive the first input signal. The third transistor includes a first electrode configured to receive the first voltage, a second electrode connected to the first node, and a control electrode configured to receive the first clock signal. The fourth transistor includes a first electrode connected to the first node, a second electrode configured to receive the second voltage, and a control electrode connected to the fourth node; and The first capacitor includes a first electrode connected to the first node and a second electrode connected to the second node.

12. The display device according to claim 11, wherein, The first inverter includes: The fifth transistor includes a first electrode configured to receive the first voltage, a second electrode connected to the fourth node, and a control electrode configured to receive the first clock signal; and The sixth transistor includes a first electrode connected to the second node, a second electrode connected to the fourth node, and a control electrode configured to receive the first clock signal.

13. The display device according to claim 12, wherein, The second inverter includes: The seventh transistor includes a first electrode configured to receive the first voltage, a second electrode connected to the third node, and a control electrode connected to the fourth node; and The eighth transistor includes a first electrode configured to receive the second voltage, a second electrode connected to the third node, and a control electrode connected to the fourth node. The fifth and seventh transistors are PMOS transistors, and the sixth and eighth transistors are NMOS transistors.

14. The display device according to claim 13, wherein, The first output buffer includes: The ninth transistor includes a first electrode configured to receive the first voltage, a second electrode connected to an output terminal that outputs the first scan signal, and a control electrode connected to the third node; and The tenth transistor includes a first electrode connected to the output terminal, a second electrode configured to receive the second voltage, and a control electrode connected to the fourth node.

15. The display device according to claim 13, further comprising: The reset part is connected to the second node. The reset unit includes: A first reset transistor includes a first electrode connected to the second node, a second electrode configured to receive the first voltage, and a control electrode configured to receive a first reset signal, wherein the first reset signal is a shift signal of the first scan signal; and The second reset transistor includes a first electrode connected to the second node, a second electrode configured to receive the first voltage, and a control electrode configured to receive a second reset signal.

16. The display device according to claim 13, further comprising: The second node controller is connected to the first node controller and the fourth node. The second node controller includes: The eleventh transistor includes a first electrode connected to the fifth node, a second electrode configured to receive the second voltage, and a control electrode configured to receive the first input signal; The twelfth transistor includes a first electrode connected to the sixth node, a second electrode configured to receive the second voltage, and a control electrode connected to the fourth node; The thirteenth transistor includes a first electrode configured to receive the first voltage, a second electrode connected to the sixth node, and a control electrode configured to receive the first clock signal; and The second capacitor includes a first electrode connected to the fifth node and a second electrode connected to the sixth node.

17. The display device according to claim 1, further comprising: A second scan driver is configured to provide a second scan signal to the pixel. The second scan driver includes: The first-1 inverter is configured to invert the signal applied to the input node and output the inverted signal; The first-1 node controller is configured to control the voltage levels of the first-1 node and the second-1 node to have different levels from each other in response to a second input signal, a second clock signal having a phase opposite to that of the first clock signal, and the output signal of the first-1 inverter. The second output buffer is configured to output the second scan signal in response to the voltage levels of the 3-1 node and the 4-1 node; and The second-first inverter is configured to invert the voltage level of the fourth-first node and provide the inverted voltage level of the fourth-first node to the third-first node. The first-1 node controller provides the second input signal to the input node in response to the second clock signal, and the second-1 node is connected to the fourth-1 node through the first-1 inverter.

18. The display device according to claim 17, further comprising: A third scan driver is configured to provide a third scan signal to the pixel. The third scan driver has the same circuit configuration as the second scan driver, and the second input signal provided to the third scan driver has an inverted level of the second input signal provided to the second scan driver.

19. The display device according to claim 17, wherein, The first-1 node controller includes: The first transistor includes a first electrode configured to receive the second input signal, a second electrode connected to the input node, and a control electrode configured to receive the second clock signal; The second-1 transistor includes a first electrode configured to receive a first voltage, a second electrode connected to the first-1 node, and a control electrode connected to the input node; The third-1 transistor includes a first electrode connected to the second-1 node, a second electrode configured to receive a second voltage having a level lower than the first voltage, and a control electrode configured to receive the second clock signal. The fourth-1 transistor includes a first electrode connected to the first-1 node, a second electrode configured to receive the second voltage, and a control electrode connected to the fourth-1 node; and The first-1 capacitor includes a first electrode connected to the first-1 node and a second electrode connected to the second-1 node. The first-1 inverter includes: The 5-1 transistor includes a first electrode configured to receive the first voltage, a second electrode connected to the 4-1 node, and a control electrode connected to the input node; and The 6-1 transistor includes a first electrode connected to the 2-1 node, a second electrode connected to the 4-1 node, and a control electrode connected to the input node. The 5-1st transistor includes a PMOS transistor, and the 6-1st transistor includes an NMOS transistor.

20. An electronic device, comprising: The display device according to any one of claims 1 to 19; as well as A processor is electrically connected to the display device and configured to control the operation of the display device.

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