A multi-tube parallel driving detection protection circuit

Abstract

The application discloses a kind of multi-tube parallel drive detection protection circuits, including power supply circuit, sampling circuit, signal processing circuit and protection execution circuit;The power supply circuit provides hierarchical power supply and negative voltage clamping voltage for multi-tube parallel drive circuit;The multi-tube parallel drive circuit includes the bridge arm of multiple groups of power tube that is arranged in parallel;The sampling circuit collects power supply voltage, power tube driving state, bridge arm switch state and additional fault characteristic signal, is transmitted to the signal processing circuit;The signal processing circuit carries out logic integration and fault judgment to the signal collected, and outputs unified fault feedback signal;The protection execution circuit carries out hardware sealing wave and software sealing wave double protection action according to fault feedback signal, and realizes the protection of multi-tube parallel drive circuit.The application is protected to multi-tube parallel circuit by constructing multi-angle detection system, optimizing signal integration logic and soft and hardware multistage protection mechanism, realizes comprehensive, fast, reliable protection.

Description

Technical Field

[0001] This invention relates to the field of power electronic circuit protection technology, and in particular to a drive detection and protection circuit with multiple transistors connected in parallel. Background Technology

[0002] In power electronic devices, multi-transistor parallel technology is widely used in the circuit design of power devices such as IGBTs, silicon MOS, and SiC-MOS because it can increase the power capacity of the circuit and reduce the load of individual power devices. However, the circuit complexity increases significantly under multi-transistor parallel operation, leading to frequent problems such as drive oscillation, bridge arm shoot-through, and failure to detect single-transistor faults in a timely manner, which seriously affects the reliability of equipment operation.

[0003] Existing drive protection technologies suffer from the following shortcomings: First, there is a lack of specialized detection and protection research for multi-tube parallel scenarios. Most solutions are only applicable to single-tube or module-level drive protection and VCE short-circuit voltage detection, failing to adapt to the special fault characteristics of multi-tube parallel connections. Second, the detection dimensions are limited, lacking a comprehensive detection system covering drive power supply, resistor segmentation sampling, and bridge arm status monitoring, making it difficult to cover various fault points in multi-tube parallel connections. Third, the signal processing and protection response mechanisms are imperfect, lacking integration logic for multiple fault signals and relying solely on hardware blocking after single fault detection, resulting in low protection efficiency and poor reliability. Fourth, the protection response speed is insufficient, with delays in software-level fault handling, failing to meet the rapid protection requirements of multi-tube parallel circuits.

[0004] Therefore, developing a drive detection and protection circuit that has comprehensive detection dimensions, rapid protection response, and adaptability to multi-tube parallel operation has become a technical problem that the industry urgently needs to solve. Summary of the Invention

[0005] The purpose of this invention is to provide a multi-transistor parallel drive detection and protection circuit. By constructing a multi-angle detection system, optimizing signal integration logic, and implementing a multi-level hardware and software protection mechanism, it achieves comprehensive, fast, and reliable protection for multi-transistor parallel circuits.

[0006] To achieve the above objectives, the present invention provides the following solution: A multi-transistor parallel drive detection and protection circuit includes a power supply circuit, a sampling circuit, a signal processing circuit, and a protection execution circuit; The power supply circuit provides graded power supply and negative voltage clamping voltage for the multi-transistor parallel drive circuit; the multi-transistor parallel drive circuit includes multiple sets of power bridge arms arranged in parallel; The sampling circuit collects power supply voltage, power transistor drive status, bridge arm switch status, and additional fault characteristic signals, and transmits them to the signal processing circuit. The signal processing circuit performs logical integration and fault judgment on the collected signals and outputs a unified fault feedback signal. The protection execution circuit performs dual protection actions of hardware blocking and software blocking based on the fault feedback signal, thereby realizing the protection of the multi-tube parallel drive circuit.

[0007] Furthermore, the power supply circuit includes an auxiliary power source primary winding circuit, an auxiliary power source secondary winding circuit, and a drive power supply circuit connected in sequence; the auxiliary power source secondary winding circuit provides independent power supply for the drive branches of at least two parallel power transistors; the drive power supply circuit includes a Zener diode, a resistor, and a capacitor, forming a positive voltage drive circuit and a negative voltage clamping circuit. The positive voltage drive circuit outputs a 15V drive voltage, and the negative voltage clamping circuit outputs a 5V clamping voltage. The clamping midpoint is connected to the source (S) terminal of the power transistor bridge arm.

[0008] Furthermore, the sampling circuit includes an isolated sampling unit and an R com The system includes a resistance sampling unit, a bridge arm status sampling unit, and an auxiliary sampling unit; the isolation sampling unit comprises several sets of identical voltage sampling circuits, which respectively acquire the primary-side voltage of the auxiliary source and the power supply voltage of each drive path; the R com The resistance sampling unit includes a common resistor R. com Branch resistance R com1~n The system includes an isolation operational amplifier to collect the voltage divider signal of the multi-transistor parallel circuit; the bridge arm status sampling unit includes AND gate logic and NOT gate logic to collect the drive status signals of the upper and lower bridge arms on the bus; the auxiliary sampling unit collects overvoltage and overcurrent fault signals.

[0009] Furthermore, the voltage sampling circuit of the isolation sampling unit includes a Zener diode, a current-limiting resistor, an optocoupler, and a protection diode; the Zener diode and the current-limiting resistor are connected in series to the voltage to be sampled, the primary side of the optocoupler is connected in parallel with the Zener diode, and the protection diode is connected in reverse parallel across the primary side of the optocoupler; when the sampling voltage is normal, the optocoupler is turned on and outputs a high level; when the sampling voltage is lower than the threshold, the optocoupler is turned off and outputs a low level.

[0010] Furthermore, the R com In the resistance sampling unit, the branch resistance R com1~n After connecting them in series with their respective parallel power transistors, they are then connected to a common resistor R. com The series connection forms a drive circuit; the input terminal of the isolation operational amplifier is connected to a common resistor R. com The two ends of the signal are connected, with the output terminal connected to the comparator input terminal of the signal processing circuit, to convert R... com The voltage signal is conditioned and then output.

[0011] Furthermore, the AND gate input of the bridge arm state sampling unit is respectively connected to the R of the upper and lower bridge arms. comThe sampling signal is connected to the output of the AND gate logic and the input of the NOT gate logic. When both the upper and lower bridge arm sampling signals are high, the AND gate logic outputs a high level, and the NOT gate logic outputs a low level fault signal after inversion.

[0012] Furthermore, the signal processing circuit includes a comparator and a logic gate integration unit; the first input terminal of the comparator is connected to the conditioning signal output by the sampling circuit, and the second input terminal is connected to the reference voltage REF, which is used to output high and low level logic signals; the logic gate integration unit adopts a multi-level AND gate and OR gate combination structure, the input terminal is connected to the comparator output signal and the auxiliary sampling signal, and the output terminal outputs a unified fault feedback signal NP.

[0013] Furthermore, in the logic gate integration unit, when all input signals are high, a high-level normal signal (NP set high) is output; when any input signal is low, a low-level fault signal (NP set low) is output.

[0014] Furthermore, the protection execution circuit includes an inverting buffer controller, a drive interlock conditioning circuit, and an MCU controller; the enable terminal of the inverting buffer controller is connected to the NP signal output by the signal processing circuit. When the NP signal is low, the inverting buffer controller performs hardware blocking; after receiving the NP signal, the MCU controller issues a software blocking command and a shutdown control command through the drive interlock conditioning circuit.

[0015] Furthermore, the power transistor bridge arm includes two sets of power transistors connected vertically in a half-bridge configuration (full-bridge and other topologies can also be extended in this way). This protection logic can be used for power transistor connection topologies that are located in the middle of the bus and pose a shoot-through risk. The power transistors are IGBTs, silicon MOSFETs, or SiC-MOS transistors.

[0016] According to specific embodiments of the present invention, the multi-transistor parallel drive detection and protection circuit provided by the present invention achieves comprehensive, fast, and reliable protection for the multi-transistor parallel drive circuit by constructing a multi-angle detection system, optimizing signal integration logic, and a hardware-software collaborative protection mechanism. Specifically, the following technical effects are disclosed: (1) Comprehensive detection coverage, with no omissions in fault identification: It covers multiple fault points, including primary / secondary power supply of auxiliary power source, negative voltage clamping of drive, status of multi-tube parallel circuit, bridge arm shoot-through risk, overvoltage and overcurrent, etc., providing more comprehensive coverage compared to traditional single fault detection solutions; through R com The resistor segmentation sampling technology only requires one set of sampling signals to identify short circuits or driving abnormalities of any power transistor in a multi-transistor parallel circuit, thus solving the pain point of the difficulty in detecting multi-transistor parallel circuits.

[0017] (2) Rapid protection response reduces the risk of fault escalation: The hardware blocking path is directly implemented through the enable terminal of the inverting buffer controller, eliminating the need for MCU software processing delays. When a fault occurs, the drive signal can be quickly cut off, significantly shortening the protection response time. The multi-level protection of hardware and software works together, with hardware blocking achieving instantaneous response and MCU software blocking further issuing shutdown commands. This dual protection enhances the reliability of the protection and prevents the spread of faults.

[0018] (3) Improved operational stability, adaptable to various operating conditions: Negative voltage clamping detection ensures stable drive voltage levels, effectively suppressing drive oscillations when multiple transistors are connected in parallel, and avoiding the risk of power transistors opening simultaneously beyond the threshold. The upper and lower transistor AND gate logic design of the bridge arm accurately identifies potential bridge arm shoot-through hazards and triggers protection in advance, significantly reducing the probability of power device damage. It is also compatible with both multi-transistor parallel and single-transistor operation, and can meet the protection needs of circuits with different power levels.

[0019] (4) The circuit design is practical and easily implemented: It is constructed using conventional components such as resistors, transistors, and logic gates, eliminating the need for dedicated driver chips, thus simplifying the circuit structure and reducing hardware costs. The signal integration logic is clear, and multiple fault signals are processed uniformly through multi-level AND gate combinations. Protection can be triggered by any fault, and the logic is reliable and easy to debug. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This is a logic block diagram of a multi-transistor parallel drive detection and protection circuit according to an embodiment of the present invention; Figure 2 This is an overall topology diagram of the multi-transistor parallel drive detection and protection circuit according to an embodiment of the present invention; Figure 3 This is a schematic diagram of the power and sampling principle in an embodiment of the present invention; Figure 4 This is a schematic diagram of the negative pressure clamping sampling circuit in an embodiment of the present invention; Figure 5 R in the embodiments of the present invention com Voltage acquisition circuit schematic diagram; Figure 6 This is a schematic diagram of the voltage comparison circuit in an embodiment of the present invention; Figure 7 This is a schematic diagram of the logic processing circuit in an embodiment of the present invention; Figure 8This is a schematic diagram of the NP signal logic in an embodiment of the present invention. Detailed Implementation

[0022] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0023] Parallel connection of multiple transistors: refers to the use of multiple devices with the same power in parallel, such as IGBTs, silicon MOS and SiC-MOS transistors, etc.

[0024] Drive detection: refers to the signal circuit used for sampling and comparison in this invention. When multiple transistors are connected in parallel, how to collect a certain signal can determine any damage in the parallel devices, thereby achieving the purpose of full detection.

[0025] Drive protection: This refers to the multi-channel detection signal scheme in this invention, such as the drive oscillation and negative voltage clamping protection circuit for multiple tubes in parallel, and the sampling of a resistor signal to confirm whether the entire parallel branch circuit is faulty when multiple groups are in parallel.

[0026] The technical problem this invention aims to solve is to develop a detection and protection scheme for the drive circuit of multiple power transistors connected in parallel, based on the characteristics of parallel faults, thereby improving the reliability of multi-transistor parallel equipment. The problem solved is as follows: 1. This invention first detects the driving voltage level of the parallel circuit to ensure reliable negative voltage clamping and avoid oscillation exceeding the threshold and simultaneous opening; 2. Adopt R com The resistor is used to divide the drive, which increases the drive synchronization and the number of sampling points. The voltage of the resistor is used to determine whether the MOS switch state of the parallel circuit is abnormal. 3. The upper and lower pipes of the bridge arm (the pipes with shoot-through risk) adopt AND gate logic. When both are open, the NOT gate outputs a low signal to report the fault, further reducing the risk of bridge arm shoot-through.

[0027] 4. The fault signals from each path are integrated by AND gates and then the logic control signal is output. 5. An inverse buffer control circuit (enable port) is added to the wave generation logic to directly construct the hardware wave blocking path with the hardware feedback signal, thereby reducing the protection time and enabling rapid response for fault protection.

[0028] In summary, this invention mainly addresses the challenges of detecting and protecting the drive circuit of power transistors in parallel operation, based on fault characteristics such as drive oscillation and difficulties in multi-transistor drive detection. It provides a feasible and reliable solution to improve the reliability of multi-transistor parallel operation devices.

[0029] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0030] like Figures 1 to 8 As shown, the present invention provides a multi-transistor parallel drive detection and protection circuit, including a power supply circuit, a sampling circuit, a signal processing circuit and a protection execution circuit; The power supply circuit provides graded power supply and negative voltage clamping voltage for the multi-transistor parallel drive circuit; the multi-transistor parallel drive circuit includes multiple sets of power bridge arms arranged in parallel; The sampling circuit collects power supply voltage, power transistor drive status, bridge arm switch status, and additional fault characteristic signals, and transmits them to the signal processing circuit. The signal processing circuit performs logical integration and fault judgment on the collected signals and outputs a unified fault feedback signal. The protection execution circuit performs dual protection actions of hardware blocking and software blocking based on the fault feedback signal, thereby realizing the protection of the multi-tube parallel drive circuit.

[0031] In this embodiment of the invention, the multi-transistor parallel drive circuit includes four sets of power transistor bridge arms arranged in parallel; each power transistor bridge arm includes two sets of MOS transistors connected vertically to the half-bridge.

[0032] like Figure 1 The diagram shown is the main logic block diagram of this invention. The black lines represent the power supply circuit, mainly for the auxiliary power source and the drive isolator. The blue lines represent the MCU signal control circuit. The drive signal issued by the MCU passes through the interlock conditioning circuit and the inverted buffer controller to the drive wave generation circuit at the MOS drive end. The red signal lines represent the signal acquisition and feedback protection signals in this invention, which are the isolation sampling circuits 1 to 5 in the diagram for the power supply voltage (auxiliary power source primary side and drive power supply). For abnormal drive signal sampling (switch abnormality, bridge arm shoot-through, etc.), the red sampling signal is processed by the logic gate through the green feedback loop and then fed back to the hardware protection end (inverted buffer controller) and the software protection port (MCU) respectively. The drive is adjusted according to the fault logic, thereby realizing fault handling.

[0033] like Figure 2 The diagram shown is the circuit topology of this invention, where drive1~4 correspond to... Figure 1 The "output end of the blue signal line" (the drive signal is sent from the MCU to the drive end through various conditioning circuits). Figure 2 TO_1~5 correspond to "isolation sampling circuits 1~5" in the logic block diagram. The topology diagram only shows the circuit diagram of TO_1. The other TO_2~4 have the same circuit structure and are shown in the topology as schematic ports. The main function is to sample the auxiliary source primary voltage (Supply±) and the four drive supply voltages (20V_1 / GND1, 20V_2 / GND2, 20V_3 / GND3, 20V_4 / GND4) to ensure that the negative voltage clamping signal is good. Figure 2 OP_COM1~4 correspond Figure 1 The "parallel power transistor drive circuit resistor division, differential sampling R" in the text com "Voltage" refers to the differential sampling performed after dividing the parallel circuit resistance.

[0034] TO_6~9 corresponds to Figure 1 "each R" com "Voltage sample value and normal value are output through comparator". This mainly compares the differential sampled signal with the standard voltage value REF, outputting the corresponding logic level to acquire fault signals. TO_10~11 correspond to... Figure 1 "Busline upper and lower bridge arms R" com The voltage sampling is processed by a comparator output AND gate logic processor, which mainly samples the upper and lower power transistors of the bridge arm to prevent bridge arm shoot-through and collect fault signals in advance. TO_12 corresponds to... Figure 1 The "Other Sampling Protection Circuits" section mainly refers to the sampling signals of output voltage and current in the product. This invention can also incorporate these signals into the overall sampling feedback signal for protection. The NP signal corresponds to... Figure 1 The "AND gate logic circuit (any signal low indicates an error, so the signal is blocked)" logically integrates all sampled fault signals and outputs them according to the specified parameters. Figure 1 The feedback shown is sent to the buffer circuit for hardware blocking or to the MCU port for software fault blocking.

[0035] Combination Figures 1 to 8 The various circuit modules in this invention are described in detail below: 1. Power supply circuit The power supply circuit includes an auxiliary power supply primary circuit, an auxiliary power supply secondary circuit with multiple windings (taking 4 channels as an example), and a drive power supply circuit. The auxiliary power supply primary circuit provides the basic power for the entire power supply system. The auxiliary power supply secondary circuit, through a multi-winding design, provides independent 20V_1 / GND1, 20V_2 / GND2, 20V_3 / GND3, and 20V_4 / GND4 power supplies for the drive branches of the 4 parallel power transistors. In the drive power supply circuit, each channel is equipped with a voltage regulation clamping circuit composed of diodes, resistors, and capacitors. For example, in the 20V_1 branch, the voltage regulation circuit composed of diode D1, resistor R1, capacitor C1, and capacitor C2 outputs a 15V positive drive voltage at C1 and a 5V negative clamping voltage at C2. The clamping midpoint S1_Q_S is connected to the source (S) terminal of the upper MOSFET of the MOS bridge arm to ensure reliable turn-off of the power transistor and avoid drive oscillation.

[0036] 2. Sampling circuit The sampling circuit includes isolated sampling units (TO_1~5), R com The system includes a resistance sampling unit (OP_COM1~4), a bridge arm status sampling unit (TO_10~11), and an auxiliary sampling unit (TO_12).

[0037] The isolation sampling unit TO_1 acquires the primary-side voltage Supply± of the auxiliary power supply, while TO_2~5 acquire the four drive power supply voltages respectively. Taking TO_1 as an example, Zener_D1 in the circuit is a 19V Zener diode. The resistance value of R02 is adjusted so that the optocoupler is turned on when the power supply voltage is normal (20V), and TO_1 outputs a high level; when the power supply voltage is lower than 19V, the optocoupler is turned off, and TO_1 outputs a low level. Diode D02 and resistor R02 form a protection circuit to prevent damage to the optocoupler when the voltage is reversed, clamping the optocoupler voltage at 0.7V.

[0038] R com In the resistance sampling unit, each drive circuit is equipped with a common resistor R. com and branch resistance R com_1~4 Under normal operating conditions, R com =4Ω, R com_1~4 =4Ω, during switching process, the 15V voltage is at R com The voltage divider is 12V; when one of the MOSFETs is short-circuited, R com The voltage is divided to 7.5V. The isolated operational amplifier OP_COM1 acquires this voltage signal, conditions it, and outputs it to the comparator.

[0039] Bridge arm state sampling units TO_10~11 respectively collect the R of the upper and lower bridge arms. com The sampled signal is processed by an AND gate and then fed into a NOT gate. When both the upper and lower bridge arm sampled signals are high, it indicates that the bridge arm is open. The AND gate outputs a high level, and the NOT gate inverts the signal and outputs a low-level fault signal.

[0040] The auxiliary sampling unit TO_12 collects other fault signals such as overvoltage and overcurrent, and incorporates them into the overall protection logic.

[0041] Figure 3 This shows the power and sampling schematic of the sampling circuit. (For example...) Figure 3 As shown: The left side Supply± is a schematic diagram of the primary-side circuit of the auxiliary source (not covered by this invention). This schematic diagram is only used to illustrate the sampling source of TO_1. The circuit topology diagram on the right is the sampling core. Taking the 20V_1 and GND1 branches as an example, the voltage regulator circuit is composed of D1, R1, C1, and C2. The C1 terminal is 15V, and the C2 terminal is 5V. The clamping midpoint S1_Q_S is connected to the S terminal of the upper MOSFET of the MOS bridge arm, forming a positive 15V drive and a negative 5V clamp to ensure reliable turn-off. The other drive branches are consistent with this principle. R com_1 and R com_1_1~4 The drive resistor is divided to detect any abnormality in a power transistor when multiple transistors are connected in parallel. The circuit is simple and only needs to detect a single signal to sample the fault signal. The sampling circuit formed by OP_COM1 and the isolation operational amplifier is used to judge the parallel connection of multiple transistors (the voltage sampling judgment point of the parallel circuit S1_Q1~4 in the figure). DC± is the power bus port. The specific circuit topology is not shown here and can be confirmed according to the actual use.

[0042] As mentioned above, Figure 3 The main focus is on the driving power framework, intended to illustrate the actual driving topology composition and the corresponding basic signal sampling positions.

[0043] like Figure 4As shown: supply± is the auxiliary power supply primary side power supply sampling; 4-channel drive isolation power supply voltage (20V_1 / GND1, 20V_2 / GND2, 20V_3 / GND3, 20V_4 / GND4) sampling, the circuit mechanism is basically the same. Taking 20V_1 / GND1 as an example, the circuit topology principle is explained. As mentioned above, the acquisition of drive power supply voltage is mainly to ensure the negative voltage clamping function and avoid the oscillation and shoot-through of multi-transistor parallel drive. The power supply voltage first passes through Zener_D1 and R02 and then is voltage limited. If a 19V Zener_D1 can be selected, the resistor R02 can be adjusted so that the optocoupler can just meet the turn-on requirement. If it is lower than 19V, the optocoupler is turned off. The secondary side of the optocoupler is powered by a control 5V (C_vcc in the figure). If the drive power supply is normal, TO_1 outputs a high level; if it is lower than 19V, it outputs a low level, which can be detected. The sampling principle of the other auxiliary power supply primary side and the other 3 drive power supplies is the same. For example, the normal power supply is 20V, the Zener diode is 15V, and the optocoupler is in the on state. At this time, TO_1 is high level, that is, normally set high. If the power supply voltage drops to 19V, the negative voltage clamp will gradually decrease to -4V. The risk of power transistor drive oscillation and shoot-through will increase, so the optocoupler will be turned off. The path formed by diode D02 and resistor R02 can avoid damage to the optocoupler when the auxiliary power supply primary side voltage is reversed. The circuit forms a loop through diode D02 and resistor R02, and the optocoupler voltage is clamped to 0.7V (the voltage drop of one diode).

[0044] like Figure 5 As shown: (a) The figure represents the circuit model topology when the drive circuit is normal and the MOS is in no abnormal state, where the drive circuit is represented by Drive and R. com_1 The analysis and explanation of the branch road is as follows: R com_1 This refers to the common driving resistor in the overall circuit, R. com_1_1~4 This represents the branch drive resistor, with C02~05 representing a simplified model of the MOSFET. During actual charging and discharging, the capacitor initially operates in a short-circuit state, and the value is calculated as follows: R com_1 =4Ω, R com_1_1~4 =4Ω, then in this circuit, under normal operating conditions, the actual 15V voltage distribution during switching is R com_1 The voltage is 12V; after being conditioned and sampled by an isolated operational amplifier, it can be compared with REF. If a short circuit occurs in a MOS device during actual circuit operation, as shown in the circuit topology of Figure (b), then the 15V voltage is distributed to R. com_1 The voltage will become 7.5V, which is significantly different and can be compared with REF, thus outputting a fault sampling signal via the op-amp.

[0045] As described above, this solution can detect situations where the MOSS is short-circuited or the drive is abnormal when multiple transistors are connected in parallel. This can be achieved by adjusting the common resistor R of the parallel circuit. com (R) com_1~4The circuit uses voltage sampling to detect abnormalities when a device is damaged in a multi-transistor parallel drive. In practice, only one set of sampling signals is needed to determine the state of the entire parallel circuit, making it highly practical and providing a reliable detection method for multi-transistor parallel drive schemes.

[0046] 3. Signal processing circuit The signal processing circuit includes comparators (TO_6~9) and a logic gate integration unit. The inputs of comparators TO_6~9 are respectively connected to the conditioning signals output from OP_COM1~4 and the reference voltage REF. Under normal conditions, R... com The 12V voltage divider, after being divided by resistors, becomes 4V, which is higher than REF, so TO_6~9 output a high level. In case of a fault, the sampled voltage, after being divided, becomes 2.5V, which is lower than REF, so TO_6~9 output a low level. The logic gate integration unit uses a multi-stage AND gate combination. When all signals TO_1~12 are high, a high-level normal signal is output; when any one signal is low, a low-level fault signal NP is output.

[0047] like Figure 6 As shown: REF is the reference voltage, and its actual value can be confirmed according to the actual circuit; R012 and R013 form an operational amplifier circuit, and D06 and D07 represent TVS transistors, which can ultimately form a comparator; as mentioned above, under normal conditions R com_1 The voltage divider is 12V, but the op-amp input voltage is limited. This can be adjusted using resistors (e.g., by using a resistor divider to reduce it to 4V). In this case, the REF voltage can be set to 3V, and the TO_6 output will be high. If the circuit malfunctions, the sampling voltage will be a continuous 7.5V (proportionally reduced to 2.5V), lower than REF=3V, and the TO_6 output will show a low-level abnormal signal. Additionally, considering the difficulty in controlling transient switching signals during actual operation, the circuit can also be adjusted so that REF is set to 3V. When the circuit is fully turned on under normal conditions, R... com_1 When the voltage is close to 0V and the circuit is short-circuited, the Rcom_7.5V voltage (adjusted to approximately 5V using resistor voltage dividers) is compared. Under normal conditions, the output is low; under abnormal conditions, it is high. However, this logic conflicts with the current active high logic. The circuit can be adjusted by swapping the positions of OP_COM1 and REF at the op-amp's input ports to meet the required level. This example only considers the parallel design of four power transistors. For actual parallel designs with multiple transistors, the distance needs to be determined based on R... com Resistance value and R com_1_1~4 The resistance ratio of the branch drive resistors is used to confirm and set the corresponding REF parameters, etc.

[0048] Taking ports TO_6 and TO_7 as examples, in actual design, TO_6 and TO_7 are the sampling signals for the upper and lower arms of a parallel multi-transistor bridge. If both are set low simultaneously, it means that there is a short circuit in the power transistors of both the upper and lower arms, which poses a risk of bridge arm shoot-through. However, a high level is actually a normal signal. For logical consistency, an AND gate is added. If one of the upper or lower arms experiences a short circuit, the NOT gate outputs a low signal. A high level is only output when both are normal, ensuring logical consistency. Here, we analyze the bridge arm shoot-through sampling port using TO_10 as an example. The approach for the other arms is basically the same. Depending on the full-bridge or cascaded scheme, multiple sets of sampling logic can be applied to this signal according to actual needs to achieve this function.

[0049] like Figure 7 As shown: This circuit uses multiple AND gates to integrate and process the signals. TO_1~12 are the previously acquired signal values ​​(set low as an anomaly according to logic requirements). After processing by the subsequent AND gate logic, if all signals of the "AND gate" (TO_1~12) are high (normal), the output is normal; if any one or more anomalies are present, the output is low. The number of logic gate channels and the number of sampled signals are adjusted (the logic device sampled signals are all processed by the previous stage and are currently control signals, so there is no isolation risk). This embodiment uses three-channel and two-channel AND gates. Figure 7 TO_1 represents the sampling signal of the primary side of the auxiliary source in the example scheme; TO_2~TO_5 represent the sampling signals of the negative voltage clamping of the secondary side of the auxiliary source in the example scheme; TO_6~TO_9 represent the sampling signals of the parallel circuit when the power transistors are connected in parallel in the example scheme; TO_10~TO_11 represent the sampling signals of the bridge arm shoot-through detection and suppression in the example scheme; TO_12 represents other fault signals that may exist in the example scheme (such as overcurrent sampling signals). The remaining gate circuits are for the integration and adjustment of the above signals. If multi-channel AND gates are actually selected, they can be combined according to the requirements to meet the design requirements. The final output NP is used as a feedback signal for hardware blocking protection and software feedback blocking signal.

[0050] 4. Protect the execution circuit The protection execution circuit includes an inverting buffer controller, a drive interlock conditioning circuit, and an MCU controller. The NP signal is fed back to the enable terminal of the inverting buffer controller. When NP is low, the inverting buffer controller directly performs hardware blocking without MCU processing, reducing protection delay. At the same time, the NP signal is fed back to the MCU, and the MCU issues software blocking instructions and shutdown control instructions. The drive interlock conditioning circuit cuts off the drive signal, realizing multi-level hardware and software protection.

[0051] like Figure 8As shown: Multiple sampled signals are integrated into an NP signal, which is fed back to the hardware drive conditioning circuit (enable terminal of the inverting buffer controller) for hardware protection. At this time, the inverting buffer can be uniformly floated through the enable port for hardware blocking, ensuring that when the power circuit is abnormal, there is no need for software settings and calculations, which can further reduce the protection time and achieve the purpose of fast response protection. In addition, the NP is synchronously fed back to the MCU port. After the power circuit stops, the MCU can perform signal processing internally and issue other protection commands synchronously according to the fault. At the same time, multi-level hardware and software protection is adopted to ensure reliability.

[0052] The working principle of the multi-transistor parallel drive detection and protection circuit described in this invention is as follows: When the multi-transistor parallel drive circuit is running normally, all sampled signals are at a high level, the logic gate integration unit outputs a high-level NP signal, the inverting buffer controller works normally, and the MCU sends drive signals to the power transistors through the drive interlock conditioning circuit and the inverting buffer controller, and the circuit generates waves normally.

[0053] When an abnormal power supply voltage occurs (such as the drive power supply voltage dropping to 18V), the isolation sampling unit TO_2 outputs a low level, the logic gate integration unit outputs a low-level NP signal, the inverting buffer controller immediately executes hardware blocking, and at the same time the MCU receives the NP signal and sends a software blocking command to cut off the drive circuit, thus achieving rapid protection.

[0054] When a MOSFET is short-circuited, R com When the resistor sampling unit detects an abnormal voltage, the comparator outputs a low level. After being integrated by the logic gate, NP is set low, triggering dual hardware and software protection to prevent the fault from escalating.

[0055] When both the upper and lower tubes of the bridge arm are open, the bridge arm status sampling unit outputs a low-level fault signal, and the logic gate integration unit outputs an NP low level, triggering the blocking protection to prevent the bridge arm from shoot-through.

[0056] The key innovations of this invention are as follows: Based on the risks associated with multiple tubes connected in parallel, this invention proposes reasonable detection schemes for specific risks, offering a comprehensive and reliable solution. The idea of ​​detecting risk signals from multiple angles is one of the innovative aspects of this invention. This invention proposes specific protection methods for the design of multi-transistor parallel drive, such as the auxiliary source primary voltage detection circuit and principle; the secondary negative voltage clamping signal detection circuit and principle; the multi-transistor loop detection circuit and principle when multiple transistors are connected in parallel; and the detection and principle of bridge arm shoot-through, etc. This invention targets multi-transistor parallel circuits. By combining actual fault information, it logically integrates multiple detection signals and adopts a multi-level hardware and software protection approach to improve protection efficiency and increase protection reliability. This idea and solution is also one of the protection points of this invention. This invention addresses a multi-transistor parallel detection and protection scheme (also applicable to single-transistor systems). It integrates power supply anomaly and drive detection, as well as signal logic such as bridge arm shoot-through, overvoltage, and overcurrent, to comprehensively output a feasible drive detection and protection scheme. This comprehensive scheme is also an innovative protection method. It is not limited to using the specific sampling circuit and logic circuit mentioned in this invention to achieve this scheme, but also includes other scheme designs that use this scheme but whose circuits and principles are slightly different from this invention. These are also within the protection scope of this invention.

[0057] Compared to current driver hardware logic protection circuit solutions, this invention mainly combines fault phenomena and risk factors in practical applications. For fault points (difficulty in detecting multi-device drive signals) and risk points (severe drive oscillation increases negative voltage clamping detection), it adopts a multi-angle detection method (simultaneous detection of single-channel drive status and bridge arm transistor status). From the perspectives of drive, wave generation, and transistor detection, it provides a more comprehensive and feasible solution (AND gate protection after integration of multiple protection signal logics, protection can be triggered by any fault) to detect and protect the drive of multiple transistors in parallel, thereby improving product reliability.

[0058] In summary, this invention discloses a driving, detection, and protection scheme for multi-transistor parallel connections. From the basis of the invention and the specific logic of the scheme, to the specific circuit design and principle analysis, and then to the mechanism analysis, the feasibility, comprehensiveness, and reliability of this invention are verified from the perspectives of signal integration and advantage analysis. Multi-transistor parallel connection products can be designed and adjusted according to the design based on this invention, and product reliability can be further improved through comprehensive detection and multi-level protection schemes.

[0059] 1. Feasibility and effectiveness analysis of the present invention: This invention, based on the strong demand for negative driving voltage from multi-transistor parallel drive oscillation in actual designs and the high requirements for drive negative voltage by power transistors such as SiC, and considering the difference between the output voltage of the auxiliary power supply multi-winding and the protection blocking of the main feedback winding, proposes a detection method for the negative voltage clamping of the primary side and the drive power supply. Through detection, it can ensure that the power transistors are preferentially turned off when the auxiliary power supply malfunctions or stops, reducing the risk of oscillation shoot-through. This invention not only proposes a macroscopic solution but also designs sampling protection points for each solution, conducts principle analysis, performs related circuit design, and provides specific feasibility demonstrations. In summary, the solution designed in this invention is feasible and effective.

[0060] 2. Analysis and explanation of the practicality and comprehensiveness of the present invention: This invention addresses the main risks associated with actual design and the failure of currently available power devices. It comprehensively detects risks such as drive oscillation, bridge arm shoot-through, drive anomalies, and overvoltage / overcurrent. Compared to traditional detection schemes that only target specific faults (such as hardware overvoltage / overcurrent detection), this invention is more comprehensive. It uses an OR operation on fault signals, allowing protection functions to be triggered by any fault, resulting in more comprehensive sampling and protection logic coverage. This invention also designs circuits for different fault generation mechanisms and protection detection methods, validating its practicality. In summary, the solution designed in this invention is more practical and comprehensive than traditional solutions, significantly improving product reliability.

[0061] 3. Comparison of the functional completeness and reliability of the present invention: The design scheme of this invention is relatively complete. As mentioned above, based on the risk points in the actual product design and debugging process, comprehensive testing is carried out on power devices from aspects such as auxiliary power supply, drive negative pressure clamping, anti-straight-through detection, multi-tube parallel connection (single tube also applicable) drive signal detection, and overvoltage and overcurrent detection. Logic gate circuits are used for sampling signal processing, and the power circuit will block the signal and stop in the event of any abnormality. Combined with hardware and software two-level protection measures, the hardware protection is relatively fast, without the need for internal processing of the MCU and other chip delays. Hardware blocking (the signal before the drive chip) is performed directly at the buffer enable terminal, which can further reduce the power protection delay and provide a fast response. At the same time, the total fault signal is fed back to the MCU. The MCU issues shutdown protection commands to the control circuit and other relays based on the feedback signal, and takes multi-level reliable protection measures to ensure the reliable execution of the protection scheme.

[0062] The remaining technical features in this embodiment can be flexibly selected by those skilled in the art to meet different specific practical needs. However, it is obvious to those skilled in the art that these specific details are not necessary to implement the present invention. In other instances, to avoid obscuring the present invention, well-known components, structures, or parts are not specifically described, and all are within the scope of technical protection defined by the claims of the present invention.

[0063] This document uses specific examples to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of the present invention. Furthermore, those skilled in the art will recognize that, based on the ideas of the present invention, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A multi-transistor parallel drive detection and protection circuit, characterized in that, Includes power supply circuit, sampling circuit, signal processing circuit, and protection execution circuit; The power supply circuit provides graded power supply and negative voltage clamping voltage for the multi-transistor parallel drive circuit; the multi-transistor parallel drive circuit includes multiple sets of power bridge arms arranged in parallel; The sampling circuit collects power supply voltage, power transistor drive status, bridge arm switch status, and additional fault characteristic signals, and transmits them to the signal processing circuit. The signal processing circuit performs logical integration and fault judgment on the collected signals and outputs a unified fault feedback signal. The protection execution circuit performs dual protection actions of hardware blocking and software blocking based on the fault feedback signal, thereby realizing the protection of the multi-tube parallel drive circuit.

2. The multi-transistor parallel drive detection and protection circuit according to claim 1, characterized in that, The power supply circuit includes an auxiliary power source primary circuit, an auxiliary power source secondary multi-winding circuit, and a drive power supply circuit connected in sequence. The auxiliary power supply secondary winding circuit provides independent power supply for the drive branches of at least two parallel power transistors; the drive power supply circuit includes a Zener diode, a resistor and a capacitor, forming a positive voltage drive circuit and a negative voltage clamping circuit. The positive voltage drive circuit outputs a 15V drive voltage, and the negative voltage clamping circuit outputs a 5V clamping voltage. The clamping midpoint is connected to the source (S) terminal of the power transistor bridge arm.

3. The multi-transistor parallel drive detection and protection circuit according to claim 2, characterized in that, The sampling circuit includes an isolation sampling unit and an R com The system includes a resistance sampling unit, a bridge arm status sampling unit, and an auxiliary sampling unit; the isolation sampling unit comprises several sets of identical voltage sampling circuits, which respectively acquire the primary-side voltage of the auxiliary source and the power supply voltage of each drive path; the R com The resistance sampling unit includes a common resistor R. com Branch resistance R com1~n The system includes an isolation operational amplifier to collect the voltage divider signal of the multi-transistor parallel circuit; the bridge arm status sampling unit includes AND gate logic and NOT gate logic to collect the drive status signals of the upper and lower bridge arms on the bus; the auxiliary sampling unit collects overvoltage and overcurrent fault signals.

4. The multi-transistor parallel drive detection and protection circuit according to claim 3, characterized in that, The voltage sampling circuit of the isolation sampling unit includes a Zener diode, a current-limiting resistor, an optocoupler, and a protection diode. The Zener diode and the current-limiting resistor are connected in series to the voltage to be sampled. The primary side of the optocoupler is connected in parallel with the Zener diode, and the protection diode is connected in reverse parallel across the primary side of the optocoupler. When the sampled voltage is normal, the optocoupler is turned on and outputs a high level. When the sampled voltage is lower than the threshold, the optocoupler is turned off and outputs a low level.

5. The multi-transistor parallel drive detection and protection circuit according to claim 3, characterized in that, The R com In the resistance sampling unit, the branch resistance R com1~n After connecting them in series with their respective parallel power transistors, they are then connected to a common resistor R. com The series connection forms a drive circuit; the input terminal of the isolation operational amplifier is connected to a common resistor R. com The two ends of the signal are connected, with the output terminal connected to the comparator input terminal of the signal processing circuit, to convert R... com The voltage signal is conditioned and then output.

6. The multi-transistor parallel drive detection and protection circuit according to claim 3, characterized in that, The AND gate input of the bridge arm state sampling unit is connected to the R of the upper and lower bridge arms respectively. com The sampling signal is connected to the output of the AND gate logic and the input of the NOT gate logic. When both the upper and lower bridge arm sampling signals are high, the AND gate logic outputs a high level, and the NOT gate logic outputs a low level fault signal after inversion.

7. The multi-transistor parallel drive detection and protection circuit according to claim 1, characterized in that, The signal processing circuit includes a comparator and a logic gate integration unit; the first input terminal of the comparator is connected to the conditioning signal output by the sampling circuit, and the second input terminal is connected to the reference voltage REF, which is used to output high and low level logic signals; the logic gate integration unit adopts a multi-level AND gate and OR gate combination structure, the input terminal is connected to the comparator output signal and the auxiliary sampling signal, and the output terminal outputs a unified fault feedback signal NP.

8. The multi-transistor parallel drive detection and protection circuit according to claim 7, characterized in that, In the logic gate integration unit, when all input signals are high, a high-level normal signal is output; when any input signal is low, a low-level fault signal is output.

9. The multi-transistor parallel drive detection and protection circuit according to claim 7, characterized in that, The protection execution circuit includes an inverting buffer controller, a drive interlock conditioning circuit, and an MCU controller. The enable terminal of the inverting buffer controller is connected to the NP signal output by the signal processing circuit. When the NP signal is low, the inverting buffer controller performs hardware blocking. After receiving the NP signal, the MCU controller issues software blocking instructions and shutdown control instructions through the drive interlock conditioning circuit.

10. The multi-transistor parallel drive detection and protection circuit according to any one of claims 1-9, characterized in that, The power transistor bridge arm includes two sets of power transistors connected vertically to the half-bridge. The power transistors are IGBTs, silicon MOS transistors, or SiC-MOS transistors.

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