Phase comparison circuit and radio frequency chip

Abstract

This invention relates to the field of radio frequency (RF) technology, and particularly to a phase comparison circuit and an RF chip. The phase comparison circuit includes a first amplifier, a second amplifier, a first frequency divider, a second frequency divider, a first Schmitt trigger, a second Schmitt trigger, a first flip-flop, a second flip-flop, an AND gate, a first filter unit, and a second filter unit. The input of the first amplifier receives a first RF signal, and its output is connected to the input of the first frequency divider. The input of the second amplifier receives a second RF signal, and its output is connected to the input of the second frequency divider. The first and second frequency dividers are used to down-convert the amplified first and second RF signals, respectively. Compared with existing technologies, the phase comparison circuit provided by this invention has a simple structure, a wide phase detection range, stable output, and can effectively reduce the complexity of RF front-end power control.

Description

Technical Field

[0001] This invention relates to the field of radio frequency technology, and particularly to a phase comparison circuit and a radio frequency chip. Background Technology

[0002] The radio frequency (RF) front-end module is a core component of a wireless communication system, enabling signal transmission and reception. Precise closed-loop control of its transmit power directly determines the stability of the communication link, the energy consumption level of the equipment, and the intensity of electromagnetic radiation. The phase comparator circuit, as the core detection unit in the power control loop, converts the phase difference information of two input RF signals into an electrical signal that can be recognized by subsequent control circuits, providing a basis for the dynamic adjustment of transmit power.

[0003] Currently, phase comparison circuits in existing technologies are mainly divided into two categories: analog and digital. Both have obvious shortcomings in practical applications.

[0004] Analog phase comparator circuits: These circuits often use analog multipliers or mixers. In high-frequency radio frequency signal processing scenarios, they suffer from severe signal nonlinear distortion, weak anti-interference capabilities, and poor temperature drift characteristics. The accuracy of the output signal is difficult to guarantee, and additional temperature compensation and calibration circuits are required, which increases the complexity of the system.

[0005] Digital phase comparison circuits: The mainstream uses basic logic units such as XOR gates and RS flip-flops to build them. They generally have defects such as large phase detection dead zone and limited phase detection range (usually only covering 0°~180°). They cannot accurately detect the phase difference in the 180°~360° range, which causes the power control loop to fail to adjust in some phase ranges.

[0006] In summary, existing phase comparison circuits, in order to adapt to high-frequency radio frequency signals, often require complex signal preprocessing, level conversion, and error compensation circuits. This results in a large number of components, low integration, and high manufacturing costs, which not only significantly increases the difficulty of implementing transmit power control but also leads to higher static power consumption and electromagnetic radiation, thus shortening the long-term service life of the product.

[0007] Therefore, there is an urgent need for a new phase comparison circuit and RF chip to solve the above-mentioned technical problems. Summary of the Invention

[0008] This invention provides a phase comparison circuit and an RF chip, aiming to provide a phase comparison circuit with simple structure, wide phase detection range, stable output, and effective reduction of the complexity of RF front-end power control.

[0009] In a first aspect, the present invention provides a phase comparison circuit, the phase comparison circuit comprising a first amplifier, a second amplifier, a first frequency divider, a second frequency divider, a first Schmitt trigger, a second Schmitt trigger, a first flip-flop, a second flip-flop, an AND gate unit, a first filter unit, and a second filter unit.

[0010] The input terminal of the first amplifier is used to receive a first radio frequency signal, and the output terminal of the first amplifier is connected to the input terminal of the first frequency divider. The input terminal of the second amplifier is used to receive a second radio frequency signal, and the output terminal of the second amplifier is connected to the input terminal of the second frequency divider. The first amplifier and the second amplifier are used to amplify the first radio frequency signal and the second radio frequency signal, respectively.

[0011] The output of the first frequency divider is connected to the input of the first Schmitt trigger, and the output of the second frequency divider is connected to the input of the second Schmitt trigger; the first frequency divider and the second frequency divider are respectively used to down-convert the amplified first radio frequency signal and the amplified second radio frequency signal.

[0012] The output terminal of the first Schmitt trigger is connected to the clock terminal of the first trigger, and the output terminal of the second Schmitt trigger is connected to the clock terminal of the second trigger. The first Schmitt trigger and the second Schmitt trigger are respectively used to shape the down-frequency first radio frequency signal and the down-frequency second radio frequency signal, and respectively output a first square wave signal and a second square wave signal to the clock terminal of the first trigger and the clock terminal of the second trigger.

[0013] The reset terminals of the first and second flip-flops are both connected to the output terminal of the AND gate unit. The data input terminal of the first flip-flop is connected to an external power supply voltage. The output terminal of the first flip-flop is connected to the input terminal of the first filter unit and the first input terminal of the AND gate unit, respectively. The data input terminal of the second flip-flop is connected to an external power supply voltage. The output terminal of the second flip-flop is connected to the input terminal of the second filter unit and the second input terminal of the AND gate unit, respectively. The first flip-flop is used to output a first phase detection signal based on the received first square wave signal, and the second flip-flop is used to output a second phase detection signal based on the received second square wave signal.

[0014] The first filtering unit is used to filter the received first phase detection signal and then output it, and the second filtering unit is used to filter the received second phase detection signal and then output it.

[0015] Preferably, the first frequency divider and the second frequency divider have the same division ratio.

[0016] Preferably, when the phase difference between the first square wave signal and the second square wave signal is within the range of 0° to 180°, the first phase detection signal output by the first trigger is at a high level, and the second phase detection signal output by the second trigger is at a low level. The duty cycle of the first phase detection signal is proportional to the phase difference between the first square wave signal and the second square wave signal.

[0017] Preferably, when the phase difference between the first square wave signal and the second square wave signal is within the range of 180° to 360°, the second phase detection signal output by the second trigger is at a high level, the first phase detection signal output by the first trigger is at a low level, and the duty cycle of the second phase detection signal is inversely proportional to the phase difference between the first square wave signal and the second square wave signal.

[0018] Preferably, the first filtering unit includes a first resistor and a first capacitor; The first end of the first resistor serves as the input end of the first filter unit, the second end of the first resistor serves as the output end of the first filter unit, the first end of the first capacitor is connected to the second end of the first resistor, and the second end of the first capacitor is grounded.

[0019] Preferably, the second filter unit includes a second resistor and a second capacitor; The first end of the second resistor serves as the input terminal of the second filter unit, the second end of the second resistor serves as the output terminal of the second filter unit, the first end of the second capacitor is connected to the second end of the second resistor, and the second end of the second capacitor is grounded.

[0020] Secondly, the present invention also provides a radio frequency chip, the radio frequency chip including a phase comparison circuit as described in any of the above embodiments.

[0021] Compared with existing technologies, this invention, by combining a first flip-flop, a second flip-flop, and an AND gate unit, can accurately detect any phase difference between two input RF signals within the 0-360° range, completely solving the problems of narrow linear range and detection dead zone in traditional analog phase detectors. Simultaneously, noise is shaped and filtered out using a Schmitt trigger, significantly improving phase detection accuracy. By setting a frequency divider with the same division ratio before the phase detector core, the high-frequency input RF signal is converted into a low-frequency signal before phase comparison, greatly reducing the operating frequency requirements of subsequent circuits, avoiding timing risks in high-frequency digital circuits, and improving the overall stability of the phase comparison circuit. At the same time, the low-frequency operating mode effectively reduces the dynamic power consumption of the circuit. The core structure of the phase comparison circuit consists only of an amplifier, a frequency divider, a Schmitt trigger, a flip-flop, an AND gate unit, and a filter unit. It eliminates the need for complex digital signal processing units or analog multipliers, resulting in fewer components, simpler wiring, and easy integration into the RF front-end module chip, effectively reducing chip area and lowering product manufacturing costs. Meanwhile, the phase comparison circuit provided by this invention has high-precision phase detection capability, enabling the RF transmission system to achieve more precise power closed-loop control, avoiding the problem of excessive RF radiation caused by power adjustment deviation, while reducing the overall energy consumption of the system and significantly extending the product's service life. Attached Figure Description

[0022] The present invention will now be described in detail with reference to the accompanying drawings. The above and other aspects of the present invention will become clearer and more readily understood through the detailed description following the accompanying drawings. In the drawings: Figure 1 This is a circuit diagram of the phase comparison circuit provided in an embodiment of the present invention; Figure 2 This is a waveform diagram of the phase detector when the phase difference between the first square wave signal and the second square wave signal of the phase comparison circuit provided in this embodiment of the invention is in the range of 0° to 180°. Figure 3 This is a waveform diagram of the phase detector when the phase difference between the first square wave signal and the second square wave signal of the phase comparison circuit provided in this embodiment of the invention is in the range of 180°~360°. Detailed Implementation

[0023] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0024] Example 1 Please refer to Figure 1The present invention provides a phase comparison circuit 100, which includes a first amplifier 11, a second amplifier 12, a first frequency divider 21, a second frequency divider 22, a first Schmitt trigger 31, a second Schmitt trigger 32, a first flip-flop 41, a second flip-flop 42, an AND gate unit 5, a first filter unit 61, and a second filter unit 62.

[0025] The input terminal of the first amplifier 11 is used to receive the first radio frequency signal (Refe), and the output terminal of the first amplifier 11 is connected to the input terminal of the first frequency divider 21. The input terminal of the second amplifier 12 is used to receive the second radio frequency signal (Refl), and the output terminal of the second amplifier 12 is connected to the input terminal of the second frequency divider 22. The first amplifier 11 and the second amplifier 12 are used to amplify the first radio frequency signal and the second radio frequency signal, respectively.

[0026] The output of the first frequency divider 21 is connected to the input of the first Schmitt trigger 31, and the output of the second frequency divider 22 is connected to the input of the second Schmitt trigger 32; the first frequency divider 21 and the second frequency divider 22 are respectively used to down-convert the amplified first radio frequency signal and the amplified second radio frequency signal.

[0027] The output of the first Schmitt trigger 31 is connected to the clock terminal (CLK terminal) of the first trigger 41, and the output of the second Schmitt trigger 32 is connected to the clock terminal (CLK terminal) of the second trigger 42. The first Schmitt trigger 31 and the second Schmitt trigger 32 are used to shape the down-frequency first RF signal and the down-frequency second RF signal, respectively, and output the first square wave signal and the second square wave signal to the clock terminal (CLK terminal) of the first trigger 41 and the clock terminal (CLK terminal) of the second trigger 42, respectively.

[0028] The reset terminals of the first flip-flop 41 and the second flip-flop 42 are both connected to the output terminal of the AND gate unit 5. The data input terminal (D terminal) of the first flip-flop 41 is connected to the external power supply voltage VDD. The output terminal (Q terminal) of the first flip-flop 41 is connected to the input terminal of the first filter unit 61 and the first input terminal of the AND gate unit 5, respectively. The data input terminal (D terminal) of the second flip-flop 42 is connected to the external power supply voltage VDD. The output terminal (Q terminal) of the second flip-flop 42 is connected to the input terminal of the second filter unit 62 and the second input terminal of the AND gate unit 5, respectively. The first flip-flop 41 is used to output a first phase detection signal according to the received first square wave signal, and the second flip-flop 42 is used to output a second phase detection signal according to the received second square wave signal.

[0029] The first filtering unit 61 is used to filter the received first phase detection signal and then output it, and the second filtering unit 62 is used to filter the received second phase detection signal and then output it.

[0030] In this embodiment of the invention, the first frequency divider 21 and the second frequency divider 22 have the same division ratio.

[0031] In this embodiment of the invention, when the phase difference between the first square wave signal and the second square wave signal is within the range of 0° to 180°, the first phase detection signal output by the first trigger 41 is at a high level, and the second phase detection signal output by the second trigger 42 is at a low level. The duty cycle of the first phase detection signal is proportional to the phase difference between the first square wave signal and the second square wave signal.

[0032] In this embodiment of the invention, when the phase difference between the first square wave signal and the second square wave signal is within the range of 180° to 360°, the second phase detection signal output by the second flip-flop 42 is at a high level, and the first phase detection signal output by the first flip-flop 41 is at a low level. The duty cycle of the second phase detection signal is inversely proportional to the phase difference between the first square wave signal and the second square wave signal.

[0033] In this embodiment of the invention, the first filtering unit 61 includes a first resistor R1 and a first capacitor C1; the first end of the first resistor R1 serves as the input end of the first filtering unit 61, the second end of the first resistor R1 serves as the output end of the first filtering unit 61, the first end of the first capacitor C1 is connected to the second end of the first resistor R1, and the second end of the first capacitor C1 is grounded.

[0034] In this embodiment of the invention, the second filter unit 62 includes a second resistor R2 and a second capacitor C2; the first end of the second resistor R2 serves as the input end of the second filter unit 62, the second end of the second resistor R2 serves as the output end of the second filter unit 62, the first end of the second capacitor C2 is connected to the second end of the second resistor R2, and the second end of the second capacitor C2 is grounded.

[0035] Please refer to Figures 1-2 , Figure 2 This is a phase detector waveform diagram of the phase comparison circuit 100 provided in this embodiment of the invention when the phase difference between the first square wave signal and the second square wave signal is in the range of 0° to 180°; when the first square wave signal leads the second square wave signal (leading phase < 180 degrees): At time 1: The first square wave signal output by the first Schmitt trigger 31 is high, the clock input (CLK input) of the first trigger 41 is high, and the first phase detection signal output by the output (Q input) of the first trigger 41 is high. The second square wave signal output by the second Schmitt trigger 32 is low, the clock input (CLK input) of the second trigger 42 is low, and the second phase detection signal output by the output (Q input) of the second trigger 42 is low. AND gate unit 5 outputs a low level.

[0036] The input terminal (Up terminal) of the first filter unit 61 is at a high level, and the input terminal (Dn terminal) of the second filter unit 62 is at a low level.

[0037] At time 2: The first square wave signal output by the first Schmitt trigger 31 is high, the clock input (CLK input) of the first trigger 41 is high, and the output (Q input) of the first trigger 41 outputs a high level. The second square wave signal output by the second Schmitt trigger 32 is high, the clock input (CLK input) of the second trigger 42 is high, and the output (Q input) of the second trigger 42 outputs a high level. AND gate unit 5 outputs a high level.

[0038] When the reset terminals of the first flip-flop 41 and the second flip-flop 42 are at high levels, the first flip-flop 41 and the second flip-flop 42 are reset, and the output terminals (Q terminals) of the first flip-flop 41 and the second flip-flop 42 turn to low voltage.

[0039] The input terminal (Up terminal) of the first filter unit 61 is at a low level, and the input terminal (Dn terminal) of the second filter unit 62 is at a low level.

[0040] At time 3: The first square wave signal output by the first Schmitt trigger 31 returns to a high level after one cycle, and the input terminal (Up terminal) of the first filter unit 61 and the input terminal (Dn terminal) of the second filter unit 62 repeat the above pulse waveform.

[0041] Please refer to Figure 3 , Figure 3 This is a waveform diagram of the phase detector when the phase difference between the first square wave signal and the second square wave signal of the phase comparison circuit provided in this embodiment of the invention is within the range of 180° to 360°. When the phase of the first square wave signal output by the first Schmitt trigger 31 leads the phase of the second square wave signal output by the second Schmitt trigger 32 by >= 180 degrees, this can be equivalent to the second square wave signal leading the phase of the first square wave signal.

[0042] At time 1: When the second square wave signal output by the second Schmitt trigger 32 is high, the clock terminal (CLK terminal) of the second trigger 42 is high, and the output terminal (Q terminal) of the second trigger 42 outputs a high level.

[0043] The first square wave signal output by the first Schmitt trigger 31 is low, the clock terminal (CLK terminal) of the first trigger 41 is low, and the output terminal (Q terminal) of the first trigger 41 outputs a low level. AND gate unit 5 outputs a low level.

[0044] The input terminal (Up terminal) of the first filter unit 61 is at a low level, and the input terminal (Dn terminal) of the second filter unit 62 is at a high level.

[0045] At time 2: The second square wave signal output by the second Schmitt trigger 32 is high, the clock input (CLK input) of the second trigger 42 is high, and the output (Q input) of the second trigger 42 outputs a high level. The first square wave signal output by the first Schmitt trigger 31 is high, the clock input (CLK input) of the first trigger 41 is high, and the output (Q input) of the first trigger 41 outputs a high level. AND gate 5 outputs a high level.

[0046] When the reset terminals of the first flip-flop 41 and the second flip-flop 42 are at high levels, the first flip-flop 41 and the second flip-flop 42 are reset, and the output terminals (Q terminals) of the first flip-flop 41 and the second flip-flop 42 turn to low voltage.

[0047] The input terminal (Up terminal) of the first filter unit 61 is at a low level, and the input terminal (Dn terminal) of the second filter unit 62 is at a low level.

[0048] At time 3: The second square wave signal output by the second Schmitt trigger 32 returns to a high level again after one cycle. The input terminal (Up terminal) of the first filter unit 61 and the input terminal (Dn terminal) of the second filter unit 62 repeat the above pulse waveform.

[0049] After the first phase detection signal passes through the filter unit composed of the first resistor R1 and the first capacitor C1, it is converted into a stable phase detection DC signal PDet1. The maximum voltage of PDet1 is PDetM, so the voltage range of PDet1 is between 0 and PDetM (V).

[0050] After the second phase detection signal passes through the filter unit composed of the second resistor R2 and the second capacitor C2, the second phase detection signal is converted into a stable phase detection DC signal PDet2. The maximum voltage of PDet2 is PDetM, so the voltage range of PDet2 is between 0 and PDetM (V).

[0051] Compared with existing technologies, this invention, by combining a first flip-flop, a second flip-flop, and an AND gate unit, can accurately detect any phase difference between two input RF signals within the 0-360° range, completely solving the problems of narrow linear range and detection dead zone in traditional analog phase detectors. Simultaneously, noise is shaped and filtered out using a Schmitt trigger, significantly improving phase detection accuracy. By setting a frequency divider with the same division ratio before the phase detector core, the high-frequency input RF signal is converted into a low-frequency signal before phase comparison, greatly reducing the operating frequency requirements of subsequent circuits, avoiding timing risks in high-frequency digital circuits, and improving the overall stability of the phase comparison circuit. At the same time, the low-frequency operating mode effectively reduces the dynamic power consumption of the circuit. The core structure of the phase comparison circuit consists only of an amplifier, a frequency divider, a Schmitt trigger, a flip-flop, an AND gate unit, and a filter unit. It eliminates the need for complex digital signal processing units or analog multipliers, resulting in fewer components, simpler wiring, and easy integration into the RF front-end module chip, effectively reducing chip area and lowering product manufacturing costs. Meanwhile, the phase comparison circuit provided by this invention has high-precision phase detection capability, enabling the RF transmission system to achieve more precise power closed-loop control, avoiding the problem of excessive RF radiation caused by power adjustment deviation, while reducing the overall energy consumption of the system and significantly extending the product's service life.

[0052] Example 2 This invention also provides a radio frequency chip, which includes the phase comparison circuit 100 as described in the above embodiments and can achieve the same technical effect. Please refer to the description in the above embodiments, which will not be repeated here.

[0053] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0054] The embodiments of the present invention have been described above with reference to the accompanying drawings. The disclosed embodiments are merely preferred embodiments of the present invention. However, the present invention is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many equivalent changes in form under the guidance of the present invention without departing from the spirit and scope of the claims. All such changes are within the protection scope of the present invention.

Claims

1. A phase comparison circuit, characterized by, The phase comparison circuit includes a first amplifier, a second amplifier, a first frequency divider, a second frequency divider, a first Schmitt trigger, a second Schmitt trigger, a first flip-flop, a second flip-flop, an AND gate unit, a first filter unit, and a second filter unit. The input terminal of the first amplifier is used to receive a first radio frequency signal, and the output terminal of the first amplifier is connected to the input terminal of the first frequency divider. The input terminal of the second amplifier is used to receive a second radio frequency signal, and the output terminal of the second amplifier is connected to the input terminal of the second frequency divider. The first amplifier and the second amplifier are used to amplify the first radio frequency signal and the second radio frequency signal, respectively. The output of the first frequency divider is connected to the input of the first Schmitt trigger, and the output of the second frequency divider is connected to the input of the second Schmitt trigger; the first frequency divider and the second frequency divider are respectively used to down-convert the amplified first radio frequency signal and the amplified second radio frequency signal. The output of the first Schmitt trigger is connected to the clock terminal of the first trigger, and the output of the second Schmitt trigger is connected to the clock terminal of the second trigger. The first Schmitt trigger and the second Schmitt trigger are used to shape the down-frequency first radio frequency signal and the down-frequency second radio frequency signal, respectively, and output the first square wave signal and the second square wave signal to the clock terminal of the first trigger and the clock terminal of the second trigger, respectively. The reset terminals of the first and second flip-flops are both connected to the output terminal of the AND gate unit. The data input terminal of the first flip-flop is connected to an external power supply voltage. The output terminal of the first flip-flop is connected to the input terminal of the first filter unit and the first input terminal of the AND gate unit, respectively. The data input terminal of the second flip-flop is connected to an external power supply voltage. The output terminal of the second flip-flop is connected to the input terminal of the second filter unit and the second input terminal of the AND gate unit, respectively. The first flip-flop is used to output a first phase detection signal based on the received first square wave signal, and the second flip-flop is used to output a second phase detection signal based on the received second square wave signal. The first filtering unit is used to filter the received first phase detection signal and then output it; the second filtering unit is used to filter the received second phase detection signal and then output it. When the phase difference between the first square wave signal and the second square wave signal is within the range of 0° to 180°, the first phase detection signal output by the first trigger is at a high level, and the second phase detection signal output by the second trigger is at a low level. The duty cycle of the first phase detection signal is proportional to the phase difference between the first square wave signal and the second square wave signal.

2. The phase comparison circuit of claim 1, wherein, The first frequency divider and the second frequency divider have the same division ratio.

3. The phase comparison circuit of claim 1, wherein, When the phase difference between the first square wave signal and the second square wave signal is within the range of 180° to 360°, the second phase detection signal output by the second flip-flop is at a high level, and the first phase detection signal output by the first flip-flop is at a low level. The duty cycle of the second phase detection signal is inversely proportional to the phase difference between the first square wave signal and the second square wave signal.

4. The phase comparison circuit of claim 1, wherein, The first filter unit includes a first resistor and a first capacitor; The first end of the first resistor serves as the input end of the first filter unit, the second end of the first resistor serves as the output end of the first filter unit, the first end of the first capacitor is connected to the second end of the first resistor, and the second end of the first capacitor is grounded.

5. The phase comparison circuit of claim 1, wherein, The second filter unit includes a second resistor and a second capacitor; The first end of the second resistor serves as the input terminal of the second filter unit, the second end of the second resistor serves as the output terminal of the second filter unit, the first end of the second capacitor is connected to the second end of the second resistor, and the second end of the second capacitor is grounded.

6. A radio frequency chip, characterized by The radio frequency chip includes the phase comparison circuit as described in any one of claims 1-5.

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