Driving fault self-resetting circuit and device of switching tube
By employing a self-reset circuit consisting of a first timing circuit, a voltage divider network, and a Schmitt trigger in the IGBT driver board, the problems of fault signal transmission interference and reset circuit complexity are solved, achieving self-reset functionality and improved reliability, making it suitable for industrial production of IGBT driver boards.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- SICHUAN INJET ELECTRIC CO LTD
- Filing Date
- 2025-05-19
- Publication Date
- 2026-05-15
AI Technical Summary
When existing IGBT driver boards fail, the fault signal and reset signal are easily interfered with during transmission, the cable reliability is low, and the existing fault self-reset circuit has a complex structure and high cost, which is not conducive to industrial production.
A self-reset circuit consisting of a first timing circuit, a voltage divider network, diodes, and Schmitt triggers is used to achieve automatic reset of fault signals through hysteresis processing, reducing dependence on external signals. Multiple Schmitt triggers are used for signal hysteresis processing to suppress noise and voltage fluctuations, simplifying the circuit structure.
It realizes the self-reset function of IGBT driver board, reduces dependence on communication cables, avoids signal transmission interference, improves the reliability of the device, reduces costs, and is easy to industrialize.
Smart Images
Figure CN224249682U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of IGBT driving technology, and in particular to a self-reset circuit and device for driving faults of switching transistors. Background Technology
[0002] When an existing IGBT driver board malfunctions, the host computer needs to locate the faulty board. This is done by the corresponding driver module sending a fault signal to the host computer. During reset, the host computer sends a reset signal to the driver module to reset and restart the IGBT driver board. However, the driver module and the host computer are typically connected via a transmission line, which is susceptible to interference during transmission of the fault and reset signals, resulting in low cable reliability. Furthermore, existing IGBT driver board self-reset circuits are mostly complex in structure and expensive, hindering industrial mass production. Utility Model Content
[0003] The purpose of this invention is to provide a self-reset circuit and device for driving faults of switching transistors, so as to improve the above-mentioned technical problems.
[0004] To achieve the above-mentioned objectives, the present invention provides the following technical solutions:
[0005] A self-reset circuit for driving a switching transistor in case of a fault includes a first timing circuit, a voltage divider network, a diode D1, a Schmitt trigger U2, and a Schmitt trigger U3. The voltage divider network includes resistors R1 and R2 connected in series. One end of resistor R2 receives a fault signal. The signal input terminal of the first timing circuit receives the fault signal. The signal output terminal of the first timing circuit is connected to the signal input terminal of the Schmitt trigger U2. The signal output terminal of the Schmitt trigger U2 is connected to the anode of diode D1. The cathode of diode D1 is connected to the other end of resistor R2, one end of resistor R1, and the signal input terminal of Schmitt trigger U3. The other end of resistor R1 is connected to Vdd. The signal output terminal of Schmitt trigger U3 outputs a reset signal.
[0006] Furthermore, the first timing circuit includes a transistor Q1, a resistor R3, a capacitor C2, and a resistor RT2; the base of transistor Q1 is connected to one end of resistor R3; the other end of resistor R3 serves as the signal input terminal of the first timing circuit; the emitter of transistor Q1 is connected to one end of grounded capacitor C2 and grounded; the collector of transistor Q1 is connected to the other end of capacitor C2 and one end of resistor RT2 respectively, and serves as the signal output terminal of the first timing circuit; the other end of resistor RT2 is connected to Vdd; wherein, the charging time of the first timing circuit is changed by adjusting the capacitance value of capacitor C2.
[0007] Furthermore, both Schmitt trigger U2 and Schmitt trigger U3 are non-inverting Schmitt triggers.
[0008] Furthermore, the fault self-reset circuit also includes a second timing circuit and a Schmitt trigger U1; the signal input terminal of the second timing circuit receives the fault signal, and the signal output terminal of the second timing circuit is connected to one end of the Schmitt trigger U1; the other end of the Schmitt trigger U1 is connected to the signal input terminal of the first timing circuit and one end of the resistor R2 respectively.
[0009] Furthermore, the second timing circuit includes a resistor RT1 and a capacitor C1 connected in series; the two ends of the resistor RT1 serve as the signal input terminal and the signal output terminal of the second timing circuit, respectively.
[0010] Furthermore, the resistance values of resistors R1 and R2 are related as follows: R1 >> R2.
[0011] A self-reset device for a drive fault of a switching transistor includes a drive fault self-reset circuit, an MCU control module, and a fault detection drive module; the MCU control module outputs a drive signal to the fault detection drive module; the fault detection drive module outputs a fault signal to the MCU control module and the fault self-reset circuit; and the fault self-reset circuit outputs a reset signal to the fault detection drive module.
[0012] Furthermore, when the IGBT driver board malfunctions, the logic state of the fault signal output by the fault detection driver module is low; when the IGBT driver board is functioning normally, the logic state of the fault signal output by the fault detection driver module is high.
[0013] Furthermore, when the logic state of the reset signal is low, the reset device is reset; when the logic state of the reset signal is high, the reset device is released.
[0014] The beneficial effects of this utility model are as follows:
[0015] 1. This circuit features a self-reset function, reducing reliance on external signals. Through the first timing circuit, voltage divider network, diode D1, Schmitt trigger U2, and Schmitt trigger U3, it automatically completes fault reset without the need for upper-level computer intervention, reducing dependence on communication cables and avoiding interference problems in signal transmission found in traditional reset circuits.
[0016] 2. This device has strong anti-interference capabilities, effectively improving its reliability. It employs a fault-reset circuit trigger to perform hysteresis processing on the input signal, effectively suppressing noise and voltage fluctuations and ensuring the stability of signal transitions. The device allows for flexible configuration of the reset time, and its simple structure, low cost, and ease of industrial production require only common components, eliminating the need for complex chips or high-cost components. Attached Figure Description
[0017] To more clearly illustrate the technical solutions of the embodiments of this utility model, the drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this utility model and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.
[0018] Figure 1 This is a circuit diagram of a drive fault self-reset circuit in Embodiment 1 of this utility model;
[0019] Figure 2 This is a first timing circuit diagram in Embodiment 1 of this utility model;
[0020] Figure 3 This is a structural diagram of the drive fault self-reset device in Embodiment 1 of this utility model;
[0021] Figure 4 This is a circuit diagram of the fault self-reset module in Embodiment 2 of this utility model;
[0022] Figure 5 This is a signal diagram of the fault self-reset module of the IGBT driver board in a fault state in Embodiment 2 of this utility model. Detailed Implementation
[0023] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.
[0024] Example 1:
[0025] Please see Figure 1A self-reset circuit for driving a switching transistor to automatically reset an input fault signal is disclosed. It includes a first timing circuit, a voltage divider network, a diode D1, a Schmitt trigger U2, and a Schmitt trigger U3. The voltage divider network includes resistors R1 and R2 connected in series. One end of resistor R2 receives the fault signal. The signal input terminal of the first timing circuit receives the fault signal. The signal output terminal of the first timing circuit is connected to the signal input terminal of the Schmitt trigger U2. The signal output terminal of the Schmitt trigger U2 is connected to the anode of diode D1. The cathode of diode D1 is connected to the other end of resistor R2, one end of resistor R1, and the signal input terminal of Schmitt trigger U3. The other end of resistor R1 is connected to Vdd. The signal output terminal of Schmitt trigger U3 outputs a reset signal.
[0026] like Figure 2 As shown, the first timing circuit includes a transistor Q1, a resistor R3, a capacitor C2, and a resistor RT2. The base of transistor Q1 is connected to one end of resistor R3; the other end of resistor R3 serves as the signal input terminal of the first timing circuit. The emitter of transistor Q1 is connected to one end of grounded capacitor C2 and grounded. The collector of transistor Q1 is connected to the other end of capacitor C2 and one end of resistor RT2, respectively, and serves as the signal output terminal of the first timing circuit. The other end of resistor RT2 is connected to Vdd. The charging time of the first timing circuit is changed by adjusting the capacitance of capacitor C2.
[0027] Both Schmitt triggers U2 and U3 are non-inverting Schmitt triggers, which perform hysteresis processing on their respective input voltages. That is, when the input voltage (signal) gradually increases from a low voltage and exceeds the positive threshold voltage, the output voltage (signal) jumps from a low level to a high level; when the input voltage (signal) gradually decreases from a high voltage and falls below the negative threshold voltage, the output voltage jumps from a high level to a low level.
[0028] The first timing circuit is used to receive fault signals, control the generation of reset signals through charging time T2, and output signal s4 to Schmitt trigger U2.
[0029] Schmitt trigger U2 is used to perform hysteresis processing on the output s4 of the first timing circuit to obtain signal s5 and output it to diode D1.
[0030] Schmitt trigger U3 is used to receive the output signals from the voltage divider network and diode D1, and to generate a reset signal.
[0031] A voltage divider network (resistors R1 and R2) is used to pull down the voltage of signal S3 in a fault condition to trigger a reset signal.
[0032] Diode D1 is used to clamp signal s3 to a high level to achieve automatic reset.
[0033] This embodiment achieves the fault self-reset function of the IGBT driver board by cooperating with timing logic and a Schmitt trigger. When the IGBT driver board is working normally, the fault signal is a high-level signal. The fault signal enters the first timing circuit and the voltage divider network composed of R1 and R2. When the fault signal enters the first timing circuit, transistor Q1 conducts, C2 discharges, and the output signal of the first timing circuit gradually changes from high level to low level; correspondingly, the input signal of Schmitt trigger U2 gradually changes from high level to low level. When it falls below the low-level threshold of Schmitt trigger U2, Schmitt trigger U2 outputs a low level, and diode D1 is reverse-biased and cut off. At this time, in the voltage divider network composed of R1 and R2, the fault signal is set to be equal to Vdd voltage when it is high. Therefore, the voltage divider network outputs a high level, which is then output as a high-level reset signal by Schmitt trigger U3.
[0034] When the IGBT driver board malfunctions (such as overcurrent), the fault signal abruptly goes low. The fault signal then enters the first timing circuit and the voltage divider network composed of R1 and R2. In the voltage divider network, R1 >> R2. At this time, the voltage of the output signal of the voltage divider network is Vdd*R2 / (R1+R2), which is lower than the low-level threshold voltage of the Schmitt trigger U3. Therefore, the reset signal is pulled low. Simultaneously, the fault signal enters the first timing circuit, transistor Q1 is turned off, and Vdd charges C2 through RT2. After a preset time, the output signal of the first timing circuit is charged from low to the high-level threshold of the Schmitt trigger. At the preset time point, U2 outputs a high level to the anode of diode D1, D1 conducts, and the input of the Schmitt trigger U3 is clamped to a high level. The Schmitt trigger U3 then outputs a high level, thereby achieving fault self-reset.
[0035] like Figure 3 As shown, a self-reset device for a drive fault of a switching transistor includes a drive fault self-reset circuit, an MCU control module, and a fault detection drive module; the MCU control module outputs a drive signal to the fault detection drive module; the fault detection drive module outputs a fault signal to the MCU control module and the fault self-reset circuit; and the fault self-reset circuit outputs a reset signal to the fault detection drive module.
[0036] When the IGBT driver board malfunctions, the logic state of the fault signal output by the fault detection driver module is low; when the IGBT driver board is functioning normally, the logic state of the fault signal output by the fault detection driver module is high.
[0037] When the logic state of the reset signal is low, the reset device is reset; when the logic state of the reset signal is high, the reset device is released.
[0038] Example 2:
[0039] Example 2 is an improvement on Example 1, and adds a Schmitt trigger U1 and a second timing circuit for fault self-holding.
[0040] The drive fault self-reset circuit in Embodiment 2 includes the first timing circuit, voltage divider network, diode D1, Schmitt trigger U2 and Schmitt trigger U3 from Embodiment 1, and also includes a second timing circuit and Schmitt trigger U1; the signal input terminal of the second timing circuit receives the fault signal, and the signal output terminal of the second timing circuit is connected to one end of the Schmitt trigger U1; the other end of the Schmitt trigger U1 is connected to the signal input terminal of the first timing circuit and one end of resistor R2 respectively.
[0041] The second timing circuit includes a resistor RT1 and a capacitor C1 connected in series; the two ends of the resistor RT1 serve as the signal input and signal output terminals of the second timing circuit, respectively.
[0042] like Figure 4 As shown, the signal input terminal of the second timing circuit receives the fault signal and outputs signal s1 to the signal input terminal of Schmitt trigger U1; the output signal s2 of Schmitt trigger U1 is connected to the signal input terminal of the voltage divider network and the signal input terminal of the first timing circuit respectively; the output signal s4 of the first timing circuit is connected to the signal input terminal of Schmitt trigger U2; the output signal S5 of Schmitt trigger U2 is connected to the anode of diode D1; the cathode of diode D1 is connected to the signal output terminal of the voltage divider network; Schmitt trigger U3 is used to receive the signals output by the voltage divider network and diode D1 and generate the corresponding reset signal.
[0043] In Embodiment 2, the fault self-reset circuit (first timing circuit, second timing circuit, voltage divider network, three Schmitt triggers and diode D1) is used to realize the automatic reset function of the input fault signal.
[0044] The second timing circuit receives the fault signal at its input and outputs signal s1 to the Schmitt trigger U1 to set the delay time T1 for fault handling.
[0045] The first timing circuit receives the signal s2 output by the Schmitt trigger U1 at its input terminal and outputs the signal s4 to the Schmitt trigger U2 at its output terminal, which is used to achieve self-reset through the charging time T2.
[0046] A voltage divider network (resistors R1 and R2) is used to pull the voltage of signal S3 low in a fault condition to trigger a low-level reset signal.
[0047] Diode D1 is used to clamp signal s3 to a high level to achieve automatic reset.
[0048] Schmitt trigger U1 is used to detect fault signals and output signal s2 to the first timing circuit and voltage divider network; Schmitt trigger U2 is used to receive the output s4 of the first timing circuit, obtain signal s5 and output it to diode D1; Schmitt trigger U3 is used to generate a reset signal.
[0049] When the IGBT driver board is in normal operation, the fault signal is a high-level signal. After passing through the second timing circuit, capacitor C1 charges via resistor RT1, changing signal s1 (voltage) to a high-level signal. The voltage at the input of Schmitt trigger U1 rises to a high-level signal, outputting a high-level signal (s2) at terminal a. Signal s2 then enters both the first timing circuit and the voltage divider network formed by resistors R1 and R2. When signal s2 enters the first timing circuit, transistor Q1 turns on, capacitor C2 discharges, and signal s4 output by the first timing circuit becomes low. The corresponding output signal s5 from Schmitt trigger U2 remains low, and diode D1 is reverse-biased and cut off. At this time, in the voltage divider network formed by R1 and R2, signal s2 equals the Vdd voltage. Therefore, signal s3 remains high at terminal b, and signal s3 outputs a high level through U3.
[0050] like Figure 5 As shown, when the IGBT driver board is in a fault state, at time t0, the fault signal abruptly changes to a low-level signal. During the second timing circuit, capacitor C1 discharges through resistor RT1 within the time period T1 until the output voltage (signal s1) of the first timing circuit decreases from a high-level signal to the low-level threshold of the Schmitt trigger U1. During the T1 time period, signals s2, s3, and the reset signal all remain at a high level. At time t1, the Schmitt trigger U1 outputs a low level to endpoint a. In the voltage divider network formed by R1 and R2, the resistance R1 is much larger than the resistance R2, so the voltage level at terminal b is s3 = Vdd * R2 / (R1 + R2), which is lower than the low-level threshold voltage of the Schmitt trigger U3. Therefore, the reset signal is pulled low. At the same time, the low-level signal s2 enters the first timing circuit, the transistor Q1 is turned off, and Vdd charges the capacitor C2 through the resistor RT2. After a time interval T2, the signal s4 is charged from low level to the high-level threshold of the Schmitt trigger U2. At time t2, the Schmitt trigger U2 outputs a high-level signal s5, the diode D1 is turned on, the signal s3 is clamped to a high level, and the Schmitt trigger U3 outputs a high level, thereby realizing fault self-reset.
[0051] In summary, this invention features a self-reset function, reducing reliance on external signals. Fault self-holding and self-reset are automatically completed through the first and second timing circuits, eliminating the need for upper-level computer intervention, reducing dependence on communication cables, and avoiding interference problems in signal transmission found in traditional reset circuits. This invention has strong anti-interference capabilities, effectively improving the reliability of the device. Multiple Schmitt triggers are used to perform hysteresis processing on the input signal, effectively suppressing noise and voltage fluctuations, ensuring the stability of signal transitions. This invention allows for flexible configuration of the reset time, and its simple structure, low cost, and ease of industrial production make it suitable for various applications. By adjusting the capacitance of capacitor C2, the charging time of the second timing circuit 2 can be changed, thus flexibly setting the reset delay time to meet the needs of different application scenarios; the device can be built using only common components, eliminating the need for complex chips or high-cost components. The design of the voltage divider network (resistors R1 and R2) and clamping diode D1 simplifies the reset logic and reduces hardware complexity; both fault signals and reset signals are processed locally, reducing signal attenuation or false triggering caused by long-distance transmission.
[0052] The above description is merely a specific embodiment of this utility model, but the protection scope of this utility model is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this utility model should be included within the protection scope of this utility model. Therefore, the protection scope of this utility model should be determined by the scope of the claims.
Claims
1. A self-reset circuit for a drive fault of a switching transistor, characterized in that, It includes a first timing circuit, a voltage divider network, a diode D1, a Schmitt trigger U2, and a Schmitt trigger U3. The voltage divider network includes resistors R1 and R2 connected in series. One end of resistor R2 receives a fault signal. The signal input terminal of the first timing circuit receives a fault signal. The signal output terminal of the first timing circuit is connected to the signal input terminal of Schmitt trigger U2. The signal output terminal of Schmitt trigger U2 is connected to the anode of diode D1. The cathode of diode D1 is connected to the other end of resistor R2, one end of resistor R1, and the signal input terminal of Schmitt trigger U3. The other end of resistor R1 is connected to Vdd. The signal output terminal of Schmitt trigger U3 outputs a reset signal.
2. The self-reset circuit for drive failure of the switching transistor according to claim 1, characterized in that, The first timing circuit includes a transistor Q1, a resistor R3, a capacitor C2, and a resistor RT2. The base of transistor Q1 is connected to one end of resistor R3. The other end of resistor R3 serves as the signal input terminal of the first timing circuit. The emitter of transistor Q1 is connected to one end of grounded capacitor C2 and grounded. The collector of transistor Q1 is connected to the other end of capacitor C2 and one end of resistor RT2, respectively, and serves as the signal output terminal of the first timing circuit. The other end of resistor RT2 is connected to Vdd. The charging time of the first timing circuit is changed by adjusting the capacitance of capacitor C2.
3. The self-reset circuit for a drive fault of a switching transistor according to claim 1, characterized in that, Both Schmitt triggers U2 and U3 are in-direction Schmitt triggers.
4. The self-reset circuit for a drive fault of a switching transistor according to claim 1, characterized in that, The drive fault self-reset circuit also includes a second timing circuit and a Schmitt trigger U1; The signal input terminal of the second timing circuit receives the fault signal, and the signal output terminal of the second timing circuit is connected to one end of the Schmitt trigger U1; the other end of the Schmitt trigger U1 is connected to the signal input terminal of the first timing circuit and one end of the resistor R2.
5. The self-reset circuit for a drive fault of a switching transistor according to claim 4, characterized in that, The second timing circuit includes a resistor RT1 and a capacitor C1 connected in series; the two ends of the resistor RT1 serve as the signal input terminal and the signal output terminal of the second timing circuit, respectively.
6. The self-reset circuit for a drive fault of a switching transistor according to claim 1, characterized in that, The resistance values of resistors R1 and R2 are related as follows: R1 >> R2.
7. A self-resetting device for a drive fault of a switching transistor, used to implement the self-resetting circuit for a drive fault of a switching transistor as described in any one of claims 1 to 6, characterized in that, It includes a drive fault self-reset circuit, an MCU control module, and a fault detection drive module; the MCU control module outputs a drive signal to the fault detection drive module; the fault detection drive module outputs a fault signal to the MCU control module and the fault self-reset circuit; the fault self-reset circuit outputs a reset signal to the fault detection drive module.
8. The self-reset device for driving a switching transistor according to claim 7, characterized in that, When the IGBT driver board malfunctions, the logic state of the fault signal output by the fault detection driver module is low; when the IGBT driver board is functioning normally, the logic state of the fault signal output by the fault detection driver module is high.
9. The self-reset device for driving a switching transistor according to claim 7, characterized in that, When the logic state of the reset signal is low, the reset device is reset; when the logic state of the reset signal is high, the reset device is released.