Integrated magnetic switch chip

Abstract

The application discloses an integrated magnetic switch chip, which is used for improving the accuracy of data collection of the integrated magnetic switch chip. The application comprises a Wheatstone bridge, a low-offset amplifier, a first Schmitt trigger, a second Schmitt trigger, a power supply module, a digital control module, a first transistor, a second transistor, a ground pin, a clock input pin CKI, a clock sending pin CKO and an output pin. The power supply module is connected with the Wheatstone bridge, the low-offset amplifier and the first Schmitt trigger respectively. The Wheatstone bridge is connected with the low-offset amplifier and the first transistor respectively. The digital control module is connected with the low-offset amplifier, the first Schmitt trigger, the second Schmitt trigger, the clock input pin CKI, the clock sending pin CKO and the first transistor respectively. The first Schmitt trigger is connected with the low-offset amplifier and the second transistor respectively. The output pin is connected with the second Schmitt trigger and the second transistor respectively. The first transistor and the second transistor are connected with the ground pin.

Description

Technical Field

[0001] This application relates to the field of magnetic switches, and more particularly to an integrated magnetic switch chip. Background Technology

[0002] A magnetic switch is a component that controls switching via magnetic signals. The magnetic signals from a magnetic switch have extremely strong penetrating power, easily penetrating common obstacles such as non-magnetic materials like plastics, metals, wood, and rocks, and transmitting signals completely. Furthermore, the signal transmission is unaffected by environmental dust, oil, smoke, or background light sources. These characteristics make magnetic switches widely used in various non-contact control systems, with applications spanning military defense, medical electronics, industrial control, and consumer electronics. Currently, magnetic switches can be broadly classified into two categories: traditional non-integrated magnetic switches represented by reed switches and electromagnetic induction coils, and integrated magnetic switches developed using Hall effect devices, magnetoresistive devices, and microelectronic processes to create magnetically sensitive elements. Traditional non-integrated magnetic switches, due to their large size, short lifespan, and low sensitivity, are gradually being replaced by integrated magnetic switches.

[0003] Nowadays, industrial applications widely require the measurement of various non-electrical physical quantities, such as temperature, pressure, and liquid level. These quantities must be converted into analog electrical signals by transmitters before being transmitted to control rooms or display devices hundreds of meters away. Currently, the most widely used transmitter in industrial testing is the 4-20mA current transmitter. The reason for using current signals is their resistance to interference. Furthermore, the current source has infinite internal resistance, and the resistance of the wires connected in series in the loop does not affect accuracy. It can transmit over hundreds of meters on ordinary twisted-pair cables. In industrial applications, the distance between the measuring equipment and the control room or display device can be tens to hundreds of meters. For cost reasons, two-wire 4-20mA current transmitters are commonly used. The upper limit is set at 20mA because of explosion-proof requirements: the spark energy caused by the switching of a 20mA current is insufficient to ignite gas. The lower limit is not set to 0mA to allow for the detection of broken wires. During normal operation, the current will not be lower than 4mA, so the power consumption of the measured device and the signal conditioning circuit must be less than 4mA; otherwise, the transmitter cannot output a 4mA zero potential.

[0004] Currently, non-contact level detection solutions, such as radar, infrared, and ultrasonic level detection, are typically chosen for detecting the liquid level in industrial water storage devices. However, traditional low-power magnetic switch level detection solutions use reed switches. A magnetic float is placed inside the industrial water storage device, and the reed switches are cascaded at equal intervals along the device wall. The reed switches detect the external magnetic field and break the circuit through mechanical movement, making them ideal switching devices in electrical engineering. While their structure is simple, manufacturing process is easy, and power consumption is low, leading to their widespread application in level detection, their accuracy and sensitivity are low, and their reliability is poor, failing to meet the requirements for real-time, high-precision level detection.

[0005] To address the aforementioned technical shortcomings, a traditional integrated magnetic switch chip was proposed to replace the reed switch. This integrated magnetic switch chip periodically detects the external magnetic field using a wake-up-sleep cycle, with its internal timer configured so that only one chip is awake at any given time, achieving low-power, high-precision liquid level detection. However, during application, it was discovered that the clock frequency of the internal timer in the traditional integrated magnetic switch chip is random, with a probability that multiple chips will be awake simultaneously, a phenomenon known as frequency concurrency. Since there is no communication between the cascaded chips, this frequency concurrency cannot be eliminated. This concurrency causes large fluctuations in GND, interfering with the port sampling voltage VADC and leading to incorrect liquid level height reporting. In other words, the frequency concurrency reduces the accuracy of data acquisition by the integrated magnetic switch chip. Summary of the Invention

[0006] This application discloses an integrated magnetic switch chip for improving the accuracy of data acquisition by the integrated magnetic switch chip.

[0007] The first aspect of this application provides an integrated magnetic switch chip, comprising:

[0008] Wheatstone bridge, low offset amplifier, first Schmitt trigger, second Schmitt trigger, power supply module, digital control module, first NMOS transistor, second NMOS transistor, ground pin GND, clock input pin CKI, clock transmit pin CKO, output pin OUT, and settings in the digital control module are related to the CNT module.

[0009] The power supply module is connected to the Wheatstone bridge, the low offset amplifier, and the first Schmitt trigger, respectively.

[0010] The Wheatstone bridge is connected to the low offset amplifier and the first transistor NMOS, respectively.

[0011] The Digital Control module is connected to the low offset amplifier, the first Schmitt trigger, the second Schmitt trigger, the clock input pin CKI, the clock transmit pin CKO, and the first transistor NMOS, respectively.

[0012] The first Schmitt trigger is connected to the low offset amplifier and the second NMOS transistor, respectively;

[0013] The output pin OUT is connected to the second Schmitt trigger and the second NMOS transistor, respectively;

[0014] Both the first NMOS transistor and the second NMOS transistor are connected to the ground pin GND.

[0015] Optionally, the integrated magnetic switch chip may also include a low-power clock OSC;

[0016] The low-power clock OSC is connected to the digital control module.

[0017] Optionally, the Digital Control module is divided into internal modules and external modules;

[0018] External modules include the CONFIG_EN module, the cutoff enable module, the CNT module, and the OSC TRIM module;

[0019] The CONFIG_EN module is connected to the cutoff enable module and the second Schmitt trigger, respectively.

[0020] The cutoff enable module is connected to the CNT module, the clock input pin CKI, and the clock transmit pin CKO, respectively.

[0021] The OSC TRIM module connects to the low-power clock OSC;

[0022] The OSC TRIM module is connected to the internal module via the CLK signal line;

[0023] The CNT module is connected to the internal module via the DUT_EN signal line;

[0024] The CNT module is connected to the clock input pin CKI.

[0025] Optionally, the cutoff enable modules include the Tgate module and the RX / TX module;

[0026] The Tgate module is connected to the CONFIG_EN module, the clock input pin CKI, and the clock transmit pin CKO, respectively.

[0027] The RX / TX modules are connected to the CNT module, the clock input pin CKI, and the clock transmit pin CKO, respectively.

[0028] Optionally, the power supply module includes a power supply voltage pin VCC and a reference voltage module VREG;

[0029] The power supply voltage pin VCC is connected to the reference voltage module VREG.

[0030] The reference voltage module VREG is connected to the Wheatstone bridge, the low offset amplifier, and the first Schmitt trigger, respectively.

[0031] Optionally, the Wheatstone bridge consists of magnetic sensitive elements R1, R2, R3, and R4.

[0032] Magnetic elements R1, R2, R3, and R4 are connected in sequence to form a bridge circuit.

[0033] Optionally, the interfaces of magnetic sensing elements R1 and R2 are connected to a low offset amplifier;

[0034] The interfaces of magnetic sensitive elements R3 and R4 are connected to the low offset amplifier;

[0035] The interfaces of magnetic sensing elements R2 and R3 are connected to the first transistor NMOS;

[0036] The interfaces of magnetic sensitive elements R1 and R4 are connected to the power supply module.

[0037] Optionally, the magnetic sensing elements R1, R2, R3, and R4 can be Hall magnetoresistive, AMR magnetoresistive, GMR magnetoresistive, or TMR magnetoresistive.

[0038] The second aspect of this application provides a cascaded chip comprising: an MCU module, an integrated magnetic switch chipset, and a resistor R5;

[0039] The MCU module includes an IN_LH interface and a START interface;

[0040] The IN_LH interface of the MCU module is connected to the first end of resistor R5;

[0041] The IN_LH interface of the MCU module is connected to the output pin OUT of each integrated magnetic switch chip in the integrated magnetic switch chipset;

[0042] The START interface of the MCU module is connected to the integrated magnetic switch chipset;

[0043] The second terminal of resistor R5 is connected to the power supply VCC;

[0044] In an integrated magnetic switch chipset, the ground pin GND of each integrated magnetic switch chip is grounded.

[0045] In the integrated magnetic switch chipset, the power supply module of each integrated magnetic switch chip is connected to the power supply VCC.

[0046] Optionally, the clock input pin CKI of the first integrated magnetic switch chip in the integrated magnetic switch chipset is connected to the START interface of the MCU module.

[0047] The clock transmit pin CKO of the first integrated magnetic switch chip is connected to the clock input pin CKI of the second integrated magnetic switch chip;

[0048] The clock transmit pin CKO of the (n-1)th integrated magnetic switch chip is connected to the clock input pin CKI of the nth integrated magnetic switch chip.

[0049] As can be seen from the above technical solutions, the embodiments of this application have the following advantages:

[0050] In this application, the integrated magnetic switch chip specifically includes a Wheatstone bridge, a low-offset amplifier, a first Schmitt trigger, a second Schmitt trigger, a power supply module, a digital control module (Digital Control), a first NMOS transistor, a second NMOS transistor, a ground pin (GND), a clock input pin (CKI), a clock transmit pin (CKO), and an output pin (OUT). The digital control module is connected to the CNT module. The specific connection method is as follows: the power supply module is connected to the Wheatstone bridge, the low-offset amplifier, and the first Schmitt trigger. The Wheatstone bridge is connected to the low-offset amplifier and the first NMOS transistor. The digital control module is connected to the low-offset amplifier, the first Schmitt trigger, the second Schmitt trigger, the clock input pin (CKI), the clock transmit pin (CKO), and the first NMOS transistor. The first Schmitt trigger is connected to the low-offset amplifier and the second NMOS transistor. The output pin (OUT) is connected to the second Schmitt trigger and the second NMOS transistor. Both the first and second NMOS transistors are connected to the ground pin (GND). The CNT module is configured within the Digital Control module and used for operation. Specifically, the CNT module counts the cycles of the signal input to the CKI. The integrated magnetic switch chip is enabled only when the count result equals the chip number. This ensures that only one chip operates at a time, preventing clock frequency congestion that could lead to multiple chips working simultaneously. This reduces GND fluctuations and lowers the port sampling voltage V. ADC Interference was reduced, improving the accuracy of data acquisition for integrated magnetic switch chips. Attached Figure Description

[0051] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0052] Figure 1 This is a schematic diagram of a chip system architecture for the integrated magnetic switch chip in this application;

[0053] Figure 2 This is a schematic diagram of key waveforms of the integrated magnetic switch chip in Active operating mode in this application;

[0054] Figure 3 This is a schematic diagram of key waveforms of the integrated magnetic switch chip in the Reset operating mode in this application;

[0055] Figure 4 This is a schematic diagram of the power-on process of the integrated magnetic switch chip in this application;

[0056] Figure 5 This is a schematic diagram of the clock calibration and switch numbering mode of the integrated magnetic switch chip in this application;

[0057] Figure 6 This is a timing diagram illustrating the configuration mode of the integrated magnetic switch chip in this application;

[0058] Figure 7 This is a schematic diagram of the external module of the Digital Control digital control module with integrated magnetic switch chip in this application;

[0059] Figure 8 This is a schematic diagram of a chip system architecture for the cascaded chip in this application;

[0060] Figure 9 This is a schematic diagram of the key signal waveforms of the cascaded chip in this application;

[0061] Figure 10 This is a schematic diagram of the key waveforms of the i-th chip Ui in the cascaded chips of this application. Detailed Implementation

[0062] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of this application with unnecessary detail.

[0063] It should be understood that, when used in this application specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or a collection thereof.

[0064] It should also be understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0065] As used in this application specification and the appended claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if detected [the described condition or event]" may be interpreted, depending on the context, as meaning "once determined," "in response to determination," "once detected [the described condition or event]," or "in response to detection [the described condition or event]."

[0066] Furthermore, in the description of this application and the appended claims, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0067] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0068] In existing technologies, industrial applications commonly require the measurement of various non-electrical physical quantities, such as temperature, pressure, and liquid level. These quantities must be converted into analog electrical signals by transmitters before being transmitted to control rooms or display devices hundreds of meters away. Currently, the most widely used transmitter in industrial testing is the 4-20mA current transmitter. The reason for using current signals is their resistance to interference. Furthermore, the current source has infinite internal resistance, and the resistance of the wires connected in series in the loop does not affect accuracy. It can transmit over hundreds of meters on ordinary twisted-pair cables. In industrial applications, the distance between the measuring equipment and the control room or display device can be tens to hundreds of meters. For cost reasons, two-wire 4-20mA current transmitters are commonly used. The upper limit is set at 20mA because of explosion-proof requirements: the spark energy caused by the switching of a 20mA current is insufficient to ignite gas. The lower limit is not set to 0mA to allow for the detection of broken wires. During normal operation, the current will not be lower than 4mA, so the power consumption of the measured device and the signal conditioning circuit must be less than 4mA; otherwise, the transmitter cannot output a 4mA zero potential.

[0069] Currently, in the operation of detecting the liquid level in industrial water storage devices, non-contact liquid level detection schemes are usually selected, such as radar liquid level detection, infrared liquid level detection, and ultrasonic liquid level detection. However, the main drawbacks of the above schemes are: (1) The above schemes are expensive, have slow response speed, low sensitivity, require regular maintenance, and have short lifespan. (2) The liquid level measurement range of the above schemes is generally no more than 20m. When the required liquid level height and its accuracy requirements are high, the power consumption will exceed the minimum current (4mA) of the 4-20mA transmitter, which cannot meet the high-precision liquid level measurement requirements of large industrial liquid storage devices.

[0070] Traditional low-power magnetic switch liquid level detection schemes use reed switches. A magnetic float is placed inside the industrial water storage device, and the reed switches are cascaded at equal intervals along the device wall. The reed switches detect the external magnetic field and break the circuit through mechanical movement, making them ideal switching devices in electrical engineering. They have a simple structure, are easy to manufacture, and have low power consumption, making them widely used in liquid level detection. However, they also have shortcomings: (1) low accuracy and sensitivity, poor reliability, and cannot meet the requirements for real-time high-precision liquid level detection. (2) Because they are mechanical active switches, they have a short lifespan, are sensitive to vibration, have a large size, and are difficult to integrate.

[0071] To address the aforementioned technical shortcomings, a traditional integrated magnetic switch chip was proposed to replace the reed switch. This integrated magnetic switch chip periodically detects the external magnetic field using a wake-up-sleep cycle, with its internal timer configured so that only one chip is awake at any given time, achieving low-power, high-precision liquid level detection. However, during application, it was discovered that the clock frequency of the internal timer in the traditional integrated magnetic switch chip is random, with a probability that multiple chips will be awake simultaneously, a phenomenon known as frequency concurrency. Since there is no communication between the cascaded chips, this frequency concurrency cannot be eliminated. This concurrency causes large fluctuations in GND, interfering with the port sampling voltage VADC and leading to incorrect liquid level height reporting. In other words, the frequency concurrency reduces the accuracy of data acquisition by the integrated magnetic switch chip.

[0072] Furthermore, the co-frequency phenomenon will cause a sudden surge in current, leading to overload of the power supply chip. If the power supply chip does not have overcurrent limiting, it may burn out. The co-frequency phenomenon also causes a drop in the chip's supply voltage, which may lead to abnormal chip reset.

[0073] Based on this, this application discloses an integrated magnetic switch chip to improve the accuracy of data acquisition by the integrated magnetic switch chip.

[0074] The technical solutions of this application will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0075] Please see Figure 1 , Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 and Figure 9 This application provides an embodiment of an integrated magnetic switch chip, comprising:

[0076] Wheatstone bridge, low offset amplifier, first Schmitt trigger, second Schmitt trigger, power supply module, digital control module, first NMOS transistor, second NMOS transistor, ground pin GND, clock input pin CKI, clock transmit pin CKO, output pin OUT, and settings in the digital control module are related to the CNT module.

[0077] The power supply module is connected to the Wheatstone bridge, the low offset amplifier, and the first Schmitt trigger, respectively.

[0078] The Wheatstone bridge is connected to the low offset amplifier and the first transistor NMOS, respectively.

[0079] The Digital Control module is connected to the low offset amplifier, the first Schmitt trigger, the second Schmitt trigger, the clock input pin CKI, the clock transmit pin CKO, and the first transistor NMOS, respectively.

[0080] The first Schmitt trigger is connected to the low offset amplifier and the second NMOS transistor, respectively;

[0081] The output pin OUT is connected to the second Schmitt trigger and the second NMOS transistor, respectively;

[0082] Both the first NMOS transistor and the second NMOS transistor are connected to the ground pin GND.

[0083] In this embodiment, the integrated magnetic switch chip can sense changes in the external magnetic field, convert the magnetic signal into an electrical signal, and then compare the potential of this signal with a set threshold voltage through an integrated circuit. The result is output via open-drain, and the output level is used to represent the signal. The integrated magnetic switch chip has a power supply voltage range of 1.65V-5.5V and an operating temperature of -40-125℃. In this embodiment, the integrated magnetic switch chip operates in a wake-up-sleep cycle during magnetic field detection, and the wake-up-sleep cycle is adjustable. Specifically, the five pins are: power supply voltage pin VCC, ground pin GND, clock input pin CKI, clock transmit pin CKO, and output pin OUT. The power supply voltage pin VCC is located in the power supply module.

[0084] The integrated magnetic switch chip in this embodiment can meet the low-power, high-precision liquid level measurement requirements of medium and large industrial liquid storage devices, reduce the co-frequency phenomenon, and improve the accuracy of data acquisition by the integrated magnetic switch chip.

[0085] The clock input pin CKI of the integrated magnetic switch chip has multiple functions: one is as the clock input in CNT mode, the second is as the RST of the CNT mode chip, the third is as the enable in Active mode, and the fourth is as the communication interface in configuration mode to receive data from the upper-level or host MCU.

[0086] The clock transmit pin (CKO) of the integrated magnetic switch chip also has multiple functions. One is as a clock output in CNT mode, and the second is as a communication interface in configuration mode to transmit configuration data to the lower level.

[0087] The low-power magnetic switch chip can be configured to support both single-chip and multi-chip cascade applications. This will be described in detail later.

[0088] Optionally, the integrated magnetic switch chip may also include a low-power clock OSC;

[0089] The low-power clock OSC is connected to the digital control module.

[0090] Optionally, the Digital Control module is divided into internal modules and external modules;

[0091] External modules include the CONFIG_EN module, the cutoff enable module, the CNT module, and the OSC TRIM module;

[0092] The CONFIG_EN module is connected to the cutoff enable module and the second Schmitt trigger, respectively.

[0093] The cutoff enable module is connected to the CNT module, the clock input pin CKI, and the clock transmit pin CKO, respectively.

[0094] The OSC TRIM module connects to the low-power clock OSC;

[0095] The OSC TRIM module is connected to the internal module via the CLK signal line;

[0096] The CNT module is connected to the internal module via the DUT_EN signal line;

[0097] The CNT module is connected to the clock input pin CKI.

[0098] Optionally, the cutoff enable modules include the Tgate module and the RX / TX module;

[0099] The Tgate module is connected to the CONFIG_EN module, the clock input pin CKI, and the clock transmit pin CKO, respectively.

[0100] The RX / TX modules are connected to the CNT module, the clock input pin CKI, and the clock transmit pin CKO, respectively.

[0101] OSC is the chip's internal clock, controlling the magnetic field detection cycle. The second flip-flop's main function is to prevent false triggering of the OUT pin; it only enters the designated state when OUT is pulled low for a set period. vreg provides the power supply voltage to the Wheatstone bridge and the low-offset amplifier. The low-offset amplifier amplifies the output signal induced by the bridge and inputs it to the Schmitt trigger. When the amplified signal exceeds the threshold of the Schmitt trigger, the output of the Schmitt trigger reverses, thus realizing the basic function of a magnetic switch.

[0102] Please refer to Figure 2 and Figure 3 , Figure 2 and Figure 3This is a schematic diagram of key waveforms for the integrated magnetic switch chip in both Active and single-chip Reset operating modes.

[0103] When configured for a single-chip application, there are two operating modes: single-chip Active and single-chip Reset. When the high-level time t of pin CKI is greater than T... s1 (i.e., t>T) s1 When Ts1 is a preset time threshold, the chip will enter Active mode, enabling a self-loop wake-up-sleep mode that detects external magnetic fields: In wake-up mode, all internal circuit modules are enabled, detect external magnetic fields, refresh the detection results, and send them to pin OUT (output pin OUT); in sleep mode, all circuit modules are disabled, and only the built-in low-power clock operates. When the low-level time t of pin CKI is greater than T... RST When (t>T) RST T RST When another preset time threshold is reached, the chip will enter Reset mode, resetting the chip. Only the built-in low-power clock OSC and some digital control modules will operate, and pin OUT will return to a high-impedance state. In single-chip applications, the chip's wake-up-sleep cycle will first be set in configuration mode. In single-chip applications, pins CKI and CKO are directly connected.

[0104] Where CKI is the input voltage waveform signal of the chip at the CKI pin, and i represents the chip number of the cascaded multiple chips. cc (i) represents the current consumption of the i-th chip, and OUT(i) represents the output of the i-th chip.

[0105] Please refer to Figure 4 , Figure 4 This is a schematic diagram of the power-on process for an integrated magnetic switch chip. First, a VDD power-on operation is performed, starting via a low-power always-on OSC, pulling the OSC_OK signal high. In this embodiment, the OSC_OK signal going high indicates clock startup is complete. The OUT pin is monitored for being pulled low. If not, it continues monitoring. If it is pulled low, it checks if the OUT pin has changed from high to low and if the low-level duration T is greater than TENC. If yes, it enters the configuration mode; otherwise, it waits again. When configuration is successful, it checks if the CKI pin is high. If yes, it checks if the high-level duration t is less than a preset value T. s1 If t is greater than T, then proceed to CNT mode; if t is greater than T, then proceed to Active mode. RST When this happens, it enters Reset mode.

[0106] After the integrated magnetic switch chip is powered on, the OUT pin enters the signal receiving state. When the OUT pin is pulled low from high level and the low level time T is greater than T... ENC (T>TENC T ENC The chip enters configuration mode when a preset time threshold is reached. A single chip enters configuration mode after a configuration time TCONFIG (where T is the time threshold). CONFIG After 20 * CLK, the calibration is completed and exited from the calibration mode, while multi-chip calibration requires a configuration time of N * T. CONFIG (N is the number of cascaded chips) After completing and exiting the calibration mode; enable the receiver pin CKI to enter the signal receiving state, and determine the working mode to enter based on the high level time t of the input signal.

[0107] Please refer to Figure 5 , Figure 5 This is a schematic diagram of the clock calibration and switch numbering mode for an integrated magnetic switch chip.

[0108] INT_LH is a pin signal of the MCU in the cascaded chip, T OUTL That is, the time T is pulled low on the chip's OUT pin. ENC It is the time specified by any designer.

[0109] CKI(1) is the CKI signal corresponding to the first chip, and CKO(N) is the CKO signal corresponding to the Nth chip.

[0110] Figure 6 The timing diagram for the configuration mode chip is as follows: Handshake: 2*CLK, Clock calibration: 2*CLK, Calibration accuracy 1%, Mode setting: 2*CLK, 00: Encoding; 01: Active reset time; 10: PreOP gain, Data encoding: 12*CLK, 12-bit configurable code value, End flag: 2*CLK.

[0111] The OUT pin is pulled low from high level and the low level time T is greater than T. ENC (T>T ENCWhen the chip enters configuration mode, it completes the Active reset time setting or sequence number encoding setting by sending commands to CKI: 1) Active reset time setting in single-chip application: Mode setting value 01, sets the Active mode chip reset time, with a total of 13 levels: 0 / 0.1 / 0.2 / 0.4 / 0.8 / 1 / 2 / 4 / 8 / 16 / 32 / 64 / 128ms. 2) Sequence number encoding mode in multi-chip cascade application: Mode setting value 00, the host MCU writes sequence number 1 to the first chip, and after the first chip is written, it writes sequence number 2 to the second chip through CKO, and so on, until all chip sequence numbers are written, supporting a maximum of 4095 sequence number values; if the i-th chip configuration fails, it will feed back the write code to the host through the CKO / CKI bus; if everything is normal, no feedback signal will be given. After the chip is configured, it automatically enters CNT working mode, listening to and counting the clock signal of the input pin CKI. In configuration mode, commands are sent to CKI. The command packet timing is as follows: The first two clock cycles complete the handshake, and the next two clock cycles complete clock calibration with a calibration accuracy of 1%. The fifth and sixth clock cycles complete the mode setting, where mode setting value 00 is the sequence number encoding and mode setting value 01 is the Active reset time setting. The next 12 clock cycles set the 12-bit code value. The last two clock cycles are the end marker, completing and exiting the configuration mode.

[0112] Please refer to Figure 7 , Figure 7 This is a schematic diagram of the external module of the Digital Control module. The specific configuration mode scheme is as follows: When pin OUT detects a pull-down from high to low and the low-level duration T is greater than T... ENC (T>T ENC When the configuration is complete, the CONFIG_EN module sends a signal to the Tgate & RX / TX module (ring enable module), turning Tgate off and RX / TX enabled. Pins CKI and CKO are no longer pass-through, and the Tgate & RX / TX module sends a signal to the CNT module to turn it off. Pin CKI receives external input commands to complete the Active reset time setting or sequence number encoding setting. After chip configuration is complete, the CNT module is re-enabled, and pin CKI transmits the command to pin CKO via TX and inputs it into pin CKI of the next chip. If the configuration fails, pin CKO will feed back the write code to the host via RX and pin CKI.

[0113] The CNT module is a serial number configuration module used for counting. The chip is enabled when the period of the signal input from the CKI pin equals the set chip number. The DUT_EN input is sent to the internal module of the digital control module. clk is the on-chip clock, which is also input to the internal module of the digital control module as a digital clock signal.

[0114] Optionally, the power supply module includes a power supply voltage pin VCC and a reference voltage module VREG;

[0115] The power supply voltage pin VCC is connected to the reference voltage module VREG.

[0116] The reference voltage module VREG is connected to the Wheatstone bridge, the low offset amplifier, and the first Schmitt trigger, respectively.

[0117] Optionally, the Wheatstone bridge consists of magnetic sensitive elements R1, R2, R3, and R4.

[0118] Magnetic elements R1, R2, R3, and R4 are connected in sequence to form a bridge circuit.

[0119] Optionally, the interfaces of magnetic sensing elements R1 and R2 are connected to a low offset amplifier;

[0120] The interfaces of magnetic sensitive elements R3 and R4 are connected to the low offset amplifier;

[0121] The interfaces of magnetic sensing elements R2 and R3 are connected to the first transistor NMOS;

[0122] The interfaces of magnetic sensitive elements R1 and R4 are connected to the power supply module.

[0123] Optionally, the magnetic sensing elements R1, R2, R3, and R4 can be Hall magnetoresistive, AMR magnetoresistive, GMR magnetoresistive, or TMR magnetoresistive.

[0124] Please refer to Figure 8 , Figures 9 to 10 . Figure 8 This is a schematic diagram of a cascaded chip structure. Figure 9 This is a schematic diagram of the key signal waveforms of a cascaded chip. Figure 10 This is a schematic diagram of the key waveforms of the i-th chip Ui in a cascaded chip system.

[0125] Optionally, the cascaded chips include an MCU module, an integrated magnetic switch chipset, and a resistor R5;

[0126] The MCU module includes an IN_LH interface and a START interface;

[0127] The IN_LH interface of the MCU module is connected to the first end of resistor R5;

[0128] The IN_LH interface of the MCU module is connected to the output pin OUT of each integrated magnetic switch chip in the integrated magnetic switch chipset;

[0129] The START interface of the MCU module is connected to the integrated magnetic switch chipset;

[0130] The second terminal of resistor R5 is connected to the power supply VCC;

[0131] In an integrated magnetic switch chipset, the ground pin GND of each integrated magnetic switch chip is grounded.

[0132] In the integrated magnetic switch chipset, the power supply module of each integrated magnetic switch chip is connected to the power supply VCC.

[0133] Optionally, the clock input pin CKI of the first integrated magnetic switch chip in the integrated magnetic switch chipset is connected to the START interface of the MCU module.

[0134] The clock transmit pin CKO of the first integrated magnetic switch chip is connected to the clock input pin CKI of the second integrated magnetic switch chip;

[0135] The clock transmit pin CKO of the (n-1)th integrated magnetic switch chip is connected to the clock input pin CKI of the nth integrated magnetic switch chip.

[0136] Please refer to Figure 8 and Figure 9 The cascaded chip consists of an MCU, a pull-up resistor R5, a magnetic float, and multiple chips arranged in series at equal intervals. The START pin of the MCU is connected to the CKI(1) pin of the first chip U1, and the CK0(i) pin of the i-th chip Ui is connected to the CKI(i-1) pin of the (i-1)-th chip U(i-1) (i = 2 to n). The output pin OUT of all magnetic switch chips is connected to the INT_LH pin of the MCU and the pull-up resistor R. The power supply voltage pin VCC of the magnetic switch chip is connected to the power supply VCC at the other end of the pull-up resistor.

[0137] like Figure 10 As shown, when the high-level time t of pin CKI is less than T s1 (t <T s1When the chip enters CNT mode, a clock signal is continuously sent to pin CKI. Only when the number of CKI clock cycles equals the chip's set sequence number will the internal circuit modules of the chip be enabled, detecting the external magnetic field, refreshing the detection result, and sending it to pin OUT. After detection, it automatically enters Reset mode, resetting the chip. Only the built-in low-power clock and some digital control modules operate, and pin OUT returns to a high-impedance state. In multi-chip cascaded applications, the chip sequence number will first be set in configuration mode. In multi-chip cascaded applications, pins CKI and CKO are directly connected.

[0138] When configured for multi-chip cascading applications, there are two operating modes: multi-chip CNT and multi-chip Reset. When the high-level time t of pin CKI is less than T... s1 (t <T s1 When the chip enters CNT mode, a clock signal is continuously sent to pin CKI. Only when the number of CKI clock cycles equals the chip's set sequence number will the internal circuit modules of the chip be enabled, detecting the external magnetic field, refreshing the detection result, and sending it to pin OUT. After detection, it automatically enters Reset mode, resetting the chip. Only the built-in low-power clock and some digital control modules operate, and pin OUT returns to a high-impedance state. In multi-chip cascaded applications, the chip sequence number will first be set in configuration mode. In multi-chip cascaded applications, pins CKI and CKO are directly connected.

[0139] After the chip powers on, the OUT pin enters the signal receiving state. When the OUT pin is pulled low from high and the low-level time T is greater than TENC (T>TENC), the chip enters the configuration mode. The single chip then enters configuration mode after a configuration time T. CONFIG (T CONFIG After 20 * CLK, the calibration is completed and exited from the calibration mode, while multi-chip calibration requires a configuration time of N * T. CONFIG (N is the number of cascaded chips) After completing and exiting the calibration mode; enable the receiver pin CKI to enter the signal receiving state, and determine the working mode to enter based on the high level time t of the input signal.

[0140] When pin OUT is pulled low from high and the low-level time T is greater than TENC (T>TENC), it enters chip configuration mode. Active reset time setting or sequence number encoding setting is completed by sending commands to CKI (refer to timing instructions for command packets): 1) Active reset time setting in single-chip applications: Mode setting value 01 sets the active mode chip reset time, with a total of 13 levels: 0 / 0.1 / 0.2 / 0.4 / 0.8 / 1 / 2 / 4 / 8 / 16 / 32 / 64 / 128ms. 2) Sequence number encoding mode in multi-chip cascade applications: Mode setting value 00, the host MCU writes sequence number 1 to the first chip. After the first chip is written, sequence number 2 is written to the second chip via CKO, and so on, until all chip sequence numbers are written, supporting a maximum of 4095 sequence number values. If the i-th chip configuration fails, the write code will be fed back to the host via the CKO / CKI bus; if everything is normal, no feedback signal will be given. After configuration, the chip automatically enters CNT working mode, listening to and counting the clock signal of the input pin CKI.

[0141] The specific configuration mode scheme is as follows: When pin OUT detects a pull-down from high level to low level and the low level duration T is greater than T... ENC (T>T ENC When the configuration is complete, the CONFIG_EN module sends a signal to the Tgate & RX / TX module, turning Tgate off and enabling RX / TX. Pins CKI and CKO are no longer pass-through, and the Tgate & RX / TX module sends a signal to the CNT module to turn it off. Pin CKI receives external input commands to complete the Active reset time setting or sequence number encoding setting. After chip configuration is complete, the CNT module is re-enabled, and pin CKI transmits the command to pin CKO via TX and inputs it into pin CKI of the next chip. If the configuration fails, pin CKO will feed back the write code to the host via RX and pin CKI.

[0142] In configuration mode, commands are sent to CKI. The command packet timing is as follows: The first two clock cycles complete the handshake, and the next two clock cycles complete clock calibration with a calibration accuracy of 1%. The fifth and sixth clock cycles complete the mode setting, where mode setting value 00 is the sequence number encoding and mode setting value 01 is the Active reset time setting. The next 12 clock cycles set the 12-bit code value. The last two clock cycles are the end marker, completing and exiting the configuration mode.

[0143] One application scenario in the multi-chip cascade mode is a high-precision, low-power liquid level detection scheme, which includes an MCU, a pull-up resistor, a magnetic float, and multiple chips arranged in series at equal intervals. The START pin of the MCU is connected to the CKI(1) pin of the first chip U1, and the CK0(i) pin of the i-th chip Ui is connected to the CKI(i-1) pin of the (i-1)-th chip U(i-1) (i = 2 to n). The output pin OUT of all magnetic switch chips is connected to the INT_LH pin of the MCU and the pull-up resistor R. The power supply voltage pin VCC of the magnetic switch chip is connected to the power supply VCC at the other end of the pull-up resistor.

[0144] The liquid level detection process is as follows: Magnetic switch chips are arranged at equal intervals along the wall of the device, with each unit interval set to LSB. After the chip serial number is configured, the device enters CNT mode. The MCU's START pin continuously sends clock signals to the chip tape. Each chip's CKO pin is directly connected to CKI and counts the number of CKI rises. Only when the number of CKI clock cycles count equals the chip's set serial number i, the internal circuit modules of the chip are enabled to work, detect the external magnetic field, refresh the magnetic field detection result, and send it to the OUT pin. After the detection is completed, the device automatically enters Reset mode, the chip is reset, and only the built-in low-power clock and some digital control modules work. The OUT pin returns to a high-impedance state. There is a magnetic float on the liquid surface. When the liquid level reaches a certain height, the magnetic switch Ui near the float will close, and the pull-up resistor connected to the OUT(i) pin of the magnetic switch chip Ui will be pulled to GND. The voltage of the MCU's INT_LH pin will also be pulled to GND. At this time, the count value i directly corresponds to the liquid level height, that is, the measured liquid level height is:

[0145] Height = i * LSB

[0146] The above liquid level detection solution eliminates the need for series resistors, corresponding bias circuits, and high-precision ADCs required in traditional solutions. The MCU counts the time from the start signal to the INT_Line being pulled low to calculate the liquid level height, making the solution simple and reliable.

[0147] In the above liquid level detection scheme, the chips work sequentially. At any given time, only one low-power magnetic switch chip is awakened, and the power consumption of a single low-power magnetic switch chip does not exceed 500nA, which meets the minimum current limit of industrial 4-20mA transmitters, thus realizing low-power detection of liquid level in medium and large liquid storage devices.

[0148] In the above liquid level detection scheme, the chips are arranged with LSBs at equal intervals. Assuming the height of the liquid storage device is FS_Height, the liquid level measurement accuracy is:

[0149]

[0150] The following example illustrates this: assuming the LSB is 1 cm, if the height of the liquid storage device is 10 m, the liquid level measurement accuracy is 1‰; if the height of the liquid storage device is 40 m, the liquid level accuracy is 0.25‰, thus achieving high-precision liquid level detection for medium and large-sized liquid storage devices.

[0151] In this application, the terms "upper", "lower", "left", "right", "front", "rear", "top", "bottom", "inner", "outer", "middle", "vertical", "horizontal", "lateral", "longitudinal" and other terms indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only used to describe the relative positional relationship between the components or parts and do not specifically limit the specific installation orientation of each component or part.

[0152] Furthermore, in addition to indicating location or positional relationship, some of the aforementioned terms may also have other meanings. For example, the term "above" may also be used in some cases to indicate a certain dependency or connection relationship. Those skilled in the art can understand the specific meaning of these terms in this application based on the specific circumstances.

[0153] Furthermore, the terms "installation," "setup," "equipped with," "connection," and "linked" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral structure; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium, or an internal connection between two devices, components, or parts. Those skilled in the art can understand the specific meaning of these terms in this application based on the specific circumstances.

[0154] Furthermore, the structures, proportions, sizes, etc., drawn in the accompanying drawings of this application are only used to complement the content disclosed in the specification for those skilled in the art to understand and read, and are not intended to limit the conditions under which this application can be implemented. Therefore, they have no substantial technical significance. Any modification to the structure, change in the proportional relationship, or adjustment of the size, without affecting the effects and purposes that this application can produce, should still fall within the scope of the technical content disclosed in this application.

Claims

1. An integrated magnetic switch chip, characterized in that, include: The system includes a Wheatstone bridge, a low offset amplifier, a first Schmitt trigger, a second Schmitt trigger, a power supply module, a digital control module, a first NMOS transistor, a second NMOS transistor, a ground pin (GND), a clock input pin (CKI), a clock transmit pin (CKO), and an output pin (OUT). The digital control module includes a CNT module, which counts the cycles of the signal input to CKI. The integrated magnetic switch chip is enabled only when the count result equals the chip number, and only one chip operates at a time. The power supply module is connected to the Wheatstone bridge, the low offset amplifier, and the first Schmitt trigger, respectively. The Wheatstone bridge is connected to the low offset amplifier and the first transistor NMOS, respectively. The Digital Control module is connected to the low offset amplifier, the first Schmitt trigger, the second Schmitt trigger, the clock input pin CKI, the clock transmit pin CKO, and the first transistor NMOS, respectively. The first Schmitt trigger is connected to the low offset amplifier and the second NMOS transistor, respectively; The output pin OUT is connected to the second Schmitt trigger and the second NMOS transistor, respectively. Both the first NMOS transistor and the second NMOS transistor are connected to the ground pin GND.

2. The integrated magnetic switch chip according to claim 1, characterized in that, The integrated magnetic switch chip also includes a low-power clock OSC; The low-power clock OSC is connected to the digital control module.

3. The integrated magnetic switch chip according to claim 2, characterized in that, The DigitalControl module is divided into an internal module and an external module; The external modules include the CONFIG_EN module, the cutoff enable module, the CNT module, and the OSC TRIM module; The CONFIG_EN module is connected to the cutoff enable module and the second Schmitt trigger, respectively. The cutoff enable module is connected to the CNT module, the clock input pin CKI, and the clock transmit pin CKO, respectively. The OSC TRIM module is connected to the low-power clock OSC; The OSC TRIM module is connected to the internal module via the CLK signal line; The CNT module is connected to the internal module via the DUT_EN signal line; The CNT module is connected to the clock input pin CKI.

4. The integrated magnetic switch chip according to claim 3, characterized in that, The cutoff enable module includes a Tgate module and an RX / TX module; The Tgate module is connected to the CONFIG_EN module, the clock input pin CKI, and the clock transmit pin CKO, respectively. The RX / TX module is connected to the CNT module, the clock input pin CKI, and the clock transmit pin CKO, respectively.

5. The integrated magnetic switch chip according to claim 1, characterized in that, The power supply module includes a power supply voltage pin VCC and a reference voltage module VREG. The power supply voltage pin VCC is connected to the reference voltage module VREG; The reference voltage module VREG is connected to the Wheatstone bridge, the low offset amplifier, and the first Schmitt trigger, respectively.

6. The integrated magnetic switch chip according to any one of claims 1 to 5, characterized in that, The Wheatstone bridge is composed of magnetic sensitive elements R1, R2, R3, and R4. The magnetic sensitive elements R1, R2, R3, and R4 are connected in sequence to form a bridge circuit.

7. The integrated magnetic switch chip according to claim 6, characterized in that, The interfaces of the magnetic sensitive element R1 and the magnetic sensitive element R2 are connected to the low offset amplifier; The interfaces of the magnetic sensitive element R3 and the magnetic sensitive element R4 are connected to the low offset amplifier; The interfaces of the magnetic sensitive elements R2 and R3 are connected to the first transistor NMOS. The interfaces of the magnetic sensitive elements R1 and R4 are connected to the power supply module.

8. The integrated magnetic switch chip according to claim 6, characterized in that, The magnetic sensing elements R1, R2, R3, and R4 are Hall magnetoresistive, AMR magnetoresistive, GMR magnetoresistive, or TMR magnetoresistive.

9. A cascaded chip based on the integrated magnetic switch chip as described in claim 1, characterized in that, The cascaded chip includes an MCU module, an integrated magnetic switch chipset, and a resistor R5; The MCU module includes an IN_LH interface and a START interface; The IN_LH interface of the MCU module is connected to the first end of the resistor R5; The IN_LH interface of the MCU module is connected to the output pin OUT of each integrated magnetic switch chip in the integrated magnetic switch chipset. The START interface of the MCU module is connected to the integrated magnetic switch chipset; The second end of the resistor R5 is connected to the power supply VCC. The ground pin GND of each integrated magnetic switch chip in the integrated magnetic switch chipset is grounded. The power supply module of each integrated magnetic switch chip in the integrated magnetic switch chipset is connected to power supply VCC.

10. The cascaded chip according to claim 9, characterized in that, The clock input pin CKI of the first integrated magnetic switch chip in the integrated magnetic switch chipset is connected to the START interface of the MCU module. The clock transmit pin CKO of the first integrated magnetic switch chip is connected to the clock input pin CKI of the second integrated magnetic switch chip; The clock transmit pin CKO of the (n-1)th integrated magnetic switch chip is connected to the clock input pin CKI of the nth integrated magnetic switch chip.

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