Package including integrated devices and passive devices

Abstract

A package includes a first integrated device, an interposer coupled to the first integrated device, a passive device coupled to the first integrated device, a plurality of pillar interconnects coupled to the first integrated device, a second integrated device coupled to the interposer, the passive device, and the plurality of pillar interconnects, and an encapsulation layer between the first integrated device and the second integrated device.

Description

Cross-reference to related applications

[0001] This application claims priority and benefit to U.S. Non-Provisional Application Serial No. 18 / 540,542, filed December 14, 2023, with the United States Patent and Trademark Office, the entire contents of which are incorporated herein by reference as if fully set forth herein and for all applicable purposes. Technical Field

[0002] Various features involve packages with integrated devices. Background Technology

[0003] Packages may include various components, including integrated devices. There is a continued need for smaller packages with improved performance, such as packages with improved passive device performance and / or packages with reliable and robust connector connections for passive devices within the package. Summary of the Invention

[0004] Various features involve packages with integrated devices.

[0005] One example provides a package comprising: a first integrated device; an interposer coupled to the first integrated device; a passive device coupled to the first integrated device; a plurality of pillar interconnects coupled to the first integrated device; a second integrated device coupled to the interposer, the passive device, and the plurality of pillar interconnects; and an encapsulation layer located between the first integrated device and the second integrated device.

[0006] Another example provides a method for manufacturing a package. The method provides a first integrated device. The method forms a first encapsulation layer coupled to the first integrated device. The method forms a first metallization portion coupled to the first integrated device. The method couples an interposer to the first metallization portion. The method couples a passive device to the first metallization portion. The method forms a plurality of pillar interconnects coupled to the first metallization portion. The method forms a second encapsulation layer coupled to the first metallization portion, the interposer, the passive device, and the plurality of pillar interconnects. The method forms a second metallization portion coupled to the interposer, the passive device, and the plurality of pillar interconnects. The method couples a second integrated device to the second metallization portion. Attached Figure Description

[0007] The various features, essence, and advantages will become apparent when the detailed description set forth below is understood in conjunction with the accompanying drawings, in which similar reference characters are used for corresponding identification throughout.

[0008] Figure 1An exemplary cross-sectional view of a package having integrated devices and deep trench capacitor devices is shown.

[0009] Figure 2 An exemplary cross-sectional view of a package having integrated devices and deep trench capacitor devices is shown.

[0010] Figure 3 An exemplary cross-sectional view of a package having integrated devices and deep trench capacitor devices is shown.

[0011] Figure 4 An exemplary cross-sectional view of an integrated device is shown.

[0012] Figure 5 An exemplary cross-sectional view of a deep trench capacitor device is shown.

[0013] Figures 6A to 6D An exemplary process for manufacturing a package having integrated devices and deep trench capacitor devices is illustrated.

[0014] Figure 7 An exemplary flowchart illustrating a method for manufacturing a package having integrated devices and deep trench capacitor devices is shown.

[0015] Figures 8A to 8D An exemplary process for manufacturing a package having integrated devices and deep trench capacitor devices is illustrated.

[0016] Figure 9 An exemplary flowchart illustrating a method for manufacturing a package having integrated devices and deep trench capacitor devices is shown.

[0017] Figures 10A to 10B An exemplary process for manufacturing metallized parts is illustrated.

[0018] Figure 11 Examples are provided of various electronic devices that can integrate the dies, electronic circuits, integrated devices, integrated passive devices (IPDs), passive components, packages and / or device packages described herein. Detailed Implementation

[0019] In the following description, specific details are set forth to provide a thorough understanding of the various aspects of this disclosure. However, those skilled in the art will understand that these aspects can be practiced without these specific details. For example, circuits may be shown as block diagrams to avoid complicating these aspects with unnecessary detail. In other instances, well-known circuits, structures, and techniques may not be shown in detail to avoid complicating these aspects of this disclosure.

[0020] This disclosure describes a package comprising: a first integrated device; an interposer coupled to the first integrated device; a passive device coupled to the first integrated device; a plurality of pillar interconnects coupled to the first integrated device; a second integrated device coupled to the interposer, the passive device, and the plurality of pillar interconnects; and an encapsulation layer located between the first integrated device and the second integrated device. The passive device is located between the first integrated device and the second integrated device. The passive device may include a deep trench capacitor device located between the first integrated device and the second integrated device. In some embodiments, the positioning and / or location of the passive device between the two integrated devices helps to provide improved power distribution for the first integrated device and / or the second integrated device, thereby improving the performance in the first integrated device and / or the second integrated device.

[0021] Exemplary package with integrated devices and passive devices Figure 1 A cross-sectional view of a package 100 including integrated devices and passive devices is illustrated. The package 100 includes an integrated device 101, an encapsulation layer 102, an integrated device 103, a plurality of pillar interconnects 104, a plurality of passive devices 105, an interposer layer 107, and a plurality of solder interconnects 109. The plurality of passive devices 105 may include passive device 105a (e.g., a first passive device) and passive device 105b (e.g., a second passive device).

[0022] Integrated device 101 can be a first integrated device or a second integrated device. Integrated device 103 can be a first integrated device or a second integrated device. More detailed examples of integrated device 101 and / or integrated device 103 are given below. Figure 4 As described in the description. Integrated device 101 may include a front side and a back side. Integrated device 103 may include a front side and a back side. Integrated device 101 and / or integrated device 103 may include a die. A plurality of solder interconnects 109 may be coupled to the front side of integrated device 101. A plurality of solder interconnects 109 may be coupled to pad interconnects of integrated device 101.

[0023] Passive devices 105a and / or 105b may include silicon capacitors, deep trench capacitors (DTC), and / or deep trench capacitor (DTC) devices. The silicon capacitor may be a capacitor formed on a silicon substrate. For example, passive device 105a may include a silicon substrate 150, a plurality of deep trench capacitors 151, and a plurality of substrate vias 152. More detailed examples of deep trench capacitor devices are provided below. Figure 5 As described in the text.

[0024] Passive device 105a is coupled to integrated device 101 and integrated device 103. Passive device 105a can be coupled to the back side of integrated device 101 via at least a plurality of solder interconnects 108a. For example, the plurality of solder interconnects 108a can be coupled to a plurality of substrate vias (e.g., 152) of passive device 105a. The plurality of solder interconnects 108a can be coupled to a plurality of substrate vias of integrated device 101. Passive device 105a can be coupled to the front side of integrated device 101 via at least a plurality of solder interconnects 106a.

[0025] Passive device 105a may have a front side and a back side. The front side of passive device 105a may include a deep trench capacitor. The back side of passive device 105a may be opposite to the front side of passive device 105a. The front side of passive device 105a may face and / or point towards integrated device 103. In some embodiments, the front side of passive device 105a may face and / or point towards integrated device 101. In some embodiments, the front side of passive device 105a may be closer to integrated device 101 than the back side of passive device 105a.

[0026] Passive device 105b is coupled to integrated device 101 and integrated device 103. Passive device 105b is coupled to the back side of integrated device 101 via at least a plurality of solder interconnects 108b. For example, the plurality of solder interconnects 108b may be coupled to a plurality of substrate vias (e.g., 152) of passive device 105b. The plurality of solder interconnects 108b may be coupled to a plurality of substrate vias of integrated device 101. Passive device 105b may be coupled to the front side of integrated device 103 via at least a plurality of solder interconnects 106b.

[0027] Passive device 105b may have a front side and a back side. The front side of passive device 105b may include a deep trench capacitor. The back side of passive device 105b may be opposite to the front side of passive device 105b. The front side of passive device 105b may face and / or point towards integrated device 103. In some embodiments, the front side of passive device 105b may face and / or point towards integrated device 101. In some embodiments, the front side of passive device 105b may be closer to integrated device 101 than the back side of passive device 105b.

[0028] Multiple pillar interconnects 104 are coupled to integrated device 101 and integrated device 103. The multiple pillar interconnects 104 may be located between integrated device 101 and integrated device 103. The multiple pillar interconnects 104 may be located between the back side of integrated device 101 and the front side of integrated device 103. Therefore, the multiple pillar interconnects 104 may be coupled to (i) the back side of integrated device 101 and (ii) the front side of integrated device 103. The multiple pillar interconnects 104 may or may not contact (i) the back side of integrated device 101 and (ii) the front side of integrated device 103. In some specific embodiments, solder interconnects may be used to couple the multiple pillar interconnects 104 to integrated device 101 and / or integrated device 103. For example, a first plurality of solder interconnects may be used to couple the multiple pillar interconnects 104 to integrated device 101, and / or a second plurality of solder interconnects may be used to couple the multiple pillar interconnects 104 to integrated device 103.

[0029] Intermediate layer 107 is located between integrated device 101 and integrated device 103. Intermediate layer 107 may include a silicon substrate 170 and a plurality of intermediate interconnects 172. The plurality of intermediate interconnects 172 may include substrate vias. Intermediate layer 107 is coupled to integrated device 101 and integrated device 103. Intermediate layer 107 may be coupled to the back side of integrated device 101 via a plurality of solder interconnects 108c. Intermediate layer 107 may be coupled to the front side of integrated device 103 via a plurality of solder interconnects 106c. The pitch of the plurality of intermediate interconnects 172 of intermediate layer 107 may be smaller than the pitch of the plurality of pillar interconnects 104.

[0030] Encapsulation layer 102 is located between integrated device 101 and integrated device 103. Encapsulation layer 102 may contact the back side of integrated device 101 and the front side of integrated device 103. Encapsulation layer 102 may at least partially encapsulate passive device 105a, passive device 105b, interposer 107, and multiple pillar interconnects 104. Encapsulation layer 102 may at least partially encapsulate integrated device 103. Encapsulation layer 102 may include molding materials, resin, and / or epoxy resin. Encapsulation layer 102 may be a component for encapsulation. Encapsulation layer 102 may be provided using compression and transfer molding processes, sheet molding processes, or liquid molding processes.

[0031] Providing passive components 105a and / or 105b between two integrated devices offers several advantages. First, providing passive components between two integrated devices helps improve power distribution network performance because the passive components are closer to integrated devices 101 and / or 103. In some specific implementations, the power distribution network performance of integrated device 103 is significantly improved because the passive components are very close to the front side of integrated device 103. Furthermore, the positioning and / or location of the passive components helps avoid large loop inductance between the circuit and the power supply. Second, the positioning and / or location of the passive components and / or the interposer helps avoid offset of the top integrated components relative to the package to accommodate interconnects for power supply, thus making the package more compact or as compact as possible.

[0032] The electrical path between integrated device 101 and integrated device 103 may include components from integrated device 101, passive device 105a, and / or components from integrated device 103. The electrical path between integrated device 101 and integrated device 103 may include components from integrated device 101, interposer 107, and / or components from integrated device 103. The electrical path between integrated device 101 and integrated device 103 may include components from integrated device 101, multiple pillar interconnects 104, and / or components from integrated device 103. Examples of components of the integrated device that may be part of the electrical path are given below at least in Figure 4 Further details are provided below.

[0033] Figure 1 The example illustrates that the lateral dimension of integrated device 101 is larger than that of integrated device 103. For example, the width of integrated device 101 may be greater than the width of integrated device 103. However, in some embodiments, integrated device 101 may have a lateral dimension similar to or smaller than that of integrated device 103.

[0034] Figure 2 A cross-sectional view of a package 200 including integrated devices and passive devices is illustrated. Package 200 includes integrated device 101, integrated device 103, multiple pillar interconnects 104, multiple passive devices 105, an interposer 107, multiple solder interconnects 109, metallized portions 201, 203, 205, encapsulation layers 202, 204, and 206. The multiple passive devices 105 may include passive device 105a (e.g., a first passive device) and passive device 105b (e.g., a second passive device).

[0035] Package 200 is similar to Figure 1Package 100 provides similar technical advantages. However, package 200 includes metallization portions between some of these components. Any of the metallization portions (e.g., 201, 203, 205) can be a first metallization portion, a second metallization portion, or a third metallization portion. Different embodiments may have different numbers of metallization portions, and each metallization portion may have different or similar numbers of metal layers. Therefore, metallization portions 201, 203, and / or 205 are all optional. The metallization portions may be redistributed portions. Figure 2 The description utilizes all three metallized portions included in the package 200. However, any of the metallized portions may be optional and may be removed.

[0036] The front side of the integrated device 101 may be coupled to and contact the metallization portion 205. The metallization portion 205 may include at least one dielectric layer 250, a plurality of metallized interconnects 252, and a solder mask layer 254. The metallization portion 205 may include redistribution portions. The plurality of metallized interconnects 252 may include a plurality of redistributed interconnects. The plurality of metallized interconnects 252 may be coupled to pad interconnects of the integrated device 101. A plurality of solder interconnects 109 are coupled to the metallization portion 205. For example, the plurality of solder interconnects 109 are coupled to the plurality of metallized interconnects 252.

[0037] Metallization portion 203 is coupled to and contacts the back side of integrated device 101. Metallization portion 203 may include at least one dielectric layer 230 and a plurality of metallized interconnects 232. Metallization portion 203 may include redistribution portions. The plurality of metallized interconnects 232 may include a plurality of redistributed interconnects. The plurality of metallized interconnects 232 may be coupled to a substrate via of integrated device 101. Encapsulation layer 206 is coupled to and contacts integrated device 101, metallization portion 203, and metallization portion 205. Encapsulation layer 206 and integrated device 101 are located between metallization portion 203 and metallization portion 205.

[0038] The metallized portion 201 may include at least one dielectric layer 210 and a plurality of metallized interconnects 212. The metallized portion 201 may include a redistribution portion. The plurality of metallized interconnects 212 may include a plurality of redistributed interconnects.

[0039] Passive device 105a is coupled to metallized portion 203 via multiple solder interconnects 108a. The multiple solder interconnects 108a can be coupled to multiple metallized interconnects 232 of metallized portion 203. Passive device 105a is coupled to metallized portion 201 via multiple solder interconnects 106a. The multiple solder interconnects 106a can be coupled to multiple metallized interconnects 212 of metallized portion 201. Passive device 105b is coupled to metallized portion 203 via multiple solder interconnects 108b. The multiple solder interconnects 108b can be coupled to multiple metallized interconnects 232 of metallized portion 203. Passive device 105b is coupled to metallized portion 201 via multiple solder interconnects 106b. The multiple solder interconnects 106b can be coupled to multiple metallized interconnects 212 of metallized portion 201. Intermediate layer 107 is coupled to metallized portion 203 via a plurality of solder interconnects 108c. The plurality of solder interconnects 108c may be coupled to a plurality of metallized interconnects 232 of metallized portion 203. Intermediate layer 107 is coupled to metallized portion 201 via a plurality of solder interconnects 106c. The plurality of solder interconnects 106c may be coupled to a plurality of metallized interconnects 212 of metallized portion 201. A plurality of pillar interconnects 104 are coupled to metallized portion 201 and metallized portion 203. The plurality of pillar interconnects 104 may be coupled to a plurality of metallized interconnects 212 and / or a plurality of metallized interconnects 232. In some embodiments, solder interconnects may be used to couple the plurality of pillar interconnects 104 to metallized portion 201 and / or metallized portion 203. For example, a first plurality of solder interconnects may be used to couple a plurality of pillar interconnects 104 to a metallized interconnect of a metallized portion 201, and / or a second plurality of solder interconnects may be used to couple a plurality of pillar interconnects 104 to a metallized interconnect of a metallized portion 203.

[0040] Encapsulation layer 204 may be coupled to and contact metallized portion 201, metallized portion 203, multiple pillar interconnects 104, passive device 105a, passive device 105b and interposer 107. Encapsulation layer 204, multiple pillar interconnects 104, passive device 105a, passive device 105b and interposer 107 are located between metallized portion 201 and metallized portion 203.

[0041] Integrated device 103 is coupled to metallization portion 201. For example, the front side of integrated device 103 may be coupled to and contact metallization portion 201. Multiple metallization interconnects 212 may be coupled to pad interconnects of integrated device 103. Encapsulation layer 202 is coupled to and contacts metallization portion 201 and integrated device 103. Encapsulation layer 102 may include molding material, resin, and / or epoxy resin. Any of the encapsulation layers (e.g., 202, 204, 206) may be a component for encapsulation. Encapsulation layers may be provided using compression and transfer molding processes, sheet molding processes, or liquid molding processes. Any of the encapsulation layers (e.g., 202, 204, 206) may be a first encapsulation layer, a second encapsulation layer, and / or a third encapsulation layer.

[0042] The electrical path between integrated device 101 and integrated device 103 may include components from integrated device 101, metallization portion 203, passive device 105a, metallization portion 201, and / or components from integrated device 103. The electrical path between integrated device 101 and integrated device 103 may include components from integrated device 101, metallization portion 203, interposer 107, metallization portion 201, and / or components from integrated device 103. The electrical path between integrated device 101 and integrated device 103 may include components from integrated device 101, metallization portion 203, multiple pillar interconnects 104, metallization portion 201, and / or components from integrated device 103. The electrical path between integrated device 103 and multiple solder interconnects 109 may include components from integrated device 101, metallization portion 201, passive device 105a, passive device 105b, interposer 107, multiple pillar interconnects 104, metallization portion 203, components from integrated device 103, and / or metallization portion 205. Examples of components of the integrated device that may be part of the electrical path are given below at least in Figure 4 Further details are provided below.

[0043] Figure 3 A cross-sectional view of a package 300 including integrated devices and passive devices is illustrated. Package 300 includes integrated device 101, integrated device 103, multiple pillar interconnects 104, multiple passive devices 105, an interposer 107, multiple solder interconnects 109, metallized portions 301, 303, 305, encapsulation layers 202, 204, and 206. The multiple passive devices 105 may include passive device 105a (e.g., a first passive device) and passive device 105b (e.g., a second passive device).

[0044] Package 300 is similar to Figure 2Package 200 provides similar technical advantages. However, package 300 includes metallized portions that can be formed and / or manufactured in different ways. In some embodiments, the processes used to manufacture the metallized portions may differ from the methods used to manufacture the metallized portions in package 200. Any of the metallized portions (e.g., 301, 303, 305) may be a first metallized portion, a second metallized portion, or a third metallized portion. Different embodiments may have different numbers of metallized portions, and each metallized portion may have different or similar numbers of metal layers. Therefore, metallized portions 301, 303, and / or 305 are all optional. The metallized portions may be redistributed portions. Figure 3 The description utilizes all three metallized portions included in the package 200. However, any one of the metallized portions may be removed.

[0045] The front side of the integrated device 101 may be coupled to and contact a metallization portion 305. The metallization portion 305 may include at least one dielectric layer 250, a plurality of metallized interconnects 352, and a solder mask layer 254. The metallization portion 305 may include redistribution portions. The plurality of metallized interconnects 352 may include a plurality of redistributed interconnects. The plurality of metallized interconnects 352 may be coupled to and contact pad interconnects of the integrated device 101. A plurality of solder interconnects 109 are coupled to the metallization portion 305. For example, the plurality of solder interconnects 109 are coupled to the plurality of metallized interconnects 352.

[0046] Metallization portion 303 may be coupled to and contact the back side of integrated device 101. Metallization portion 303 may include at least one dielectric layer 230 and a plurality of metallized interconnects 332. Metallization portion 303 may include redistribution portions. The plurality of metallized interconnects 332 may include a plurality of redistributed interconnects. The plurality of metallized interconnects 332 may be coupled to and contact a plurality of substrate vias of integrated device 101. Encapsulation layer 206 is coupled to and contacted with integrated device 101, metallization portion 303, and metallization portion 305. Encapsulation layer 206 and integrated device 101 are located between metallization portion 303 and metallization portion 305.

[0047] The metallized portion 301 may include at least one dielectric layer 210 and a plurality of metallized interconnects 312. The metallized portion 301 may include a redistribution portion. The plurality of metallized interconnects 312 may include a plurality of redistributed interconnects.

[0048] Passive device 105a is coupled to metallized portion 303 via multiple solder interconnects 108a. The multiple solder interconnects 108a can be coupled to multiple metallized interconnects 332 of metallized portion 303. Passive device 105a is coupled to metallized portion 301 via multiple solder interconnects 106a. The multiple solder interconnects 106a can be coupled to multiple metallized interconnects 312 of metallized portion 301. Passive device 105b is coupled to metallized portion 303 via multiple solder interconnects 108b. The multiple solder interconnects 108b can be coupled to multiple metallized interconnects 332 of metallized portion 303. Passive device 105b is coupled to metallized portion 301 via multiple solder interconnects 106b. The multiple solder interconnects 106b can be coupled to multiple metallized interconnects 312 of metallized portion 301. Intermediate layer 107 is coupled to metallized portion 303 via a plurality of solder interconnects 108c. The plurality of solder interconnects 108c may be coupled to a plurality of metallized interconnects 332 of metallized portion 303. Intermediate layer 107 is coupled to metallized portion 301 via a plurality of solder interconnects 106c. The plurality of solder interconnects 106c may be coupled to a plurality of metallized interconnects 312 of metallized portion 301. A plurality of pillar interconnects 104 are coupled to metallized portion 301 and metallized portion 303. The plurality of pillar interconnects 104 may be coupled to a plurality of metallized interconnects 312 and / or a plurality of metallized interconnects 332. In some embodiments, solder interconnects may be used to couple the plurality of pillar interconnects 104 to metallized portion 301 and / or metallized portion 303. For example, a first plurality of solder interconnects may be used to couple a plurality of pillar interconnects 104 to a metallized interconnect of a metallized portion 301, and / or a second plurality of solder interconnects may be used to couple a plurality of pillar interconnects 104 to a metallized interconnect of a metallized portion 303.

[0049] Encapsulation layer 204 is coupled to and contacts metallized portion 301, metallized portion 303, multiple pillar interconnects 104, passive devices 105a, passive devices 105b, and interposer 107. Encapsulation layer 204, multiple pillar interconnects 104, passive devices 105a, passive devices 105b, and interposer 107 are located between metallized portion 301 and metallized portion 303. Encapsulation layer 204 may at least partially encapsulate multiple pillar interconnects 104, passive devices 105a, passive devices 105b, and / or interposer 107.

[0050] Integrated device 103 is coupled to metallization portion 301. For example, the front side of integrated device 103 is coupled to metallization portion 301. Encapsulation layer 202 is coupled to and contacts metallization portion 301 and integrated device 103. Encapsulation layer 102 may include molding material, resin, and / or epoxy resin. Any of the encapsulation layers (e.g., 202, 204, 206) may be a component for encapsulation. Encapsulation layers may be provided using compression and transfer molding processes, sheet molding processes, or liquid molding processes. Any of the encapsulation layers (e.g., 202, 204, 206) may be a first encapsulation layer, a second encapsulation layer, and / or a third encapsulation layer.

[0051] The electrical path between integrated device 101 and integrated device 103 may include components from integrated device 101, metallization portion 303, passive device 105a, metallization portion 301, and / or components from integrated device 103. The electrical path between integrated device 101 and integrated device 103 may include components from integrated device 101, metallization portion 303, interposer 107, metallization portion 301, and / or components from integrated device 103. The electrical path between integrated device 101 and integrated device 103 may include components from integrated device 101, metallization portion 303, multiple pillar interconnects 104, metallization portion 301, and / or components from integrated device 103. The electrical path between integrated device 103 and multiple solder interconnects 109 may include components from integrated device 101, metallization portion 301, passive device 105a, passive device 105b, interposer 107, multiple pillar interconnects 104, metallization portion 303, components from integrated device 103, and / or metallization portion 305. Examples of components of the integrated device that may be part of the electrical path are given below at least in Figure 4 Further details are provided below.

[0052] For the electrical paths described in this disclosure, if one or more solder interconnects are used to electrically couple interconnects from two components, such solder interconnects may be part of one or more electrical paths between the two components. An electrical path including a specific metallization portion may include metallized interconnects from that specific metallization portion. An electrical path including a specific passive device may include interconnects from that specific passive device. An electrical path including an interposer may include interconnects from that interposer.

[0053] Exemplary integrated device Figure 4A cross-sectional view of an integrated device 400 including a die substrate is illustrated. Integrated device 400 may represent integrated device 101 and / or integrated device 103. Integrated device 400 includes a die substrate portion 402 and a die interconnect portion 404. Die substrate portion 402 includes a die substrate 420, an active region 422, and a plurality of substrate vias 421. Active region 422 may include a plurality of logic cells, a plurality of transistors, and / or a plurality of filters. Different embodiments may use different types of transistors, such as field-effect transistors (FETs), planar FETs, finned FETs, and gate-all-around FETs. In some embodiments, front-end process (FEOL) technology may be used to fabricate the active region 422 of die substrate 420.

[0054] The die substrate 420 may include silicon (Si). The die substrate 420 may include bulk silicon. A plurality of substrate vias 421 extend through the die substrate 420. A plurality of pad interconnects (not shown) may be coupled to the plurality of substrate vias 421. The plurality of pad interconnects may be formed on the back side of the die substrate 420.

[0055] The die interconnect portion 404 includes at least one dielectric layer 440 and a plurality of die interconnects 442. The die interconnect portion 404 is coupled to a die substrate portion 402. The plurality of die interconnects 442 are coupled to an active region 422 of the die substrate portion 402. The plurality of die interconnects 442 may be coupled to a plurality of substrate vias 421. The die interconnect portion 404 may also include a plurality of pad interconnects 401 and a passivation layer 406. In some embodiments, a back-to-end (BEOL) process may be used to fabricate the die interconnect portion 404. The plurality of pad interconnects 401 may be coupled to the plurality of die interconnects 442. The passivation layer 406 may be formed and coupled to the die interconnect portion 404.

[0056] The front side of the integrated device 400 may include a side comprising a plurality of pad interconnects 401. A component coupled to the front side of the integrated device (e.g., 400) may mean that the component is coupled to and contacts the plurality of pad interconnects 401. In some embodiments, the integrated device may include additional metallized interconnects coupled to the plurality of pad interconnects 401. In such instances, when a component is coupled to the front side of the integrated device, the component may be coupled to and contact the additional metallized interconnects coupled to the plurality of pad interconnects 401. In some embodiments, a component may be coupled to the front side of the integrated device via a plurality of solder interconnects and / or a plurality of pillar interconnects.

[0057] The back side of the integrated device 400 may include a side comprising a die substrate 420. A component coupled to the back side of the integrated device (e.g., 400) may mean that the component is coupled to and contacts a plurality of substrate vias 421 of the integrated device. In some embodiments, the integrated device may include additional metallized interconnects (e.g., pad interconnects) coupled to the plurality of substrate vias 421. In such instances, when a component is coupled to the back side of the integrated device, the component may be coupled to and contact the additional metallized interconnects coupled to the plurality of substrate vias 421. In some embodiments, the component may be coupled to the back side of the integrated device via a plurality of solder interconnects and / or a plurality of pillar interconnects.

[0058] In some embodiments, the electrical path to and / or from the active region 422 may include at least one die interconnect from a plurality of die interconnects 442 and at least one substrate via from a plurality of substrate vias 421. In some embodiments, the electrical path to and / or from the active region 422 may include at least one die interconnect from a plurality of die interconnects 442 and at least one pad interconnect from a plurality of pad interconnects 401. The electrical path through the integrated device 400 may include a plurality of substrate vias 421, a plurality of die interconnects 442 and / or a plurality of pad interconnects 401. The electrical path through the integrated device 400 may include a plurality of substrate vias 421, a plurality of die interconnects 442, an active region 422 and / or a plurality of pad interconnects 401.

[0059] Integrated devices (e.g., 101, 103, 400) may include dies (e.g., bare semiconductor dies). Integrated devices may include power management integrated circuits (PMICs). Integrated devices may include application processors. Integrated devices may include modems. Integrated devices may include radio frequency (RF) devices, passive devices, filters, capacitors, inductors, antennas, transmitters, receivers, gallium arsenide (GaAs)-based integrated devices, surface acoustic wave (SAW) filters, bulk acoustic wave (BAW) filters, light-emitting diode (LED) integrated devices, silicon (Si)-based integrated devices, silicon carbide (SiC)-based integrated devices, memories, power management processors, and / or combinations thereof. Integrated devices may include at least one electronic circuit (e.g., a first electronic circuit, a second electronic circuit, etc.). Integrated devices may include input / output (I / O) hubs. Integrated devices may include transistors. Integrated devices may be examples of electronic components and / or electronic devices.

[0060] In some embodiments, the integrated device may be a chiplet. Chipslets can be manufactured using processes that offer better yields compared to other processes used to manufacture other types of integrated devices, which can reduce the overall cost of manufacturing chiplets. Different chiplets may have different sizes and / or shapes. Different chiplets may be configured to provide different functions. Different chiplets may have different interconnect densities (e.g., interconnects with different widths and / or pitches). In some embodiments, several chiplets may be used to perform the functionality of one or more chips (e.g., one or more integrated devices). As mentioned above, using several chiplets performing several functions can reduce the overall cost of the package compared to using a single chip to perform all the functions of the package. In some embodiments, one or more chiplets and / or one or more integrated devices (e.g., 100) of the chiplets described in this disclosure may be manufactured using the same technology node or two or more different technology nodes. For example, an integrated device may be manufactured using a first technology node, and a chiplet may be manufactured using a second technology node that is less advanced than the first technology node. In such examples, the integrated device may include components (e.g., interconnects, transistors) having a first minimum size, and the chiplet may include components (e.g., interconnects, transistors) having a second minimum size, wherein the second minimum size is larger than the first minimum size. In some embodiments, the first and second integrated devices of the package may be manufactured using the same or different technology nodes. In some embodiments, the chiplets and another chiplet of the package may be manufactured using the same or different technology nodes.

[0061] A technology node can refer to a specific manufacturing process and / or technology used to manufacture integrated devices and / or chiplets. A technology node can specify the minimum possible size (e.g., minimum size) that can be manufactured (e.g., transistor size, trace width, gap width between two transistors). Different technology nodes may have different yield losses. Different technology nodes may have different costs. Technology nodes for components with finer manufacturing details are more expensive and may have higher yield losses compared to technology nodes for components with less fine manufacturing details (e.g., traces, transistors). Therefore, more advanced technology nodes may be more expensive and may have higher yield losses compared to less advanced technology nodes. When all functions of a package are implemented in a single integrated device, the same technology node is used to manufacture the entire integrated device, even if some functions of the integrated device do not require manufacturing using that specific technology node. Therefore, the integrated device is locked to a single technology node. To optimize the cost of the package, some functions can be implemented in different integrated devices and / or chiplets, where different technology nodes can be used to manufacture different integrated devices and / or chiplets to reduce the overall cost. For example, functionality requiring state-of-the-art technology nodes can be implemented in an integrated device, while functionality achievable with less advanced technology nodes can be implemented in another integrated device and / or one or more chiplets. An example would be an integrated device manufactured using a first technology node (e.g., a more advanced technology node) and configured to provide computing applications, and at least one chiplet manufactured using a second technology node and configured to provide additional functionality, wherein the second technology node is less expensive than the first technology node, and wherein the second technology node manufactures a component with a minimum size larger than the minimum size of a component manufactured using the first technology node. Examples of computing applications could include high-performance computing and / or high-performance processing, which can be achieved by manufacturing and packing as many transistors as possible into the integrated device. This is why the integrated device configured for computing applications can be manufactured using the most advanced available technology nodes, while other chiplets can be manufactured using less advanced technology nodes, as these chiplets may not require as many transistors to be manufactured in the chiplet. Therefore, using a combination of different technology nodes (which may have different associated yield losses) for different integrated devices and / or chiplets can reduce the overall cost of the package compared to using a single integrated device to perform all the functions of the package.

[0062] Another advantage of dividing functionality into several integrated devices and / or chiplets is that it allows for improvements in package performance without having to redesign each individual integrated device and / or chiplet. For example, if a package configuration uses a first integrated device and a first chiplet, it may be possible to improve package performance by changing the design of the first integrated device while keeping the design of the first chiplet unchanged. Therefore, the first chiplet can be reused along with improved and / or differently configured first integrated devices. This saves costs when manufacturing packages with improved integrated devices because the first chiplet does not need to be redesigned.

[0063] Exemplary passive devices Different implementations may provide different types of passive devices. In some implementations, passive devices may include integrated passive devices (IPDs). In some implementations, passive devices may include deep trench capacitors (e.g., trench capacitor devices). In some implementations, passive devices are implemented as passive chiplets.

[0064] Figure 5 A cross-sectional view of a passive device 500 configured as a trench capacitor device is illustrated. The passive device 500 may be an integrated passive device including multiple trench capacitors (e.g., deep trench capacitors). The passive device 500 may be a component for trench capacitors. The passive device 500 may represent passive device 105a and / or passive device 105b. The passive device 500 includes a front side and a back side. The front side of the passive device 500 may include a side including multiple trench capacitors. The back side of the passive device 500 may be opposite the front side of the passive device 500. Although not shown in the diagram... Figure 5 As shown, passive device 500 may include a polyimide layer (e.g., 115) coupled to a surface (e.g., front surface) of passive device 500.

[0065] The passive device 500 includes a passive device substrate 502 and a plurality of trench capacitors 505. A plurality of solder interconnects (not shown) may be coupled to the passive device 500. The passive device substrate 502 may include silicon (Si). The passive device substrate 502 may include a plurality of trenches and / or cavities thereon on which capacitors may be formed.

[0066] Multiple trench capacitors 505 include trench capacitor 505a and trench capacitor 505b. Trench capacitors 505a and 505b may be configured as part of the same capacitor (e.g., a first capacitor, a first trench capacitor). Trench capacitors 505a and 505b may be configured to be coupled to and / or configured as part of a first power distribution network (PDN). Trench capacitors 505a and 505b may be configured as part of a first electrical path of a first power supply to the package. Trench capacitors 505a and 505b may be configured to be coupled to an integrated device.

[0067] like Figure 5 As shown, the passive device 500 includes a passive device substrate 502, an oxide layer 504, a first conductive layer 506, a dielectric layer 508, and a second conductive layer 510. The first conductive layer 506 and / or the second conductive layer 510 may comprise polysilicon. The oxide layer 504 and / or the dielectric layer 508 may comprise SiO2 (e.g., low-pressure chemical vapor deposition (LPCVD) SiO2) or Si3N4 (e.g., LPCVD Si3N4). Portions of the oxide layer 504, the first conductive layer 506, the dielectric layer 508, and the second conductive layer 510 may be located in respective trenches and / or cavities of the passive device substrate 502. It should be noted that the passive device substrate 502 may be considered to have trenches or cavities, even if the trenches or cavities are filled with one or more materials.

[0068] The trench capacitor 505a (e.g., a first trench capacitor, a first capacitor, a component for a first trench capacitor) may be defined by (i) a first portion of an oxide layer 504, (ii) a first portion of a first conductive layer 506, (iii) a first portion of a dielectric layer 508 and (iv) a first portion of a second conductive layer 510 located in a trench (e.g., a first trench) of a passive device substrate 502.

[0069] The trench capacitor 505b (e.g., a second trench capacitor, a second capacitor, a component for a second trench capacitor) may be defined by (i) a second portion of an oxide layer 504, (ii) a second portion of a first conductive layer 506, (iii) a second portion of a dielectric layer 508, and (iv) a second conductive layer 510 located in a trench (e.g., a second trench) of the passive device substrate 502. It should be noted that the trench capacitor 505b may be part of a capacitor, just like the trench capacitor 505a. That is, the trench capacitors 505a and 505b may be configured to be electrically coupled together to form a capacitor (e.g., a first capacitor) with a large capacitance.

[0070] As mentioned above, the passive device 500 may include a polyimide layer 115 coupled to the front side of the passive device 500. The front side of the passive device 500 may be the side that includes a trench capacitor.

[0071] As mentioned above, the metallized portions (e.g., 201, 203, 205, 301, 303, 305) may include redistributed portions that include redistributed interconnects (e.g., redistributed layer (RDL) interconnects). The redistributed interconnects may include portions having a U-shape or a V-shape. The terms "U-shape" and "V-shape" should be used interchangeably. The terms "U-shape" and "V-shape" may refer to the side profile shape of the interconnect and / or the redistributed interconnect. U-shaped interconnects (e.g., U-shaped side profile interconnects) and V-shaped interconnects (e.g., V-shaped side profile interconnects) may have a top portion and a bottom portion. The bottom portion of a U-shaped interconnect (or V-shaped interconnect) may be coupled to the top portion of another U-shaped interconnect (or V-shaped interconnect).

[0072] Exemplary process for manufacturing packages including integrated devices and passive devices. Figures 6A to 6D Exemplary steps for providing or manufacturing packages having integrated devices and passive devices are illustrated. In some specific implementations, Figures 6A to 6D The processes described herein can be used to provide or manufacture any of the packages described in this disclosure. In some specific embodiments, Figures 6A to 6D The process can be used to provide or manufacture the package 300 described in this disclosure.

[0073] It should be noted that Figures 6A to 6D The processes can be combined in one or more stages to simplify and / or clarify the processes used to provide or manufacture the package. In some embodiments, the order of the processes can be changed or modified. In some embodiments, one or more of these processes can be substituted or replaced without departing from the spirit of this disclosure. Different embodiments can manufacture the package in different ways.

[0074] like Figure 6A As shown, stage 1 illustrates the state after the integrated device 101 and the carrier 600 are provided. The integrated device 101 can be placed and coupled to the carrier 600 by an adhesive (not shown). The front side of the integrated device 101 can be coupled to the carrier 600. The carrier 600 may include a strip.

[0075] Phase 2 illustrates the state after the encapsulation layer 206 is formed on the carrier 600. The encapsulation layer 206 may be coupled to the carrier and the integrated device 101. The encapsulation layer 206 may be formed on the back side of the integrated device 101, and portions of the encapsulation layer 206 may be removed (e.g., ground away, polished). In some embodiments, portions of the integrated device 101 may also be removed (e.g., ground away). For example, the back side of the integrated device 101 may be removed. In one example, the die substrate of the integrated device 101 may be removed and / or thinned. Portions of the substrate vias of the integrated device 101 may be exposed. The encapsulation layer 206 may be provided using compression and transfer molding processes, sheet molding processes, or liquid molding processes.

[0076] Phase 3 illustrates the state after the metallization portion 303 is formed and coupled to the back side of the integrated device 101. The metallization portion 303 may include at least one dielectric layer 230 and a plurality of metallized interconnects 332. The metallization portion 303 may include redistribution portions. The plurality of metallized interconnects 332 may include a plurality of redistributed interconnects. The metallization portion 303 may contact the back side of the integrated device 101. The plurality of metallized interconnects 332 may be coupled to a plurality of substrate vias of the integrated device 101. The metallization portion 303 may be formed using lamination and electroplating processes. Examples of fabricating the metallization portion are given below at least in Figures 10A to 10B As described in the text.

[0077] Phase 4 illustrates the state after the plurality of pillar interconnects 104 are formed and coupled to the metallization portion 303. The plurality of pillar interconnects 104 may be coupled to and contact the plurality of metallization interconnects 332. The plurality of pillar interconnects 140 may be formed using an electroplating process. In the absence of the metallization portion 303, the plurality of pillar interconnects 104 may be formed and coupled to the back side of the integrated device 101.

[0078] like Figure 6B As shown, stage 5 illustrates the state after passive device 105a, passive device 105b, and interposer 107 are placed and coupled to metallization portion 303. Passive device 105a can be coupled to metallization portion 303 via multiple solder interconnects 108a using a solder reflow process. Passive device 105b can be coupled to metallization portion 303 via multiple solder interconnects 108b using a solder reflow process. Interposer 107 can be coupled to metallization portion 303 via multiple solder interconnects 108c using a solder reflow process. In the absence of metallization portion 303, passive device 105a, passive device 105b, and / or interposer 107 can be coupled to the back side of integrated device 101.

[0079] Stage 6 illustrates the state after the encapsulation layer 204 is formed on the metallization portion 303. The encapsulation layer 204 may be coupled to the metallization portion 303. The encapsulation layer 204 may be formed on passive device 105a, passive device 105b, interposer 107, and multiple pillar interconnects 104, and portions of the encapsulation layer 204 may be removed (e.g., ground away, polished). In some embodiments, portions of passive device 105a, passive device 105b, interposer 107, and / or multiple pillar interconnects 104 may also be removed (e.g., ground away). The encapsulation layer 204 may be provided using compression and transfer molding processes, sheet molding processes, or liquid molding processes.

[0080] Phase 7 illustrates the state after the metallization portion 301 is formed and coupled to passive devices 105a, 105b, interposer 107, and / or multiple pillar interconnects 104. The metallization portion 301 may include at least one dielectric layer 210 and multiple metallization interconnects 312. The metallization portion 301 may include redistribution portions. The multiple metallization interconnects 312 may include multiple redistribution interconnects. The metallization portion 301 may contact the passive devices 105a, 105b, interposer 107, and / or multiple pillar interconnects 104. Solder interconnects may or may not be present between (i) the metallization portion 301 and (ii) the passive devices 105a, 105b, interposer 107, and / or multiple pillar interconnects 104. The metallization portion 301 may be formed using lamination and electroplating processes. Examples of manufacturing the metallization portion are given below at least in Figures 10A to 10B As described in the text.

[0081] like Figure 6C As shown, stage 8 illustrates the state after the integrated device 103 has been placed and coupled to the metallization portion 301. A solder reflow process can be used to couple the integrated device 103 to the metallization portion 301 via at least a plurality of solder interconnects (not shown). The plurality of solder interconnects can be coupled to a plurality of pad interconnects of the integrated device 103 and a plurality of metallization interconnects 312 of the metallization portion 301. The front side of the integrated device 103 may face and / or point towards the surface of the metallization portion 301. In some specific embodiments, the front side of the integrated device 103 may be closer to the metallization portion 301 than the back side of the integrated device 103.

[0082] In some implementations, the integrated device 103 is coupled to the metallization portion 301 via at least a plurality of pillar interconnects and a plurality of solder interconnects (not shown). In the absence of the metallization portion 301, the integrated device 103 may be coupled to the passive device 105a, the passive device 105b, the interposer 107 and the plurality of pillar interconnects 104 via a plurality of solder interconnects using a solder reflow process.

[0083] Stage 9 illustrates the state after the encapsulation layer 202 is formed on the metallization portion 301 and the integrated device 103. The encapsulation layer 202 can be coupled to the metallization portion 301 and the integrated device 103. The encapsulation layer 202 can be provided using compression and transfer molding processes, sheet molding processes, or liquid molding processes.

[0084] Phase 10 illustrates the state after the carrier 600 is decoupled from the integrated device 101 and the encapsulation layer 206. The carrier 600 can be separated and / or removed from the integrated device 101 and / or the encapsulation layer 206.

[0085] like Figure 6D As shown, stage 11 illustrates the state after the metallization portion 305 is formed and coupled to the front side of the integrated device 101. The metallization portion 305 may include at least one dielectric layer 250 and a plurality of metallized interconnects 352. The metallization portion 305 may include redistribution portions. The plurality of metallized interconnects 352 may include a plurality of redistributed interconnects. The metallization portion 305 may contact the front side of the integrated device 101. The plurality of metallized interconnects 352 may be coupled to a plurality of pad interconnects of the integrated device 101. The metallization portion 305 may be formed using lamination and electroplating processes. Examples of manufacturing the metallization portion are given below at least in Figures 10A to 10B As described in the text.

[0086] Phase 12 illustrates the state after the plurality of solder interconnects 109 are coupled to the metallization portion 305. A solder reflow process can be used to couple the plurality of solder interconnects 109 to the plurality of metallization interconnects 352 of the metallization portion 305. In the absence of the metallization portion 305, the plurality of solder interconnects 109 can be coupled to the integrated device 101 (e.g., the front side of the integrated device 101) using a solder reflow process.

[0087] Stage 13 illustrates the state after a portion of the encapsulation layer 202 has been removed (e.g., thinned, ground, polished). The process of removing a portion of the encapsulation layer 202 may also remove a portion of the integrated device 103. For example, a portion of the back side of the integrated device 103 may be removed, wherein a portion of the die substrate of the integrated device 103 is removed and / or thinned. Stage 13 illustrates an example of the package 300.

[0088] An exemplary flowchart of a method for manufacturing a package including integrated devices and passive devices. In some specific implementations, manufacturing the package involves several processes. Figure 7 An exemplary flowchart illustrating a method 700 for providing or manufacturing a package having integrated devices and passive devices is shown. In some specific embodiments, Figure 7 Method 700 can be used to provide or manufacture package 300.

[0089] It should be noted that Figure 7 Method 700 may combine one or more stages and / or processes to simplify and / or clarify the method for providing or manufacturing a package. In some embodiments, the order of processes may be changed or modified. In some embodiments, one or more processes may be substituted or replaced without departing from the spirit of this disclosure. Different embodiments may manufacture packages in different ways.

[0090] The method (at 705) provides a carrier and a first integrated device. Figure 6A Phase 1 illustrates and describes an example of the state after the integrated device 101 and the carrier 600 are provided. The integrated device 101 can be placed and coupled to the carrier 600 by an adhesive (not shown). The front side of the integrated device 101 can be coupled to the carrier 600. The carrier 600 may include a strip.

[0091] This method (at 710) forms a first encapsulation layer coupled to the first integrated device. Figure 6A Phase 2 illustrates and describes an example of the state after the encapsulation layer 206 is formed on the carrier 600. The encapsulation layer 206 may be coupled to the carrier and the integrated device 101. The encapsulation layer 206 may be formed on the back side of the integrated device 101, and portions of the encapsulation layer 206 may be removed (e.g., ground away, polished). In some embodiments, portions of the integrated device 101 may also be removed (e.g., ground away). For example, the back side of the integrated device 101 may be removed. In one example, the die substrate of the integrated device 101 may be removed and / or thinned. Portions of the substrate vias of the integrated device 101 may be exposed. The encapsulation layer 206 may be provided using compression and transfer molding processes, sheet molding processes, or liquid molding processes.

[0092] The method (at 715) forms a first metallized portion comprising a plurality of metallized interconnects. Figure 6A Phase 3 illustrates and describes an example of the state after the metallization portion 303 is formed and coupled to the back side of the integrated device 101. The metallization portion 303 may include at least one dielectric layer 230 and a plurality of metallized interconnects 332. The metallization portion 303 may include redistribution portions. The plurality of metallized interconnects 332 may include a plurality of redistributed interconnects. The metallization portion 303 may contact the back side of the integrated device 101. The plurality of metallized interconnects 332 may be coupled to a plurality of substrate vias of the integrated device 101. The metallization portion 303 may be formed using lamination and electroplating processes. Examples of fabricating the metallization portion are given below at least in Figures 10A to 10B As described in the text.

[0093] This method (at 720) forms multiple pillar interconnects. These multiple pillar interconnects can be coupled to the metallized portion. Figure 6APhase 4 illustrates and describes an example of the state after the plurality of pillar interconnects 104 are formed and coupled to the metallization portion 303. The plurality of pillar interconnects 104 may be coupled to and contact the plurality of metallization interconnects 332. The plurality of pillar interconnects 140 may be formed using an electroplating process. In the absence of the metallization portion 303, the plurality of pillar interconnects 104 may be formed and coupled to the back side of the integrated device 101.

[0094] The method (at 725) places and couples at least one passive device and an interposer to the metallized portion. Figure 6B Phase 5 illustrates and describes an example of the state after passive device 105a, passive device 105b, and interposer 107 are placed and coupled to metallization portion 303. Passive device 105a can be coupled to metallization portion 303 via multiple solder interconnects 108a using a solder reflow process. Passive device 105b can be coupled to metallization portion 303 via multiple solder interconnects 108b using a solder reflow process. Interposer 107 can be coupled to metallization portion 303 via multiple solder interconnects 108c using a solder reflow process. In the absence of metallization portion 303, passive device 105a, passive device 105b, and / or interposer 107 can be coupled to the back side of integrated device 101.

[0095] This method (at 730) forms a second encapsulation coupled to the passive device, the interposer, and multiple pillar interconnects. Figure 6B Stage 6 illustrates and describes an example of the state after the encapsulation layer 204 is formed on the metallization portion 303. The encapsulation layer 204 may be coupled to the metallization portion 303. The encapsulation layer 204 may be formed on passive device 105a, passive device 105b, interposer 107, and multiple pillar interconnects 104, and portions of the encapsulation layer 204 may be removed (e.g., ground away, polished). In some embodiments, portions of passive device 105a, passive device 105b, interposer 107, and / or multiple pillar interconnects 104 may also be removed (e.g., ground away). The encapsulation layer 204 may be provided using compression and transfer molding processes, sheet molding processes, or liquid molding processes.

[0096] This method (at 735) forms a second metallization portion. Figure 6BStage 7 illustrates and describes an example of the state after the metallization portion 301 is formed and coupled to passive devices 105a, 105b, interposer 107, and / or multiple pillar interconnects 104. The metallization portion 301 may include at least one dielectric layer 210 and multiple metallization interconnects 312. The metallization portion 301 may include redistribution portions. The multiple metallization interconnects 312 may include multiple redistribution interconnects. The metallization portion 301 may contact the passive devices 105a, 105b, interposer 107, and / or multiple pillar interconnects 104. Solder interconnects may or may not be present between (i) the metallization portion 301 and (ii) the passive devices 105a, 105b, interposer 107, and / or multiple pillar interconnects 104. The metallization portion 301 may be formed using lamination and electroplating processes. Examples of manufacturing the metallization portion are given below at least in Figures 10A to 10B As described in the text.

[0097] The method (at 740) couples the second integrated device to the second metallization portion and forms a third encapsulation layer. Figure 6C Phases 8 and 9 illustrate examples of coupling a second integrated device to a second metallization portion and forming a third encapsulation layer.

[0098] Figure 6C Stage 8 illustrates and describes an example of the state after the integrated device 103 has been placed and coupled to the metallization portion 301. A solder reflow process can be used to couple the integrated device 103 to the metallization portion 301 via at least a plurality of solder interconnects (not shown). The plurality of solder interconnects can be coupled to a plurality of pad interconnects of the integrated device 103 and a plurality of metallization interconnects 312 of the metallization portion 301. The front side of the integrated device 103 may face and / or point towards the surface of the metallization portion 301. In some embodiments, the front side of the integrated device 103 may be closer to the metallization portion 301 than the back side of the integrated device 103. In some embodiments, the integrated device 103 is coupled to the metallization portion 301 via at least a plurality of pillar interconnects and a plurality of solder interconnects (not shown). In the absence of the metallization portion 301, the integrated device 103 can be coupled to the passive device 105a, the passive device 105b, the interposer 107 and the multiple pillar interconnects 104 via a solder reflow process.

[0099] Figure 6C Stage 9 illustrates and describes an example of the state after the encapsulation layer 202 is formed on the metallization portion 301 and the integrated device 103. The encapsulation layer 202 can be coupled to the metallization portion 301 and the integrated device 103. The encapsulation layer 202 can be provided using compression and transfer molding processes, sheet molding processes, or liquid molding processes.

[0100] This method (at 745) decouples the carrier. Figure 6C Phase 10 illustrates and describes an example of the state after the carrier 600 is decoupled from the integrated device 101 and the encapsulation layer 206. The carrier 600 can be separated and / or removed from the integrated device 101 and / or the encapsulation layer 206.

[0101] This method (at 750) forms a third metallization portion. Figure 6D Stage 11 illustrates and describes an example of the state after the metallization portion 305 is formed and coupled to the front side of the integrated device 101. The metallization portion 305 may include at least one dielectric layer 250 and a plurality of metallized interconnects 352. The metallization portion 305 may include redistributed portions. The plurality of metallized interconnects 352 may include a plurality of redistributed interconnects. The metallization portion 305 may contact the front side of the integrated device 101. The plurality of metallized interconnects 352 may be coupled to a plurality of pad interconnects of the integrated device 101. The metallization portion 305 may be formed using lamination and electroplating processes. Examples of fabricating the metallization portion are given below at least in Figures 10A to 10B As described in the text.

[0102] This method (at 755) couples multiple solder interconnects to a third metallization portion. Figure 6D Phase 12 illustrates and describes an example of the state after multiple solder interconnects 109 are coupled to the metallization portion 305. A solder reflow process can be used to couple the multiple solder interconnects 109 to multiple metallization interconnects 352 of the metallization portion 305. In the absence of the metallization portion 305, the multiple solder interconnects 109 can be coupled to the integrated device 101 using a solder reflow process.

[0103] In some implementations, this method may remove a portion of the third encapsulation layer. This removal of the third encapsulation layer may occur before or after the coupling of multiple solder interconnects to the third metallization portion, such as... Figure 6D The stage 12 described. Figure 6D Stage 13 illustrates and describes an example of the state after a portion of the encapsulation layer 202 has been removed (e.g., thinned, ground, polished). The process of removing a portion of the encapsulation layer 202 may also remove a portion of the integrated device 103. For example, a portion of the back side of the integrated device 103 may be removed, wherein a portion of the die substrate of the integrated device 103 is removed and / or thinned. Figure 6D Phase 13 illustrates an example of package 300.

[0104] It should be noted that the use and / or marking of the first integrated device and the second integrated device are arbitrary. Any of these integrated devices can be the first integrated device and / or the second integrated device. It should be noted that the use and / or marking of the first metallized portion, the second metallized portion, and the third metallized portion are arbitrary. Any of these metallized portions can be the first metallized portion, the second metallized portion, and / or the third metallized portion. It should be noted that the use and / or marking of the first encapsulation layer, the second encapsulation layer, and the third encapsulation layer are arbitrary. Any of these encapsulation layers can be the first encapsulation layer, the second encapsulation layer, and / or the third encapsulation layer.

[0105] Exemplary process for manufacturing packages including integrated devices and passive devices. Figures 8A to 8D Exemplary steps for providing or manufacturing packages having integrated devices and passive devices are illustrated. In some specific implementations, Figures 8A to 8D The processes described herein can be used to provide or manufacture any of the packages described in this disclosure. In some specific embodiments, Figures 8A to 8D The process can be used to provide or manufacture the package 200 described in this disclosure.

[0106] It should be noted that Figures 8A to 8D The processes can be combined in one or more stages to simplify and / or clarify the processes used to provide or manufacture the package. In some embodiments, the order of the processes can be changed or modified. In some embodiments, one or more of these processes can be substituted or replaced without departing from the spirit of this disclosure. Different embodiments can manufacture the package in different ways.

[0107] like Figure 8A As shown, stage 1 illustrates the state after the integrated device 103 and the carrier 800 are provided. The integrated device 103 can be placed and coupled to the carrier 800 by an adhesive (not shown). The back side of the integrated device 103 can be coupled to the carrier 800. The carrier 800 may include a tape.

[0108] Phase 2 illustrates the state after the encapsulation layer 202 is formed on the carrier 800. The encapsulation layer 202 can be coupled to the carrier and the integrated device 103. The encapsulation layer 202 can be formed on the front side of the integrated device 103, and portions of the encapsulation layer 202 can be removed (e.g., ground away, polished). The encapsulation layer 202 can be provided using compression and transfer molding processes, sheet molding processes, or liquid molding processes.

[0109] Phase 3 illustrates the state after the metallization portion 201 is formed and coupled to the front side of the integrated device 103. The metallization portion 201 may include at least one dielectric layer 210 and a plurality of metallized interconnects 212. The metallization portion 201 may include redistributed portions. The plurality of metallized interconnects 112 may include a plurality of redistributed interconnects. The metallization portion 201 may contact the front side of the integrated device 103. The plurality of metallized interconnects 112 may be coupled to a plurality of pad interconnects of the integrated device 103. The metallization portion 201 may be formed using lamination and electroplating processes. Examples of fabricating the metallization portion are given below at least in Figures 10A to 10B As described in the text.

[0110] Phase 4 illustrates the state after the plurality of pillar interconnects 104 are formed and coupled to the metallization portion 201. The plurality of pillar interconnects 104 may be coupled to and contact the plurality of metallization interconnects 112. The plurality of pillar interconnects 140 may be formed using an electroplating process. In the absence of the metallization portion 201, the plurality of pillar interconnects 104 may be formed and coupled to the front side of the integrated device 103.

[0111] like Figure 8B As shown, stage 5 illustrates the state after passive device 105a, passive device 105b, and interposer 107 are placed and coupled to metallization portion 201. Passive device 105a can be coupled to metallization portion 201 via multiple solder interconnects 106a using a solder reflow process. Passive device 105b can be coupled to metallization portion 201 via multiple solder interconnects 106b using a solder reflow process. Interposer 107 can be coupled to metallization portion 201 via multiple solder interconnects 106c using a solder reflow process. In the absence of metallization portion 201, passive device 105a, passive device 105b, and / or interposer 107 can be coupled to the front side of integrated device 103 via multiple solder interconnects.

[0112] Stage 6 illustrates the state after the encapsulation layer 204 is formed on the metallization portion 303. The encapsulation layer 204 may be coupled to the metallization portion 303. The encapsulation layer 204 may be formed on passive device 105a, passive device 105b, interposer 107, and multiple pillar interconnects 104, and portions of the encapsulation layer 204 may be removed (e.g., ground away, polished). In some embodiments, portions of passive device 105a, passive device 105b, interposer 107, and / or multiple pillar interconnects 104 may also be removed (e.g., ground away). The encapsulation layer 204 may be provided using compression and transfer molding processes, sheet molding processes, or liquid molding processes.

[0113] Phase 7 illustrates the state after the metallization portion 203 is formed and coupled to passive devices 105a, 105b, interposer 107, and / or multiple pillar interconnects 104. The metallization portion 203 may include at least one dielectric layer 230 and multiple metallization interconnects 232. The metallization portion 203 may include redistribution portions. The multiple metallization interconnects 232 may include multiple redistribution interconnects. The metallization portion 203 may contact the passive devices 105a, 105b, interposer 107, and / or multiple pillar interconnects 104. Solder interconnects may or may not be present between (i) the metallization portion 203 and (ii) the passive devices 105a, 105b, interposer 107, and / or multiple pillar interconnects 104. The metallization portion 203 may be formed using lamination and electroplating processes. Examples of manufacturing the metallization portion are given below at least in Figures 10A to 10B As described in the text.

[0114] like Figure 8C As shown, stage 8 illustrates the state after the integrated device 101 has been placed and coupled to the metallization portion 203. The back side of the integrated device 101 may be coupled to the metallization portion 203. The back side of the integrated device 101 may face and / or point towards the surface of the metallization portion 203. In some specific embodiments, the back side of the integrated device 101 may be closer to the metallization portion 203 than the front side of the integrated device 101. A solder reflow process may be used to couple the integrated device 101 to the metallization portion 203 through at least a plurality of solder interconnects (not shown). The plurality of solder interconnects may be coupled to a plurality of substrate vias of the integrated device 101 and a plurality of metallization interconnects 232 of the metallization portion 203. In the absence of the metallization portion 203, the integrated device 101 (back side of the integrated device 101) can be coupled to the passive device 105a, the passive device 105b, the interposer 107 and the multiple pillar interconnects 104 via a solder reflow process.

[0115] Stage 9 illustrates the state after the encapsulation layer 206 is formed on the metallization portion 203 and the integrated device 101. The encapsulation layer 206 can be coupled to the metallization portion 203 and the integrated device 101. The encapsulation layer 206 can be provided using compression and transfer molding processes, sheet molding processes, or liquid molding processes. In some embodiments, portions of the encapsulation layer 206 can be removed (e.g., thinned, ground away).

[0116] Phase 10 illustrates the state after the metallization portion 205 is formed and coupled to the front side of the integrated device 101. The metallization portion 205 may include at least one dielectric layer 250 and a plurality of metallized interconnects 252. The metallization portion 205 may include redistribution portions. The plurality of metallized interconnects 252 may include a plurality of redistributed interconnects. The metallization portion 205 may contact the front side of the integrated device 101. The plurality of metallized interconnects 252 may be coupled to a plurality of pad interconnects of the integrated device 101. The metallization portion 205 may be formed using lamination and electroplating processes. Examples of fabricating the metallization portion are given below at least in Figures 10A to 10B As described in the text.

[0117] like Figure 8D As shown, stage 11 illustrates the state after the plurality of solder interconnects 109 are coupled to the metallization portion 205. A solder reflow process can be used to couple the plurality of solder interconnects 109 to the plurality of metallization interconnects 252 of the metallization portion 205. In the absence of the metallization portion 205, the plurality of solder interconnects 109 can be coupled to the integrated device 101 using a solder reflow process.

[0118] Phase 12 illustrates the state after the carrier 800 is decoupled from the integrated device 103 and the encapsulation layer 202. The carrier 800 can be separated and / or removed from the integrated device 103 and / or the encapsulation layer 202. Phase 12 illustrates an example of the package 200.

[0119] An exemplary flowchart of a method for manufacturing a package including integrated devices and passive devices. In some specific implementations, manufacturing the package involves several processes. Figure 9 An exemplary flowchart illustrating a method 900 for providing or manufacturing a package having integrated devices and passive devices is shown. In some specific embodiments, Figure 9 Method 900 can be used to provide or manufacture package 200.

[0120] It should be noted that Figure 9 Method 900 may combine one or more stages and / or processes to simplify and / or clarify the method for providing or manufacturing a package. In some embodiments, the order of processes may be changed or modified. In some embodiments, one or more processes may be substituted or replaced without departing from the spirit of this disclosure. Different embodiments may manufacture packages in different ways.

[0121] The method (at 905) provides a carrier and a first integrated device. Figure 8A Phase 1 illustrates and describes an example of the state after the integrated device 103 and the carrier 800 are provided. The integrated device 103 can be placed and coupled to the carrier 800 by an adhesive (not shown). The back side of the integrated device 103 can be coupled to the carrier 800. The carrier 800 may include a strip.

[0122] This method (at 910) forms a first encapsulation layer coupled to the first integrated device. Figure 8A Phase 2 illustrates and describes an example of the state after the encapsulation layer 202 is formed on the carrier 800. The encapsulation layer 202 may be coupled to the carrier and the integrated device 103. The encapsulation layer 202 may be formed on the front side of the integrated device 103, and portions of the encapsulation layer 202 may be removed (e.g., ground away, polished). The encapsulation layer 202 may be provided using compression and transfer molding processes, sheet molding processes, or liquid molding processes.

[0123] This method (at 915) forms a first metallization portion coupled to the first integrated device. Figure 8A Phase 3 illustrates and describes an example of the state after the metallization portion 201 is formed and coupled to the front side of the integrated device 103. The metallization portion 201 may include at least one dielectric layer 210 and a plurality of metallized interconnects 212. The metallization portion 201 may include redistributed portions. The plurality of metallized interconnects 112 may include a plurality of redistributed interconnects. The metallization portion 201 may contact the front side of the integrated device 103. The plurality of metallized interconnects 112 may be coupled to a plurality of pad interconnects of the integrated device 103. The metallization portion 201 may be formed using lamination and electroplating processes. Examples of fabricating the metallization portion are given below at least in Figures 10A to 10B As described in the text.

[0124] The method (at 920) forms a plurality of pillar interconnects coupled to the first metallized portion. Figure 8A Phase 4 illustrates and describes an example of the state after the plurality of pillar interconnects 104 are formed and coupled to the metallization portion 201. The plurality of pillar interconnects 104 may be coupled to and contact the plurality of metallization interconnects 112. The plurality of pillar interconnects 140 may be formed using an electroplating process. In the absence of the metallization portion 201, the plurality of pillar interconnects 104 may be formed and coupled to the front side of the integrated device 103.

[0125] The method (at 925) places and couples the passive device and the interposer to the first metallization portion. Figure 8BPhase 5 illustrates and describes an example of the state after passive device 105a, passive device 105b, and interposer 107 are placed and coupled to metallization portion 201. Passive device 105a can be coupled to metallization portion 201 via multiple solder interconnects 106a using a solder reflow process. Passive device 105b can be coupled to metallization portion 201 via multiple solder interconnects 106b using a solder reflow process. Interposer 107 can be coupled to metallization portion 201 via multiple solder interconnects 106c using a solder reflow process. In the absence of metallization portion 201, passive device 105a, passive device 105b, and / or interposer 107 can be coupled to the front side of integrated device 103 via multiple solder interconnects.

[0126] This method (at 930) forms a second encapsulation layer coupled to the first metallization portion. Figure 8B Stage 6 illustrates and describes an example of the state after the encapsulation layer 204 is formed on the metallization portion 303. The encapsulation layer 204 may be coupled to the metallization portion 303. The encapsulation layer 204 may be formed on passive device 105a, passive device 105b, interposer 107, and multiple pillar interconnects 104, and portions of the encapsulation layer 204 may be removed (e.g., ground away, polished). In some embodiments, portions of passive device 105a, passive device 105b, interposer 107, and / or multiple pillar interconnects 104 may also be removed (e.g., ground away). The encapsulation layer 204 may be provided using compression and transfer molding processes, sheet molding processes, or liquid molding processes.

[0127] The method (at 935) forms a second metallization portion coupled to a passive device, an interposer, and / or multiple pillar interconnects. Figure 8B Stage 7 illustrates and describes the state after the metallization portion 203 is formed and coupled to passive devices 105a, 105b, interposer 107, and / or multiple pillar interconnects 104. The metallization portion 203 may include at least one dielectric layer 230 and multiple metallization interconnects 232. The metallization portion 203 may include redistribution portions. The multiple metallization interconnects 232 may include multiple redistribution interconnects. The metallization portion 203 may contact the passive devices 105a, 105b, interposer 107, and / or multiple pillar interconnects 104. Solder interconnects may or may not be present between (i) the metallization portion 203 and (ii) the passive devices 105a, 105b, interposer 107, and / or multiple pillar interconnects 104. Lamination and electroplating processes can be used to form the metallization portion 203. Examples of manufacturing the metallization portion are given below at least in Figures 10A to 10B As described in the text.

[0128] This method (at 940) couples the second integrated device to the second metallization portion. Figure 8C Stage 8 illustrates and describes an example of the state after the integrated device 101 has been placed and coupled to the metallization portion 203. The back side of the integrated device 101 may be coupled to the metallization portion 203. The back side of the integrated device 101 may face and / or point towards the surface of the metallization portion 203. In some specific embodiments, the back side of the integrated device 101 may be closer to the metallization portion 203 than the front side of the integrated device 101. A solder reflow process can be used to couple the integrated device 101 to the metallization portion 203 via at least a plurality of solder interconnects (not shown). The plurality of solder interconnects may be coupled to a plurality of substrate vias of the integrated device 101 and a plurality of metallization interconnects 232 of the metallization portion 203. In the absence of the metallization portion 203, the integrated device 101 (back side of the integrated device 101) can be coupled to the passive device 105a, the passive device 105b, the interposer 107 and the multiple pillar interconnects 104 via a solder reflow process.

[0129] This method (at 945) forms a third encapsulation layer coupled to the second integrated device and the second metallization portion. Figure 8C Stage 9 illustrates and describes an example of the state after the encapsulation layer 206 is formed on the metallization portion 203 and the integrated device 101. The encapsulation layer 206 may be coupled to the metallization portion 203 and the integrated device 101. The encapsulation layer 206 may be provided using compression and transfer molding processes, sheet molding processes, or liquid molding processes. In some specific embodiments, portions of the encapsulation layer 206 may be removed (e.g., thinned, ground away).

[0130] This method (at 950) forms a third metallization portion coupled to the second integrated device. Figure 8C Stage 10 illustrates and describes an example of the state after the metallization portion 205 is formed and coupled to the front side of the integrated device 101. The metallization portion 205 may include at least one dielectric layer 250 and a plurality of metallized interconnects 252. The metallization portion 205 may include redistributed portions. The plurality of metallized interconnects 252 may include a plurality of redistributed interconnects. The metallization portion 205 may contact the front side of the integrated device 101. The plurality of metallized interconnects 252 may be coupled to a plurality of pad interconnects of the integrated device 101. The metallization portion 205 may be formed using lamination and electroplating processes. Examples of fabricating the metallization portion are given below at least in Figures 10A to 10B As described in the text.

[0131] This method (at 955) couples multiple solder interconnects to a third metallization portion. Figure 8DPhase 11 illustrates and describes an example of the state after multiple solder interconnects 109 are coupled to the metallization portion 205. A solder reflow process can be used to couple the multiple solder interconnects 109 to multiple metallization interconnects 252 of the metallization portion 205. In the absence of the metallization portion 205, the multiple solder interconnects 109 can be coupled to the integrated device 101 using a solder reflow process.

[0132] The method also (at 955) decouples the carrier from the first integrated device. Figure 8D Phase 12 illustrates and describes an example of the state after the carrier 800 is decoupled from the integrated device 103 and the encapsulation layer 202. The carrier 800 can be separated and / or removed from the integrated device 103 and / or the encapsulation layer 202. Phase 12 illustrates an example of the package 200.

[0133] It should be noted that the use and / or marking of the first integrated device and the second integrated device are arbitrary. Any of these integrated devices can be the first integrated device and / or the second integrated device. It should be noted that the use and / or marking of the first metallized portion, the second metallized portion, and the third metallized portion are arbitrary. Any of these metallized portions can be the first metallized portion, the second metallized portion, and / or the third metallized portion. It should be noted that the use and / or marking of the first encapsulation layer, the second encapsulation layer, and the third encapsulation layer are arbitrary. Any of these encapsulation layers can be the first encapsulation layer, the second encapsulation layer, and / or the third encapsulation layer.

[0134] Exemplary process for manufacturing metallized parts In some specific implementations, manufacturing the metallized parts involves several processes. Figures 10A to 10B Exemplary processes for providing or manufacturing metallized portions are illustrated. In some specific implementations, Figures 10A to 10B The process can be used to provide or manufacture the metallized part 201. However, it can be used... Figures 10A to 10B The process is used to manufacture any of the metallized portions described in this disclosure (e.g., 203, 205, 301, 303, 305).

[0135] It should be noted that Figures 10A to 10B The processes may be combined in one or more stages to simplify and / or clarify the processes used to provide or manufacture the metallized portion. In some embodiments, the order of the processes may be changed or modified. In some embodiments, one or more of these processes may be substituted or replaced without departing from the scope of this disclosure.

[0136] like Figure 10A As shown, stage 1 illustrates the state after the provision and / or formation of the carrier 1002, the integrated device 101, and the encapsulation layer 1006.

[0137] Phase 2 illustrates the state after the dielectric layer 1010 is formed on the integrated device 101 and the encapsulation layer 1006. The dielectric layer 1010 may include a plurality of openings 1011. The dielectric layer 1010 may be formed using deposition and / or lamination processes. The dielectric layer 1010 may include a prepreg. The plurality of openings 1011 may be formed using etching processes (e.g., photolithography) or laser processes. The plurality of openings 1011 may be formed using exposure and development processes.

[0138] Phase 3 illustrates the state after multiple interconnects 1012 are formed in and over the dielectric layer 1010 (including in and over the multiple openings 1011). For example, via interconnects, pad interconnects, and / or trace interconnects may be formed. Plating processes may be used to form the interconnects. Phase 3 illustrates that some portions of the interconnects 1012 may have a U-shape or a V-shape. The terms “U-shape” and “V-shape” should be used interchangeably. The terms “U-shape” and “V-shape” may refer to the side profile shape of the interconnect and / or redistributed interconnect. U-shaped interconnects (e.g., U-shaped side profile interconnects) and V-shaped interconnects (e.g., V-shaped side profile interconnects) may have a top portion and a bottom portion. The bottom portion of a U-shaped interconnect (or V-shaped interconnect) may be coupled to the top portion of another U-shaped interconnect (or V-shaped interconnect).

[0139] like Figure 10B As shown, stage 4 illustrates the state after the dielectric layer 1020 is formed on the dielectric layer 1010. The dielectric layer 1020 may include a plurality of openings 1021. The dielectric layer 1020 may be formed using deposition and / or lamination processes. The dielectric layer 1020 may include a prepreg. The plurality of openings 1021 may be formed using etching processes (e.g., photolithography) or laser processes. The plurality of openings 1021 may be formed using exposure and development processes.

[0140] Phase 5 illustrates the state after multiple interconnects 1022 are formed in and over the dielectric layer 1020 (including in and over the multiple openings 1021). For example, via interconnects, pad interconnects, and / or trace interconnects may be formed. Plating processes may be used to form the interconnects. Phase 5 illustrates that some portions of the interconnects 1022 may have a U-shape or a V-shape. The terms “U-shape” and “V-shape” should be used interchangeably. The terms “U-shape” and “V-shape” may refer to the side profile shape of the interconnect and / or redistributed interconnect. U-shaped interconnects (e.g., U-shaped side profile interconnects) and V-shaped interconnects (e.g., V-shaped side profile interconnects) may have a top portion and a bottom portion. The bottom portion of a U-shaped interconnect (or V-shaped interconnect) may be coupled to the top portion of another U-shaped interconnect (or V-shaped interconnect). Multiple interconnects 1012 and / or multiple interconnects 1022 may represent multiple metallized interconnects (e.g., 212, 232, 252, 312, 332, 352).

[0141] It should be noted that the process of forming the dielectric layer, multiple openings, and multiple interconnects can be performed iteratively to form an additional metal layer in the metallized portion.

[0142] Different implementations may use different processes to form the metal layers and / or interconnects. In some implementations, chemical vapor deposition (CVD), physical vapor deposition (PVD), sputtering, spraying, and / or plating processes may be used to form the metal layers.

[0143] Exemplary electronic devices Figure 11 Examples are illustrated of various electronic devices that may integrate any of the aforementioned devices, integrated devices, integrated circuit (IC) packages, integrated circuit (IC) devices, semiconductor devices, integrated circuits, dies, interposers, packages, stacked packages (PoP), system-in-packages (SiP), or system-on-a-chip (SoC). For example, mobile phone device 1102, laptop computer device 1104, fixed-location terminal device 1106, wearable device 1108, or motor vehicle 1110 may include device 1100 as described herein. For example, device 1100 may be any of the devices and / or integrated circuit (IC) packages described herein. Figure 11The illustrated devices 1102, 1104, 1106, and 1108, as well as vehicle 1110, are merely exemplary. Other electronic devices may also feature device 1100, including but not limited to a group of devices (e.g., electronic devices) comprising: mobile devices, handheld personal communication system (PCS) units, portable data units (such as personal digital assistants), GPS-enabled devices, navigation devices, set-top boxes, music players, video players, entertainment units, fixed location data units (such as meter reading devices), communication devices, smartphones, tablet computers, computers, wearable devices (e.g., watches, glasses), Internet of Things (IoT) devices, servers, routers, electronic devices implemented in motor vehicles (e.g., autonomous vehicles), or any other device or any combination thereof that stores or retrieves data or computer instructions.

[0144] Figures 1 to 5 , Figures 6A to 6D , Figure 7 , Figures 8A to 8D , Figure 9 , Figures 10A to 10B and / or Figure 11 One or more of the illustrated components, processes, features, and / or functions may be rearranged and / or combined into a single component, process, feature, or function, or embodied in several components, processes, or functions. Additional elements, components, processes, and / or functions may also be added without departing from this disclosure. It should also be noted that... Figures 1 to 5 , Figures 6A to 6D , Figure 7 , Figures 8A to 8D , Figure 9 , Figures 10A to 10B and / or Figure 11 The corresponding descriptions herein are not limited to dies and / or ICs. In some specific implementations, Figures 1 to 5 , Figures 6A to 6D , Figure 7 , Figures 8A to 8D , Figure 9 , Figures 10A to 10B and / or Figure 11 The descriptions and their corresponding information can be used to manufacture, build, provide, and / or produce equipment and / or integrated devices. In some specific implementations, devices may include dies, integrated devices, integrated passive devices (IPDs), die packages, integrated circuit (IC) devices, device packages, integrated circuit (IC) packages, wafers, semiconductor devices, stacked package (PoP) devices, thermal devices, and / or interposers.

[0145] It should be noted that the accompanying drawings in this disclosure may represent actual and / or conceptual representations of various parts, components, objects, devices, packages, integrated devices, integrated circuits, and / or transistors. In some instances, the drawings may not be to scale. In some instances, not all components and / or parts are shown for clarity. In some instances, the positioning, location, size, and / or shape of the various parts and / or components in the drawings may be exemplary. In some specific embodiments, the various components and / or parts in the drawings may be optional.

[0146] The term “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any specific implementation or aspect described herein as “exemplary” is not necessarily to be construed as superior to or better than other aspects of this disclosure. Similarly, the term “aspect” does not require that all aspects of this disclosure include the features, advantages, or modes of operation discussed. The term “coupled” is used herein to refer to direct or indirect coupling (e.g., mechanical coupling) between two objects. For example, if object A physically contacts object B, and object B contacts object C, objects A and C can still be considered coupled to each other, even if they are not in direct physical contact. An object coupled to another object may be coupled to at least a portion of another object. The term “electrically coupled” may mean that two objects are directly or indirectly coupled together such that current (e.g., signal, power, ground) can flow between the two objects. Electrically coupled objects may or may not have current flowing between them. The use of the terms “first,” “second,” “third,” and “fourth” (and / or anything above the fourth) is arbitrary. Any component described can be a first component, a second component, a third component, or a fourth component. For example, a component referred to as a second component can be a first component, a second component, a third component, or a fourth component. The term "enclosing" means that an object can partially enclose or completely enclose another object. A first component "located" within a second component can mean that the first component is "partially located" within or "completely located" within the second component. A first component "embedded" within a second component can mean that the first component is "partially embedded" within or "completely embedded" within the second component. The terms "top" and "bottom" are arbitrary. A component located at the top can be above a component located at the bottom. A top component can be considered a bottom component, and vice versa. As described in this disclosure, a first component located "above" a second component can mean that the first component is located above or below the second component, depending on how bottom or top is arbitrarily defined. In another example, a first component can be located above (e.g., above) a first surface of a second component, and a third component can be located above (e.g., below) a second surface of a second component, where the second surface is opposite to the first surface. It should also be noted that the term "on top of" as used in this application in the context of one component being on top of another component can be used to mean that a component is on and / or in another component (e.g., on the surface of a component or embedded in a component). Thus, for example, "first component on top of second component" can mean: (1) the first component is on top of the second component but does not directly contact the second component; (2) the first component is on the second component (e.g., on the surface of the second component); and / or (3) the first component is in the second component (e.g., embedded in the second component). A first component "in" the second component can be partially or entirely located within the second component.As used in this disclosure, the terms “about 'value X'” or “approximately value X” mean within 10% of “value X”. For example, a value of about 1 or approximately 1 would mean a value in the range of 0.9 to 1.1. “Multiple” components can include all possible components or only some of all possible components. For example, if a device comprises ten components, the use of the term “multiple components” can refer to all ten components or only some of those ten components. An object “facing” and / or “pointing” to another object can mean that the surface of that object (e.g., an outer surface) can face and / or point toward the other object. An object “facing” to another object can mean that the surface of that object (e.g., an outer surface) can point and / or be directed toward and / or toward the other object. For example, an object A having a first surface (e.g., a first outer surface) facing a second surface (e.g., a second outer surface) of object B can mean that the first surface of object A can point toward the second surface of object B (e.g., toward the second surface of object B). This can still be true even if there are one or more components between the first surface of object A and the second surface of object B. Therefore, for example, if object A is coupled to object C, and object B is coupled to object C such that object C is between object A and object B, it is possible for the surface of object A to point in a direction toward object B (e.g., toward object B) even though object C exists between object A and object B. The direction that an object faces and / or points toward it can be a direction perpendicular to the surface of that object (e.g., the outer surface). The front side of an object facing and / or pointing toward another object can mean that the surface on that front side faces and / or points toward the other object.

[0147] In some embodiments, an interconnect is a component or assembly in a device or package that allows or facilitates an electrical connection between two points, elements, and / or assemblies. In some embodiments, an interconnect may include traces, vias, pads, pillars, metallization layers, redistribution layers, and / or under-bump metallization (UBM) layers / interconnects. In some embodiments, an interconnect may include a conductive material configured to provide an electrical path for signals (e.g., data signals), ground, and / or power. An interconnect may include more than one element or assembly. An interconnect may be defined by one or more interconnects. An interconnect may include one or more metal layers. An interconnect may be part of a circuit. Different embodiments may use different processes and / or steps to form interconnects. In some embodiments, chemical vapor deposition (CVD), physical vapor deposition (PVD), sputtering, spraying, and / or plating processes may be used to form interconnects.

[0148] It should also be noted that the various disclosures contained herein can be described as processes depicted as work diagrams, flowcharts, structure diagrams, or block diagrams. Although flowcharts may describe operations as sequential processes, many operations within an operation can be performed in parallel or concurrently. Furthermore, the order of operations can be rearranged. A process terminates when its operations are completed.

[0149] Further examples are described below to facilitate understanding of this disclosure.

[0150] Aspect 1: A package comprising: a first integrated device; an interposer coupled to the first integrated device; a passive device coupled to the first integrated device; a plurality of pillar interconnects coupled to the first integrated device; a second integrated device coupled to the interposer, the passive device and the plurality of pillar interconnects; and an encapsulation layer located between the first integrated device and the second integrated device.

[0151] Aspect 2: The package according to aspect 1, wherein the encapsulation layer at least partially encapsulates the interposer, the passive device and the plurality of pillar interconnects.

[0152] Aspect 3: The package according to aspects 1 to 2, wherein the passive device includes a deep trench capacitor.

[0153] Aspect 4: The package according to aspects 1 to 3, wherein the interposer includes a silicon substrate; and a plurality of interposer interconnects.

[0154] Aspect 5: The package according to aspects 1 to 4, wherein the first integrated device includes a first front side and a first back side; and wherein the second integrated device includes a second front side and a second back side.

[0155] Aspect 6: The package according to aspect 5, wherein the first front side of the first integrated device points toward the second integrated device.

[0156] Aspect 7: The package according to aspect 5, wherein the first front side of the first integrated device points toward the second back side of the second integrated device.

[0157] Aspect 8: The package according to aspect 5, wherein the first front side of the first integrated device points toward the second front side of the second integrated device.

[0158] Aspect 9: The package according to aspects 1 to 8 further includes a first metallization portion located between the first integrated device and the interposer.

[0159] Aspect 10: The package according to aspect 9 further includes a second metallization portion located between the second integrated device and the interposer.

[0160] Aspect 11: The package according to aspect 10, wherein the encapsulation layer is located between the first metallized portion and the second metallized portion.

[0161] Aspect 12: The package according to aspects 10 to 11 further includes a third metallization portion coupled to the second integrated device.

[0162] Aspect 13: The package according to aspects 10 to 12, wherein the first metallization portion includes: at least one first dielectric layer; and a first plurality of metallized interconnects; wherein the second metallization portion includes: at least one second dielectric layer; and a second plurality of metallized interconnects.

[0163] Aspect 14: The package according to aspects 10 to 13, wherein the first integrated device is coupled to the interposer and the passive device via at least the first metallization portion, and wherein the second integrated device is coupled to the interposer and the passive device via at least the second metallization portion.

[0164] Aspect 15: The package according to aspects 1 to 8 further includes a first metallization portion located between the second integrated device and the interposer.

[0165] Aspect 16: The package according to aspects 1 to 15, wherein the first integrated device and / or the second integrated device includes a plurality of substrate vias.

[0166] Aspect 17: The package according to aspects 1 to 8 further includes: a first metallization portion coupled to the front side of the first integrated device; a second metallization portion coupled to the back side of the first integrated device; and a third metallization portion coupled to the second integrated device.

[0167] Aspect 18: The package according to aspect 17 further includes: a second encapsulation layer located between the first metallized portion and the second metallized portion; and a third encapsulation layer coupled to the third metallized portion, wherein the encapsulation layer is located between the second metallized portion and the third metallized portion.

[0168] Aspect 19: A method for manufacturing a package. The method provides a first integrated device. The method forms a first encapsulation layer coupled to the first integrated device. The method forms a first metallization portion coupled to the first integrated device. The method couples an interposer layer to the first metallization portion. The method couples a passive device to the first metallization portion. The method forms a plurality of pillar interconnects coupled to the first metallization portion. The method forms a second encapsulation layer coupled to the first metallization portion, the interposer layer, the passive device, and the plurality of pillar interconnects. The method forms a second metallization portion coupled to the interposer layer, the passive device, and the plurality of pillar interconnects. The method couples a second integrated device to the second metallization portion.

[0169] Aspect 20: The method according to aspect 19, the method further comprising: forming a third encapsulation layer coupled to the second integrated device; and forming a third metallization portion coupled to the second integrated device.

[0170] Aspect 21: According to the method of aspect 20, wherein the third metallization portion is coupled to the front side of the second integrated device.

[0171] Aspect 22: The method according to aspects 19 to 21, wherein the second metallization portion is coupled to the back side of the second integrated device.

[0172] Aspect 23: The method according to aspects 19 to 21, wherein the first metallization portion is coupled to the front side of the first integrated device.

[0173] Aspect 24: The method according to aspects 19 to 21, wherein the first metallization portion is coupled to the back side of the first integrated device.

[0174] Aspect 25: The method according to aspects 19 to 21, wherein the first integrated device is located between the first metallized portion and the second metallized portion.

[0175] The various features of this disclosure described herein can be implemented in different systems without departing from this disclosure. It should be noted that the foregoing aspects of this disclosure are merely illustrative and should not be construed as limiting the scope of this disclosure. The description of aspects of this disclosure is intended to be illustrative and not to limit the scope of the appended claims. Therefore, the teachings herein are readily applicable to other types of devices, and many substitutions, modifications, and variations will be apparent to those skilled in the art.

Claims

1. A package, the package comprising: First integrated device; An intermediary layer, the intermediary layer being coupled to the first integrated device; A passive device, wherein the passive device is coupled to the first integrated device; A plurality of pillar interconnects coupled to the first integrated device; A second integrated device is coupled to the interposer, the passive device, and the plurality of pillar interconnects; and An encapsulation layer is located between the first integrated device and the second integrated device.

2. The package of claim 1, wherein the encapsulation layer at least partially encapsulates the interposer, the passive device, and the plurality of pillar interconnects.

3. The package of claim 1, wherein the passive device comprises a deep trench capacitor.

4. The package according to claim 1, wherein the interposer layer comprises: silicon substrate; and Multiple intermediate layer interconnects.

5. The packaging component according to claim 1, The first integrated device includes a first front side and a first back side; and The second integrated device includes a second front side and a second back side.

6. The package according to claim 5, wherein the first front side of the first integrated device points toward the second integrated device.

7. The package of claim 5, wherein the first front side of the first integrated device points toward the second back side of the second integrated device.

8. The package of claim 5, wherein the first front side of the first integrated device points toward the second front side of the second integrated device.

9. The package according to claim 1, the package further comprising a first metallization portion located between the first integrated device and the interposer.

10. The package of claim 9, further comprising a second metallization portion located between the second integrated device and the interposer.

11. The package of claim 10, wherein the encapsulation layer is located between the first metallized portion and the second metallized portion.

12. The package of claim 10, further comprising a third metallization portion coupled to the second integrated device.

13. The package according to claim 10, The first metallized portion includes: At least one first dielectric layer; and The first multiple metallized interconnects; and The second metallization portion includes: At least one second dielectric layer; and The second is multiple metallized interconnects.

14. The package according to claim 10, The first integrated device is coupled to the interposer and the passive device through at least the first metallization portion, and The second integrated device is coupled to the interposer and the passive device via at least the second metallization portion.

15. The package of claim 1, further comprising a first metallization portion located between the second integrated device and the interposer.

16. The package of claim 1, wherein the first integrated device and / or the second integrated device includes a plurality of substrate vias.

17. The package according to claim 1, further comprising: A first metallization portion is coupled to the front side of the first integrated device; The second metallization portion is coupled to the back side of the first integrated device; and A third metallization portion is coupled to the second integrated device.

18. The package of claim 17, further comprising: A second encapsulation layer is located between the first metallized portion and the second metallized portion; and A third encapsulation layer, coupled to the third metallization portion. The encapsulation layer is located between the second metallized portion and the third metallized portion.

19. A method for manufacturing a package, the method comprising: Provide the first integrated device; A first encapsulation layer is formed and coupled to the first integrated device; A first metallization portion is formed and coupled to the first integrated device; Couple the intermediate layer to the first metallization portion; Couple the passive device to the first metallization portion; Forming a plurality of pillar interconnects coupled to the first metallized portion; A second encapsulation layer is formed that is coupled to the first metallization portion, the interposer layer, the passive device, and the plurality of pillar interconnects; A second metallization portion is formed that is coupled to the interposer layer, the passive device, and the plurality of pillar interconnects; as well as The second integrated device is coupled to the second metallized portion.

20. The method of claim 19, further comprising: A third encapsulation layer is formed that is coupled to the second integrated device; as well as A third metallization portion is formed and coupled to the second integrated device.

21. The method of claim 20, wherein the third metallization portion is coupled to the front side of the second integrated device.

22. The method of claim 19, wherein the second metallized portion is coupled to the back side of the second integrated device.

23. The method of claim 19, wherein the first metallized portion is coupled to the front side of the first integrated device.

24. The method of claim 19, wherein the first metallized portion is coupled to the back side of the first integrated device.

25. The method of claim 19, wherein the first integrated device is located between the first metallized portion and the second metallized portion.

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