A method for improving the period resolution of a PWM signal

Abstract

According to embodiments of the present invention, a method for improving the period resolution of a PWM signal is disclosed. The present invention can dynamically detect the number of delay units required for one clock cycle in real time, thereby improving design accuracy; it satisfies both the conditions for low-frequency clocks and the requirements for count clearing and clock synchronization; and it does not require a DLL module for implementation, saving the chip area occupied by the design DLL, and avoiding the need for the DLL module to route clock clusters, thus avoiding errors caused by routing.

Description

Technical Field

[0001] This invention relates to the field of power electronics, and more specifically, to a method for improving the period resolution of PWM signals. Background Technology

[0002] In digital chips, the resolution of PWM is typically determined by the clock frequency; therefore, increasing the PWM resolution requires increasing the clock frequency. In chip design, high-frequency clocks place stringent demands on manufacturing processes and layout / routing, undoubtedly increasing design complexity and cost. Besides increasing the clock frequency, using a delay-locked loop (DLL) is another common method. While DLLs can achieve high PWM resolution, they also have drawbacks: although they can output clocks with a fixed delay, they increase the design area and cost; furthermore, when the clock cluster output by the DLL is input to the PWM module, inconsistencies in routing can lead to errors in PWM resolution, thus requiring precise clock cluster routing. Summary of the Invention

[0003] In view of this, the present invention proposes a method to improve the period resolution of PWM signals, so as to solve the technical problems of high requirements for wiring and high cost of DLL in the prior art, and at the same time, it can meet the requirements of low frequency clock, as well as the requirements of count clearing and clock synchronization.

[0004] In a first aspect, embodiments of the present invention provide a method for improving the period resolution of a PWM signal, comprising the following steps: generating a first pulse width modulation signal according to a clock signal;

[0005] The period of the second pulse width modulation signal is divided into a first resolution that is a first integer multiple and a second resolution that is a second integer multiple;

[0006] The delay time is generated based on the number of delay units included in the second integer and one clock cycle;

[0007] The rising and falling edges of the first pulse width modulation signal are offset by an amount corresponding to the delay time to generate the second pulse width modulation signal.

[0008] Preferably, the number of delay units included in one clock cycle is detected;

[0009] A selection signal is generated based on the delay time and the number of delay units included in one clock cycle;

[0010] The output of the corresponding delay unit is selected according to the selection signal, thereby outputting the transition edge of the second pulse width modulation signal.

[0011] Preferably, the selection signal is generated based on the ratio of the first value and the second value, and based on the product of the ratio and the third value.

[0012] Wherein, the first value is used to characterize the number of delay units detected in one clock cycle, the second value is used to characterize the number of time units included in one clock cycle, and the third value is used to characterize the delay time, wherein the time unit is the theoretical delay time of one delay unit.

[0013] Preferably, the second integer is accumulated and cyclically counted. When the accumulated value is less than the second value, the counter is reset to the first integer. When the accumulated value is greater than or equal to the second value, the counter is reset to the first integer plus 1.

[0014] Wherein, the second value represents the number of time units included in one clock cycle, the first resolution corresponds to the clock cycle, the second resolution corresponds to the time unit, and the time unit is the theoretical delay time of one delay unit.

[0015] Preferably, when the count value reaches the value corresponding to the first and second modulation signals, the modulation signal is delayed relative to the accumulated value, thereby outputting the transition edge of the second pulse width modulation signal;

[0016] The modulation signal is used to control the rising edge of the first pulse width modulation signal, and the second modulation signal controls the falling edge of the first pulse width modulation signal.

[0017] Preferably, when the accumulated value is less than the second value, when the count value reaches the value corresponding to the modulation signal, the delay time relative to the modulation signal is obtained based on the accumulated value.

[0018] Preferably, when the accumulated value is greater than or equal to the second value, the accumulated value is configured as the current accumulated value minus the second value. When the count value reaches the value corresponding to the modulation signal plus 1, the delay time relative to the first or second modulation signal is obtained according to the accumulated value.

[0019] Preferably, the method further includes the following steps:

[0020] The decrement value is cumulatively and cyclically decreased based on the second integer. When the decrement value is greater than the second integer, the counter is reset to zero at the time when the first integer is incremented by 1; when the decrement value is less than or equal to the second integer, the counter is reset to zero at the time when the first integer is incremented by 1.

[0021] Wherein, the first resolution corresponds to the clock cycle, the second resolution corresponds to the time unit, and the time unit is the theoretical delay time of a delay unit.

[0022] Preferably, when the count value reaches the value corresponding to the third or fourth modulation signal, the modulation signal is delayed relative to the decreasing value, thereby outputting the transition edge of the second pulse width modulation signal;

[0023] The third modulation signal is used to control the rising edge of the first pulse width modulation signal, and the fourth modulation signal is used to control the rising edge of the first pulse width modulation signal.

[0024] Preferably, when the decrement value is less than or equal to the second integer, the decrement value is configured to be the current decrement value plus the second value. In the current PWM cycle, when the count value reaches the value corresponding to the modulation signal, the delay time relative to the modulation signal is obtained according to the decrement value. The second value represents the number of time units included in one clock cycle.

[0025] Preferably, when the decrement value is greater than the second integer, in the current PWM cycle, when the count value of the carrier counting module reaches the value corresponding to the modulation signal minus 1, the delay time relative to the modulation signal is obtained according to the decrement value.

[0026] Compared with the prior art, the technical solution of the present invention has the following advantages: the present invention can dynamically adjust the number of delay modules required for one clock cycle in real time, thereby improving the design accuracy; it satisfies both the conditions for low-frequency clocks and the requirements for count clearing and clock synchronization; and it does not require DLL modules for implementation, saving the chip area occupied by the design DLL, while also eliminating the need for routing clock clusters, thus avoiding errors caused by inconsistent routing. Attached Figure Description

[0027] The above and other objects, features and advantages of the present invention will become clearer from the following description of embodiments of the invention with reference to the accompanying drawings, in which:

[0028] Figure 1 This is a block diagram of the modulation circuit according to an embodiment of the present invention;

[0029] Figure 2 This is a circuit diagram of the modulation circuit according to an embodiment of the present invention;

[0030] Figure 3 This is a timing diagram of the clock calibration module according to an embodiment of the present invention;

[0031] Figure 4 This is a high-resolution waveform diagram of the PWM in an embodiment of the present invention;

[0032] Figure 5 This is a first high-resolution waveform diagram of the PWM cycle according to an embodiment of the present invention;

[0033] Figure 6 This is a second waveform diagram with high resolution of the PWM cycle according to an embodiment of the present invention. Detailed Implementation

[0034] The present invention is described below based on embodiments, but the invention is not limited to these embodiments. In the detailed description of the invention below, certain specific details are described in detail. Those skilled in the art will fully understand the invention even without these details. To avoid obscuring the essence of the invention, well-known methods, processes, flows, elements, and circuits are not described in detail.

[0035] Furthermore, those skilled in the art should understand that the accompanying drawings provided herein are for illustrative purposes only and are not necessarily drawn to scale.

[0036] Furthermore, it should be understood that in the following description, "circuit" refers to a conductive loop consisting of at least one element or sub-circuit connected by electrical or electromagnetic connections. When an element or circuit is said to be "connected" to another element or "connected" between two nodes, it can be directly coupled or connected to another element, or there may be intermediate elements. The connection between elements can be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly connected" to another element, it means that there are no intermediate elements between them.

[0037] like Figure 1 The diagram shown is a structural block diagram of the modulation circuit according to an embodiment of the present invention. The modulation circuit includes: a delay module 11, comprising a plurality of delay units connected in series, configured to receive a first pulse width modulation signal S_IN at the input terminal and generate a second pulse width modulation signal S_OUT at the output terminal; a delay unit detection module 12, configured to detect the number of delay units included in one clock cycle; and a calibration module 13, which generates a selection signal K2 based on the input signal representing the desired resolution information and the number of detected delay units. The delay module 11 selects the output of the corresponding delay unit according to the selection signal K2 for output, thereby delaying the rising edge or falling edge of the first pulse width modulation signal to output the second pulse width modulation signal.

[0038] like Figure 1 As shown, the modulation circuit also includes a pulse width modulation signal generation circuit 14, configured to receive the clock signal Clock and generate the first pulse width modulation signal S_IN, wherein the resolution of the first pulse width modulation signal S_IN is the clock period T of the clock signal Clock.

[0039] The number of delay units included in the delay module 11 is determined based on the theoretical delay time of each delay unit. Specifically, the number of delay units included in the delay module 11 is determined based on the theoretical delay time of one clock cycle delay unit. For example, if the clock cycle is T, the theoretical delay time of one delay unit is t. delay_1 Then one clock cycle is T, which includes T / t. delay_1 The theoretical delay time of each delay unit. However, due to factors such as temperature and air pressure, the actual delay time of the delay unit may differ from the theoretical delay time, affecting the resolution accuracy of the second pulse width modulation signal. Therefore, in this embodiment of the invention, the number of delay units needs to have a certain margin, which should be greater than T / t. delay_1 In one embodiment, the delay module includes two delay units. k There are 12 delay units, where k is a positive integer. Each delay unit outputs a delay signal, which also serves as the input signal to the delay unit detection module 12. This invention calibrates the number of delay units using a calibration module to obtain the number of delay units corresponding to the resolution of the second pulse width modulation signal.

[0040] Specifically, as an example, the delay unit detection module detects the number of delay units included in one clock cycle to generate a first value N representing the number of delay units. The calibration module generates a selection signal K2 based on the ratio of the first value N to a second value M, and the product of this ratio and a third value K1. The delay module selects the output of the corresponding delay unit based on the selection signal K2, thereby obtaining a second pulse width modulation signal with the desired resolution. Here, the second value M represents the number of time units included in one clock cycle, the third value K1 is a signal representing the desired resolution information, and the time unit is the theoretical delay time of the delay unit. Thus, by calibrating the number of delay units within one clock cycle, the modulation circuit of this embodiment can dynamically adjust the number of delay modules included in one clock cycle T in real time, thereby improving design accuracy.

[0041] like Figure 2The diagram shown is a circuit diagram of the modulation circuit 1 according to an embodiment of the present invention. The delay module 11 includes n delay units 111 connected in series, each corresponding to an output delay signal delay_1 to delay_n, with an offset of one delay time between the rising edges of adjacent delay signals. The delay unit detection module 12 is configured to receive the delay signals delay_1 to delay_n generated by each delay unit and a delay detection signal LINE_SAM. During the effective level of the delay detection signal LINE_SAM, it generates a first value N representing the number of delay units detected within one clock cycle based on each delay signal. The delay unit detection module 12 includes a holding module 121, which includes the same number of holding units 1211 as the delay units 111. Each holding unit 1211 receives the output of a corresponding delay unit 111. When the holding unit 1211 detects a rising edge of the received delay signal, it holds the step level after the rising edge. The delay unit detection module 12 determines the number of delay units included in one clock cycle based on the number of step levels.

[0042] like Figure 2 As shown, the delay unit detection module 12 also includes a counting unit 122, used to detect and count the number of step levels included in one clock cycle, thereby obtaining a first value N. Specifically, the counting unit 122 receives the output signals Q1 to Qn of the holding unit to generate the first value N. Additional delays may be introduced in the chip wiring, which can be eliminated by adding a clock synchronization module. When the delay unit detection module calibrates the number of delay units included in one clock cycle according to the actual delay time of the delay unit, a clock synchronization module is needed to synchronize the delay detection signal LINE_SAM and the first pulse width modulation signal S_IN with the clock signal Clock. That is, the rising edge of the delay detection signal LINE_SAM and the first pulse width modulation signal S_IN needs to be aligned with the rising edge or falling edge of the clock signal Clock. This embodiment takes the alignment of rising edges with rising edges and the step level as a high level as an example for explanation, but it is not limited to this.

[0043] Specifically, such as Figure 2As shown, the modulation circuit also includes a clock synchronization module, used to synchronize the first pulse width modulation signal S_IN and the delay detection signal LINE_SAM with the clock signal Clock, respectively. The synchronized delay detection signal contains a high level for one clock cycle and lags the synchronized first pulse width modulation signal by one clock cycle. The clock synchronization module includes a first synchronization module 14 and a second synchronization module 15, both of which are D flip-flops. The first input of the D flip-flop is the data input, and the second input is the clock signal input. The first input terminals of the first synchronization module 14 and the second synchronization module 15 are respectively connected to the first pulse width modulation signal S_IN and the delay detection signal LINE_SAM. The second input terminals of both the first synchronization module 14 and the second synchronization module 15 are connected to the clock signal Clock, thereby synchronizing the first pulse width modulation signal S_IN, the delay detection signal LINE_SAM, and the clock signal Clock. Specifically, when the rising edge of the first pulse width modulation signal S_IN is detected, the delay detection signal LINE_SAM outputs a high level for one clock cycle, causing the synchronized delay detection signal LINE_SAM_SYN output by the second synchronization module 15 to lag the synchronized first pulse width modulation signal S_IN_SYN output by the first synchronization module 14 by one clock cycle. When the rising edge of the LINE_SAM_SYN signal is detected, each holding unit latches the levels of the delay signals delay_1 to delay_n at the rising edge of the LINE_SAM_SYN signal. Here, delay_1 is the output after one delay unit 111, and delay_n is the output after n delay units 111.

[0044] like Figure 2 As shown, as an example, the holding unit 1211 is a D flip-flop. The first input terminal of each holding unit 1211 receives the output of the corresponding delay unit 111. The second input terminal of each holding unit 1211 is connected to the output of the second synchronization module 15. The output signal of each holding unit 1211 is input to the counting unit 122.

[0045] As an example, the delay module 11 also includes a multiplexer 112, wherein the delayed signals delay_1 to delay_n and the undelayed signal delay_0 are used as input signals to the multiplexer 112. The undelayed signal delay_0 is the first pulse width modulation signal S_IN, and one of delay_0 to delay_n is selected by the selection signal K2 as the second pulse width modulation signal output. Figure 3The diagram shows the timing of the delay unit detection module in this embodiment. At time t1, the rising edge of the clock signal Clock is detected. The first pulse width modulation signal S_IN received by the first synchronization module 14 at its first input terminal is at a high level, and the first synchronization module 14 outputs the synchronized first pulse width modulation signal S_IN_SYN at a high level. The delay detection signal LINE_SAM received by the second synchronization module 15 at its first input terminal is at a low level, and the second synchronization module 15 outputs the synchronized delay detection signal LINE_SAM_SYN at a low level. At time t2, when another rising edge of the clock signal Clock is detected, the first pulse width modulation signal S_IN is at a high level, and the synchronized first pulse width modulation signal S_IN_SYN remains at a high level. The delay detection signal LINE_SAM is at a high level, and the synchronized delay detection signal LINE_SAM_SYN output by the second synchronization module 15 jumps to a high level. Between time t1 and time t2 is one clock cycle T, and each delay unit outputs the corresponding delay signal delay_1 to delay_n. After time t2, once the synchronized delay detection signal LINE_SAM_SYN is pulled high, each holding unit 1211 latches the levels of delay_1 to delay_n at the first input terminal at time t2. Therefore, after time t2, the counting unit 122 can determine the number of delay units required for one clock cycle by judging the number of high levels among Q1 to Qn output by all holding units 1211. As shown in Figure 3 as an example, the high levels among Q1 to Qn are Q1 to QN, that is, the number of high levels is N, that is, the number of delay units required for one clock cycle T after calibration is N, that is, the first value is N.

[0046] As an example, the counting unit 122 includes a first counter for counting the high level output of the holding unit 1211 after time t2, that is, counting the number of step levels included in one clock cycle, thereby obtaining the number of delay units included in an actual clock cycle, that is, realizing the detection and calibration of the number of delay units included in one clock cycle based on the actual delay time of the delay units.

[0047] Specifically, such as Figure 2 As shown, the modulation circuit 1 further includes a calibration module 13, which generates a selection signal K2 based on the ratio of a first value and a second value, and the product of the ratio and the third value, wherein the second value is a number of theoretical delay times of delay units included in one clock cycle, and the third value is a signal representing the desired resolution information.

[0048] As an example, the output of the K2th delay unit is selected as the signal output by selecting signal K2, where K2 = K1 * N / M, and K1 is a signal characterizing the resolution information of the second pulse modulation signal of the desired output. As an example, K1 is the delay time t required to delay the rising or falling edge of the first pulse width signal and the theoretical delay time t of a delay unit. delay_1 The required number of delay units, K1 = t / t, is calculated. delay_1 M is a second value, representing the number of time units included in one clock cycle. The time unit is the theoretical delay time of the delay unit, M = T / t delay_1 N is the first value, so the signal K2 is selected as the input signal to the multiplexer 112. The multiplexer 112 selects the output of the K2th delay unit as the signal output, that is, the output of the K2th delay unit is output as the second pulse width modulation signal S_OUT.

[0049] Specifically, the delay unit detection module 12 can calibrate the first value N once at certain preset time intervals based on the actual delay time of the delay unit. This allows for real-time dynamic adjustment of the number of delay modules required for one clock cycle T, improving design accuracy.

[0050] Based on the modulation circuit described above, a pulse width modulation method can be implemented, including the following steps:

[0051] The first pulse width modulation signal is input to the delay module, wherein the delay module includes a plurality of delay units connected in series; the number of delay units included in one clock cycle is detected; a selection signal is generated according to the input signal representing the desired resolution information and the number of detected delay units; the output of the corresponding delay unit is selected according to the selection signal for output, thereby delaying the rising edge or falling edge of the first pulse width modulation signal to output the second pulse width modulation signal.

[0052] Specifically, a clock signal is received to generate the first pulse width modulation signal, wherein the resolution of the first pulse width modulation signal is the period of the clock signal. The selection signal is generated based on the ratio of a first value N and a second value M, and the product of the ratio and a third value K1, wherein the first value N represents the number of delay units detected within one clock cycle, the second value M represents the theoretical delay time of the delay units included in one clock cycle, and the third value K1 represents the signal representing the desired resolution information.

[0053] As an example, a delay detection signal and delay signals generated by each delay unit are received. During the active level of the delay detection signal, a first value representing the number of delay units detected within one clock cycle is generated based on each delay signal. The first pulse width modulation signal and the delay detection signal are synchronized with a clock signal, wherein the synchronized delay detection signal contains an active level of one clock cycle. As an example, the synchronized delay detection signal lags the synchronized first pulse width modulation signal by one clock cycle.

[0054] Specifically, such as Figure 4 As shown in the figures, as a first example, PWM1 in the figure, delays the rising edge of the first pulse width modulation signal S_IN, but does not delay the falling edge to achieve high duty cycle resolution of the PWM signal; as a second example, PWM2 in the figure, delays the falling edge of the first pulse width modulation signal S_IN, but does not delay the rising edge to achieve high duty cycle resolution or high dead zone resolution of the PWM signal; as a third example, PWM3 in the figure, delays both the rising and falling edges of the first pulse width modulation signal S_IN to achieve high phase resolution.

[0055] Based on the modulation circuit above, a method to improve the period resolution of the PWM signal can be implemented, including the following steps: generating a first pulse width modulation signal according to the clock signal;

[0056] The period of the second pulse width modulation signal is divided into a first resolution that is a first integer multiple and a second resolution that is a second integer multiple;

[0057] The delay time is generated based on the number of delay units included in the second integer and one clock cycle;

[0058] The rising and falling edges of the first pulse width modulation signal are offset by an amount corresponding to the delay time to generate a second pulse width modulation signal.

[0059] Specifically, it also includes the following steps: detecting the number of delay units included in one clock cycle;

[0060] A selection signal is generated based on the delay time and the number of delay units included in one clock cycle;

[0061] The output of the corresponding delay unit is selected according to the selection signal, thereby outputting the transition edge of the second pulse width modulation signal.

[0062] Specifically, the selection signal is generated based on the ratio of a first value and a second value, and the product of the ratio and a third value; wherein the first value is used to characterize the number of delay units detected in one clock cycle, the second value characterizes the number of time units included in one clock cycle, and the third value is a signal used to characterize the delay time, wherein the time unit is the theoretical delay time of one delay unit.

[0063] Specifically, the period value of the second pulse width modulation signal includes a first resolution multiple of a first integer PRD and a first resolution multiple of a fraction, and the first resolution multiple of the fraction is converted into a second resolution multiple of a second integer PRDHR; that is, the period value of the converted PWM signal includes a first resolution multiple of a first integer PRD and a second resolution multiple of a second integer PRDHR; wherein, the first resolution corresponds to one clock cycle, the second resolution corresponds to one time unit, and the time unit is the theoretical delay time of a delay unit.

[0064] The following describes the first method for improving the period resolution of a PWM signal, including the following steps:

[0065] The accumulated value PRDSUM is accumulated and cyclically counted according to the second integer PRDHR. When the accumulated value PRDSUM is less than the second value M, the count value counter corresponding to the control counter reset time is the first integer PRD. When the accumulated value PRDSUM is greater than or equal to the second value M, the count value counter corresponding to the control counter reset time is the first integer PRD plus 1. Wherein, the second value M is the number of time units contained in one clock cycle, and the time unit is the theoretical delay time of one delay unit.

[0066] The number of time units included in the delay of the transition edge of the second pulse width modulation signal relative to the modulation signal is obtained based on the modulation signal, the accumulated value PRDSUM, and the counter value counter. Then, the number of theoretical delay units is converted into the actual number of delay units required, thereby outputting the transition edge of the second pulse width modulation signal with high resolution, thus realizing high resolution of the PWM signal period.

[0067] In each PWM period, when the count value reaches the value corresponding to the modulation signal, a delay is performed relative to the modulation signal according to the accumulated value, so as to output the transition edge of the second pulse-width modulation signal; wherein, the modulation signal is used to control the rising edge or falling edge of the first pulse-width modulation signal. Specifically, when the count value counter of the counter reaches the value corresponding to the modulation signal, the number of theoretical delay time units of the delay units included in the delay relative to the modulation signal is obtained according to the accumulated value PRDSUM. When the accumulated value PRDSUM is greater than or equal to the second value M, the accumulated value PRDSUM is configured as the current accumulated value minus the second value M. In the current PWM period, when the count value of the carrier counting module reaches the value corresponding to the modulation signal plus 1, the number of time units included in the delay relative to the modulation signal is obtained according to the accumulated value PRDSUM.

[0068] It should be noted that the values in the above steps are all calculated based on the theoretical delay time of the delay unit. After calculating the number of time units (i.e., the theoretical delay time of the delay unit) included in the delay relative to the modulation signal, it is also necessary to calibrate according to the number of actual delay units included in one clock cycle to obtain the number of actual delay times of the delay units included in the delay relative to the modulation signal, so as to delay the transition edge of the first pulse-width modulation signal through the above modulation circuit.

[0069] Specifically, from the above analysis, it can be known that: K2 = K1 * N / M. Corresponding to this example, K1 is the number of time units included in the delay time relative to the modulation signal; K2 is the selection signal; the output of the corresponding delay unit is selected according to the selection signal, so as to output the transition edge of the second pulse-width modulation signal; the second value M is the number of time units included in one clock cycle T, N is the first value, and the time unit is the theoretical delay time of the delay unit.

[0070] Assume that one clock cycle T contains M time units. The moment when the counter is cleared is not only related to the first integer PRD, but also related to the second integer PRDHR. In the k-th period of the PWM signal, when PRDHR + PRDSUM(k) < M, the moment when the count value counter of the counter is cleared is PRD, that is, the current period includes PRD clock cycles, and then the accumulated value PRDSUM(k) = PRDSUM(k - 1) + PRDHR is recorded; when PRDHR + PRDSUM(k) >= M, the moment when the count value counter of the counter is cleared is PRD + 1, that is, the current period includes PRD + 1 clock cycles, and then the accumulated value PRDSUM(k) = PRDSUM(k - 1) + PRDHR - M is recorded; where k refers to the k-th period of the PWM signal.

[0071] The modulation signal also has an integer part (CMP) and a fractional part (CMPHR). In the k-th period of the PWM signal, when CMPHR + PRDSUM(k) < M, the PWM transition edge corresponding to the modulation signal is at the counter value counter = CMP of the counter, and the number of delay units required for the delay time of the PWM transition edge relative to the modulation signal is CMPHR + PRDSUM(k); when CMPHR + PRDSUM(k) >= M, the PWM transition edge corresponding to the modulation signal is at the carrier counter = CMP + 1, and the number of delay units required for the delay time of the PWM transition edge corresponding to the modulation signal is CMPHR + PRDSUM(k) - M. At this time, it can also be considered that the PWM transition edge is at the carrier counter = CMP, and the delay time of the transition edge relative to the modulation signal is CMPHR + PRDSUM(k).

[0072] As Figure 5 shown, it is the waveform diagram of the PWM period with high resolution. In this example, assume M = 16, the period value of the second pulse width modulation signal is 9.375 clock cycles, that is, the theoretical delay time of 9 clock cycles and 0.375 / (1 / 16) = 0.375 * 16 = 6 delay units, that is, the first integer PRD = 9, the second integer PRDHR = 6; the low level of the second pulse width modulation signal is 6 clock cycles, the number of the second resolution included in the low level of the second pulse width modulation signal CMPAHR = 0, the high level of the second pulse width modulation signal is 3.375 clock cycles, the number of the second resolution included in the high level of the second pulse width modulation signal CMPBHR = PRDHR = 6; in this example, the modulation signal includes the first modulation signal and the second modulation signal, which respectively control the rising edge and the falling edge of the first pulse width modulation signal S_IN, and respectively correspond to the counter values counter of the counter being 4 and 7, that is, the number of the first resolution corresponding to the first modulation signal is CMPA = 4, and the number of the first resolution corresponding to the second modulation signal is CMPB = 7.

[0073] The first PWM period: PRDSUM(1) = 0, PRDHR + PRDSUM(1) = 0 + 6 = 6 < 16, the moment when the counter value counter of the counter is cleared is PRD, so the current PWM period is 9 clock cycles, the delay value CMPAHR(1) = PRDSUM(1) = 0 of the rising edge relative to the counter value counter = CMPA = 4 of the counter, and the delay value CMPBHR(1) = PRDSUM(1) + CMPBHR = 0 + 6 = 6 of the falling edge relative to the counter value counter = CMPB = 7 of the second modulation signal;

[0074] The second PWM cycle: PRDSUM(2)=PRDHR+PRDSUM(1)=6+0=6,PRDHR+PRDSUM(2)=6+6=12<16,The counter's count value counter is cleared at PRD,therefore the current PWM cycle is 9 clock cycles; The rising edge is relative to the counter's count value counter=CMPA=4, the delay value CMPAHR(2)=CMPAHR+PRDSUM(2)=0+6=6,The falling edge is relative to the second modulation signal counter's count value counter=CMPB=7, the delay value CMPBHR(2)=PRDSUM(2)+CMPBHR=6+6=12;

[0075] The third PWM cycle: PRDSUM(3)=PRDHR+PRDSUM(2)=6+6=12,PRDHR+PRDSUM(3)=6+12=18>16,The counter value counter is cleared at PRD+1,Therefore, the current PWM cycle is 10 clock cycles. The rising edge is delayed by the counter value counter=CMPA=4, the rising edge is delayed by the counter value counter=CMPB+1=8, and the falling edge is delayed by the counter value counter=CMPB+1=8, which is 18-16=2;

[0076] The fourth PWM cycle: PRDSUM(4)=PRDHR+PRDSUM(3)=12+6=18>16, so PRDSUM(4)=PRDHR+PRDSUM(3)-M=12+6-16=2, PRDSUM(4)+PRDHR=8<16, so the current PWM cycle is 9 clock cycles; the delay value of the rising edge relative to the counter value counter=CMPA=4 is CMPAHR(4)=PRDSUM(4)+CMPAHR=2, and the delay value of the falling edge relative to the counter value counter=CMPB=7 is CMPBHR(4)=PRDSUM(4)+CMPBHR=2+6=8.

[0077] Then, according to K2 = K1 * N / M, where K1 corresponds to CMPAHR(k) and CMPBHR(k) in this example, k corresponds to the kth period of the second pulse width modulation signal, M is the number of time units included in one clock period T, and N is the first value; CMPAHR(k) is the theoretical delay time of the rising edge of the kth period of the PWM signal relative to the delay unit that needs to be delayed by the first modulation signal, and CMPBHR(k) is the theoretical delay time of the falling edge of the kth period of the second pulse width modulation signal relative to the delay unit that needs to be delayed by the second modulation signal. Specifically, CMPAHR(k) is converted using CMPAHR(k)*N / M to obtain the actual delay of the rising edge of the second pulse width modulation signal relative to the first modulation signal in the k-th cycle. That is, in the k-th cycle, the modulation circuit selects the output of the CMPAHR(k)*N / M delay unit relative to the first modulation signal as the rising edge of the PWM signal for output. Similarly, CMPBHR(k) is converted using CMPBHR(k)*N / M to obtain the actual delay of the falling edge of the PWM wave relative to the second modulation signal in the k-th cycle. That is, in the k-th cycle, the modulation circuit selects the output of the CMPBHR(k)*N / M delay unit relative to the second modulation signal as the falling edge of the second pulse width modulation signal for output. This achieves high resolution of the PWM signal cycle by delaying the rising edge (or the first modulation signal corresponding to the rising edge) or falling edge (or the second modulation signal corresponding to the falling edge) of the first pulse width modulation signal S_IN.

[0078] The second method for improving the period resolution of PWM signals is described below, including the following steps:

[0079] The decrement value EXPRDHR is cumulatively and cyclically decremented based on the second integer PRDHR. When the decrement value EXPRDHR is greater than the second integer PRDHR, the counter value counter is reset to the first integer PRD at the time of reset. When the decrement value EXPRDHR is less than or equal to the second integer PRDHR, the counter value counter is reset to the first integer PRD plus 1 at the time of reset. The second value M represents the number of time units included in one clock cycle, and the time unit is the theoretical delay time of one delay unit.

[0080] When the count value reaches the value corresponding to the modulation signal, a delay is applied relative to the modulation signal based on the decrement value, thereby outputting the rising edge of the second pulse width modulation signal; wherein, the modulation signal is used to control the rising or falling edge of the first pulse width modulation signal. Specifically, the theoretical delay time of the delay unit included in the delay of the rising edge of the second pulse width modulation signal relative to the modulation signal is obtained based on the modulation signal, the decrement value, and the counter value, thereby achieving high resolution of the PWM signal period. When the decrement value EXPRDHR(k) is less than or equal to the second integer PRDHR, the decrement value EXPRDHR(k) is configured as the current decrement value plus the second value M. In the current PWM cycle, when the count value of the carrier counting module reaches the value corresponding to the modulation signal, the number of time units included in the delay relative to the modulation signal is obtained according to the decrement value EXPRDHR(k). When the decrement value EXPRDHR(k) is greater than the second integer PRDHR, in the current PWM cycle, when the count value of the carrier counting module reaches the modulation signal minus 1, the number of time units included in the delay relative to the modulation signal is obtained according to the decrement value EXPRDHR(k).

[0081] It should be noted that the values ​​in the above steps are all calculated based on the theoretical delay time of the delay unit. After calculating the number of time units included in the delay time of the relative modulation signal, it is necessary to calibrate according to the actual number of delay units included in one clock cycle to obtain the actual delay time of the delay units included in the delay time of the relative modulation signal. Thus, the above modulation circuit can delay the transition edge of the PWM signal.

[0082] Specifically, as can be seen from the above analysis: K2 = K1 * N / M, which corresponds to the following in this example: K1 is the number of theoretical delay times of the delay units included in the delay time of the relative modulation signal; K2 is the number of actual delay times of the delay units included in the delay time of the relative modulation signal; M is the number of time units included in one clock cycle T; and N is the first value.

[0083] The following example illustrates this. Assume that, based on the theoretical delay time of the delay unit, one clock cycle contains M time units. The time for the counter module to be cleared is related not only to the first integer PRD, but also to the second integer PRDHR.

[0084] In the k-th cycle of the second pulse width modulation signal, when PRDHR >= EXPRDHR(k), the counter value counter is cleared at PRD + 1, that is, the current cycle includes PRD + 1 clock cycles, and then record the value EXPRDHR(k) = M + EXPRDHR(k - 1) - PRDHR; when PRDHR < EXPRDHR(k), the counter value counter is cleared at PRD, that is, the current cycle includes PRD + 1 clock cycles, and then record the decreasing value EXPRDHR(k) = EXPRDHR(k - 1) - PRDHR; where k refers to the k-th cycle of the PWM signal.

[0085] The modulation signal also has an integer part (CMP) and a fractional part (CMPHR). When CMPHR >= EXPRDHR(k), the PWM transition edge corresponding to the modulation signal is at the position where the counter value counter = CMP, and the number of delay units corresponding to the delay is CMPHR - EXPRDHR(k); when CMPHR < EXPRDHR(k), the PWM transition edge corresponding to the modulation signal is at the position where the counter value counter = CMP - 1, and the number of delay units corresponding to the delay time is M + CMPHR - EXPRDHR(k).

[0086] As Figure 6 shown, it is the waveform diagram of the high resolution of the PWM period. Assume M = 16, the period value of the second pulse width modulation signal is 9.375 clock cycles, that is, 9 clock cycles and 0.375 / (1 / 16) = 0.375 * 16 = 6 delay units, that is, the first integer PRD = 9, the second integer PRDHR = 6; the low level of the second pulse width modulation signal is 6 clock cycles, and the number of the second resolution included in the low level of the second pulse width modulation signal CMPCHR = 0; the high level of the second pulse width modulation signal is 3.375 clock cycles, and the number of the second resolution included in the high level of the second pulse width modulation signal CMPDHR = PRDHR = 6; in this example, the modulation signal includes the third modulation signal and the fourth modulation signal, which respectively control the rising edge and the falling edge of the first pulse width modulation signal S_IN, and respectively correspond to the counter values counter of 4 and 7, that is, the third modulation signal corresponds to the number of the first resolution of 4, and the fourth modulation signal corresponds to the number of the first resolution of CMPD = 7.

[0087] The first PWM period: EXPRDHR(1) = 0, PRDHR > EXPRDHR(1), the counter value counter is cleared at PRD + 1 = 10, so the current PWM period value is 10 clock cycles; CMPCHR >= EXPRDHR(1), the rising edge is at the counter value counter = CMPC, and the number of delay units required for the delay CMPCHR(1) = CMPCHR – EXPRDHR(1) = 0; CMPDHR >= EXPRDHR(1), the falling edge is at the counter value counter = CMPD, and the number of delay units required for the delay CMPDHR(1) = CMPDHR – EXPRDHR(1) = 6;

[0088] The second PWM period: Since EXPRDHR(1) < PRDHR, then EXPRDHR(2) = M + EXPRDHR(1) - PRDHR = 16 + 0 - 6 = 10; PRDHR < EXPRDHR(2), the counter value counter is cleared at PRD = 9, so the current PWM period value is 9 clock cycles; CMPCHR < EXPRDHR(2), the rising edge is at the counter value counter = CMPC - 1, and the number of delay units required for the delay CMPCHR(2) = M + CMPCHR – EXPRDHR(2) = 16 + 0 - 10 = 6; CMPDHR < EXPRDHR(2), the falling edge is at the counter value counter = CMPD - 1, and the number of delay units required for the delay CMPDHR(2) = M + CMPDHR – EXPRDHR(2) = 16 + 6 - 10 = 12;

[0089] The third PWM period: EXPRDHR(3) = EXPRDHR(2) - PRDHR = 10 - 6 = 4; PRDHR > EXPRDHR(3), the counter value counter is cleared at PRD + 1 = 10, so the current PWM period value is 10 clock cycles; CMPCHR < EXPRDHR(3), the rising edge is at the counter value counter = CMPC - 1, and the number of delay units required for the delay CMPCHR(3) = M + CMPCHR – EXPRDHR(3) = 16 + 0 - 4 = 12; CMPDHR >= EXPRDHR(3), the falling edge is at the counter value counter = CMPD, and the number of delay units required for the delay is CMPDHR(3) = CMPDHR – EXPRDHR(3) = 6 - 4 = 2;

[0090] Fourth PWM period: Since EXPRDHR(3) < PRDHR, then EXPRDHR(4) = M + EXPRDHR(3) - PRDHR = 16 + 4 - 6 = 14; PRDHR < EXPRDHR(4), the counter value counter is cleared at PRD, so the current PWM period value is 9 clock cycles; CMPCHR < EXPRDHR(4), the rising edge of the PWM is at the counter value counter = CMPC - 1, and the number of delay units required for the delay CMPCHR(4) = M + CMPCHR – EXPRDHR(4) = 16 + 0 - 14 = 2; CMPDHR < EXPRDHR(4), the falling edge of the PWM is at the counter value counter = CMPD - 1, and the number of delay units required for the delay CMPDHR(4) = M + CMPDHR – EXPRDHR(4) = 16 + 6 - 14 = 8; then EXPRDHR(5) = EXPRDHR(4) - PRDHR = 14 - 6 = 8.

[0091] Similarly, in this embodiment, according to K2 = K1 * N / M, K1 corresponds to CMPCHR(k) and CMPDHR(k) in this example, where k is the k-th period of the second pulse width modulation signal; the second value M is the number of time units included in one clock cycle T, and N is the first value. Specifically, CMPCHR(k) is converted by CMPCHR(k) * N / M to obtain the actual number of delay units of the rising edge of the PWM signal relative to the third modulation signal in the k-th period, that is, in the k-th period, the modulation circuit selects the output of the CMPCHR(k) * N / M-th delay unit relative to the counter value equal to CMPC - 1 or CMPC as the rising edge of the PWM signal to output; CMPDHR(k) is converted by CMPDHR(k) * N / M to obtain the actual number of delay units of the falling edge of the PWM signal relative to the fourth modulation signal in the k-th period, that is, in the k-th period, the modulation circuit selects the output of the CMPDHR(k) * N / M-th delay unit relative to the counter value equal to CMPD - 1 or CMPD as the falling edge of the PWM signal to output, thereby achieving high-resolution PWM signal period by delaying the rising edge (or the third modulation signal corresponding to the rising edge) or the falling edge (or the fourth modulation signal corresponding to the falling edge) of the first pulse width modulation signal S_IN.

[0092] In summary, this invention provides a method for improving the period resolution of a PWM signal. The method involves generating a first pulse width modulation (PWM) signal based on a clock signal; dividing the period of a second PWM signal into a first resolution multiple of a first integer and a second resolution multiple of a second integer; generating a delay time based on the second integer and the number of delay units included in a clock cycle; and offsetting the rising and falling edges of the first PWM signal by an offset corresponding to the delay time to generate the second PWM signal. This invention can dynamically adjust the number of delay modules required for one clock cycle in real time, improving design accuracy; it satisfies both the conditions for low-frequency clocks and the requirements for count clearing and clock synchronization; and it eliminates the need for DLL modules, saving chip area occupied by DLL design and avoiding errors caused by DLL module routing of clock clusters.

[0093] Although the embodiments or implementations are described and explained separately above, some common technologies are involved. Those skilled in the art can replace and integrate them among the embodiments or implementations. If any content is not explicitly described in one embodiment or implementation, reference can be made to another embodiment that is described.

[0094] As described above, these embodiments of the present invention do not exhaustively cover all details, nor do they limit the invention to the specific embodiments described. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to effectively utilize the invention and its modifications. The invention is limited only by the claims and their full scope and equivalents.

Claims

1. A method for improving the period resolution of a PWM signal, comprising the following steps: The first pulse width modulation signal is generated based on the clock signal; The period of the second pulse width modulation signal is divided into a first resolution that is a first integer multiple and a second resolution that is a second integer multiple; The delay time is generated based on the number of delay units included in the second integer and one clock cycle; The rising and falling edges of the first pulse width modulation signal are offset by an amount corresponding to the delay time to generate the second pulse width modulation signal.

2. The method according to claim 1, characterized in that, The method further includes the following steps: Detect the number of delay units included in one clock cycle; A selection signal is generated based on the delay time and the number of delay units included in one clock cycle; The output of the corresponding delay unit is selected according to the selection signal, thereby outputting the transition edge of the second pulse width modulation signal.

3. The method according to claim 2, characterized in that, The method further includes the following steps: The selection signal is generated based on the ratio of the first value and the second value, and based on the product of the ratio and the third value. Wherein, the first value is used to characterize the number of delay units detected in one clock cycle, the second value is used to characterize the number of time units included in one clock cycle, and the third value is used to characterize the delay time, wherein the time unit is the theoretical delay time of one delay unit.

4. The method according to claim 1, characterized in that, The method further includes the following steps: The second integer is incremented in a loop. When the incremented value is less than the second integer, the counter is reset to the first integer. When the incremented value is greater than or equal to the second integer, the counter is reset to the first integer plus 1. Wherein, the second value represents the number of time units included in one clock cycle, the first resolution corresponds to the clock cycle, the second resolution corresponds to the time unit, and the time unit is the theoretical delay time of one delay unit.

5. The method according to claim 4, characterized in that: When the count value reaches the value corresponding to the first and second modulation signals, the accumulated value is used to delay the modulation signal, thereby outputting the transition edge of the second pulse width modulation signal; The modulation signal is used to control the rising edge of the first pulse width modulation signal, and the second modulation signal controls the falling edge of the first pulse width modulation signal.

6. The method according to claim 5, characterized in that: When the accumulated value is less than the second value, when the count value reaches the value corresponding to the modulation signal, the delay time relative to the modulation signal is obtained based on the accumulated value.

7. The method according to claim 5, characterized in that: When the accumulated value is greater than or equal to the second value, the accumulated value is configured as the current accumulated value minus the second value. When the count value reaches the value corresponding to the modulation signal plus 1, the delay time relative to the first or second modulation signal is obtained according to the accumulated value.

8. The method according to claim 1, characterized in that, The method further includes the following steps: The decrement value is cumulatively and cyclically decreased based on the second integer. When the decrement value is greater than the second integer, the counter is reset to zero at the time when the first integer is incremented by 1; when the decrement value is less than or equal to the second integer, the counter is reset to zero at the time when the first integer is incremented by 1. Wherein, the first resolution corresponds to the clock cycle, the second resolution corresponds to the time unit, and the time unit is the theoretical delay time of a delay unit.

9. The method according to claim 8, characterized in that: When the count value reaches the value corresponding to the third or fourth modulation signal, the modulation signal is delayed relative to the count value, thereby outputting the transition edge of the second pulse width modulation signal; The third modulation signal is used to control the rising edge of the first pulse width modulation signal, and the fourth modulation signal is used to control the rising edge of the first pulse width modulation signal.

10. The method according to claim 9, characterized in that: When the decrement value is less than or equal to the second integer, the decrement value is configured to be the current decrement value plus the second value. In the current PWM cycle, when the count value reaches the value corresponding to the modulation signal, the delay time relative to the modulation signal is obtained according to the decrement value. The second value represents the number of time units included in one clock cycle.

11. The method according to claim 9, characterized in that: When the decrement value is greater than the second integer, in the current PWM cycle, when the count value of the carrier counting module reaches the value corresponding to the modulation signal minus 1, the delay time relative to the modulation signal is obtained according to the decrement value.

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