Adder circuit, chip, computing device and electronic device

Abstract

This disclosure provides an adder circuit, chip, computing device, and electronic device. The circuit includes: a cascaded half-adder, at least one full-adder, and a sign-selectable adder; the half-adder performs addition on the least significant bit of a first multi-bit number and the least significant bit of a second multi-bit number, outputting a first carry-in and a least significant bit result; at least one full-adder performs addition on the middle bit of the first multi-bit number, the middle bit of the second multi-bit number, and the first carry-in, or the second carry-in output by the previous full-adder, outputting at least one second carry-in and at least one middle bit result; and a sign-selectable adder performs addition on the most significant bit of the first multi-bit number, the most significant bit of the second multi-bit number, and the second carry-in output by the previous full-adder, outputting the most significant bit result and the most significant carry-in, or outputting the most significant bit result and the sign result.

Description

Technical Field

[0001] This disclosure relates to the field of data computing technology, and in particular to an adder circuit, chip, computing device, and electronic device. Background Technology

[0002] Adders are a fundamental component in digital circuits. Their operation is based on the rules of binary number addition and the design of logic gates. They receive the addend and augend (and possibly carry-in) as inputs and output the sum and carry. In data processing / computation chip design, adder trees composed of full adders and half adders are typically used to perform operations on multi-bit binary numbers. Summary of the Invention

[0003] Embodiments of this disclosure provide an adder circuit, a chip, a computing device, and an electronic device.

[0004] According to one aspect of the present disclosure, an adder circuit is provided, comprising: a cascaded half adder, at least one full adder, and a sign-selectable adder;

[0005] The half-adder is used to perform an addition operation on the least significant bit value of the first multi-bit number and the least significant bit value of the second multi-bit number to be calculated, and outputs the first carry value and the least significant bit result value; wherein, the first multi-bit number and the second multi-bit number are signed numbers, or the first multi-bit number and the second multi-bit number are unsigned numbers;

[0006] The at least one full adder is used to perform an addition operation on the middle bit value of the first multi-bit number, the middle bit value of the second multi-bit number, and the first carry value or the second carry value output by the previous full adder, and output at least one second carry value and at least one middle bit result value.

[0007] The sign-selectable adder is used to perform addition operations on the highest bit value of the first multi-bit number, the highest bit value of the second multi-bit number, and the second carry value output by the previous full adder, and output the highest bit result value and the highest carry value, or output the highest bit result value and the sign result value.

[0008] Optionally, the sign-selectable adder includes: a full adder module, a carry calculation module, a sign calculation module, and an output control module;

[0009] The full adder module is used to perform unsigned addition on the input data to obtain the highest bit result value; wherein, the input data includes the highest bit value of the first multi-bit number, the highest bit value of the second multi-bit number, and the second carry value output by the previous full adder;

[0010] The carry calculation module is used to perform at least one logical operation on the input data to obtain the highest carry value;

[0011] The symbol calculation module is used to perform at least one logical operation on the input data to obtain a symbol result value;

[0012] The output control module is connected to the carry calculation module and the sign calculation module respectively, and is used to output the highest carry value or the sign result value according to the control signal.

[0013] Optionally, the carry calculation module includes: a first AND gate, a second AND gate, a third AND gate, and a first OR gate;

[0014] The first AND gate performs an AND logic operation on the highest bit value of the first multi-bit number and the highest bit value of the second multi-bit number, and inputs the result of the first logic operation into the first OR gate;

[0015] The second AND gate performs an AND logic operation on the highest bit value in the first multi-bit number and the second carry value output by the full adder in the previous stage, and inputs the result of the second logic operation into the first OR gate;

[0016] The third AND gate performs an AND logic operation on the highest bit value of the second multi-bit number and the second carry value output by the previous full adder, and inputs the result of the third logic operation into the first OR gate;

[0017] The first OR gate performs an OR logic operation on the first logic operation result, the second logic operation result, and the third logic operation result to obtain the highest carry value.

[0018] Optionally, the symbol computation module includes: a first AND gate, a fourth AND gate, a fifth AND gate, and a second OR gate;

[0019] The fourth AND gate performs an AND logic operation on the highest bit value and the third carry value in the first multi-bit number, and inputs the result of the fourth logic operation into the second OR gate; the third carry value is obtained by inverting the second carry value output by the previous stage full adder;

[0020] The fifth AND gate performs an AND logic operation on the highest bit value in the second multi-bit number and the third carry value, and inputs the result of the fifth logic operation into the second OR gate.

[0021] The second OR gate performs an OR logic operation on the first logic operation result, the fourth logic operation result, and the fifth logic operation result to obtain the symbolic result value.

[0022] Optionally, the symbol computation module further includes: a NOT gate;

[0023] The NOT gate is used to invert the second carry value output by the previous full adder to obtain the third carry value.

[0024] Optionally, the control signal includes a first control signal and a second control signal;

[0025] The output control module includes a first transmission gate and a second transmission gate;

[0026] The first transmission gate is used to output the highest carry value according to the control of the first control signal and the second control signal;

[0027] The second transmission gate is used to output the symbol result value according to the control of the first control signal and the second control signal.

[0028] Optionally, the values ​​of the first control signal and the second control signal are opposite;

[0029] When the first control signal is low and the second control signal is high, the first transmission gate outputs the highest carry value; the second transmission gate does not output the sign result value.

[0030] In response to the second control signal being low and the first control signal being high, the second transmission gate outputs the symbol result value; the first transmission gate does not output the highest carry value.

[0031] According to another aspect of the present disclosure, a chip is provided, including the adder circuit described in any of the foregoing embodiments.

[0032] According to another aspect of the present disclosure, a computing device is provided, including the adder circuit or the chip described in any of the foregoing embodiments.

[0033] According to another aspect of the present disclosure, an electronic device is provided, including the chip or computing device described in the above embodiments.

[0034] The adder circuit, chip, computing device, and electronic device provided in the above embodiments of this disclosure include: a cascaded half adder, at least one full adder, and a sign-selectable adder; the half adder is used to perform an addition operation on the least significant bit value of a first multi-bit number to be computed and the least significant bit value of a second multi-bit number, and outputs a first carry value and a least significant bit result value; wherein the first multi-bit number and the second multi-bit number are signed numbers, or the first multi-bit number and the second multi-bit number are unsigned numbers; the at least one full adder is used to perform an addition operation on the middle bit value of the first multi-bit number, the middle bit value of the second multi-bit number, and the first carry value, or the second carry value output by the previous full adder, and outputs at least one second carry value and at least one middle bit result value; the sign-selectable adder is used to perform an addition operation on the highest significant bit value of the first multi-bit number, the highest significant bit value of the second multi-bit number, and the second carry value output by the previous full adder, and outputs the highest significant bit result value and the highest carry value, or outputs the highest significant bit result value and the sign result value. This embodiment of the disclosure enables the same circuit to perform calculations on both signed and unsigned numbers by using a sign-selectable adder. Compared to the prior art, which requires separate adders for signed and unsigned numbers, this embodiment of the disclosure integrates the two algorithms and achieves the sign selection function at a lower cost.

[0035] The technical solutions of this disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0036] The accompanying drawings, which form part of this specification, illustrate embodiments of this disclosure and, together with the description, serve to explain the principles of this disclosure.

[0037] This disclosure will become clearer with reference to the accompanying drawings and the following detailed description, wherein:

[0038] Figure 1a A schematic diagram of an unsigned 4-bit number adder is shown;

[0039] Figure 1b A schematic diagram of a signed 4-bit number adder is shown;

[0040] Figure 2a This is a circuit diagram of Sum4 processing in existing unsigned computation techniques;

[0041] Figure 2b This is a circuit diagram of Sum4 processing in symbolic computation in the prior art;

[0042] Figure 2c Karnaugh maps corresponding to Sum4 in both unsigned and signed computation in existing technologies;

[0043] Figure 3 This is a schematic diagram of the structure of an adder circuit provided in an exemplary embodiment of the present disclosure;

[0044] Figure 4 This is a schematic diagram of the circuit structure of a full adder in the prior art;

[0045] Figure 5 This is a schematic diagram of the structure of an adder circuit with selectable symbol provided in another exemplary embodiment of this disclosure;

[0046] Figure 6 This is a partial structural schematic diagram of an adder circuit with selectable symbol provided in yet another exemplary embodiment of this disclosure;

[0047] Figure 7 This is a schematic diagram of the circuit structure of an adder circuit with selectable symbol provided in an exemplary embodiment of the present disclosure;

[0048] Figure 8 This is a schematic diagram comparing the dynamic power consumption delay and static power consumption of the adder provided by the prior art solution and the embodiments of this disclosure. Detailed Implementation

[0049] Hereinafter, exemplary embodiments according to the present disclosure will be described in detail with reference to the accompanying drawings. Obviously, the described embodiments are merely some embodiments of the present disclosure, and not all embodiments of the present disclosure, and it should be understood that the present disclosure is not limited to the exemplary embodiments described herein.

[0050] It should be noted that, unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps set forth in these embodiments do not limit the scope of this disclosure.

[0051] Those skilled in the art will understand that the terms "first," "second," etc., in the embodiments of this disclosure are only used to distinguish different steps, devices, or modules, and do not represent any specific technical meaning, nor do they indicate a necessary logical order between them.

[0052] It should also be understood that in the embodiments disclosed herein, "a plurality of" may refer to two or more, and "at least one" may refer to one, two or more.

[0053] It should also be understood that any component, data or structure mentioned in the embodiments of this disclosure can generally be understood as one or more unless expressly defined or given to the contrary in the context.

[0054] Furthermore, the term "and / or" in this disclosure is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this disclosure generally indicates that the preceding and following related objects have an "or" relationship. The data referred to in this disclosure can include unstructured data such as text, images, and videos, as well as structured data.

[0055] It should also be understood that the description of the various embodiments in this disclosure emphasizes the differences between the various embodiments, and the similarities or similarities can be referred to each other. For the sake of brevity, they will not be described in detail.

[0056] At the same time, it should be understood that, for ease of description, the dimensions of the various parts shown in the accompanying drawings are not drawn according to actual scale.

[0057] The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit this disclosure or its application or use.

[0058] Techniques, methods, and equipment known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and equipment should be considered part of the specification.

[0059] It should be noted that similar labels and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be discussed further in subsequent figures.

[0060] The embodiments disclosed herein can be applied to electronic devices such as terminal devices, computer systems, and servers, and can operate together with a wide range of other general-purpose or special-purpose computing system environments or configurations. Examples of well-known terminal devices, computing systems, environments, and / or configurations suitable for use with electronic devices such as terminal devices, computer systems, and servers include, but are not limited to: personal computer systems, server computer systems, thin clients, thick clients, handheld or laptop devices, microprocessor-based systems, set-top boxes, programmable consumer electronics, network PCs, minicomputer systems, mainframe computer systems, and distributed cloud computing environments including any of the above systems, etc.

[0061] Electronic devices such as terminal devices, computer systems, and servers can be described in the general context of computer system executable instructions (such as program modules) executed by a computer system. Typically, program modules can include routines, programs, object programs, components, logic, data structures, etc., which perform specific tasks or implement specific abstract data types. Computer systems / servers can be implemented in distributed cloud computing environments, where tasks are executed by remote processing devices linked through communication networks. In distributed cloud computing environments, program modules can reside on local or remote computing system storage media, including storage devices.

[0062] Application Overview

[0063] In developing this disclosure, the inventors discovered that binary arithmetic is divided into unsigned arithmetic and signed arithmetic, and related technologies implement these operations using unsigned adders and signed adders. Unsigned adders accept non-negative inputs and do not require handling the sign bit in negative number or overflow detection; they simply perform bit-by-bit addition on the two binary numbers. Signed adders, on the other hand, perform addition on two signed binary numbers (positive or negative), requiring handling carry and overflow. They typically use two's complement representation, where the highest bit is the sign bit (0 for positive, 1 for negative). The two's complement of a positive number is itself, while the two's complement of a negative number is obtained by inverting its binary representation (excluding the highest bit) and adding 1.

[0064] In related technical solutions, calculations involving unsigned and signed binary numbers require completely independent design of corresponding adders. Taking the addition of two 4-bit binary numbers as an example, unsigned addition requires one half-adder and three full adders, while signed addition requires an additional full adder for sign bit calculation. Figure 1a and Figure 1b As shown, Figure 1a A schematic diagram of an unsigned 4-bit number adder is shown. Figure 1b The diagram illustrates a signed 4-bit number adder. Let A and B be the two 4-bit numbers. The binary representations of A and B are: A = a3a2a1a0 and B = b3b2b1b0, respectively. The sum SUM is represented as: SUM = Sum4Sum3Sum2Sum1Sum0. In unsigned operations, the highest bit Sum4 of SUM represents the carry from the sum of a3 and b3, which can be calculated using the following formula:

[0065] Sum4=Co4 (1-1)

[0066]

[0067]

[0068]

[0069]

[0070] Co₄=a³b³+a³Co₃+b³Co₃ (1-6)

[0071] Co3=a2b2+a2Co2+b2Co2 (1-7)

[0072] Co2=a1b1+a1Co1+b1Co1 (1-8)

[0073] Co1=a0b0 (1-9)

[0074] In signed arithmetic, the highest bit of SUM, Sum4, is used as the sign bit. The calculation formula is as follows:

[0075]

[0076]

[0077]

[0078]

[0079]

[0080] Co₄=a³b³+a³Co₃+b³Co₃ (2-6)

[0081] Co3=a2b2+a2Co2+b2Co2 (2-7)

[0082] Co2=a1b1+a1Co1+b1Co1 (2-8)

[0083] Co1=a0b0 (2-9)

[0084] The two operations mentioned above differ only in the highest bit Sum4, as shown in formulas 1-1 and 2-1. Figure 2a This is a circuit diagram of Sum4 processing in existing unsigned computation techniques; Figure 2b This is a circuit diagram of Sum4 processing in symbolic computation in the prior art; Figure 2c This is a Karnaugh map showing the Sum4 operation in both unsigned and signed computation in existing technologies. For the unsigned Sum4 operation, according to formulas 1-1 and 1-6, only a single-stage full adder is needed, such as... Figure 2a As shown; however, the signed operation Sum4, according to formulas 2-1 and 2-6, requires two cascaded full adders, as shown. Figure 2b .

[0085] In real-world large-scale computing scenarios, the frequency of use of unsigned and signed computation depends on the specific application scenario and data type. Therefore, data types and computational requirements are complex and diverse, leading to the application of both computational methods. Unsigned computation cannot be applied to scenarios requiring the handling of negative numbers (e.g., physics simulations, financial calculations); while signed computation is generally applicable, its range of calculated values ​​is halved when dealing with non-negative numbers. Therefore, existing technologies have at least the following drawbacks: first, poor versatility across different application scenarios; second, the need to apply different computational methods to different scenarios, resulting in high costs; and third, the need to adapt to different scenarios. Figure 2b It can be seen that an additional MOSFET is needed for the sign bit. Figure 2b The number of MOSFETs in the middle is Figure 2a The chip requires twice the number of MOSFETs, increasing chip area cost, latency, and power consumption.

[0086] Exemplary circuit

[0087] Figure 3 This is a schematic diagram of an adder circuit provided in an exemplary embodiment of this disclosure. This embodiment can be applied to any chip or electronic device, such as... Figure 3 As shown, the adder circuit provided in this embodiment includes: a cascaded half adder 31, at least one full adder 32, and a sign-selectable adder 33.

[0088] Half adder 31 is used to perform addition operations on the least significant bit value of the first multi-bit number to be calculated and the least significant bit value of the second multi-bit number, and outputs the first carry value and the least significant bit result value.

[0089] The first and second multi-bit numbers are either signed or unsigned; both the first and second multi-bit numbers are binary numbers.

[0090] The circuit structure of the half-adder 31 in this embodiment can be any half-adder structure in the prior art. For example, the half-adder includes an XOR gate and an AND gate. The XOR gate performs logical calculations on the two least significant bit values ​​and outputs the least significant bit result value. The AND gate performs logical calculations on the two least significant bit values ​​and outputs the first carry value. The first carry value output by the half-adder 31 is input into a full adder.

[0091] At least one full adder 32 is used to perform an addition operation on the middle bit value of the first multi-bit number, the middle bit value of the second multi-bit number and the first carry value or the second carry value output by the previous full adder, and output at least one second carry value and at least one middle bit result value.

[0092] In this embodiment, at least one full adder is cascaded together, as can be referred to... Figure 1a and Figure 1bAs shown, Figure 1a The topmost output Sum0 is a half adder, and the others are full adders. Each full adder receives the carry value from the previous stage (e.g., ...). Figure 1a Co1, or Co2, or Co3) and two intermediate values ​​(e.g., such as Co1, ...). Figure 1a If we use a1 and b1, or a2 and b2, or a3 and b3, we can perform an addition operation (refer to the operation process of formulas 1-2, 1-3, and 1-4) to obtain the intermediate result value and the second carry value corresponding to the current full adder.

[0093] In this embodiment, the circuit structure of the full adder can be any structure of a full adder in the prior art. For example, as shown in Figure 4, the full adder includes two XOR gates (XOR gate 41 and XOR gate 42), two AND gates (AND gate 43 and AND gate 44), and one OR gate 45. Figure 1a Taking a full adder connected to a half adder as an example, the data operation process in the full adder is described. Two intermediate values, a1 and b1, are input into XOR gate 41 and AND gate 44, respectively; the first carry value, Co1, is input into XOR gate 42 and AND gate 43. The output of XOR gate 41 is connected to XOR gate 42 and AND gate 43, enabling the output value of XOR gate 41 to perform XOR and AND operations with the first carry value, Co1, respectively. XOR gate 42 directly outputs the intermediate result value, Sum1; the outputs of AND gates 43 and 44 are input into OR gate 45 to perform OR operations, and OR gate 45 outputs the second carry value, Co2. For example, refer to... Figure 2a As shown, this is a full adder constructed using a combination of MOSFETs.

[0094] There is also a special case in this embodiment: the adder does not include a full adder, that is, the binary number being processed is 2 bits. In this case, the adder only includes a half adder and a sign-selectable adder.

[0095] The sign-selectable adder 33 is used to perform addition operations on the highest bit value of the first multi-bit number, the highest bit value of the second multi-bit number, and the second carry value output by the previous full adder, and output the highest bit result value and the highest carry value, or output the highest bit result value and the sign result value.

[0096] In signed addition, an overflow occurs if adding two positive numbers results in a negative number, or adding two negative numbers results in a positive number. In two's complement representation, this can be determined by checking if the carry-in bit and the overflow bit (usually the carry-out bit) are the same; if they are the same, there is no overflow; if they are different, an overflow has occurred. Therefore, the main difference between unsigned and signed adders lies in how they handle the sign bit and overflow.

[0097] This embodiment combines the highest-order full adder (for calculating the sign bit) and the second-highest-order full adder (for calculating the highest-order result value) in a sign-selectable adder. This sign-selectable adder can perform addition calculations with or without a sign, achieving sign bit switching at low cost. It not only supports the functions of both unsigned and signed adders simultaneously, but also allows for flexible switching, making it more versatile.

[0098] The adder circuit, chip, computing device, and electronic device provided in the above embodiments of this disclosure include: a cascaded half adder, at least one full adder, and a sign-selectable adder; the half adder is used to perform an addition operation on the least significant bit value of a first multi-bit number to be computed and the least significant bit value of a second multi-bit number, and outputs a first carry value and a least significant bit result value; wherein the first multi-bit number and the second multi-bit number are signed numbers, or the first multi-bit number and the second multi-bit number are unsigned numbers; the at least one full adder is used to perform an addition operation on the middle bit value of the first multi-bit number, the middle bit value of the second multi-bit number, and the first carry value, or the second carry value output by the previous full adder, and outputs at least one second carry value and at least one middle bit result value; the sign-selectable adder is used to perform an addition operation on the highest significant bit value of the first multi-bit number, the highest significant bit value of the second multi-bit number, and the second carry value output by the previous full adder, and outputs the highest significant bit result value and the highest carry value, or outputs the highest significant bit result value and the sign result value. This embodiment of the disclosure enables the same circuit to perform calculations on both signed and unsigned numbers by using a sign-selectable adder. Compared to the prior art, which requires separate adders for signed and unsigned numbers, this embodiment of the disclosure integrates the two algorithms and achieves the sign selection function at a lower cost.

[0099] Figure 5 This is a schematic diagram of the structure of an adder circuit with selectable sign provided in another exemplary embodiment of this disclosure. For example... Figure 5 As shown, the sign-selectable adder 33 includes: a full adder module 331, a carry calculation module 332, a sign calculation module 333, and an output control module 334.

[0100] In this embodiment, the input data includes the highest bit value of the first multi-bit number, the highest bit value of the second multi-bit number, and the second carry value output by the previous full adder.

[0101] The full adder module 331 is used to perform unsigned addition on the input data to obtain the highest bit result value.

[0102] Optionally, in this embodiment, the full adder module implements only the part of the full adder that obtains the result value, for example, only including... Figure 4In the illustrated embodiment, taking a 4-bit number as an example, XOR gate 41 receives two highest bit values ​​(e.g., a3 and b3) and performs an XOR operation. The output value and the second carry value are input to XOR gate 42, which performs the XOR operation and directly outputs the highest bit result value Sum4.

[0103] The carry calculation module 332 is used to perform at least one logical operation on the input data to obtain the highest carry value.

[0104] In this embodiment, the carry calculation module independently performs at least one logical operation on the input data to obtain the highest carry value. By setting the carry calculation module independently, a basis for selecting the calculation method for signed and symbolic calculations is provided.

[0105] The symbolic calculation module 333 is used to perform at least one logical operation on the input data to obtain a symbolic result value.

[0106] In this embodiment, the sign calculation module independently performs at least one logical operation on the input data to obtain the sign result value, which simplifies the calculation circuit of the sign bit in the signed number calculation. When it is necessary to perform the addition calculation of signed binary data, the calculation of signed numbers can be realized by the full addition module, the sign calculation module and the output control module working together.

[0107] The output control module 334 is connected to the carry calculation module 332 and the sign calculation module 333 respectively, and is used to output the highest carry value or sign result value according to the control signal.

[0108] This embodiment uses an output control module to selectively output the highest carry value and the sign result value. That is, in the same calculation, only the highest carry value or the sign result value is output. Which value is output can be controlled by an externally input control signal. For example, when the first multi-bit number and the second multi-bit number are signed numbers, the output control module is controlled by the control signal to output the sign result value, realizing the output of the sign bit of the signed number; when the first multi-bit number and the second multi-bit number are unsigned numbers, the output control module is controlled by the control signal to output the highest carry value, realizing the output of the carry value of the unsigned number.

[0109] Based on the above formula and appendix Figure 1a , Figure 1b , Figure 2a and Figure 2b The formula for calculating the sign bit Sum4 can be simplified to obtain the following formula:

[0110]

[0111] Based on a comparison of formulas (1-6) and (3-1), we can see that the identical terms are a3b3 and a3x+b3x. Therefore, we can merge the identical terms, both unsigned and signed, leaving only Co3 and... Based on this, by making certain improvements to the adder, it is possible to achieve a selectable output of either the highest carry value Co4 or the sign result value Sum4.

[0112] Figure 6 This is a partial structural diagram of an adder circuit with selectable sign provided in another exemplary embodiment of this disclosure. For example... Figure 6 As shown, the carry calculation module 332 includes: a first AND gate 51, a second AND gate 52, a third AND gate 53, and a first OR gate 54.

[0113] The first AND gate 51 performs an AND logic operation on the highest bit value of the first multi-bit number and the highest bit value of the second multi-bit number, and inputs the result of the first logic operation into the first OR gate 54.

[0114] The second AND gate 52 performs an AND logic operation on the highest bit value in the first multi-bit number and the second carry value output by the previous full adder, and inputs the result of the second logic operation into the first OR gate 54.

[0115] The third AND gate 53 performs an AND logic operation on the highest bit value of the second multi-bit number and the second carry value output by the previous full adder, and inputs the result of the third logic operation into the first OR gate 54.

[0116] The first OR gate 54 performs an OR operation on the results of the first, second, and third logical operations to obtain the highest carry value, Sumn_NS.

[0117] For ease of display, the highest bit value in the first multi-bit number and the highest bit value in the second multi-bit number are labeled as a3 and b3 (the highest bit in 4-bit data), respectively. The second carry value is labeled as CO3. This is only for easy labeling and has no actual limiting function. This application does not limit the number of bits in the first and second multi-bit numbers. For example, when the first and second multi-bit numbers are 8 bits, the input is the highest bit value in the first multi-bit number and the highest bit value in the second multi-bit number, respectively, a7 and b7.

[0118] In this embodiment, based on the above formula (3-1), it can be seen that the symbol calculation module also needs to perform the calculation of a3b3. To simplify the circuit structure, the first AND gate in the carry calculation module can be combined into the symbol calculation module. Therefore, as Figure 5 As shown, the symbol calculation module 333 includes: a first AND gate 51, a fourth AND gate 55, a fifth AND gate 56, and a second OR gate 57.

[0119] The fourth AND gate 55 performs an AND logic operation on the highest bit value and the third carry value in the first multi-bit number, and inputs the result of the fourth logic operation into the second OR gate 57.

[0120] The third carry value is obtained by inverting the second carry value output by the previous full adder.

[0121] Optionally, the sign calculation module 333 further includes: a NOT gate 58; the NOT gate 58 is used to perform inversion processing on the second carry value output by the previous full adder to obtain the third carry value.

[0122] like Figure 5 As shown, the second carry value is represented as CO3, and after inversion, the third carry value is represented as CO3b. The 3 is the same as a3 and b3 above. This is only for illustration and has no practical limiting meaning.

[0123] The fifth AND gate 56 performs an AND logic operation on the highest bit value and the third carry value in the second multi-bit number, and inputs the result of the fifth logic operation into the second OR gate.

[0124] The second OR gate 57 performs an OR operation on the results of the first, fourth, and fifth logical operations to obtain the symbolic result value Sumn_S.

[0125] In this embodiment, the control signals include a first control signal SING_EN and a second control signal SING_ENB; the output control module 334 includes a first transmission gate 591 and a second transmission gate 592.

[0126] The first transmission gate 591 is used to output the highest carry value according to the control of the first control signal SING_EN and the second control signal SING_ENB.

[0127] The first control signal and the second control signal are simultaneously input into the first transmission gate to realize the logic control of the first transmission gate.

[0128] The second transmission gate 592 is used to output the symbol result value according to the control of the first control signal SING_EN and the second control signal SING_ENB.

[0129] Optionally, the values ​​of the first control signal SING_EN and the second control signal SING_ENB are opposite, forming a pair of inverted signals;

[0130] When the first control signal SING_EN is low and the second control signal SING_ENB is high, the first transmission gate 591 outputs the highest carry value; the second transmission gate 592 does not output the sign result value.

[0131] When the second control signal SING_ENB is low and the first control signal SING_EN is high, the second transmission gate 592 outputs the symbol result value; the first transmission gate 591 does not output the highest carry value.

[0132] Compared to the existing separate design of unsigned and signed adders, this disclosure combines the two at a low cost, reducing design costs. In addition, compared to existing adders that can only perform one type of calculation, the embodiments of this disclosure can switch to signed or unsigned calculations at any time, and are more versatile and have a wider range of applications.

[0133] Figure 7 This is a schematic diagram of the circuit structure of an adder circuit with selectable symbol provided in another exemplary embodiment of this disclosure. For example... Figure 7 As shown, to highlight the optional adder provided in this disclosure compared to the prior art Figure 2a as well as Figure 2b The difference between them is that in this embodiment, the various modules included in the symbol-selectable adder are expanded and represented as a combination of MOSFETs.

[0134] like Figure 7 The output control module 334 (controlled by the first control signal SING_EN and the second control signal SING_ENB) within the dashed box selects whether the Sum4 output is a signed result value. Compared to existing technical solutions, the low-power adder with sign selection function proposed in this disclosure achieves sign bit switching at a lower cost. It can not only support the functions of both unsigned and signed adders simultaneously, but also switch flexibly, making it more versatile.

[0135] Furthermore, this disclosure implements the functionality of a full adder for the highest and second-highest bits in signed computation using a coincident optional adder, by comparison. Figure 7 and Figure 2b It can be seen that the number of MOSFETs in this embodiment is 42, relative to Figure 2b The signed highest-order bit full adder provided in this disclosure uses 54 MOSFETs, which significantly reduces area and power consumption in this embodiment. Again, taking the addition of two 4-bit numbers as an example... Figure 8 The figure shows a comparison of the dynamic power consumption, latency, and static power consumption of the adder provided by the prior art and the embodiments of this disclosure under the 7nm process with PVT of tt0p75v85c. Green represents the prior art and black represents the present disclosure. The adder provided by the embodiments of this disclosure has positive gains in PPA.

[0136] Furthermore, this embodiment of the invention integrates the functions of two adders into one, and compared with existing signed adders, it reduces the number of MOS transistors, resulting in positive gains in PPA.

[0137] The embodiments of this disclosure also provide a chip that integrates the adder circuit provided in any of the above embodiments. Details of the adder circuit can be found in the description of the above embodiments, and will not be described further here.

[0138] Embodiments of this disclosure also provide a computing device, including the adder circuit provided in any of the foregoing embodiments or the chip provided in the foregoing embodiments.

[0139] Embodiments of this disclosure also provide an electronic device, characterized in that it includes the chip provided in any of the above embodiments or the computing device provided in any of the above embodiments.

[0140] The electronic device can be either or both of the first device and the second device, or a standalone device independent of them, which can communicate with the first device and the second device to receive the acquired input signals from them.

[0141] Electronic devices include one or more processors and memory.

[0142] A processor can be a central processing unit (CPU) or other form of processing unit with data processing and / or instruction execution capabilities, and can control other components in an electronic device to perform desired functions.

[0143] The memory can store one or more computer program products, and the memory can include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. The volatile memory may, for example, include random access memory (RAM) and / or cache memory. The non-volatile memory may, for example, include read-only memory (ROM), hard disk, flash memory, etc. One or more computer program products can be stored on the computer-readable storage medium, and the processor can run the computer program products.

[0144] In one example, the electronic device may also include input devices and output devices, which are interconnected via a bus system and / or other forms of connection mechanism (not shown).

[0145] In addition, the input device may also include, for example, a keyboard, a mouse, etc.

[0146] This output device can output various information to the outside, including determined distance information, direction information, etc. The output device may include, for example, a display, a speaker, a printer, and a communication network and its connected remote output devices, etc.

[0147] The basic principles of this disclosure have been described above with reference to specific embodiments. However, it should be noted that the advantages, benefits, and effects mentioned in this disclosure are merely examples and not limitations, and should not be considered as essential features of each embodiment of this disclosure. Furthermore, the specific details disclosed above are for illustrative and facilitative purposes only, and are not limitations. These details do not limit the scope of this disclosure to the necessity of employing the aforementioned specific details for implementation.

[0148] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For system embodiments, since they largely correspond to method embodiments, the description is relatively simple; relevant parts can be referred to the descriptions in the method embodiments.

[0149] The block diagrams of devices, apparatuses, devices, and systems disclosed herein are merely illustrative examples and are not intended to require or imply that they must be connected, arranged, or configured in the manner shown in the block diagrams. As those skilled in the art will recognize, these devices, apparatuses, devices, and systems can be connected, arranged, and configured in any manner. Words such as “comprising,” “including,” “having,” etc., are open-ended terms meaning “including but not limited to,” and are used interchangeably with them. The terms “or” and “and” as used herein refer to the terms “and / or,” and are used interchangeably with them unless the context clearly indicates otherwise. The term “such as” as used herein refers to the phrase “such as but not limited to,” and is used interchangeably with it.

[0150] The methods and apparatus of this disclosure may be implemented in many ways. For example, they may be implemented by software, hardware, firmware, or any combination of software, hardware, and firmware. The above-described order of steps for the methods is for illustrative purposes only, and the steps of the methods of this disclosure are not limited to the order specifically described above unless otherwise specifically stated. Furthermore, in some embodiments, this disclosure may also be implemented as a program recorded on a recording medium, the program including machine-readable instructions for implementing the methods according to this disclosure. Thus, this disclosure also covers recording media storing programs for performing the methods according to this disclosure.

[0151] It should also be noted that in the apparatus, devices, and methods of this disclosure, the components or steps can be disassembled and / or recombined. These disassemblies and / or recombinations should be considered as equivalent solutions to this disclosure.

[0152] The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use this disclosure. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects without departing from the scope of this disclosure. Therefore, this disclosure is not intended to be limited to the aspects shown herein, but rather to be carried out within the widest scope consistent with the principles and novel features disclosed herein.

[0153] The above description has been given for purposes of illustration and description. Furthermore, this description is not intended to limit the embodiments of this disclosure to the forms disclosed herein. Although numerous exemplary aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, alterations, additions, and sub-combinations thereof.

Claims

1. An adder circuit, characterized in that, include: A cascaded half-adder, at least one full adder, and a sign-selectable adder; The half-adder is used to perform an addition operation on the least significant bit value of the first multi-bit number and the least significant bit value of the second multi-bit number to be calculated, and outputs the first carry value and the least significant bit result value; wherein, the first multi-bit number and the second multi-bit number are signed numbers, or the first multi-bit number and the second multi-bit number are unsigned numbers; The at least one full adder is used to perform an addition operation on the middle bit value of the first multi-bit number, the middle bit value of the second multi-bit number, and the first carry value or the second carry value output by the previous full adder, and output at least one second carry value and at least one middle bit result value. The sign-selectable adder is used to perform addition operations on the highest bit value of the first multi-bit number, the highest bit value of the second multi-bit number, and the second carry value output by the previous full adder, and output the highest bit result value and the highest carry value, or output the highest bit result value and the sign result value.

2. The circuit according to claim 1, characterized in that, The sign-selectable adder includes: a full adder module, a carry calculation module, a sign calculation module, and an output control module; The full adder module is used to perform unsigned addition on the input data to obtain the highest bit result value; wherein, the input data includes the highest bit value of the first multi-bit number, the highest bit value of the second multi-bit number, and the second carry value output by the previous full adder; The carry calculation module is used to perform at least one logical operation on the input data to obtain the highest carry value; The symbol calculation module is used to perform at least one logical operation on the input data to obtain a symbol result value; The output control module is connected to the carry calculation module and the sign calculation module respectively, and is used to output the highest carry value or the sign result value according to the control signal.

3. The circuit according to claim 2, characterized in that, The carry calculation module includes: a first AND gate, a second AND gate, a third AND gate, and a first OR gate; The first AND gate performs an AND logic operation on the highest bit value of the first multi-bit number and the highest bit value of the second multi-bit number, and inputs the result of the first logic operation into the first OR gate; The second AND gate performs an AND logic operation on the highest bit value in the first multi-bit number and the second carry value output by the full adder in the previous stage, and inputs the result of the second logic operation into the first OR gate; The third AND gate performs an AND logic operation on the highest bit value of the second multi-bit number and the second carry value output by the previous full adder, and inputs the result of the third logic operation into the first OR gate; The first OR gate performs an OR logic operation on the first logic operation result, the second logic operation result, and the third logic operation result to obtain the highest carry value.

4. The circuit according to claim 3, characterized in that, The symbol computation module includes: a first AND gate, a fourth AND gate, a fifth AND gate, and a second OR gate; The fourth AND gate performs an AND logic operation on the highest bit value and the third carry value in the first multi-bit number, and inputs the result of the fourth logic operation into the second OR gate; the third carry value is obtained by inverting the second carry value output by the previous stage full adder; The fifth AND gate performs an AND logic operation on the highest bit value in the second multi-bit number and the third carry value, and inputs the result of the fifth logic operation into the second OR gate. The second OR gate performs an OR logic operation on the first logic operation result, the fourth logic operation result, and the fifth logic operation result to obtain the symbolic result value.

5. The circuit according to claim 4, characterized in that, The symbol computation module further includes: a NOT gate; The NOT gate is used to invert the second carry value output by the previous full adder to obtain the third carry value.

6. The circuit according to any one of claims 2-5, characterized in that, The control signal includes a first control signal and a second control signal; The output control module includes a first transmission gate and a second transmission gate; The first transmission gate is used to output the highest carry value according to the control of the first control signal and the second control signal; The second transmission gate is used to output the symbol result value according to the control of the first control signal and the second control signal.

7. The circuit according to claim 6, characterized in that, The values ​​of the first control signal and the second control signal are opposite; When the first control signal is low and the second control signal is high, the first transmission gate outputs the highest carry value; the second transmission gate does not output the sign result value. In response to the second control signal being low and the first control signal being high, the second transmission gate outputs the symbol result value; the first transmission gate does not output the highest carry value.

8. A chip, characterized in that, Includes the adder circuit as described in any one of claims 1-7.

9. A computing device, characterized in that, Includes the adder circuit according to any one of claims 1-7 or the chip according to claim 8.

10. An electronic device, characterized in that, Includes the chip of claim 8 or the computing device of claim 9.

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