Signed adder circuits, chips, computing devices, and electronic devices

Abstract

This disclosure provides a signed adder circuit, chip, computing device, and electronic device. The circuit includes: a cascaded half-adder, at least one full-adder, and a sign processor. The half-adder performs addition on the least significant bit of a first multi-bit number and the least significant bit of a second multi-bit number, outputting a first carry-value and a least significant bit result value. The at least one full-adder performs addition on the middle bit of the first multi-bit number, the middle bit of the second multi-bit number, and the first carry-value or the second carry-value output by the previous full-adder, outputting at least one second carry-value and at least one middle bit result value. The sign processor performs addition on the most significant bit of the first multi-bit number, the most significant bit of the second multi-bit number, and the second carry-value output by the previous full-adder, outputting the most significant bit result value and a sign result value.

Description

Technical Field

[0001] This disclosure relates to the field of data computing technology, and in particular to a signed adder circuit, chip, computing device, and electronic device. Background Technology

[0002] Adders are a fundamental component in digital circuits. Their operation is based on the rules of binary number addition and the design of logic gates. They receive the addend and augend (and possibly carry-in) as inputs and output the sum and carry. In data processing / computation chip design, adder trees composed of full adders and half adders are typically used to perform operations on multi-bit binary numbers. Summary of the Invention

[0003] Embodiments of this disclosure provide a signed adder circuit, a chip, a computing device, and an electronic device.

[0004] According to one aspect of the present disclosure, a signed adder circuit is provided, comprising: a cascaded half adder, at least one full adder, and a sign processor;

[0005] The half-adder is used to perform an addition operation on the least significant bit value of the first multi-bit number and the least significant bit value of the second multi-bit number to be calculated, and outputs the first carry value and the least significant bit result value; wherein, the first multi-bit number and the second multi-bit number are signed numbers, or the first multi-bit number and the second multi-bit number are unsigned numbers;

[0006] The at least one full adder is used to perform an addition operation on the middle bit value of the first multi-bit number, the middle bit value of the second multi-bit number, and the first carry value or the second carry value output by the previous full adder, and output at least one second carry value and at least one middle bit result value.

[0007] The symbol processor is used to perform addition operations on the highest bit value of the first multi-bit number, the highest bit value of the second multi-bit number, and the second carry value output by the full adder of the previous stage, and output the highest bit result value and the sign result value.

[0008] Optionally, the symbol processor includes: a symbol determination module and a full addition module;

[0009] The sign determination module is used to perform at least one logical operation on the input data to obtain a sign result value; wherein, the input data includes the highest bit value of the first multi-bit number, the highest bit value of the second multi-bit number, and the second carry value output by the previous full adder;

[0010] The full addition module is used to perform addition operations on the input data to obtain the highest bit result value.

[0011] Optionally, the symbol determination module includes: a first AND gate, a second AND gate, a third AND gate, and a first OR gate;

[0012] The first AND gate performs an AND logic operation on the highest bit value of the first multi-bit number and the highest bit value of the second multi-bit number, and inputs the result of the first logic operation into the first OR gate;

[0013] The second AND gate performs an AND logic operation on the highest bit value and the third carry value in the first multi-bit number, and inputs the result of the second logic operation into the first OR gate; the third carry value is obtained by inverting the second carry value output by the previous stage full adder;

[0014] The third AND gate performs an AND logic operation on the highest bit value of the second multi-bit number and the third carry value, and inputs the result of the third logic operation into the first OR gate;

[0015] The first OR gate performs an OR logic operation on the first logic operation result, the second logic operation result, and the third logic operation result to obtain the symbolic result value.

[0016] Optionally, the sign determination module includes: a fourth AND gate, a fifth AND gate, a second OR gate, and a third OR gate;

[0017] The second OR gate performs an OR logic operation on the highest bit value in the first multi-bit number and the highest bit value in the second multi-bit number, and inputs the result of the fourth logic operation into the fourth AND gate;

[0018] The fourth AND gate performs an AND operation on the result of the fourth logical operation and the third carry value, and inputs the result of the fifth logical operation into the third OR gate; the third carry value is obtained by inverting the second carry value output by the previous full adder;

[0019] The fifth AND gate performs an AND logic operation on the highest bit value in the first multi-bit number and the highest bit value in the second multi-bit number, and inputs the result of the sixth logic operation into the third OR gate;

[0020] The third OR gate performs an OR operation on the result of the fifth logical operation and the result of the sixth logical operation to obtain the symbolic result value.

[0021] Optionally, the sign determination module further includes: a first NOT gate;

[0022] The first NOT gate inverts the second carry value output by the previous full adder to obtain the third carry value.

[0023] Optionally, the sign determination module includes: a sixth AND gate, a seventh AND gate, a fourth OR gate, and a first NOR gate;

[0024] The fourth OR gate performs an OR logic operation on the first high-order bit value and the second high-order bit value, and inputs the result of the seventh logic operation into the sixth AND gate; the first high-order bit value is obtained by inverting the highest bit value in the first multi-bit number, and the second high-order bit value is obtained by inverting the highest bit value in the second multi-bit number;

[0025] The sixth AND gate performs an AND logic operation on the result of the seventh logic operation and the second carry value output by the previous full adder, and inputs the result of the eighth logic operation into the first NOR gate;

[0026] The seventh AND gate performs an AND logic operation on the first high-order value and the second high-order value, and inputs the result of the ninth logic operation into the first NOR gate;

[0027] The first NOR gate performs a NOR operation on the result of the eighth logical operation and the result of the ninth logical operation to obtain the symbolic result value.

[0028] Optionally, the sign determination module further includes: a second NOT gate and a third NOT gate;

[0029] The second NOT gate inverts the highest bit value in the second multi-bit number to obtain the second high bit value;

[0030] The third NOT gate inverts the highest bit value in the second multi-bit number to obtain the second high bit value.

[0031] Optionally, the symbol determination module includes: a first transistor group, a second transistor group, a third transistor group, and a fourth transistor group;

[0032] The input terminal of the first transistor group receives the second carry value output by the previous stage full adder and outputs a third carry value; the third carry value is inversely related to the second carry value output by the previous stage full adder.

[0033] The input terminal of the second transistor group receives the highest bit value of the first multi-bit number and the highest bit value of the second multi-bit number, and the output terminal is connected to the output terminal of the third transistor group and the input terminal of the fourth transistor group.

[0034] The input terminal of the third transistor group receives the highest bit value of the first multi-bit number, the highest bit value of the second multi-bit number, and the third carry value, and the output terminal is connected to the output terminal of the second transistor group and the input terminal of the fourth transistor group;

[0035] The input terminal of the third transistor group is connected to the second transistor group and the output terminal of the third transistor group, and the output terminal outputs the symbol result value.

[0036] Optionally, the first transistor group and the fourth transistor group have the same structure;

[0037] The first transistor group includes a first transistor and a second transistor whose gate terminals are connected to each other. The gate terminal serves as the input terminal of the first transistor group. The drain terminal of the first transistor is connected to a power supply signal. The source terminal of the first transistor is connected to the drain terminal of the second transistor and serves as the output terminal of the first transistor group. The source terminal of the second transistor is grounded. The first transistor is a p-type transistor and the second transistor is an n-type transistor.

[0038] Optionally, the second transistor group includes: a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor; the third transistor and the fourth transistor are p-type transistors, and the fifth transistor and the sixth transistor are n-type transistors;

[0039] The drain terminal of the third transistor is connected to the power supply signal, the gate terminal receives the highest bit value in the first multi-bit number, and the source terminal is connected to the drain terminal of the fourth transistor.

[0040] The gate of the fourth transistor receives the highest bit value in the second multi-bit number, and the source terminal is connected to the drain terminal of the fifth transistor and serves as the output terminal of the second transistor group.

[0041] The gate terminal of the fifth transistor receives the highest bit value in the second multi-bit number, and the source terminal is connected to the drain terminal of the sixth transistor.

[0042] The gate of the sixth transistor receives the highest bit value in the first multi-bit number, and the source end is grounded.

[0043] Optionally, the third transistor group includes: a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, and a twelfth transistor; the seventh transistor, the eighth transistor, and the ninth transistor are p-type transistors, and the tenth transistor, the eleventh transistor, and the twelfth transistor are n-type transistors;

[0044] The drain terminal of the seventh transistor is connected to the power supply signal, the source terminal of the seventh transistor is connected to the drain terminal of the eighth transistor and the source terminal of the ninth transistor, and the gate terminal of the seventh transistor receives the highest bit value in the first multi-bit number.

[0045] The gate of the eighth transistor is connected to the output of the first transistor group to receive the third carry value, and the source terminal is connected to the drain terminal of the tenth transistor as the output of the third transistor group.

[0046] The gate of the ninth transistor receives the highest bit value in the second multi-bit number, and the drain is connected to the power supply signal.

[0047] The gate terminal of the tenth transistor receives the third carry value, and its source terminal is connected to the drain terminal of the eleventh transistor and the drain terminal of the twelfth transistor.

[0048] The gate terminal of the eleventh transistor is connected to the output terminal of the first transistor group to receive the third carry value, and the source terminal is grounded.

[0049] The gate of the twelfth transistor receives the highest bit value in the second multi-bit number, and the source terminal is grounded.

[0050] According to another aspect of the present disclosure, a chip is provided that includes the signed adder circuit described in any of the foregoing embodiments.

[0051] According to another aspect of the present disclosure, a computing device is provided, including the signed adder circuit or the chip described in any of the foregoing embodiments.

[0052] According to another aspect of the present disclosure, an electronic device is provided, including the chip or computing device described in the above embodiments.

[0053] The signed adder circuit, chip, computing device, and electronic device provided in the above embodiments of this disclosure include: a cascaded half adder, at least one full adder, and a sign processor; the half adder is used to perform an addition operation on the least significant bit value of a first multi-bit number and the least significant bit value of a second multi-bit number to be computed, and outputs a first carry value and a least significant bit result value; wherein the first multi-bit number and the second multi-bit number are coincident numbers, or the first multi-bit number and the second multi-bit number are unsigned numbers; the at least one full adder is used to perform an addition operation on the middle bit value of the first multi-bit number, the middle bit value of the second multi-bit number, and the first carry value or the second carry value output by the previous full adder, and outputs at least one second carry value and at least one middle bit result value; the sign processor is used to perform an addition operation on the most significant bit value of the first multi-bit number, the most significant bit value of the second multi-bit number, and the second carry value output by the previous full adder, and outputs the most significant bit result value and the sign result value. The embodiments disclosed herein implement the calculation of the highest bit value of two multi-bit numbers through a symbol processor. While determining the highest bit result value, the symbol result value can also be output. The functions of two adders in the prior art are implemented with only one circuit, which reduces the number of MOSFETs, reduces the circuit area, and reduces power consumption and delay.

[0054] The technical solutions of this disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0055] The accompanying drawings, which form part of this specification, illustrate embodiments of this disclosure and, together with the description, serve to explain the principles of this disclosure.

[0056] This disclosure will become clearer with reference to the accompanying drawings and the following detailed description, wherein:

[0057] Figure 1a A schematic diagram of an unsigned 4-bit number adder is shown;

[0058] Figure 1b A schematic diagram of a signed 4-bit number adder is shown;

[0059] Figure 2a This is a circuit diagram of Sum4 processing in existing unsigned computation techniques;

[0060] Figure 2b This is a circuit diagram of Sum4 processing in symbolic computation in the prior art;

[0061] Figure 2c Karnaugh maps corresponding to Sum4 in both unsigned and signed computation in existing technologies;

[0062] Figure 3 This is a schematic diagram of the structure of a signed adder circuit provided in an exemplary embodiment of this disclosure;

[0063] Figure 4 This is a schematic diagram of the circuit structure of a full adder in the prior art;

[0064] Figure 5 This is a schematic diagram of the structure of the sign processor in a signed adder circuit provided in another exemplary embodiment of this disclosure;

[0065] Figure 6a This is a schematic diagram of the sign determination module in a signed adder circuit provided in an exemplary embodiment of this disclosure;

[0066] Figure 6b This is a schematic diagram of the sign determination module in a signed adder circuit provided in another exemplary embodiment of this disclosure;

[0067] Figure 7 This is a schematic diagram of the sign determination module in a signed adder circuit provided in yet another exemplary embodiment of this disclosure;

[0068] Figure 8 This is a schematic diagram of the sign determination module in a signed adder circuit provided in yet another exemplary embodiment of this disclosure;

[0069] Figure 9 This is a schematic diagram of the sign determination module in a signed adder circuit provided in an exemplary embodiment of the present disclosure;

[0070] Figure 10 This is a schematic diagram of the structure of the sign processor in a signed adder circuit provided in another exemplary embodiment of the present disclosure;

[0071] Figure 11 This is a schematic diagram comparing the dynamic power consumption delay and static power consumption of the signed adder provided by the prior art solution and the embodiments of this disclosure. Detailed Implementation

[0072] Hereinafter, exemplary embodiments according to the present disclosure will be described in detail with reference to the accompanying drawings. Obviously, the described embodiments are merely some embodiments of the present disclosure, and not all embodiments of the present disclosure, and it should be understood that the present disclosure is not limited to the exemplary embodiments described herein.

[0073] It should be noted that, unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps set forth in these embodiments do not limit the scope of this disclosure.

[0074] Those skilled in the art will understand that the terms "first," "second," etc., in the embodiments of this disclosure are only used to distinguish different steps, devices, or modules, and do not represent any specific technical meaning, nor do they indicate a necessary logical order between them.

[0075] It should also be understood that in the embodiments disclosed herein, "a plurality of" may refer to two or more, and "at least one" may refer to one, two or more.

[0076] It should also be understood that any component, data or structure mentioned in the embodiments of this disclosure can generally be understood as one or more unless expressly defined or given to the contrary in the context.

[0077] Furthermore, the term "and / or" in this disclosure is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this disclosure generally indicates that the preceding and following related objects have an "or" relationship. The data referred to in this disclosure can include unstructured data such as text, images, and videos, as well as structured data.

[0078] It should also be understood that the description of the various embodiments in this disclosure emphasizes the differences between the various embodiments, and the similarities or similarities can be referred to each other. For the sake of brevity, they will not be described in detail.

[0079] At the same time, it should be understood that, for ease of description, the dimensions of the various parts shown in the accompanying drawings are not drawn according to actual scale.

[0080] The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit this disclosure or its application or use.

[0081] Techniques, methods, and equipment known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and equipment should be considered part of the specification.

[0082] It should be noted that similar labels and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be discussed further in subsequent figures.

[0083] The embodiments disclosed herein can be applied to electronic devices such as terminal devices, computer systems, and servers, and can operate together with a wide range of other general-purpose or special-purpose computing system environments or configurations. Examples of well-known terminal devices, computing systems, environments, and / or configurations suitable for use with electronic devices such as terminal devices, computer systems, and servers include, but are not limited to: personal computer systems, server computer systems, thin clients, thick clients, handheld or laptop devices, microprocessor-based systems, set-top boxes, programmable consumer electronics, network PCs, minicomputer systems, mainframe computer systems, and distributed cloud computing environments including any of the above systems, etc.

[0084] Electronic devices such as terminal devices, computer systems, and servers can be described in the general context of computer system executable instructions (such as program modules) executed by a computer system. Typically, program modules can include routines, programs, object programs, components, logic, data structures, etc., which perform specific tasks or implement specific abstract data types. Computer systems / servers can be implemented in distributed cloud computing environments, where tasks are executed by remote processing devices linked through communication networks. In distributed cloud computing environments, program modules can reside on local or remote computing system storage media, including storage devices.

[0085] Application Overview

[0086] In developing this disclosure, the inventors discovered that binary arithmetic is divided into unsigned arithmetic and signed arithmetic, and related technologies implement these operations using unsigned adders and signed adders. Unsigned adders accept non-negative inputs and do not require handling the sign bit in negative number or overflow detection; they simply perform bit-by-bit addition on the two binary numbers. Signed adders, on the other hand, perform addition on two signed binary numbers (positive or negative), requiring handling carry and overflow. They typically use two's complement representation, where the highest bit is the sign bit (0 for positive, 1 for negative). The two's complement of a positive number is itself, while the two's complement of a negative number is obtained by inverting its binary representation (excluding the highest bit) and adding 1.

[0087] In related technical solutions, calculations involving unsigned and signed binary numbers require completely independent design of corresponding adders. Taking the addition of two 4-bit binary numbers as an example, unsigned addition requires one half-adder and three full adders, while signed addition requires an additional full adder for sign bit calculation. Figure 1a and Figure 1b As shown, Figure 1a A schematic diagram of an unsigned 4-bit number adder is shown. Figure 1b The diagram illustrates a signed 4-bit number adder. Let A and B be the two 4-bit numbers. The binary representations of A and B are: A = a3a1a1a0 and B = b3b2b1b0, respectively. The sum SUM is represented as: SUM = Sum4sum3Sum2Sum1Sum0. In unsigned operations, the highest bit Sum4 of SUM represents the carry from the sum of a3 and b3, which can be calculated using the following formula:

[0088] Sum4=Co4(1-1)

[0089]

[0090]

[0091] Co₄=a³b³+a³Co₃+b³Co₃ (1-6)

[0092] Co3=a2b2+a2Co2+b2Co2 (1-7)

[0093] Co2=a1b1+a1Co1+b1Co1 (1-8)

[0094] Co1=a0b0 (1-9)

[0095] In signed arithmetic, the highest bit of SUM, Sum4, is used as the sign bit. The calculation formula is as follows:

[0096]

[0097] Co₄=a³b³+a³Co₃+b³Co₃ (2-6)

[0098] Co3=a2b2+a2Co2+b2Co2 (2-7)

[0099] Co2=a1b1+a1Co1+b1Co1 (2-8)

[0100] Co1=a0b0 (2-9)

[0101] The two operations mentioned above differ only in the highest bit Sum4, as shown in formulas 1-1 and 2-1. Figure 2a This is a circuit diagram of Sum4 processing in existing unsigned computation techniques; Figure 2b This is a circuit diagram of Sum4 processing in symbolic computation in the prior art; Figure 2c This is a Karnaugh map showing the Sum4 operation in both unsigned and signed computation in existing technologies. For the unsigned Sum4 operation, according to formulas 1-1 and 1-6, only a single-stage full adder is needed, such as... Figure 2a As shown; however, the signed operation Sum4, according to formulas 2-1 and 2-6, requires two cascaded full adders, as shown. Figure 2b .

[0102] The relevant technologies have at least the following drawbacks: Figure 2b It can be seen that an additional MOSFET is needed for the sign bit. Figure 2b The number of MOSFETs in the middle is Figure 2a The chip requires twice the number of MOSFETs, increasing chip area cost, latency, and power consumption.

[0103] Exemplary circuit

[0104] Figure 3 This is a schematic diagram of a signed adder circuit provided in an exemplary embodiment of this disclosure. This embodiment can be applied to any chip or electronic device, such as... Figure 3 As shown, the signed adder circuit provided in this embodiment includes: a cascaded half adder 31, at least one full adder 32, and a sign processor 33.

[0105] Half adder 31 is used to perform addition operations on the least significant bit value of the first multi-bit number to be calculated and the least significant bit value of the second multi-bit number, and outputs the first carry value and the least significant bit result value.

[0106] Among them, the first multi-bit number and the second multi-bit number are either coincident numbers or unsigned numbers; both the first multi-bit number and the second multi-bit number are binary numbers.

[0107] The circuit structure of the half-adder 31 in this embodiment can be any half-adder structure in the prior art. For example, the half-adder includes an XOR gate and an AND gate. The XOR gate performs logical calculations on the two least significant bit values ​​and outputs the least significant bit result value. The AND gate performs logical calculations on the two least significant bit values ​​and outputs the first carry value. The first carry value output by the half-adder 31 is input into a full adder.

[0108] At least one full adder 32 is used to perform an addition operation on the middle bit value of the first multi-bit number, the middle bit value of the second multi-bit number and the first carry value or the second carry value output by the previous full adder, and output at least one second carry value and at least one middle bit result value.

[0109] In this embodiment, at least one full adder is cascaded together, as can be referred to... Figure 1a and Figure 1b As shown, Figure 1a The topmost output Sum0 is a half adder, and the others are full adders. Each full adder receives the carry value from the previous stage (e.g., ...). Figure 1a Co1, or Co2, or Co3) and two intermediate values ​​(e.g., such as Co1, ...). Figure 1a If we use a1 and b1, or a2 and b2, or a3 and b3, we can perform an addition operation (refer to the operation process of formulas 1-2, 1-3, and 1-4) to obtain the intermediate result value and the second carry value corresponding to the current full adder.

[0110] In this embodiment, the circuit structure of the full adder can be any structure of a full adder in the prior art. For example, as shown in Figure 4, the full adder includes two XOR gates (XOR gate 41 and XOR gate 42), two AND gates (AND gate 43 and AND gate 44), and one OR gate 45. Figure 1a Taking a full adder connected to a half adder as an example, the data operation process in the full adder is described. Two intermediate values, a1 and b1, are input into XOR gate 41 and AND gate 44, respectively; the first carry value, Co1, is input into XOR gate 42 and AND gate 43. The output of XOR gate 41 is connected to XOR gate 42 and AND gate 43, enabling the output value of XOR gate 41 to perform XOR and AND operations with the first carry value, Co1, respectively. XOR gate 42 directly outputs the intermediate result value, Sum1; the outputs of AND gates 43 and 44 are input into OR gate 45 to perform OR operations, and OR gate 45 outputs the second carry value, Co2. For example, refer to... Figure 2a As shown, this is a full adder constructed using a combination of MOSFETs.

[0111] There is also a special case in this embodiment: the adder does not include a full adder, that is, the binary number being processed is a 2-bit number. In this case, the adder only includes a half adder and a sign processor.

[0112] The sign processor 33 is used to perform addition operations on the highest bit value of the first multi-bit number, the highest bit value of the second multi-bit number, and the second carry value output by the previous full adder, and output the highest bit result value and the sign result value.

[0113] In signed addition, an overflow occurs if adding two positive numbers results in a negative number, or adding two negative numbers results in a positive number. In two's complement representation, this can be determined by checking if the carry-in bit and the overflow bit (usually the carry-out bit) are the same; if they are the same, there is no overflow; if they are different, an overflow has occurred. Therefore, the main difference between unsigned and signed adders lies in how they handle the sign bit and overflow.

[0114] This embodiment combines the highest-order full adder (for calculating the sign bit) and the second-highest-order full adder (for calculating the highest-order result value) in a sign processor, which can then perform addition calculations with a sign bit at a low cost.

[0115] The signed adder circuit, chip, computing device, and electronic device provided in the above embodiments of this disclosure include: a cascaded half adder, at least one full adder, and a sign processor; the half adder is used to perform an addition operation on the least significant bit value of a first multi-bit number and the least significant bit value of a second multi-bit number to be computed, and outputs a first carry value and a least significant bit result value; wherein the first multi-bit number and the second multi-bit number are coincident numbers, or the first multi-bit number and the second multi-bit number are unsigned numbers; the at least one full adder is used to perform an addition operation on the middle bit value of the first multi-bit number, the middle bit value of the second multi-bit number, and the first carry value or the second carry value output by the previous full adder, and outputs at least one second carry value and at least one middle bit result value; the sign processor is used to perform an addition operation on the most significant bit value of the first multi-bit number, the most significant bit value of the second multi-bit number, and the second carry value output by the previous full adder, and outputs the most significant bit result value and the sign result value. The embodiments disclosed herein implement the calculation of the highest bit value of two multi-bit numbers through a symbol processor. While determining the highest bit result value, the symbol result value can also be output. The functions of two adders in the prior art are implemented with only one circuit, which reduces the number of MOSFETs, reduces the circuit area, and reduces power consumption and delay.

[0116] Figure 5 This is a schematic diagram of the sign processor in a signed adder circuit provided in another exemplary embodiment of this disclosure. (As shown...) Figure 5 As shown, the symbol processor 33 includes a symbol determination module 331 and a full addition module 332.

[0117] In this embodiment, the input data includes the highest bit value of the first multi-bit number, the highest bit value of the second multi-bit number, and the second carry value output by the previous full adder.

[0118] The symbol determination module 331 is used to perform at least one logical operation on the input data to obtain a symbol result value.

[0119] In this embodiment, the sign determination module independently performs at least one logical operation on the input data to obtain the sign result value, which simplifies the calculation circuit of the sign bit in the calculation of signed numbers. When it is necessary to perform the addition calculation of signed binary data, the sign determination module and the full addition module work together to realize the calculation of signed numbers.

[0120] The full adder module 332 is used to perform addition operations on input data and obtain the highest bit result value.

[0121] Optionally, in this embodiment, the full adder module implements the part of the full adder that obtains the result value, for example, such as... Figure 2a The circuit diagram provided in the illustrated embodiment, taking 4 bits as an example, is obtained through... Figure 2a The provided full adder module can directly output the highest bit result value Sum4.

[0122] This embodiment achieves the calculation of the highest bit and sign bit of a multi-bit signed binary number by adding only a sign determination module to a full adder, thus simplifying the circuit structure.

[0123] Based on the above formula and appendix Figure 1a , Figure 1b , Figure 2a and Figure 2b The formula for calculating the sign bit Sum4 can be simplified to obtain the following formula:

[0124]

[0125] Based on a comparison of formulas (1-6) and (3-1), we can see that the identical terms are a3b3 and a3x+b3x. Therefore, we can merge the identical terms, both unsigned and signed, leaving only Co3 and... Based on this, by making certain improvements to the adder, the output sign result value Sum4 can be achieved.

[0126] Figure 6a This is a schematic diagram of the sign determination module in a signed adder circuit provided in an exemplary embodiment of this disclosure. Figure 6a As shown, the sign determination module 331 includes: a first AND gate 61, a second AND gate 62, a third AND gate 63, and a first OR gate 64.

[0127] The first AND gate 61 performs an AND logic operation on the highest bit value of the first multi-bit number and the highest bit value of the second multi-bit number, and inputs the result of the first logic operation into the first OR gate 64.

[0128] The second AND gate 62 performs an AND logic operation on the highest bit value and the third carry value in the first multi-bit number, and inputs the result of the second logic operation into the first OR gate 64.

[0129] The third carry value is obtained by inverting the second carry value output by the previous full adder.

[0130] The third AND gate 63 performs an AND logic operation on the highest bit value of the second multi-bit number and the third carry value, and inputs the result of the third logic operation into the first OR gate 64.

[0131] The first OR gate 64 performs an OR operation on the results of the first, second, and third logical operations to obtain a symbolic result value.

[0132] Optionally, the sign determination module 331 may further include: a first NOT gate 65; the first NOT gate 65 is used to perform inversion processing on the second carry value output by the previous full adder to obtain the third carry value.

[0133] This embodiment can calculate the symbol result value using just a few simple logic gates. These logic gates can be implemented based on the MOSFET structure disclosed in the prior art. By combining this circuit with a full addition module, the highest bit result value and the symbol result value can be directly output in a symbol processor.

[0134] Figure 6b This is a schematic diagram of the sign determination module in a signed adder circuit provided in another exemplary embodiment of this disclosure. (See diagram below.) Figure 6b As shown, the sign determination module 331 includes: a fourth AND gate 66, a fifth AND gate 67, a second OR gate 68, and a third OR gate 69.

[0135] The second OR gate 68 performs an OR logic operation on the highest bit value of the first multi-bit number and the highest bit value of the second multi-bit number, and inputs the result of the fourth logic operation into the fourth AND gate.

[0136] The fourth AND gate 66 performs an AND operation on the result of the fourth logical operation and the third carry value, and inputs the result of the fifth logical operation into the third OR gate.

[0137] The third carry value is obtained by inverting the second carry value output by the previous full adder.

[0138] The fifth AND gate 67 performs an AND logic operation on the highest bit value of the first multi-bit number and the highest bit value of the second multi-bit number, and inputs the result of the sixth logic operation into the third OR gate.

[0139] The third OR gate 69 performs an OR operation on the result of the fifth and sixth logical operations to obtain a symbolic result value.

[0140] Optionally, in this embodiment, the sign determination module 331 may further include: a first NOT gate 65; the first NOT gate 65 is used to perform inversion processing on the second carry value output by the previous full adder to obtain a third carry value.

[0141] This embodiment can calculate the symbol result value using just a few simple logic gates. These logic gates can be implemented based on the MOSFET structure disclosed in the prior art. By combining this circuit with a full addition module, the highest bit result value and the symbol result value can be directly output in a symbol processor.

[0142] Figure 7 This is a schematic diagram of the sign determination module in a signed adder circuit provided in another exemplary embodiment of this disclosure. For example... Figure 7 As shown, the sign determination module 331 includes: a sixth AND gate 71, a seventh AND gate 72, a fourth OR gate 73, and a first NOR gate 74.

[0143] The fourth OR gate 73 performs an OR logic operation on the first and second high-order bits, and inputs the result of the seventh logic operation into the sixth AND gate 71.

[0144] The first high-order bit value is obtained by inverting the highest bit value in the first multi-bit number, and the second high-order bit value is obtained by inverting the highest bit value in the second multi-bit number.

[0145] Optionally, the sign determination module 331 further includes a second NOT gate 75 and a third NOT gate 76.

[0146] The second NOT gate 75 inverts the highest bit value in the second multi-bit number to obtain the second highest bit value.

[0147] The third NOT gate 76 inverts the highest bit value in the second multi-bit number to obtain the second highest bit value.

[0148] The sixth AND gate 71 performs an AND logic operation on the result of the seventh logic operation and the second carry value output by the previous full adder, and inputs the result of the eighth logic operation into the first NOR gate 74.

[0149] The seventh AND gate 72 performs an AND logic operation on the first and second high-order bits, and inputs the result of the ninth logic operation into the first NOR gate 74.

[0150] The first NOR gate 74 performs a NOR operation on the results of the eighth and ninth logical operations to obtain the sign result value.

[0151] This embodiment can calculate the symbol result value using just a few simple logic gates. These logic gates can be implemented based on the MOSFET structure disclosed in the prior art. By combining this circuit with a full addition module, the highest bit result value and the symbol result value can be directly output in a symbol processor.

[0152] Figure 8 This is a schematic diagram of the sign determination module in a signed adder circuit provided in another exemplary embodiment of this disclosure. For example... Figure 8 As shown, the symbol determination module 331 includes: a first transistor group 81, a second transistor group 82, a third transistor group 83, and a fourth transistor group 84.

[0153] The input terminal of the first transistor group 81 receives the second carry value output from the previous full adder and outputs the third carry value.

[0154] The third carry value is the inverse of the second carry value output by the previous full adder.

[0155] The input terminal of the second transistor group 82 receives the highest bit value of the first multi-bit number and the highest bit value of the second multi-bit number, and the output terminal is connected to the output terminal of the third transistor group and the input terminal of the fourth transistor group.

[0156] The input terminal of the third transistor group 83 receives the highest bit value of the first multi-bit number, the highest bit value of the second multi-bit number, and the third carry value, and the output terminal is connected to the output terminal of the second transistor group and the input terminal of the fourth transistor group.

[0157] The input terminal of the fourth transistor group 84 is connected to the output terminals of the second transistor group and the third transistor group, and the output terminal outputs the symbolic result value.

[0158] Figure 9 This is a schematic diagram of the sign determination module in a signed adder circuit provided in another exemplary embodiment of this disclosure. Figure 9 As shown, the first transistor group 81 and the fourth transistor group 84 have the same structure.

[0159] The first transistor group 81 includes a first transistor 811 and a second transistor 812 whose gate terminals are connected to each other. The gate terminal serves as the input terminal of the first transistor group 81. The drain terminal of the first transistor 811 is connected to the power supply signal Vdd. The source terminal of the first transistor 811 is connected to the drain terminal of the second transistor 812 and serves as the output terminal of the first transistor group. The source terminal of the second transistor 812 is grounded.

[0160] The first transistor is a p-type transistor, and the second transistor is an n-type transistor.

[0161] Since the first transistor group 81 and the fourth transistor group 84 have the same structure, it can be understood that the fourth transistor group 84 may include two transistors with the same structural relationship as the first transistor 811 and the second transistor 812, for example, a p-type thirteenth transistor 841 and an n-type fourteenth transistor 842. In this embodiment, both the first transistor group 81 and the fourth transistor group 84 implement the function of an inverter. For example, the first transistor group inverts the input second carry value and outputs the third carry value.

[0162] like Figure 9 As shown, the second transistor group 82 includes: a third transistor 821, a fourth transistor 822, a fifth transistor 823, and a sixth transistor 824; the third transistor 821 and the fourth transistor 822 are p-type transistors, and the fifth transistor 823 and the sixth transistor 824 are n-type transistors.

[0163] The drain terminal of the third transistor 821 is connected to the power supply signal Vdd, the gate terminal receives the highest bit value in the first multi-bit number, and the source terminal is connected to the drain terminal of the fourth transistor 822.

[0164] The gate of the fourth transistor 822 receives the highest bit value in the second multi-bit number, and its source terminal is connected to the drain terminal of the fifth transistor 823 and serves as the output terminal of the second transistor group 82.

[0165] The gate of the fifth transistor 823 receives the highest bit value in the second multi-bit number, and its source terminal is connected to the drain terminal of the sixth transistor.

[0166] The gate of the sixth transistor 824 receives the most significant bit value in the first multi-bit number, and the source terminal is grounded.

[0167] like Figure 9 As shown, the third transistor group 83 includes: a seventh transistor 831, an eighth transistor 832, a ninth transistor 833, a tenth transistor 834, an eleventh transistor 835, and a twelfth transistor 836; the seventh transistor 831, the eighth transistor 832, and the ninth transistor 833 are p-type transistors, and the tenth transistor 834, the eleventh transistor 835, and the twelfth transistor 836 are n-type transistors.

[0168] The drain terminal of the seventh transistor 831 is connected to the power supply signal, the source terminal of the seventh transistor 831 is connected to the drain terminal of the eighth transistor 832 and the source terminal of the ninth transistor 833, and the gate terminal of the seventh transistor 831 receives the highest bit value in the first multi-bit number.

[0169] The gate of the eighth transistor 832 is connected to the output of the first transistor group 81 (this connection is not shown in the figure for ease of illustration), and receives the third carry value. Its source terminal is connected to the drain terminal of the tenth transistor 834 as the output of the third transistor group.

[0170] The gate of the ninth transistor 833 receives the highest bit value in the second multi-bit number, and the drain is connected to the power supply signal.

[0171] The gate of the tenth transistor 834 is connected to the output of the first transistor group 81 (this connection is not shown in the figure for ease of illustration), receives the third carry value, and its source terminal is connected to the drain terminal of the eleventh transistor 835 and the drain terminal of the twelfth transistor 836.

[0172] The gate of the eleventh transistor 835 receives the most significant bit value of the first multi-bit number, and the source terminal is grounded.

[0173] The gate of the twelfth transistor 836 receives the most significant bit value of the second multi-bit number, and the source terminal is grounded.

[0174] For ease of display in the above embodiments, taking 4-bit signed binary numbers as examples of the first and second multi-bit numbers, the highest bit value in the first and second multi-bit numbers is marked as a3 and b3 respectively (the highest bit in the 4-bit data), the second carry value is marked as Carry3, and the third carry value is marked as Carry3b. This is only for easy marking and has no actual limiting function. This application does not limit the number of bits in the first and second multi-bit numbers. For example, when the first and second multi-bit numbers are 8 bits, the input is the highest bit value in the first and second multi-bit numbers as a7 and b7 respectively, and the second carry value and the third carry value are Carry7 and Carry7b respectively.

[0175] Figure 10 This is a schematic diagram of the sign processor in a signed adder circuit provided in another exemplary embodiment of this disclosure. For example... Figure 10 As shown, Figure 9 The provided sign determination module, combined with the full addition module, yields the following result: Figure 10 The circuit structure shown in the figure, with the part circled in red, is... Figure 9 The provided symbol determination module, the rest are the same as Figure 2a The circuit structure of the full adder shown is the same; therefore, the signed adder circuit provided in this embodiment is superior to the prior art. Figure 2b The circuit diagram shown saves 12 MOSFETs, reducing circuit area, power consumption, and delay. Figure 11The figure shows a comparison of the dynamic power consumption, latency, and static power consumption of the adder provided by the prior art and the embodiments of this disclosure. Blue represents the prior art and orange represents the present disclosure. The signed adder provided by the embodiments of this disclosure has positive gains in PPA.

[0176] The embodiments of this disclosure also provide a chip that integrates the adder circuit provided in any of the above embodiments. Details of the adder circuit can be found in the description of the above embodiments, and will not be described further here.

[0177] Embodiments of this disclosure also provide a computing device, including the adder circuit provided in any of the foregoing embodiments or the chip provided in the foregoing embodiments.

[0178] Embodiments of this disclosure also provide an electronic device, characterized in that it includes the chip provided in any of the above embodiments or the computing device provided in any of the above embodiments.

[0179] The electronic device can be either or both of the first device and the second device, or a standalone device independent of them, which can communicate with the first device and the second device to receive the acquired input signals from them.

[0180] Electronic devices include one or more processors and memory.

[0181] A processor can be a central processing unit (CPU) or other form of processing unit with data processing and / or instruction execution capabilities, and can control other components in an electronic device to perform desired functions.

[0182] The memory can store one or more computer program products, and the memory can include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. The volatile memory may, for example, include random access memory (RAM) and / or cache memory. The non-volatile memory may, for example, include read-only memory (ROM), hard disk, flash memory, etc. One or more computer program products can be stored on the computer-readable storage medium, and the processor can run the computer program products.

[0183] In one example, the electronic device may also include input devices and output devices, which are interconnected via a bus system and / or other forms of connection mechanism (not shown).

[0184] In addition, the input device may also include, for example, a keyboard, a mouse, etc.

[0185] This output device can output various information to the outside, including determined distance information, direction information, etc. The output device may include, for example, a display, a speaker, a printer, and a communication network and its connected remote output devices, etc.

[0186] Of course, for the sake of simplicity, Figure 10 Only some of the components of the electronic device relevant to this disclosure are shown, omitting components such as buses, input / output interfaces, etc. In addition, the electronic device may include any other suitable components depending on the specific application.

[0187] The basic principles of this disclosure have been described above with reference to specific embodiments. However, it should be noted that the advantages, benefits, and effects mentioned in this disclosure are merely examples and not limitations, and should not be considered as essential features of each embodiment of this disclosure. Furthermore, the specific details disclosed above are for illustrative and facilitative purposes only, and are not limitations. These details do not limit the scope of this disclosure to the necessity of employing the aforementioned specific details for implementation.

[0188] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For system embodiments, since they largely correspond to method embodiments, the description is relatively simple; relevant parts can be referred to the descriptions in the method embodiments.

[0189] The block diagrams of devices, apparatuses, devices, and systems disclosed herein are merely illustrative examples and are not intended to require or imply that they must be connected, arranged, or configured in the manner shown in the block diagrams. As those skilled in the art will recognize, these devices, apparatuses, devices, and systems can be connected, arranged, and configured in any manner. Words such as “comprising,” “including,” “having,” etc., are open-ended terms meaning “including but not limited to,” and are used interchangeably with them. The terms “or” and “and” as used herein refer to the terms “and / or,” and are used interchangeably with them unless the context clearly indicates otherwise. The term “such as” as used herein refers to the phrase “such as but not limited to,” and is used interchangeably with it.

[0190] The methods and apparatus of this disclosure may be implemented in many ways. For example, they may be implemented by software, hardware, firmware, or any combination of software, hardware, and firmware. The above-described order of steps for the methods is for illustrative purposes only, and the steps of the methods of this disclosure are not limited to the order specifically described above unless otherwise specifically stated. Furthermore, in some embodiments, this disclosure may also be implemented as a program recorded on a recording medium, the program including machine-readable instructions for implementing the methods according to this disclosure. Thus, this disclosure also covers recording media storing programs for performing the methods according to this disclosure.

[0191] It should also be noted that in the apparatus, devices, and methods of this disclosure, the components or steps can be disassembled and / or recombined. These disassemblies and / or recombinations should be considered as equivalent solutions to this disclosure.

[0192] The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use this disclosure. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects without departing from the scope of this disclosure. Therefore, this disclosure is not intended to be limited to the aspects shown herein, but rather to be carried out within the widest scope consistent with the principles and novel features disclosed herein.

[0193] The above description has been given for purposes of illustration and description. Furthermore, this description is not intended to limit the embodiments of this disclosure to the forms disclosed herein. Although numerous exemplary aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, alterations, additions, and sub-combinations thereof.

Claims

1. A signed adder circuit, characterized in that, include: A cascaded half-adder, at least one full adder, and a sign processor; The half-adder is used to perform an addition operation on the least significant bit value of the first multi-bit number and the least significant bit value of the second multi-bit number to be calculated, and outputs the first carry value and the least significant bit result value; wherein, the first multi-bit number and the second multi-bit number are signed numbers, or the first multi-bit number and the second multi-bit number are unsigned numbers; The at least one full adder is used to perform an addition operation on the middle bit value of the first multi-bit number, the middle bit value of the second multi-bit number, and the first carry value or the second carry value output by the previous full adder, and output at least one second carry value and at least one middle bit result value. The symbol processor is used to perform addition operations on the highest bit value of the first multi-bit number, the highest bit value of the second multi-bit number, and the second carry value output by the full adder of the previous stage, and output the highest bit result value and the sign result value.

2. The circuit according to claim 1, characterized in that, The symbol processor includes: a symbol determination module and a full addition module; The sign determination module is used to perform at least one logical operation on the input data to obtain a sign result value; wherein, the input data includes the highest bit value of the first multi-bit number, the highest bit value of the second multi-bit number, and the second carry value output by the previous full adder; The full addition module is used to perform addition operations on the input data to obtain the highest bit result value.

3. The circuit according to claim 2, characterized in that, The symbol determination module includes: a first AND gate, a second AND gate, a third AND gate, and a first OR gate; The first AND gate performs an AND logic operation on the highest bit value of the first multi-bit number and the highest bit value of the second multi-bit number, and inputs the result of the first logic operation into the first OR gate; The second AND gate performs an AND logic operation on the highest bit value and the third carry value in the first multi-bit number, and inputs the result of the second logic operation into the first OR gate; the third carry value is obtained by inverting the second carry value output by the previous stage full adder; The third AND gate performs an AND logic operation on the highest bit value of the second multi-bit number and the third carry value, and inputs the result of the third logic operation into the first OR gate; The first OR gate performs an OR logic operation on the first logic operation result, the second logic operation result, and the third logic operation result to obtain the symbolic result value.

4. The circuit according to claim 2, characterized in that, The symbol determination module includes: a fourth AND gate, a fifth AND gate, a second OR gate, and a third OR gate; The second OR gate performs an OR logic operation on the highest bit value in the first multi-bit number and the highest bit value in the second multi-bit number, and inputs the result of the fourth logic operation into the fourth AND gate; The fourth AND gate performs an AND operation on the result of the fourth logical operation and the third carry value, and inputs the result of the fifth logical operation into the third OR gate; the third carry value is obtained by inverting the second carry value output by the previous full adder; The fifth AND gate performs an AND logic operation on the highest bit value in the first multi-bit number and the highest bit value in the second multi-bit number, and inputs the result of the sixth logic operation into the third OR gate; The third OR gate performs an OR operation on the result of the fifth logical operation and the result of the sixth logical operation to obtain the symbolic result value.

5. The circuit according to claim 3 or 4, characterized in that, The sign determination module further includes: a first NOT gate; The first NOT gate inverts the second carry value output by the previous full adder to obtain the third carry value.

6. The circuit according to claim 2, characterized in that, The symbol determination module includes: a sixth AND gate, a seventh AND gate, a fourth OR gate, and a first NOR gate; The fourth OR gate performs an OR logic operation on the first high-order bit value and the second high-order bit value, and inputs the result of the seventh logic operation into the sixth AND gate; the first high-order bit value is obtained by inverting the highest bit value in the first multi-bit number, and the second high-order bit value is obtained by inverting the highest bit value in the second multi-bit number; The sixth AND gate performs an AND logic operation on the result of the seventh logic operation and the second carry value output by the previous full adder, and inputs the result of the eighth logic operation into the first NOR gate; The seventh AND gate performs an AND logic operation on the first high-order value and the second high-order value, and inputs the result of the ninth logic operation into the first NOR gate; The first NOR gate performs a NOR operation on the result of the eighth logical operation and the result of the ninth logical operation to obtain the symbolic result value.

7. The circuit according to claim 6, characterized in that, The sign determination module further includes: a second NOT gate and a third NOT gate; The second NOT gate inverts the highest bit value in the second multi-bit number to obtain the second high bit value; The third NOT gate inverts the highest bit value in the second multi-bit number to obtain the second high bit value.

8. The circuit according to claim 2, characterized in that, The symbol determination module includes: a first transistor group, a second transistor group, a third transistor group, and a fourth transistor group; The input terminal of the first transistor group receives the second carry value output by the previous stage full adder and outputs a third carry value; the third carry value is inversely related to the second carry value output by the previous stage full adder. The input terminal of the second transistor group receives the highest bit value of the first multi-bit number and the highest bit value of the second multi-bit number, and the output terminal is connected to the output terminal of the third transistor group and the input terminal of the fourth transistor group. The input terminal of the third transistor group receives the highest bit value of the first multi-bit number, the highest bit value of the second multi-bit number, and the third carry value, and the output terminal is connected to the output terminal of the second transistor group and the input terminal of the fourth transistor group; The input terminal of the third transistor group is connected to the second transistor group and the output terminal of the third transistor group, and the output terminal outputs the symbol result value.

9. The circuit according to claim 8, characterized in that, The first transistor group and the fourth transistor group have the same structure; The first transistor group includes a first transistor and a second transistor whose gate terminals are connected to each other. The gate terminal serves as the input terminal of the first transistor group. The drain terminal of the first transistor is connected to a power supply signal. The source terminal of the first transistor is connected to the drain terminal of the second transistor and serves as the output terminal of the first transistor group. The source terminal of the second transistor is grounded. The first transistor is a p-type transistor and the second transistor is an n-type transistor.

10. The circuit according to claims 8 and 9, characterized in that, The second transistor group includes: a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor; the third transistor and the fourth transistor are p-type transistors, and the fifth transistor and the sixth transistor are n-type transistors; The drain terminal of the third transistor is connected to the power supply signal, the gate terminal receives the highest bit value in the first multi-bit number, and the source terminal is connected to the drain terminal of the fourth transistor. The gate terminal of the fourth transistor receives the highest bit value in the second multi-bit number, and the source terminal is connected to the drain terminal of the fifth transistor and serves as the output terminal of the second transistor group. The gate of the fifth transistor receives the highest bit value in the second multi-bit number, and its source terminal is connected to the drain terminal of the sixth transistor. The gate of the sixth transistor receives the highest bit value in the first multi-bit number, and the source end is grounded.

11. The circuit according to any one of claims 8-10, characterized in that, The third transistor group includes: a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, and a twelfth transistor; the seventh transistor, the eighth transistor, and the ninth transistor are p-type transistors, and the tenth transistor, the eleventh transistor, and the twelfth transistor are n-type transistors; The drain terminal of the seventh transistor is connected to the power supply signal, the source terminal of the seventh transistor is connected to the drain terminal of the eighth transistor and the source terminal of the ninth transistor, and the gate terminal of the seventh transistor receives the highest bit value in the first multi-bit number. The gate terminal of the eighth transistor is connected to the output terminal of the first transistor group to receive the third carry value, and the source terminal is connected to the drain terminal of the tenth transistor as the output terminal of the third transistor group. The gate of the ninth transistor receives the highest bit value in the second multi-bit number, and the drain is connected to the power supply signal. The gate terminal of the tenth transistor receives the third carry value, and its source terminal is connected to the drain terminal of the eleventh transistor and the drain terminal of the twelfth transistor. The gate terminal of the eleventh transistor is connected to the output terminal of the first transistor group to receive the third carry value, and the source terminal is grounded. The gate of the twelfth transistor receives the highest bit value in the second multi-bit number, and the source terminal is grounded.

12. A chip, characterized in that, Includes the signed adder circuit according to any one of claims 1-11.

13. A computing device, characterized in that, Includes the signed adder circuit according to any one of claims 1-11 or the chip according to claim 12.

14. An electronic device, characterized in that, Includes the chip of claim 12 or the computing device of claim 13.

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