Method, device and equipment for verifying direct memory access controller and storage medium

Abstract

This disclosure relates to a verification method, apparatus, device, and storage medium for a direct memory access controller (DMC). The method includes: acquiring configuration parameter information corresponding to a function of the DMC to be verified; wherein the configuration parameter information includes configuration parameter type and configuration parameter range; inputting the configuration parameter information into a sequence file generation model to obtain a verification sequence file output by the sequence file generation model; sending the verification sequence file to the DMC, so that the DMC performs verification processing according to the verification sequence file; and obtaining a target verification result corresponding to the verification processing performed according to the verification sequence file. This reduces the verification difficulty of the DMC, lowers manpower consumption, accelerates the convergence of DMC verification coverage, and meets the industry demand for shorter chip design cycles.

Description

Technical Field

[0001] This disclosure relates to the field of direct memory access technology, and in particular to a method, apparatus, device and storage medium for verifying a direct memory access controller. Background Technology

[0002] Direct Memory Access (DMA) technology is a core technology for high-speed data transfer in modern digital chips. This technology frees the Central Processing Unit (CPU) from heavy data copying tasks, significantly reducing its load and allowing for full utilization of the bandwidth potential of high-speed peripherals. With increasing chip integration, the functional complexity of the Direct Memory Access Controller (DMAC) continues to rise. This has transformed the verification scenario for DMACs into multi-dimensional verification, demanding greater comprehensiveness and depth in the verification process.

[0003] In related technologies, verification test cases for direct memory access controllers need to be written manually, which involves a lot of repetitive work, consumes a lot of manpower, and has a long coverage convergence cycle, making it difficult to meet the industry's demand for shorter chip design cycles. Summary of the Invention

[0004] To address the aforementioned technical problems, this disclosure provides a method, apparatus, device, and storage medium for verifying a direct memory access controller.

[0005] In a first aspect, this disclosure provides a method for verifying a direct memory access controller, the method comprising: Obtain the configuration parameter information corresponding to the function to be verified of the direct memory access controller; wherein, the configuration parameter information includes the configuration parameter type and the configuration parameter range; The configuration parameter information is input into the sequence file generation model to obtain the verification sequence file output by the sequence file generation model; The verification sequence file is sent to the direct memory access controller, so that the direct memory access controller performs verification processing based on the verification sequence file; Obtain the target verification result corresponding to the verification process performed based on the verification sequence file.

[0006] Secondly, this disclosure provides a verification apparatus for a direct memory access controller, the apparatus comprising: The first acquisition module is used to acquire configuration parameter information corresponding to the function to be verified of the direct memory access controller; wherein, the configuration parameter information includes configuration parameter type and configuration parameter range; The generation module is used to input the configuration parameter information into the sequence file generation model to obtain the verification sequence file output by the sequence file generation model; The verification module is used to send the verification sequence file to the direct memory access controller, so that the direct memory access controller performs verification processing according to the verification sequence file; The second acquisition module is used to acquire the target verification result corresponding to the verification process performed according to the verification sequence file.

[0007] Thirdly, embodiments of this disclosure also provide an electronic device, the device comprising: One or more processors; Storage device for storing one or more programs. When one or more programs are executed by one or more processors, the one or more processors implement the methods provided in the first aspect.

[0008] Fourthly, embodiments of this disclosure also provide a computer-readable storage medium having a computer program stored thereon that, when executed by a processor, implements the method provided in the first aspect.

[0009] The technical solution provided in this disclosure has the following advantages compared with the prior art: This disclosure discloses a method, apparatus, device, and storage medium for verifying a direct memory access controller (DMC). The method includes: acquiring configuration parameter information corresponding to a function of the DMC to be verified; wherein the configuration parameter information includes configuration parameter type and configuration parameter range; inputting the configuration parameter information into a sequence file generation model to obtain a verification sequence file output by the sequence file generation model; sending the verification sequence file to the DMC to enable the DMC to perform verification processing based on the verification sequence file; and acquiring a target verification result corresponding to the verification processing performed based on the verification sequence file.

[0010] In the above scheme, the configuration parameter type and range of the function to be verified in the direct memory access controller are obtained. A verification sequence file is generated based on this configuration parameter type and range using a sequence file generation model. This verification sequence file is then sent to the direct memory access controller to obtain the corresponding target verification results. The configuration parameter type and range record key information for verifying the direct memory access controller. Furthermore, the file generation model automatically generates a comprehensive verification sequence file for direct memory access controller verification based on this key information. This reduces the verification difficulty of the direct memory access controller, reduces repetitive manual verification work, lowers manpower consumption, accelerates the convergence of direct memory access controller verification coverage, and meets the industry demand for shorter chip design cycles. Attached Figure Description

[0011] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure.

[0012] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0013] Figure 1 A flowchart illustrating a verification method for a direct memory access controller provided in an embodiment of this disclosure; Figure 2 A flowchart illustrating another verification method for a direct memory access controller provided in this embodiment of the present disclosure; Figure 3 A schematic diagram of a verification environment provided for an embodiment of this disclosure; Figure 4 A flowchart illustrating another verification method for a direct memory access controller provided in this disclosure embodiment; Figure 5 A flowchart illustrating another verification method for a direct memory access controller provided in an embodiment of this disclosure; Figure 6 A schematic diagram illustrating the process of a verification method for a direct memory access controller provided in an embodiment of this disclosure; Figure 7 A schematic diagram of the structure of a verification device for a direct memory access controller provided in an embodiment of this disclosure; Figure 8 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present disclosure. Detailed Implementation

[0014] To better understand the above-mentioned objectives, features, and advantages of this disclosure, the solutions disclosed herein will be further described below. It should be noted that, unless otherwise specified, the embodiments and features described herein can be combined with each other.

[0015] As chip integration increases, the functional complexity of direct memory access controllers (DMCs) continues to rise. On the one hand, the number of channels has evolved from single-channel to multi-channel (e.g., 16 channels, 128 channels, etc.), and scheduling strategies such as channel priority preemption and bandwidth allocation must be supported. On the other hand, to adapt to the security and compatibility requirements of System-on-Chip (SoC), modern DMCs also need to integrate advanced functions such as address translation, cache coherence maintenance, and pointer authentication from the Input / Output Memory Management Unit (IOMMU). These characteristics expand the verification scenarios for DMCs from simple data transmission to multi-dimensional verification encompassing transmission, scheduling, security, and consistency, placing higher demands on the comprehensiveness and depth of verification.

[0016] Currently, the verification of direct memory access controllers mainly involves verification personnel building a verification framework. While the direct memory access controller is designed for on-chip system integration, independent module verification is performed first. However, this approach faces significant bottlenecks in actual implementation.

[0017] The repetitive work involved in verifying independent modules is heavy. Specifically, during the independent module verification phase, verifiers need to design test cases for every functional point of the direct memory access controller. The design and writing of these test cases rely on the verifiers' experience and involve a large amount of repetitive logic (e.g., register parameter configuration, result checking code, etc.). Taking a 16-channel direct memory access controller as an example, nearly a hundred test cases for basic functions alone need to be written, which is time-consuming and error-prone. During product iterations, the direct memory access controller usually only supports the transmission of more types of data and does not change much, and the transmitted data also has a high degree of similarity. Therefore, verifiers need to complete a large amount of repetitive work in the verification of each generation of products.

[0018] Coverage convergence is inefficient. Specifically, traditional verification relies on an iterative process of manually analyzing coverage reports, identifying uncovered points, and manually modifying test cases. Since coverage reports typically contain thousands of coverage points, manual analysis is required to investigate the causes of each uncovered point, which is extremely inefficient. Furthermore, for long-tail scenarios, it is difficult for humans to predict them, causing these scenarios to remain uncovered for a long time, becoming potential risk points after chip tape-out.

[0019] In the relevant technologies, in the verification scenario of direct memory access controllers, verification personnel need to continuously invest repetitive work through manual guidance and script assistance. Moreover, the verification effect is highly dependent on personal experience, making it difficult to achieve large-scale replication of verification capabilities and efficiency breakthroughs. The amount of repetitive work in writing verification test cases is large, and the coverage convergence cycle is long, which is difficult to meet the industry demand for shortened chip design cycles.

[0020] To address at least one of the aforementioned technical problems, a verification method for a direct memory access controller provided in this disclosure is described below. In this disclosure, the verification method for the direct memory access controller can be executed by an electronic device. This electronic device may include devices with communication capabilities, such as tablet computers, desktop computers, and laptop computers.

[0021] Figure 1 A flowchart illustrating a verification method for a direct memory access controller provided in an embodiment of this disclosure is shown. Figure 1 As shown, the verification method for the direct memory access controller may include the following steps.

[0022] Step 101: Obtain the configuration parameter information corresponding to the function to be verified of the direct memory access controller; wherein, the configuration parameter information includes the configuration parameter type and the configuration parameter range.

[0023] The Direct Memory Access (DMI) controller can be the DMI controller to be verified. DMI is a core technology for high-speed data transmission in modern digital chips such as System-on-Chip (SoC). Through the DMI controller, system bus control can be taken over, allowing peripherals such as network interface cards (NICs), memory controllers, and image processors to bypass the central processing unit (CPU) and directly perform data read / write operations with memory. During the transmission process, the peripheral initiates a request to the DMI controller and configures transmission parameters such as source address, destination address, transmission length, and burst mode. The subsequent data transfer process is completed autonomously by the DMI controller, and an interrupt notification is sent upon completion. This not only frees the CPU from heavy data copying tasks, significantly reducing its load, but also fully utilizes the bandwidth potential of high-speed peripherals. It is an important module for high-performance chips in 5G communication, artificial intelligence (AI) acceleration, and autonomous driving.

[0024] The function to be verified can be a function in the Direct Memory Access Controller (DMI) to be verified, and this function can correspond one-to-one with the test coverage points. This embodiment does not limit the type of the function to be verified. For example, the type may include one or more of the following: single-channel transmission type, multi-channel parallel transmission scheduling strategy, multi-channel priority scheduling, cyclic transmission mode, source address change mode, destination address change mode, transmission priority function, input / output memory management unit address translation, cache consistency maintenance, transmission interrupt timing, and compatibility of multiple address alignment methods. The single-channel transmission type may include one or more of the following: single-cycle transmission, burst transmission, and scatter-gather transmission. Multiple address alignment methods may include multiple of the following: byte alignment, half-word alignment, and word alignment.

[0025] Configuration parameter information can be used to record the type and value range of configuration parameters corresponding to the overall function to be verified. The configuration parameter type can be any type of configuration parameter. This embodiment does not limit the configuration parameter type; for example, the configuration parameter type may include one or more of the following: transmission type, transmission length, address alignment, and interrupt enable for a single channel. The configuration parameter range can be the value range corresponding to the corresponding configuration parameter type. Configuration parameters can be parameters configured for verifying the function to be verified.

[0026] In this embodiment of the disclosure, the verification device for the direct memory access controller can determine the function to be verified of the direct memory access controller, and determine the configuration parameter type and configuration parameter range corresponding to the function to be verified as a whole, thereby determining the parameters that change during the verification process and the value range of the parameters.

[0027] Figure 2 A flowchart illustrating another verification method for a direct memory access controller provided in this disclosure embodiment is shown below. Figure 2 As shown, in some embodiments of this disclosure, there are multiple functions to be verified; obtaining the configuration parameter information corresponding to the functions to be verified in the direct memory access controller includes: Step 201: Obtain multiple sets of verification parameters corresponding to multiple functions to be verified; wherein each set of verification parameters includes at least one verification parameter type and at least one verification parameter content, and the multiple sets of verification parameters are determined according to the specification document of the direct memory access controller.

[0028] The verification parameter set can be used to record one or more verification parameters corresponding to a function to be verified. Verification parameters can be parameters determined based on manually set documents or other means, used to verify the function. The verification parameter type can be the type of verification parameter. The verification parameter content can be used to record the specific values ​​assigned to the verification parameters. The specification document can be a document characterizing the direct memory access controller specification, which may include architecture specification documents and design specification documents.

[0029] In this embodiment, the architecture engineer and chip design engineer can respectively write architecture specification documents and design specification documents based on the overall architecture and expected functions of the direct memory access controller. The verification engineer, in conjunction with the design engineer, breaks down the core functionalities of the direct memory access controller based on these documents. These core functionalities include, but are not limited to, one or more of the following: multi-channel priority scheduling, single-cycle transfer mode, burst transfer mode, round-robin transfer mode, source address change mode, destination address change mode, transfer priority function, input / output memory management unit address translation, cache consistency maintenance, and transfer interrupt timing. Furthermore, a set of verification parameters for each function to be verified is compiled. Verification of the direct memory access controller can obtain this set of verification parameters. For example, the set of verification parameters may include channel 3, burst transfer, and address offset of 1 byte. The identifier of the function to be verified and the set of verification parameters can be recorded in a mapping table.

[0030] Step 202: Determine the configuration parameter type and configuration parameter range based on multiple sets of verification parameters.

[0031] In this embodiment, the verification device of the direct memory access controller can determine the configuration parameter type based on the verification parameter types corresponding to multiple verification parameter sets, and determine the configuration parameter range of the corresponding configuration parameter type based on the verification parameter content corresponding to each verification parameter type. Thus, based on the verification parameter sets set for different functions to be verified, a relatively comprehensive set of configuration parameter information is determined. Furthermore, this set of verification parameters is essentially determined based on the direct memory access controller's specification document, and can comprehensively cover application scenarios such as long-tail scenarios of the direct memory access controller. These long-tail scenarios may include one or more of the following: multiple channels simultaneously experiencing address out-of-bounds errors leading to interrupt requests; bandwidth preemption by low-priority channels during high-priority channel transmission gaps; the direct memory access controller retry mechanism when input / output memory management unit address translation fails; and bus conflicts caused by concurrent requests from multiple peripherals.

[0032] In some embodiments of this disclosure, determining the configuration parameter type and configuration parameter range based on multiple verification parameter sets includes: determining the verification parameter type corresponding to the multiple verification parameter sets as the configuration parameter type; for each configuration parameter type, if the verification parameter content corresponding to the configuration parameter type is multiple characters, mapping the multiple characters to multiple mapping values, and determining the configuration parameter range corresponding to the configuration parameter type based on the multiple mapping values; if the verification parameter content corresponding to the configuration parameter type is multiple numerical values, normalizing the multiple numerical values ​​to obtain a normalized range, and determining the configuration parameter range corresponding to the configuration parameter type based on the normalized range.

[0033] The characters can be parameter content recorded in Chinese, English, or other text formats. These characters are typically used to record the parameter content corresponding to the validation parameter type of the first structure type, which can include discrete enumeration types or Boolean types. The mapping value can be the numerical value mapped to the character. The numerical value can be parameter content recorded in numeric form. This numerical value is typically used to record the parameter content corresponding to the validation parameter type whose data structure is continuous. Continuous types can be consecutive values ​​within a numerical range. The normalization range can be the numerical range obtained after normalization processing.

[0034] In this embodiment, the verification device of the direct memory access controller can determine the verification parameter types included in the overall set of multiple verification parameters and identify these verification parameter types as configuration parameter types. For each configuration parameter type, if the verification parameter content corresponding to that configuration parameter type consists of multiple characters, these characters are mapped to multiple mapping values ​​that increment sequentially from 0. The configuration parameter range corresponding to the configuration parameter type is then determined based on these multiple mapping values. If the verification parameter content corresponding to the configuration parameter type consists of multiple consecutive numerical values ​​within a numerical range, these multiple numerical values ​​are normalized to obtain a normalized range. The configuration parameter range corresponding to the configuration parameter type is then determined based on this normalized range. Thus, the verification parameter content is uniformly mapped to corresponding numerical values, laying the foundation for subsequent model processing.

[0035] For example, the verification of a direct memory access controller can be based on a mapping table recording the function to be verified and the set of configuration parameters. Configuration parameter information can be extracted from the test case template and converted into numerical features in the following ways: For verification parameter content of discrete enumeration parameters or Boolean parameters, the verification parameter content is mapped to a mapping value. Taking discrete enumeration parameters as an example, single-pass transmission type, burst transmission type, and loop transmission type can be mapped to 0, 1, and 2 respectively; address-aligned 0-byte offset, address-aligned 1-byte offset, address-aligned 2-byte offset, and address-aligned 3-byte offset can be mapped to 0, 1, 2, and 3 respectively. Taking Boolean parameters as an example, enabling interrupt and disabling interrupt can be mapped to 1 and 0 respectively. For verification parameter content of continuous parameters, the verification parameter content is normalized to the [0,1] interval. For example, the transmission length of 1-1024 bytes is normalized to the [0,1] interval. Furthermore, the verification device of the direct memory access controller can perform standardization processing on the numerical features. The mean of this standardization processing can be 0, and the variance can be 1, obtaining the configuration parameter range corresponding to each configuration parameter type.

[0036] Step 102: Input the configuration parameter information into the sequence file generation model to obtain the verification sequence file output by the sequence file generation model.

[0037] The sequence file generation model can be a neural network model that generates sequence files based on the type and value range of configuration parameters. Specifically, this model can generate sequence files that can be used to perform verification on the direct memory access controller, based on the configured parameters and value range. This sequence file generation model can be obtained through reinforcement training based on a large language model.

[0038] Reinforcement learning focuses on how a model takes different actions in an environment to maximize cumulative reward. After the model performs an action, the environment transitions to a new state, providing a reward signal (which can be positive or negative). The model then executes a new action according to a specific strategy, based on the new state and the reward from the environment. Through reinforcement learning, the model can determine the appropriate action to take in a given state to maximize its reward.

[0039] A verification sequence file is a sequence file used to verify the Direct Memory Access Controller (DMI). One verification sequence file can correspond to one test case. Sequence files can include register configuration sequence files and data transfer sequence files. Register configuration sequence files are used to determine the rules for data transfer through the DMI. Data transfer sequence files are used to determine the data transferred through the DMI. The register configuration sequence file can record the types and values ​​of configuration parameters. The data transfer sequence file can be generated based on configuration parameters that define the transmitted data. These configuration parameters can include data format, etc.

[0040] In this embodiment of the disclosure, the verification device of the direct memory access controller can input configuration parameter information and prompts indicating the generation of sequence files into the sequence file generation model to obtain the verification sequence file output by the sequence file generation model.

[0041] Step 103: Send the verification sequence file to the direct memory access controller so that the direct memory access controller performs verification processing based on the verification sequence file.

[0042] In this embodiment of the disclosure, in a verification environment, the verification device of the direct memory access controller (DMC) can transmit the register configuration sequence file in the verification sequence file to the DMC to be verified via a register proxy, and also transmit the data transmission sequence file in the verification sequence file to the DMC to be verified via a data transmission proxy. The DMC determines the data to be transmitted based on the received data transmission sequence file, determines the rules for data transmission based on the register configuration sequence file, and transmits the corresponding data according to the rules, thereby verifying the corresponding function to be verified.

[0043] Figure 3 A schematic diagram of a verification environment provided in an embodiment of this disclosure, such as... Figure 3 As shown, this verification environment can be built based on the Universal Verification Methodology (UVM). The UVM is a verification environment built using the SystemVerilog (SV) language, which can improve the automation level of the verification process and shorten the chip verification cycle. Verification typically accounts for about two-thirds of the chip development cycle. In the UVM, transaction-level verification is achieved through a layered architecture and core components, and it supports constraint-based random stimulus generation and coverage-driven verification, thereby improving verification efficiency and reusability.

[0044] In the general verification methodology, the agent, as the basic unit of the verification environment, is divided into register agents and data transfer agents. Each agent includes a monitor, a driver, a sequencer, and a virtual interface. The monitor is used to monitor the output of the Design Under Test (DUT) and generate transactions. In this embodiment, the DUT can be a direct memory access controller. The driver drives transactions to the DUT and the sequencer. The sequencer coordinates the execution order of sequences. The scoreboard automatically compares the expected and actual results of the DUT performing data processing based on the corresponding sequence file with the actual results. The general verification methodology adopts a layered structure, covering the test layer, scenario layer, functional layer, command layer, and signal layer, supporting component reuse from the individual module level to the system-on-chip level.

[0045] By using general verification methodology phases, such as the build phase, connect phase, and main phase, the timing and sequence of the verification process are managed, and verification capabilities can be further enhanced by integrating external models.

[0046] like Figure 3 As shown, this verification environment includes, but is not limited to, a reference model, a scoreboard, register configuration sequence files, data transfer sequence files, register brokers, and data transfer brokers. A broker is a collection of components, each including, but not limited to, virtual interfaces, drivers, monitors, and sequence schedulers. The verification environment connects to the module to be verified and performs tests by sending stimuli to the module through the execution of test cases. The register configuration sequence files and data transfer sequence files can transmit data to the direct memory access controller via the corresponding sequence scheduler, driver, and virtual interface, respectively.

[0047] Each test case in this verification environment can send stimuli to the module to be verified based on a register configuration sequence file and a data transmission sequence file. The different sequence files are independent of each other and are generated separately through the sequence file generation model. This access environment can be encapsulated into a corresponding template so that the sequence file generation model can generate the corresponding test cases.

[0048] Step 104: Obtain the target verification result corresponding to the verification process performed based on the verification sequence file.

[0049] The target verification result can be used to characterize the result of verification processing based on the verification sequence file. This embodiment does not limit the target verification result, which includes, but is not limited to, one or more of the following: test results, simulation results, coverage percentage, coverage point name, and coverage status. Invalid simulation results include filtering protocol violations, address out-of-bounds errors, etc. Test results include test success or test failure, and simulation results can include simulation success or simulation failure. The coverage percentage can be the coverage percentage of the function to be detected, the code coverage percentage, or the interface coverage percentage. The interface can be a peripheral interface of the direct memory access controller. The code coverage percentage can characterize the proportion of the running code to the total code of the direct memory access controller during the verification process. The above coverage percentages can be represented by values ​​within the range [0,1].

[0050] In this embodiment of the disclosure, a result script is pre-written using a scripting tool. After the direct memory access controller completes the verification process and generates the simulation log, the verification device of the direct memory access controller can call the result script to extract the target verification result from the simulation log and coverage report.

[0051] This disclosure discloses a method for verifying a direct memory access controller (DMC). The method involves obtaining configuration parameter information corresponding to the function to be verified in the DMC; wherein the configuration parameter information includes configuration parameter type and configuration parameter range; inputting the configuration parameter information into a sequence file generation model to obtain a verification sequence file output by the sequence file generation model; sending the verification sequence file to the DMC so that the DMC performs verification processing based on the verification sequence file; and obtaining the target verification result corresponding to the verification processing performed based on the verification sequence file.

[0052] In the above scheme, the configuration parameter type and range of the function to be verified in the direct memory access controller are obtained. A verification sequence file is generated based on this configuration parameter type and range using a sequence file generation model. This verification sequence file is then sent to the direct memory access controller to obtain the corresponding target verification results. The configuration parameter type and range record key information for verifying the direct memory access controller. Furthermore, the file generation model automatically generates a comprehensive verification sequence file for direct memory access controller verification based on this key information. This reduces the verification difficulty of the direct memory access controller, reduces repetitive manual verification work, lowers manpower consumption, accelerates the convergence of direct memory access controller verification coverage, and meets the industry demand for shorter chip design cycles.

[0053] Furthermore, this verification method for the direct memory access controller deeply integrates the sequence file generation model with the sequence files for software and hardware verification. Under the framework of a general verification methodology, it realizes the automatic generation of test cases and the intelligent analysis of simulation results, which ultimately lowers the verification threshold, reduces manpower costs, and improves the verification coverage and convergence efficiency of the direct memory access controller.

[0054] Figure 4 A flowchart illustrating another verification method for a direct memory access controller provided in this disclosure embodiment is shown below. Figure 4 As shown in some embodiments of this disclosure, the training process of the sequence file generation model includes: Step 401: Obtain the sample parameter information corresponding to the sample function of the direct memory access controller.

[0055] The sample function can refer to the direct memory access controller (DMC) functionality involved in the training of the sequence file generation model. Configuration parameter information records the type and numerical range of the configuration parameters corresponding to the overall sample function. This sample parameter information is obtained after filtering out conflicting parameter combinations, which may include combinations that violate the Advanced eXtensible Interface (AXI) bus protocol or DMC design rules. Parameter combinations that violate DMC design rules may include combinations with a burst length greater than 16, unaligned addresses, and burst transfer types.

[0056] In this embodiment, the verification device of the direct memory access controller can acquire multiple parameter sets corresponding to multiple sample functions. The sample parameter type is determined based on the parameter types of these multiple parameter sets, and the sample parameter range is determined based on the parameter content corresponding to the parameter type.

[0057] Step 402: Input the sample parameter information into the initial model to obtain the prediction sequence file. Determine the reward value based on the prediction sequence file. Adjust the model parameters of the initial model based on the reward value until the preset convergence condition is met. Then, use the initial model as the sequence file to generate the model.

[0058] The initial model can be a neural network model that has not completed reinforcement training, and this initial model can be a large language model. The predicted sequence file can be a sequence file determined by the initial model based on sample parameter information. The reward value can be a numerical evaluation signal obtained after each round of training of the initial model in reinforcement learning, used to quantify the performance of the initial model in that round of training, and thus guide the initial model to learn the optimal decision strategy. The preset convergence condition can be a pre-set condition for stopping reinforcement training of the initial model. This embodiment does not limit the preset convergence condition, for example, it can include reaching a preset number of training rounds, or achieving a preset effect, etc.

[0059] In this embodiment, the direct memory access controller can use a simulation environment built based on a general verification methodology as the environment for reinforcement learning. The state is a coverage state vector of all current sample functions. The dimension of this coverage state vector is the same as the total number of sample functions, and each element in the coverage state vector represents whether the corresponding sample function is covered. For example, 0 can represent uncovered, and 1 can represent covered. The action space is the parameter combination after filtering out conflicting parameter combinations based on the sample parameter information. This embodiment does not limit the learning strategy of this reinforcement learning. For example, a greedy strategy can be used. The initial exploration rate can be set to the first exploration rate (e.g., 0.8), that is, to prioritize exploring uncovered scenarios. Every iteration of a preset number of rounds (e.g., 10 rounds), the exploration rate is reduced by a preset rate (e.g., 0.05). The minimum value of this exploration rate is 0.01, thereby gradually focusing on the optimal action.

[0060] In this embodiment, the verification device of the direct memory access controller can input sample parameter information into the initial model to obtain the prediction sequence file output by the initial model, and send the prediction sequence file to the direct memory access controller so that the direct memory access controller can perform verification processing based on the prediction sequence file. The direct memory access controller can determine the reward value based on the result of the verification processing, and adjust the model parameters of the initial model based on the reward value. After multiple rounds of training until the preset convergence condition is reached, the initial model is used as the sequence file to generate the model.

[0061] In some embodiments of this disclosure, determining the reward value based on the predicted sequence file includes: Step a1: The predicted sequence file is sent to the direct memory access controller so that the direct memory access controller performs verification processing based on the predicted sequence file.

[0062] In this embodiment, the verification device of the direct memory access controller can transmit the register configuration sequence file in the prediction sequence file to the direct memory access controller to be verified through a register broker, and also transmit the data transmission sequence file in the prediction sequence file to the direct memory access controller to be verified through a data transmission broker. The direct memory access controller determines the data to be transmitted based on the received data transmission sequence file, determines the data transmission rules based on the register configuration sequence file, and transmits the corresponding data according to the rules, thereby realizing verification processing based on the prediction sequence file.

[0063] Step a2: Obtain the sample verification results corresponding to the verification processing performed based on the predicted sequence file; wherein, the sample verification results include code coverage, the number of newly added coverage of sample functions, and simulation error information.

[0064] The sample validation result can be the validation result of the current training round, representing the validation effect of the predicted sequence file generated in the current training round. Code coverage can be the degree to which the validation process covers the code in the direct memory access controller. Optionally, in multiple rounds of training of the initial model, the code coverage of the current training round can be determined based on the code covered by the current training round, or it can be determined by combining the code coverage of the previous and current training rounds. Similarly, the code coverage of the next training round can be determined by combining the code coverage of the current and next training rounds. The number of newly added coverage points can be the difference between the number of sample functions covered in the current training round and the number of sample functions covered in the previous training round. Simulation error information can represent whether an error occurred during the simulation process; if at least one error occurred, the simulation error information is 1.

[0065] In this embodiment, after the direct memory access controller completes the verification process based on the predicted sequence text and generates the verification result, the verification device of the direct memory access controller can call the corresponding script to extract the sample verification result from the verification result and the coverage report.

[0066] Step a3: Determine the reward value based on code coverage, the number of new coverage items, and simulation error messages; among them, code coverage and reward value are positively correlated, and the number of new coverage items is also positively correlated with reward value.

[0067] In this embodiment, before direct memory access control, code coverage, the number of new coverage items, and simulation error information can be substituted into the reward function to obtain the reward value.

[0068] For example, the reward value may include a core reward value, which can be the sum of the product of the new coverage and the first sub-reward value, the second sub-reward value, and the third sub-reward value. In this embodiment, the specific value of the first sub-reward value is not limited; for example, it can be 10. The second sub-reward value is negative when the simulation error message is 1, for example, -5. The third sub-reward value is positive when the code coverage is greater than or equal to the coverage threshold, for example, 100. This coverage threshold can be set according to the application scenario, etc., and this embodiment does not impose any restrictions; for example, it can be 99%.

[0069] In the above scheme, the reward value is determined based on code coverage, the number of new coverage items, and simulation error information. This enhanced training can improve the overall performance of the initial model in multiple dimensions such as code coverage, the number of new coverage items, and simulation error information.

[0070] In some embodiments of this disclosure, the model parameters of the initial model are adjusted according to the reward value until a preset convergence condition is met, and then the initial model is used as a sequence file to generate a new model, including: Step b1: Adjust the model parameters of the initial model in the current training round according to the reward value to obtain the initial model for the next training round.

[0071] Step b2: If the first sample validation result and the second sample validation result satisfy the preset adjustment conditions after a preset number of consecutive training rounds, the sample parameter information is updated according to the adjustment parameters, and the reward value is determined according to the updated sample parameter information. This process continues until the preset convergence condition is met, at which point the initial model is used as a sequence file to generate a model. Here, the first sample validation result is the sample validation result of the initial model in the current training round, and the second sample validation result is the sample validation result of the initial model in the next training round. The adjustment parameters include at least one of the error injection parameters and multi-channel concurrency parameters.

[0072] In this embodiment, the preset quantity is not limited, for example, it can be 5. The preset adjustment condition can be a pre-set judgment condition for adjusting the sample parameter information on which the prediction sequence file is based. In this embodiment, the preset adjustment condition is not limited. For example, the preset adjustment condition can be that the code coverage improvement value of the current training round is less than 0.1% compared with the previous training round.

[0073] Tuning parameters can be used to adjust sample parameter information to optimize the prediction sequence file for the next training round. Error injection information can be parameter combinations that violate the design rules of the direct memory access controller. This error injection information enables the initial model to handle erroneous parameter combinations. Multi-channel concurrency parameters can be used to characterize concurrent data processing through multiple data transmission channels of the direct memory access controller. These tuning parameters may also include one or more of the following: cache consistency parameters and address mapping translation parameters.

[0074] In this embodiment, the verification device for the Direct Memory Access Controller (DMI) can perform closed-loop iterations of action selection, test case generation, simulation execution, coverage feedback, and Q-table updates within the DMI simulation environment. Each iteration can be understood as a training round. After each iteration, the code coverage on the validation set is recorded, and the difference between the current training round and the previous training round is calculated to obtain the code coverage improvement value. If the code coverage improvement value is less than the improvement threshold for a consecutive preset number of training rounds, adjustment parameters are added to the sample parameter information to expand the reinforcement learning action space. In the next training round, the sample parameter information with the added adjustment parameters is input into the initial model to obtain the corresponding prediction sequence file. The reward value is determined based on the prediction sequence file, and the model parameters of the initial model are adjusted based on the reward value until the training rounds reach a preset number of training rounds (e.g., 200 rounds), or the coverage of the sample functions is ≥99%.

[0075] In this embodiment, the ratio of the number of samples in the training set, validation set, and test set in reinforcement training can be 7:2:1. The stratification can be based on the type of sample function, thereby making the sample functions of each type evenly distributed in the dataset.

[0076] In the above scheme, a boundary scenario of cross-module interaction between peripherals, direct memory access controllers, memory, and input / output memory management units was built through a verification environment. Furthermore, by updating the sample parameter information according to the adjusted parameters during the reinforcement learning process, blind spots in key functional points such as multi-channel parallelism, cache consistency, and address mapping conversion were covered, thereby improving the comprehensiveness of the covered scenarios.

[0077] Optionally, the trained sequence text generation model can be exported as an OpenNeural Network Exchange (ONNX) format, and the sequence file generation model can be deployed to the AI ​​scheduling module of the direct memory access controller verification environment. The AI ​​scheduling module can interact with the verification environment through an interface.

[0078] Figure 5A flowchart illustrating another verification method for a direct memory access controller provided in this disclosure embodiment is shown below. Figure 5 As shown, in some embodiments of this disclosure, the target verification result includes the verification result of the first function that has been verified among the functions to be verified, and the verification method of the direct memory access controller further includes: Step 501: Determine the second function; wherein, the second function is any function other than the first function among the functions to be verified.

[0079] The second function can be an unverified function that needs to be verified.

[0080] In this implementation, the direct memory access controller can determine a first function that has been verified through the verification process, and remove the first function from the function to be verified to obtain a second function.

[0081] Step 502: Obtain the second verification parameter set corresponding to the second function, input the second verification parameter set into the sequence file generation model, and obtain the supplementary sequence file output by the sequence file generation model.

[0082] The second set of verification parameters can be the set of verification parameters corresponding to the second function. The supplementary sequence file can be the sequence file for verifying the second function, which can be understood as a sequence file for supplementing the verification of the function to be verified.

[0083] In this embodiment of the disclosure, the verification device of the direct memory access controller can input a second set of verification parameters and a prompt word indicating the generation of a sequence file into the sequence file generation model to obtain a supplementary sequence file output by the sequence file generation model.

[0084] Step 503: The supplementary sequence file is sent to the direct memory access controller so that the direct memory access controller performs verification processing based on the supplementary sequence file.

[0085] In this embodiment, the verification device for the direct memory access controller (DMC) can transmit the register configuration sequence file from the supplementary sequence file to the DMC to be verified via a register proxy, and also transmit the data transmission sequence file from the supplementary sequence file to the DMC via a data transmission proxy. The DMC determines the data to be transmitted based on the received data transmission sequence file, determines the data transmission rules based on the register configuration sequence file, and transmits the corresponding data according to the rules, thereby achieving the verification process for the second function.

[0086] Step 504: Obtain the comprehensive verification result; wherein the comprehensive verification result corresponds to the verification process performed based on the supplementary sequence file and the verification process performed based on the verification sequence file.

[0087] The comprehensive verification results can include one or more of the following: comprehensive code coverage, comprehensive functional coverage, and comprehensive interface coverage. Comprehensive code coverage can be the ratio of the comprehensive verified code to the total code. Comprehensive verified code can be the union of the code in the Direct Memory Access Controller (DMI) verified based on the supplementary sequence file and the code in the DMI verified based on the verification sequence file. Comprehensive functional coverage can be the ratio of the number of comprehensive functions to the number of functions to be verified. Comprehensive functions can be the union of the functions verified based on the supplementary sequence file and the functions verified based on the verification sequence file. Comprehensive interface coverage can be the ratio of the number of comprehensive interfaces to the total number of interfaces in the DMI. Comprehensive interfaces can be the union of the interfaces used for verification processing based on the supplementary sequence file and the interfaces used for verification processing based on the verification sequence file.

[0088] In this embodiment, after the Direct Memory Access Controller (DMC) completes the verification process based on the supplementary sequence file and generates the simulation log, the DMC's verification device can call the result script to extract the verification result corresponding to the supplementary sequence file from the simulation log and coverage report. Furthermore, the verification result corresponding to the supplementary sequence file and the verification result corresponding to the verification sequence file are integrated to obtain a comprehensive verification result.

[0089] Figure 6 This is a schematic diagram illustrating a verification method for a direct memory access controller provided in an embodiment of this disclosure. Figure 6 As shown, the AI ​​scheduling module can determine the second set of verification parameters based on the coverage of the function to be tested, by calling the model or looking up the mapping table. This second set of verification parameters is then automatically populated into the prompt word template for the test cases, generating corresponding prompt words. These prompt words are input into the sequence file generation model, resulting in a supplementary sequence file output by the model. This supplementary sequence file is then used as a new test case. The compilation and simulation of this new test case are then executed in batches through the verification environment and the direct memory access controller to be verified, generating simulation logs and a coverage report. These simulation logs and coverage reports are then returned to the AI ​​scheduling module.

[0090] The above scheme combines the sequence file generation model with the verification framework of the general verification method to design an intelligent system specifically for direct memory access controller verification. Through reinforcement learning of the sequence file generation model, test cases that fully cover various scenarios are automatically generated. After simulation, the large model can quickly analyze the coverage report, locate the uncovered points, and build supplementary test cases accordingly, forming an automated closed loop of generation, simulation, analysis, and iteration. This significantly reduces the verification difficulty, reduces manpower costs, and accelerates the coverage convergence of direct memory access controller verification.

[0091] In some embodiments of this disclosure, the verification method for the direct memory access controller further includes: determining whether the coverage in the comprehensive verification result meets the coverage convergence condition; if so, determining that the verification is complete. Otherwise, returning to the previous method, identifying the currently unverified function to be verified as a new second function, and performing verification processing on the new second function, determining the cumulative verification result corresponding to all verification processing performed on the function to be verified, until the coverage in the cumulative verification result meets the coverage convergence condition.

[0092] The coverage convergence condition can be that functional coverage, code coverage, and interface coverage are all greater than or equal to the corresponding thresholds. Specifically, the threshold for functional coverage can be 99%, the threshold for interface coverage can be 95%, and the threshold for interface coverage can be 90%.

[0093] In the above scheme, the new coverage is automatically integrated with the coverage of the previous round through simulation tools. If the integrated coverage does not meet the coverage convergence condition, new test cases are generated based on the uncovered second function, and the process of test case generation, simulation, coverage feedback, and incremental testing is repeated until the coverage meets the coverage convergence condition.

[0094] In this embodiment, based on the architecture and design specifications of the direct memory access controller (DMC) to be verified, the core functions to be verified are planned, configuration parameter information is summarized, and coverage convergence conditions are established. A verification environment for the DMC is built based on a general verification methodology, test case templates are created, and simulation logs and coverage result scripts are written. The configuration parameter information is converted into numerical features, and the data is divided into training, validation, and test sets. A reinforcement learning framework is constructed, and a sequence file generation model is iteratively trained in the simulation environment using a preset learning strategy. The trained sequence file generation model is deployed in the verification environment of the module to be verified, and the simulation logs and coverage reports are determined based on the verification sequence files generated by this model. The simulation logs and coverage reports are analyzed, new parameter combinations are constructed, and a new round of simulation is performed until the coverage convergence conditions are met.

[0095] The correctness of the Direct Memory Access Controller (DMI) is highly dependent on the peripheral interface protocol, memory controller timing, and I / O memory management unit (I / O) configuration. This peripheral interface protocol includes Advanced eXtensible Interface (AXI) and Advanced High-performance Bus (AHB), requiring verification across multiple modules in a system-on-a-chip (SoC) environment. The DMI verification method provided in this disclosure simulates the data interaction of the DMI in a verification environment, achieving simulation of a simulation environment including peripherals, memory, and I / O memory management units. It automates the writing of stimulus code and interface adaptation logic through the model, reducing the time consumed in the environment setup phase. Furthermore, by supplementing sequence files in multiple rounds, it covers the configuration parameter information of the functions to be verified based on the specification document, covering boundary scenarios of cross-module interactions and improving the convergence speed of coverage.

[0096] Figure 7 A schematic diagram of the structure of a verification device for a direct memory access controller provided in an embodiment of this disclosure is shown.

[0097] like Figure 7 As shown, the verification device 700 for the direct memory access controller may include: The first acquisition module 701 is used to acquire configuration parameter information corresponding to the function to be verified of the direct memory access controller; wherein, the configuration parameter information includes configuration parameter type and configuration parameter range; The generation module 702 is used to input the configuration parameter information into the sequence file generation model to obtain the verification sequence file output by the sequence file generation model; Verification module 703 is used to send the verification sequence file to the direct memory access controller, so that the direct memory access controller performs verification processing according to the verification sequence file; The second acquisition module 704 is used to acquire the target verification result corresponding to the verification process performed according to the verification sequence file.

[0098] Optionally, the number of functions to be verified is multiple; obtaining the configuration parameter information corresponding to the functions to be verified of the direct memory access controller includes: Obtain multiple sets of verification parameters corresponding to the multiple functions to be verified; wherein each set of verification parameters includes at least one verification parameter type and at least one verification parameter content, and the multiple sets of verification parameters are determined according to the specification document of the direct memory access controller; The configuration parameter type and the configuration parameter range are determined based on the multiple sets of verification parameters.

[0099] Optionally, determining the configuration parameter type and the configuration parameter range based on the plurality of verification parameter sets includes: The verification parameter type corresponding to the plurality of verification parameter sets is determined as the configuration parameter type; For each configuration parameter type, if the verification parameter content corresponding to the configuration parameter type is multiple characters, then the multiple characters are mapped to multiple mapping values, and the configuration parameter range corresponding to the configuration parameter type is determined according to the multiple mapping values; If the verification parameter content corresponding to the configuration parameter type is multiple values, then the multiple values ​​are normalized to obtain a normalized range, and the configuration parameter range corresponding to the configuration parameter type is determined based on the normalized range.

[0100] Optionally, the verification device for the direct memory access controller further includes a training module, the training module being used for: Obtain the sample parameter information corresponding to the sample function of the direct memory access controller; The sample parameter information is input into the initial model to obtain a prediction sequence file. The reward value is determined based on the prediction sequence file. The model parameters of the initial model are adjusted based on the reward value until a preset convergence condition is reached. The initial model is then used as the generation model for the sequence file.

[0101] Optionally, determining the reward value based on the predicted sequence file includes: The predicted sequence file is sent to the direct memory access controller, so that the direct memory access controller performs verification processing based on the predicted sequence file; Obtain the sample verification results corresponding to the verification processing performed based on the predicted sequence file; wherein, the sample verification results include code coverage, the number of newly added coverage of sample functions, and simulation error information; The reward value is determined based on the code coverage rate, the number of new coverage items, and the simulation error information; wherein the code coverage rate and the reward value are positively correlated, and the number of new coverage items and the reward value are also positively correlated.

[0102] Optionally, adjusting the model parameters of the initial model according to the reward value until a preset convergence condition is met, and then using the initial model as the generated model for the sequence file, includes: The model parameters of the initial model in the current training round are adjusted based on the reward value to obtain the initial model for the next training round. If, after a predetermined number of consecutive training rounds, the first sample validation result and the second sample validation result satisfy the predetermined adjustment conditions, the sample parameter information is updated according to the adjustment parameters. The reward value is then determined based on the updated sample parameter information. This process continues until the predetermined convergence condition is met, at which point the initial model is used as the sequence file to generate the model. Herein, the first sample validation result is the sample validation result of the initial model in the current training round, and the second sample validation result is the sample validation result of the initial model in the next training round. The adjustment parameters include at least one of error injection parameters and multi-channel concurrency parameters.

[0103] Optionally, the target verification result includes the verification result of the first function that has been verified among the functions to be verified, and the verification device of the direct memory access controller further includes: A determining module is used to determine a second function; wherein the second function is another function among the functions to be verified besides the first function; The third acquisition module is used to acquire the second verification parameter set corresponding to the second function, input the second verification parameter set into the sequence file generation model, and obtain the supplementary sequence file output by the sequence file generation model; The sending module is configured to send the supplementary sequence file to the direct memory access controller, so that the direct memory access controller performs verification processing based on the supplementary sequence file; The fourth acquisition module is used to acquire the comprehensive verification result; wherein the comprehensive verification result corresponds to the verification process performed according to the supplementary sequence file and the verification process performed according to the verification sequence file.

[0104] It should be noted that, Figure 7 The verification device 700 for the direct memory access controller shown can execute each step in the above-described verification method embodiment for the direct memory access controller, and realize each process and effect in the above-described verification method embodiment for the direct memory access controller, which will not be elaborated here.

[0105] Figure 8 A schematic diagram of the structure of an electronic device provided in an embodiment of this disclosure is shown.

[0106] like Figure 8 As shown, the electronic device may include a processor 801 and a memory 802 storing computer program instructions.

[0107] Specifically, the processor 801 may include a central processing unit (CPU), an application-specific integrated circuit (ASIC), or one or more integrated circuits that can be configured to implement the embodiments of this application.

[0108] Memory 802 may include a mass storage device for information or instructions. For example, and not limitingly, memory 802 may include a hard disk drive (HDD), a floppy disk drive, flash memory, optical disk, magneto-optical disk, magnetic tape, or a Universal Serial Bus (USB) drive, or a combination of two or more of these. Where appropriate, memory 802 may include removable or non-removable (or fixed) media. Where appropriate, memory 802 may be internal or external to the integrated gateway device. In a particular embodiment, memory 802 is a non-volatile solid-state memory. In a particular embodiment, memory 802 includes read-only memory (ROM). Where appropriate, the ROM may be a mask-programmed ROM, a programmable ROM (PROM), an erasable PROM (Electrically Programmable ROM, EPROM), an electrically erasable programmable PROM (EEPROM), an electrically alterable ROM (EAROM), or flash memory, or a combination of two or more of these.

[0109] The processor 801 performs the steps of the verification method for the direct memory access controller provided in this embodiment of the present disclosure by reading and executing computer program instructions stored in the memory 802.

[0110] In one example, the electronic device may also include a transceiver 803 and a bus 804. Wherein, as... Figure 8 As shown, the processor 801, memory 802 and transceiver 803 are connected via bus 804 and communicate with each other.

[0111] Bus 804 includes hardware, software, or both. For example, and not limitingly, the bus may include an Accelerated Graphics Port (AGP) or other graphics bus, an Extended Industry Standard Architecture (EISA) bus, a Front Side Bus (FSB), a Hyper Transport (HT) interconnect, an Industrial Standard Architecture (ISA) bus, an Infinite Bandwidth Interconnect, a Low Pin Count (LPC) bus, a memory bus, a MicroChannel Architecture (MCA) bus, a Peripheral Component Interconnect (PCI) bus, a PCI-Express (PCI-X) bus, a Serial Advanced Technology Attachment (SATA) bus, a Video Electronics Standards Association Local Bus (VLB) bus, or other suitable buses, or a combination of two or more of these. Where appropriate, bus 804 may include one or more buses. Although specific buses are described and illustrated in the embodiments of this application, this application considers any suitable bus or interconnection.

[0112] The following are embodiments of a computer-readable storage medium provided in this disclosure. This computer-readable storage medium and the verification method of the direct memory access controller in the above embodiments belong to the same inventive concept. For details not described in detail in the embodiments of the computer-readable storage medium, please refer to the embodiments of the verification method of the direct memory access controller described above.

[0113] This embodiment provides a storage medium containing computer-executable instructions, which, when executed by a computer processor, are used to perform a verification method for a direct memory access controller.

[0114] Of course, the computer-executable instructions provided in the embodiments of this disclosure are not limited to the above-described method operations, but can also perform related operations in the verification method of the direct memory access controller provided in any embodiment of this disclosure.

[0115] Based on the above description of the implementation methods, those skilled in the art can clearly understand that this disclosure can be implemented using software and necessary general-purpose hardware, and of course, it can also be implemented using hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this disclosure, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as a computer floppy disk, read-only memory (ROM), random access memory (RAM), flash memory, hard disk, or optical disk, etc., including several instructions to cause a computer cloud platform (which may be a personal computer, server, or network cloud platform, etc.) to execute the verification method of the direct memory access controller provided in the various embodiments of this disclosure.

[0116] Note that the above description is merely a preferred embodiment and the technical principles employed in this disclosure. Those skilled in the art will understand that this disclosure is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of this disclosure. Therefore, although this disclosure has been described in detail through the above embodiments, it is not limited to the above embodiments. Many other equivalent embodiments may be included without departing from the concept of this disclosure, and the scope of this disclosure is determined by the scope of the appended claims.

Claims

1. A verification method for a direct memory access controller, characterized in that, include: Obtain the configuration parameter information corresponding to the function to be verified of the direct memory access controller; wherein, the configuration parameter information includes the configuration parameter type and the configuration parameter range; The configuration parameter information is input into the sequence file generation model to obtain the verification sequence file output by the sequence file generation model; The verification sequence file is sent to the direct memory access controller, so that the direct memory access controller performs verification processing based on the verification sequence file; Obtain the target verification result corresponding to the verification process performed based on the verification sequence file.

2. The method according to claim 1, characterized in that, The number of functions to be verified is multiple; obtaining the configuration parameter information corresponding to the functions to be verified in the direct memory access controller includes: Obtain multiple sets of verification parameters corresponding to the multiple functions to be verified; wherein each set of verification parameters includes at least one verification parameter type and at least one verification parameter content, and the multiple sets of verification parameters are determined according to the specification document of the direct memory access controller; The configuration parameter type and the configuration parameter range are determined based on the multiple sets of verification parameters.

3. The method according to claim 2, characterized in that, The step of determining the configuration parameter type and the configuration parameter range based on the plurality of verification parameter sets includes: The verification parameter type corresponding to the multiple verification parameter sets is determined as the configuration parameter type; For each configuration parameter type, if the verification parameter content corresponding to the configuration parameter type is multiple characters, then the multiple characters are mapped to multiple mapping values, and the configuration parameter range corresponding to the configuration parameter type is determined according to the multiple mapping values; If the verification parameter content corresponding to the configuration parameter type is multiple values, then the multiple values ​​are normalized to obtain a normalized range, and the configuration parameter range corresponding to the configuration parameter type is determined based on the normalized range.

4. The method according to claim 1, characterized in that, The training process of the sequence file generation model includes: Obtain the sample parameter information corresponding to the sample function of the direct memory access controller; The sample parameter information is input into the initial model to obtain a prediction sequence file. The reward value is determined based on the prediction sequence file. The model parameters of the initial model are adjusted based on the reward value until a preset convergence condition is reached. The initial model is then used as the generation model of the sequence file.

5. The method according to claim 4, characterized in that, Determining the reward value based on the predicted sequence file includes: The predicted sequence file is sent to the direct memory access controller, so that the direct memory access controller performs verification processing based on the predicted sequence file; Obtain the sample verification results corresponding to the verification processing performed based on the predicted sequence file; wherein, the sample verification results include code coverage, the number of newly added coverage of sample functions, and simulation error information; The reward value is determined based on the code coverage rate, the number of new coverage items, and the simulation error information; wherein the code coverage rate and the reward value are positively correlated, and the number of new coverage items and the reward value are also positively correlated.

6. The method according to claim 4, characterized in that, The step of adjusting the model parameters of the initial model according to the reward value until a preset convergence condition is met, and then using the initial model as the sequence file to generate the model, includes: The model parameters of the initial model in the current training round are adjusted based on the reward value to obtain the initial model for the next training round. If, after a predetermined number of consecutive training rounds, the first sample validation result and the second sample validation result satisfy the predetermined adjustment conditions, the sample parameter information is updated according to the adjustment parameters. The reward value is then determined based on the updated sample parameter information. This process continues until the predetermined convergence condition is met, at which point the initial model is used as the sequence file to generate the model. Herein, the first sample validation result is the sample validation result of the initial model in the current training round, and the second sample validation result is the sample validation result of the initial model in the next training round. The adjustment parameters include at least one of error injection parameters and multi-channel concurrency parameters.

7. The method according to claim 1, characterized in that, The target verification result includes the verification result of the first function that has been verified among the functions to be verified, and the method further includes: Determine the second function; wherein the second function is any function other than the first function among the functions to be verified; Obtain the second set of verification parameters corresponding to the second function, input the second set of verification parameters into the sequence file generation model, and obtain the supplementary sequence file output by the sequence file generation model; The supplementary sequence file is sent to the direct memory access controller, so that the direct memory access controller performs verification processing based on the supplementary sequence file; Obtain a comprehensive verification result; wherein the comprehensive verification result corresponds to the verification process performed based on the supplementary sequence file and the verification process performed based on the verification sequence file.

8. A verification device for a direct memory access controller, characterized in that, include: The first acquisition module is used to acquire configuration parameter information corresponding to the function to be verified of the direct memory access controller; wherein, the configuration parameter information includes configuration parameter type and configuration parameter range; The generation module is used to input the configuration parameter information into the sequence file generation model to obtain the verification sequence file output by the sequence file generation model; The verification module is used to send the verification sequence file to the direct memory access controller, so that the direct memory access controller performs verification processing according to the verification sequence file; The second acquisition module is used to acquire the target verification result corresponding to the verification process performed according to the verification sequence file.

9. An electronic device, characterized in that, include: processor; Memory, used to store executable instructions; The processor is configured to read the executable instructions from the memory and execute the executable instructions to implement the method of any one of claims 1-7.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, The storage medium stores a computer program that, when executed by a processor, causes the processor to implement the method described in any one of claims 1-7.

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