A method and system for calculating the angle and grid coordinates of a large-size chip array

Abstract

This invention relates to a method and system for calculating the angle and grid coordinates of a large-size chip array. The method includes: obtaining the connection relationship between adjacent lines based on the pixel coordinates of each chip, and performing main direction identification and cyclic angle calculation using a histogram to obtain the cyclic angle and average distance of the chip array; constructing two coordinate vectors of the chip array based on the cyclic angle and average distance, and obtaining the array angle of the chip array based on the proximity of the coordinate vectors to 90 degrees; constructing preliminary grid coordinates for each chip based on the coordinate direction vectors, and performing block processing on the chip array; converting the local grid coordinates of all chips into chip array grid coordinates based on the local grid coordinates of the chips within the chip block, combined with the coordinate offset relationship between the chip block and the reference block. This invention can stably and noise-resistantly calculate the chip array angle, and effectively avoids coordinate drift of large-size wafers through block processing, achieving accurate chip grid coordinate positioning.

Description

Technical Field

[0001] This invention relates to the field of chip inspection technology, and in particular to a method and system for calculating the angles and grid coordinates of a large-size chip array. Background Technology

[0002] In the semiconductor manufacturing process, a large number of chips are arranged in an array structure on a wafer. For example, when the number of chips in the array is greater than 10,000, that is, the array is greater than 100×100. In order to select chips that meet the quality requirements, automated optical inspection (AOI) technology is usually used to inspect the chips. This technology uses optical principles to automatically identify appearance abnormalities such as scratches, contamination, and defects on the chip surface.

[0003] In AOI inspection, the entire wafer is first photographed using a low-magnification lens to identify its orientation and position coordinates. Then, based on the given chip coordinates, images of each chip are acquired using a high-magnification lens, either row-wise or column-wise, and inspected one by one. This process of calculating the image coordinates of each chip relative to the overall angle is called chip pre-scanning.

[0004] In existing technologies, the minimum bounding rectangle of the chip array is calculated, and the rotation angle of the rectangle is used to obtain the deflection angle of the chip array. Simultaneously, the reference distance between the rows and columns of the chips is calculated, and the coordinates of each chip are obtained by calculating row by row and column by column based on the real-time updated distance. However, the existing methods have the following shortcomings: First, the method of calculating the chip array angle based on the rotation angle of the minimum bounding rectangle is only affected by the position of the outermost chip, and the chip information inside the array is not utilized. Therefore, when there are scattered noisy chips (such as abnormal contours formed by damage or artifacts) around the chip array, the minimum bounding rectangle will deviate from the actual array direction, resulting in a significant deviation in the angle calculation.

[0005] Secondly, the coordinate calculation method based on neighborhood expansion (i.e., recursively calculating the coordinates of subsequent chips by using the coordinates of adjacent chips) is highly dependent on the coordinate accuracy of each chip along the way. Once the coordinates of a chip are incorrect, the error will propagate along the expansion path, affecting the coordinate calculation results of all subsequent chips and causing large-area coordinate drift.

[0006] Therefore, those skilled in the art urgently need a method for calculating the angle and grid coordinates of large-size chip arrays to stably calculate the chip array angles, effectively suppress the influence of external noise on the angle calculation, and avoid the propagation and accumulation of coordinate errors, so as to accurately obtain the grid coordinates of each chip in a large-size chip array. Summary of the Invention

[0007] (a) Technical problems to be solved In view of the above-mentioned shortcomings and deficiencies of the prior art, the present invention provides a method and system for calculating the angle and grid coordinates of a large-size chip array, which solves the technical problems of array angle calculation deviation caused by peripheral noise chips and coordinate drift of large-size chip arrays caused by coordinate error propagation in the prior art.

[0008] (II) Technical Solution To achieve the above objectives, the main technical solutions adopted by the present invention include: In a first aspect, embodiments of the present invention provide a method for calculating the angle and grid coordinates of a large-size chip array, including: Extract the pixel coordinates of each chip from the input wafer image; The connection relationship between each chip and its neighboring chips is obtained based on the pixel coordinates. The main direction is identified and the cyclic angle is calculated by using a preset chip angle histogram. The mean cyclic angle and mean distance of the chip array in the two main directions are obtained. Based on the mean of the cyclic angle and the mean of the distance, two coordinate direction vectors of the chip array are constructed, and the array angle of the chip array is obtained according to the degree of proximity of the coordinate direction vectors to 90 degrees. Based on the coordinate direction vector and the preset global coordinate origin, the preliminary grid coordinates of each chip are constructed, and the chip array is divided into blocks according to the preliminary grid coordinates to obtain several independent chip blocks. Based on the preliminary grid coordinates, the local grid coordinates of the chip in the corresponding chip block are obtained. Then, combined with the coordinate offset relationship between the chip block and the preset reference block, the local grid coordinates of all chips are converted into chip array grid coordinates under the global coordinate origin.

[0009] Optionally, extracting the pixel coordinates of each chip from the input wafer image includes: The input wafer image with a chip array larger than 100×100 is binarized, and the initial binarized image is subjected to closing and opening operations to obtain the optimal binarized image. Connectivity analysis is performed on the optimal binarized image to extract the contour of each chip; Draw the smallest bounding rectangle on the outline of the chip, and use the center point of the bounding rectangle as the pixel coordinates of the current chip.

[0010] Optionally, the connection relationship between each chip and its adjacent chips is obtained based on pixel coordinates, and the main direction is identified and the cyclic angle is calculated using a preset chip angle histogram. The mean cyclic angle and mean distance of the chip array in the two main directions are obtained, including: A neighboring chip query structure is constructed for each chip based on pixel coordinates, so as to query the adjacent chips of the current chip based on the pixel coordinates of each chip; Based on the pixel coordinates of each chip and its neighboring chips, the distance between the connecting lines is obtained, and the angle between the chip and its neighboring chips is calculated using the atan2 function. A chip angle histogram is established based on the angle between the chip and adjacent chips, and two peak angles are obtained from the chip angle histogram; In the chip angle histogram, the average of the angles whose cyclic angle difference with the peak angle is within 2 degrees is calculated to obtain the average of the two cyclic angles. The average distances of the lines connecting the angles whose cyclic angle difference with the peak angle is within 2 degrees are calculated to obtain two average distances. The two peak angles correspond to the two main directions of the chip array.

[0011] Optionally, in the chip angle histogram, the average value of angles whose cyclic angle difference from the peak angle is within 2 degrees is calculated to obtain the average cyclic angle, which includes: Convert all angles to be averaged into radians; The sum of the sine and cosine values ​​of all radian values ​​is obtained and denoted as the sum sine and sum cosine, respectively. The average radian is calculated based on the sum of the sine and cosine, and the resulting average radian is converted into an angle value, which is then output as the average value of the cyclic angle.

[0012] Optionally, based on the mean of the cyclic angle and the mean of the distance, two coordinate direction vectors of the chip array are constructed, and the array angle of the chip array is obtained according to the degree of proximity of the coordinate direction vectors to 90 degrees. Based on the average of two cyclic angles and the average of two distances, construct two coordinate direction vectors; The difference between the two mean cyclic angles and 90 degrees is calculated. The coordinate direction vector corresponding to the mean cyclic angle with the smaller difference is selected as the column coordinate direction vector of the chip array, and the coordinate direction vector corresponding to the mean cyclic angle is selected as the row coordinate direction vector. Subtract 90 degrees from the mean of the cyclic angles corresponding to the column coordinate direction vectors, and output the difference angle as the array angle of the chip array.

[0013] Optionally, based on the coordinate direction vector and a preset global coordinate origin, preliminary grid coordinates for each chip are constructed, and the chip array is divided into blocks according to the preliminary grid coordinates to obtain several independent chip blocks, including: Based on the center position of the chip array, the chip closest to the center position is selected as the global coordinate origin, and the coordinate direction vector is used as the direction basis vector to establish a global coordinate system; Based on the pixel coordinates of each chip, the coordinate difference of each chip relative to the global coordinate origin is obtained, and floating-point coordinates are projected based on the difference to obtain the floating-point coordinates of each chip. The floating-point coordinates of each chip are rounded and double-checked to obtain the preliminary grid coordinates of each chip; Based on the row and column indices of the initial grid coordinates, the chip array is divided into multiple rectangular regions according to the preset row and column intervals. All chips within each rectangular region constitute a chip block, and different chip blocks do not overlap and are independent of each other.

[0014] Optionally, the floating-point coordinates of each chip are rounded and subjected to secondary verification to obtain the preliminary grid coordinates of each chip, including: The floating-point coordinates of each chip are rounded down to obtain the integer grid coordinates of that chip; Obtain the difference between the floating-point coordinates and the integer grid coordinates of each chip. If the difference is less than a preset threshold, use the integer grid coordinates as the initial grid coordinates of the current chip and assign the current chip to the preset coordinate set. If the difference is greater than or equal to a preset threshold, the chip closest to the current chip is selected from the coordinate set as a temporary origin. Based on this temporary origin and the coordinate direction vector, the integer grid coordinates of the current chip are recalculated to obtain the preliminary grid coordinates of the current chip.

[0015] Optionally, based on the row and column indices of the initial grid coordinates, the chip array is divided into multiple rectangular regions according to preset row and column intervals, including: Based on the row index in the initial grid coordinates of each chip, all chips are grouped by row, and rows with fewer chips than a preset threshold number of chips in a row are filtered out. Based on the total number of rows of chips remaining after filtering and the preset row block size parameters, the chip array is divided into several row blocks along the row direction; Within each row block, based on the column index distribution of the chips in that row block and the preset column block size parameters, the current row block is divided into several column blocks along the column direction; Each column block covers a rectangular area as a chip block, and all chips within that rectangular area constitute a chip block. Different chip blocks do not overlap and are independent of each other.

[0016] Optionally, based on the preliminary grid coordinates, the local grid coordinates of the chip within the corresponding chip block are obtained. Then, combined with the coordinate offset relationship between the chip block and the preset reference block, the local grid coordinates of all chips are converted into chip array grid coordinates at the global coordinate origin, including: Based on the coordinate direction vector, a local coordinate system is established for each chip block with the central chip as the local coordinate origin. Combined with the preliminary grid coordinates of the chips within the chip block, the local grid coordinates of the chips in the corresponding local coordinate system are obtained. Based on the local coordinate origin of the chip block, the nearest adjacent chip block is selected, and the chip block with the fewest row blocks and / or column blocks is selected from the adjacent chip blocks as the reference block, and the local coordinate system of the reference block is determined as the reference coordinate system. Select at least one chip point in the chip block that is closest to the local coordinate origin of the reference block, and calculate the coordinate offset of the current chip block relative to the reference block by obtaining the local grid coordinates of the chip point in the current chip block and the reference grid coordinates in the reference coordinate system. Based on the coordinate offset, the local grid coordinates of each chip within the current chip block are converted into reference grid coordinates in the reference block coordinate system; Based on the transformation relationship between the local coordinate origin and the global coordinate origin of the reference block, the reference grid coordinates of each chip are converted into global grid coordinates; Based on the minimum row index and minimum column index of the global grid coordinates of all chips, the minimum index value is subtracted from the global grid coordinates of each chip to obtain the image grid coordinates of the chip array.

[0017] Secondly, embodiments of the present invention provide a system for calculating the angle and grid coordinates of a large-size chip array, comprising: The pixel coordinate extraction module is used to extract the pixel coordinates of each chip from the input wafer image; The orientation parameter calculation module is used to obtain the connection relationship between each chip and its neighboring chips based on pixel coordinates, and to identify the main orientation and calculate the cyclic angle through a preset chip angle histogram, so as to obtain the mean cyclic angle and mean distance of the chip array in the two main orientations. The array angle calculation module is used to construct two coordinate direction vectors of the chip array based on the average cyclic angle and the average distance, and to obtain the array angle of the chip array based on how close the coordinate direction vectors are to 90 degrees. The preliminary mesh and block segmentation module is used to construct the preliminary mesh coordinates of each chip based on the coordinate direction vector and the preset global coordinate origin, and to segment the chip array according to the preliminary mesh coordinates to obtain several independent chip blocks. The global coordinate transformation module is used to obtain the local grid coordinates of the chip in the corresponding chip block based on the preliminary grid coordinates, and then combine the coordinate offset relationship between the chip block and the preset reference block to convert the local grid coordinates of all chips into chip array grid coordinates under the global coordinate origin.

[0018] (III) Beneficial Effects The beneficial effects of this invention are as follows: The method for calculating the angle and grid coordinates of a large-size chip array, based on histogram statistics of the connection angles and distances of all adjacent chips, and extracting two main directions through cyclic angle differences and cyclic angle averages, effectively eliminates interference from peripheral noisy chips. Therefore, compared with existing technologies that rely solely on the minimum bounding rectangle or point-by-point neighborhood expansion, it can stably and accurately obtain the deflection angle and two direction vectors of the chip array, solving the problem of angle calculation deviation caused by noisy chips. At the same time, it also adopts a block-based processing method to divide the large-size array into multiple small regions, calculate the local grid coordinates separately, and then perform coordinate offset fusion based on the reference block. This can effectively suppress the long-distance propagation of coordinate errors and avoid the coordinate drift phenomenon of distant chips in large-size wafers, ultimately achieving the technical effect of accurately obtaining the image grid coordinates of each chip in the large-size chip array. Attached Figure Description

[0019] Figure 1 This invention provides a method for calculating the angle and grid coordinates of a large-size chip array according to an embodiment of the present invention. Figure 2 This is a schematic diagram of the segmentation of a wafer chip array according to an embodiment of the present invention; Figure 3 This is a schematic diagram illustrating the conversion of local grid coordinates of chips in a chip block into array image grid coordinates, as provided in an embodiment of the present invention. Detailed Implementation

[0020] To better explain and facilitate understanding of the present invention, the present invention will be described in detail below with reference to the accompanying drawings and specific embodiments.

[0021] refer to Figures 1 to 3 As shown in the embodiment of the present invention, a method for calculating the angle and grid coordinates of a large-size chip array includes: extracting the pixel coordinates of each chip from an input wafer image; obtaining the connection relationship between each chip and adjacent chips based on the pixel coordinates, and performing principal direction identification and cyclic angle calculation through a preset chip angle histogram to obtain the mean cyclic angle and mean distance of the chip array in the two principal directions; constructing two coordinate direction vectors of the chip array based on the mean cyclic angle and mean distance, and obtaining the array angle of the chip array based on the closeness of the coordinate direction vectors to 90 degrees; constructing preliminary grid coordinates of each chip based on the coordinate direction vectors and a preset global coordinate origin, and dividing the chip array into blocks based on the preliminary grid coordinates to obtain several independent chip blocks; obtaining the local grid coordinates of the chip in the corresponding chip block based on the preliminary grid coordinates, and then converting the local grid coordinates of all chips into chip array grid coordinates under the global coordinate origin by combining the coordinate offset relationship between the chip block and the preset reference block.

[0022] This embodiment employs histogram statistics based on the connection angles and distances of all adjacent chips, and extracts two main directions using the cyclic angle difference and the mean of the cyclic angle. This effectively eliminates interference from peripheral noisy chips. Therefore, compared to existing technologies that rely solely on the minimum bounding rectangle or point-by-point neighborhood expansion, it can stably and accurately obtain the deflection angle and two direction vectors of the chip array, solving the problem of angle calculation deviation caused by noisy chips. Furthermore, this embodiment divides the large-size array into multiple small regions through block processing, calculates the local grid coordinates separately, and then performs coordinate offset fusion based on the reference block. This effectively suppresses the long-distance propagation of coordinate errors and avoids coordinate drift of distant chips in large-size wafers, ultimately achieving the technical effect of accurately obtaining the image grid coordinates of each chip in the large-size chip array.

[0023] To better understand the above technical solutions, exemplary embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present invention are shown in the drawings, it should be understood that the present invention can be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that the present invention can be understood more clearly and thoroughly, and that the scope of the present invention can be fully conveyed to those skilled in the art.

[0024] Specifically, refer to Figure 1 As shown, the method for calculating the angle and grid coordinates of a large-size chip array proposed in this embodiment may include the following steps S100 to S500: S100: Extract the pixel coordinates of each chip from the input wafer image.

[0025] In this embodiment, step S100 may include the following sub-steps S110 to S130: S110. Binarize the input wafer image of the chip array larger than 100×100, and perform closing and opening operations on the obtained initial binarized image to obtain the optimal binarized image.

[0026] Furthermore, the input wafer image is binarized to obtain a binary image. Then, the binary image is subjected to closing and opening operations to repair holes and remove burrs, resulting in the optimal binarized image.

[0027] S120. Perform connected component analysis on the optimal binarized image to extract the contour of each chip.

[0028] S130. Draw the smallest bounding rectangle on the outline of the chip, and use the center point of the bounding rectangle as the pixel coordinates of the current chip.

[0029] Furthermore, after obtaining candidate contours through contour lookup, contours are filtered according to a preset area threshold range (minimum area threshold and maximum area threshold), retaining only contours within this range; then, the minimum bounding rectangle of each retained contour is calculated, and the center point of the rectangle is used as the pixel position of the chip.

[0030] S200: Obtain the connection relationship between each chip and its neighboring chips based on pixel coordinates, and perform main direction identification and cyclic angle calculation through a preset chip angle histogram to obtain the average cyclic angle and average distance of the chip array in the two main directions.

[0031] In this embodiment, the pixel coordinates of all chips are stored in an adjacent chip query structure for quick retrieval of neighboring chips around each chip. Based on this, the distance and direction angle between each chip and its neighboring chips are calculated, and the angle information is statistically analyzed using a histogram. To address the angle boundary issues near 0° and 180°, this embodiment introduces a method for calculating the cyclic angle difference and the cyclic angle mean. Based on the peak angle in the histogram and the angle data within its neighborhood, angle deviations caused by noise or abnormal chips are effectively eliminated, thereby obtaining clean and reliable angle and distance data for subsequent calculation of coordinate direction vectors and array angles. Specifically, step S200 may include the following sub-steps S210 to S250: S210. Construct an adjacent chip query structure for each chip based on pixel coordinates, so as to query the adjacent chips of the current chip based on the pixel coordinates of each chip.

[0032] Furthermore, for the large number of chip pixel coordinates input from step S100, in order to quickly find them, an adjacent chip query structure is first constructed, and then for each chip pixel coordinate, the five coordinates closest to it are queried. The first one is the chip itself, and the remaining four are the four chip pixel coordinates around it.

[0033] S220. Based on the pixel coordinates of each chip and its neighboring chips, the distance between the connecting lines is obtained, and the angle between the chip and its neighboring chips is calculated using the atan2 function.

[0034] Furthermore, the coordinate differences between the chip and the lines connecting it to its four adjacent chips are calculated, and the angle is calculated using the atan2 function. If the angle is less than 0 degrees, 180 degrees are added to the angle to obtain the angle angle, thus controlling all angles within the range of [0°, 180°]. Then, the distance dis between adjacent chips is calculated based on the coordinate differences. For chip arrays without rotation angles, most angles are around 90 degrees, 0 degrees, or 180 degrees. The 90-degree angle is the angle between the chip and its vertically adjacent chip, while the 0-degree and 180-degree angles are the angles formed by the chip and its horizontally adjacent chip. S230. Establish a chip angle histogram based on the angle between the chip and adjacent chips, and obtain two peak angles from the chip angle histogram.

[0035] Furthermore, for all angles, a chip angle histogram is constructed, and then the histogram bars are sorted in descending order based on their heights. The angle corresponding to the largest bar in the histogram is the first peak angle, anglePeak1. A search is then performed within the sorted bar bins. When the difference between the angle corresponding to the bar bin and the cyclic angle in anglePeak1 is greater than 60 degrees, this angle is recorded as the second peak angle, anglePeak2. The method for calculating the cyclic angle difference is as follows: ; In the formula, angle1 and angle2 are two angles in the range [0°, 180°], and deltaAngle is the cyclic angle difference between these two angles. Furthermore, the formula shows that the cyclic angle difference between 1 degree and 179 degrees is 2 degrees.

[0036] It is worth mentioning that the two peak angles correspond to the two main directions of the chip array.

[0037] S240. In the chip angle histogram, the average of the angles whose cyclic angle difference with the peak angle is within 2 degrees is calculated to obtain the average of the two cyclic angles.

[0038] Further, in the chip angle histogram, angles with a loop angle difference of less than 2 degrees from anglePeak1 are counted, and the average loop angle is calculated to obtain avgAnglePeak1. Similarly, angles with a loop angle difference of less than 2 degrees from anglePeak2 are counted, and the average loop angle is calculated to obtain avgAnglePeak2. The calculation of the average loop angle may include the following sub-steps S241 to S243: S241. Convert all angles to be averaged into radians (rad) respectively.

[0039] S242. Obtain the sum of the sine and cosine values ​​of all radian values, and denot them as the sum sine and sum cosine, respectively.

[0040] To further explain, the sum of sin(2·rad) for all angles is denoted as sumSin, and the sum of cos(2·rad) is denoted as sumCos. Here, sin(·) and cos(·) represent the sine and cosine functions, respectively.

[0041] S243. Calculate the average radian based on the sum of the sine and cosine, and convert the obtained average radian into an angle value, so as to output the angle value as the average value of the cyclic angle.

[0042] To further explain, we use sumSin and sumCos to calculate the average radian, meanRad. The formula is: meanRad = 0.5·atan2(sumSin,sumCos). Furthermore, when converting the average radian to degrees, if the angle is less than 0, we add 180 degrees to the angle to obtain the mean of the cyclic angle.

[0043] S250. Calculate the average distance of the lines connecting the angles whose cyclic angle difference with the peak angle is within 2 degrees, and obtain two average distance values.

[0044] Furthermore, in the chip angle histogram, angles with a cyclic angle difference of less than 2 degrees from anglePeak1 are counted, and the corresponding distances are calculated. The average of these distances is then calculated and denoted as avgPitch1. Similarly, in the chip angle histogram, angles with a cyclic angle difference of less than 2 degrees from anglePeak2 are counted, and the corresponding distances are calculated. The average of these distances is then calculated and denoted as avgPitch2.

[0045] S300. Based on the average cyclic angle and the average distance, construct two coordinate direction vectors of the chip array, and obtain the array angle of the chip array based on the degree of proximity of the coordinate direction vectors to 90 degrees.

[0046] In this embodiment, step S300 may include the following sub-steps S310 to S330: S310. Based on the average of the two cyclic angles and the average of the two distances, construct two coordinate direction vectors.

[0047] Furthermore, the formulas for calculating the coordinate direction vectors v1 and v2 are as follows: v1=avgPitch1·(cos(avgAnglePeak1),sin(avgAnglePeak1)); v2=avgPitch2·(cos(avgAnglePeak2), sin(avgAnglePeak2)).

[0048] S320. Calculate the difference between the two mean cyclic angles and 90 degrees respectively. Select the coordinate direction vector corresponding to the mean cyclic angle with the smaller difference as the column coordinate direction vector of the chip array, and the coordinate direction vector corresponding to the mean cyclic angle as the row coordinate direction vector.

[0049] S330. Subtract 90 degrees from the mean of the cyclic angles corresponding to the column coordinate direction vectors, and output the difference angle as the array angle of the chip array.

[0050] Furthermore, if avgAnglePeak1 is closer to 90 degrees, meaning the difference between avgAnglePeak1 and 90 degrees is smaller than the difference between avgAnglePeak2 and 90 degrees, then the array vector vy in the column direction (y) is v1, and the array angle chipAngle is avgAnglePeak1 - 90. Next, it is determined whether avgAnglePeak2 is greater than 90 degrees. If it is not greater than 90 degrees, the array vector vx in the row direction (x) is v2; if it is greater than 90 degrees, then vx = -v2. If avgAnglePeak2 is closer to 90 degrees, then the array vector vy in the column direction (y) is v2, and the array angle chipAngle is avgAnglePeak2 - 90. Next, it is determined whether avgAnglePeak1 is greater than 90 degrees. If it is not greater than 90 degrees, then the array vector vx in the row direction (x) is v1; if it is greater than 90 degrees, then vx = -v1.

[0051] It is worth mentioning that the y-direction vector vy of the chip array points downwards, while the x-direction vector vx points to the right. The array angle of the chip array is the rotation angle of the chip array relative to the x-axis of the image.

[0052] S400: Based on the coordinate direction vector and the preset global coordinate origin, construct the preliminary grid coordinates of each chip, and divide the chip array into blocks according to the preliminary grid coordinates to obtain several independent chip blocks.

[0053] In this embodiment, since the row and column directions in the actual chip array may not be perfectly perpendicular, this embodiment finds the origin of the coordinate system near the center of the chip array, and then uses the two vectors of the array as the x-axis and y-axis to calculate the floating-point coordinates of each chip, thereby obtaining the integer grid coordinates. Compared with the traditional method using a completely orthogonal coordinate system, this method more closely reflects the actual physical arrangement of the chips. Simultaneously, based on the difference between the floating-point coordinates and the integer coordinates, this embodiment introduces a secondary verification mechanism for points where coordinate offsets may occur. This mechanism performs secondary calculations on coordinate points that may have deviations, effectively reducing the probability of coordinate calculation errors. Specifically, step S400 may include the following sub-steps S410 to S440: S410. Based on the center position of the chip array, select the chip closest to the center position as the global coordinate origin, and use the coordinate direction vector as the direction basis vector to establish a global coordinate system.

[0054] S420. Based on the pixel coordinates of each chip, obtain the coordinate difference of each chip relative to the global coordinate origin, and perform floating-point coordinate projection based on the difference to obtain the floating-point coordinates of each chip.

[0055] Furthermore, the coordinate differences dx and dy between each chip pixel coordinate p(x,y) and the global coordinate origin origin(x,y) are: dx = p(x) - origin(x); dy = p(y) - origin(y); Floating-point coordinates (f) i ,f j ): f i =(dx·vy y -dy·vy x ) / (vx x ·vy y -vx y ·vy x ); f j =(dy·vx x -dx·vx y ) / (vx x ·vy y -vx y ·vy x ); In the formula, vx x Let vx be the x-axis component of the vector vx. y Let vy be the y-axis component of vector vx. x Let vy be the x-axis component of vector vy. y Let y be the y-axis component of vector vy.

[0056] S430: Round and perform secondary verification on the floating-point coordinates of each chip to obtain the preliminary grid coordinates of each chip.

[0057] Further, step S430 may include the following sub-steps S431 to S433: S431. Round the floating-point coordinates of each chip to obtain the integer grid coordinates of that chip.

[0058] To further explain, the floating-point coordinates of the chip are rounded to the nearest integer to obtain the integer coordinates (i, j): i = round(f i j=round(f) j ), round(·) is the floor function.

[0059] S432. Obtain the difference between the floating-point coordinates and the integer grid coordinates of each chip. If the difference is less than a preset threshold, use the integer grid coordinates as the initial grid coordinates of the current chip and assign the current chip to the preset coordinate set.

[0060] For example, if the absolute value of the difference between the floating-point coordinates and the integer coordinates is less than 0.3, then the coordinate calculation of this point is considered accurate, the coordinate calculation is finished, and the coordinates of these points are placed in a set.

[0061] S433. If the difference is greater than or equal to the preset threshold, select the chip closest to the current chip from the coordinate set as the temporary origin, and recalculate the integer grid coordinates of the current chip based on the temporary origin and the coordinate direction vector to obtain the preliminary grid coordinates of the current chip.

[0062] For example, if the value is greater than 0.3, the coordinates may be incorrect and require further evaluation. For these points, this embodiment selects the closest point from the set of points with accurate coordinates to replace the global coordinate origin, with the coordinates of the origin being (i0, j0). The integer coordinates (i1, j1) of this point are then recalculated using the previous method. Therefore, the final grid coordinates of this point are: i = i0 + i1, j = j0 + j1.

[0063] S440. Based on the row and column indices of the initial grid coordinates, the chip array is divided into multiple rectangular regions according to the preset row and column intervals. All chips in each rectangular region constitute a chip block. Different chip blocks do not overlap and are independent of each other.

[0064] Furthermore, for small-sized wafers, the preliminary grid coordinates obtained in the aforementioned steps are sufficient. However, for large-sized wafers, due to the large number of chips, chips far from the global coordinate origin may experience coordinate shifts or errors due to the accumulation of small deviations in angle and distance. Therefore, this embodiment adopts a block-based strategy: first, the coordinates of each local chip block are solved, and then the global grid coordinates are obtained through coordinate fusion. Specifically, the chip array block-based step S440 may include the following sub-steps S441 to S444: S441. Based on the row index in the initial grid coordinates of each chip, group all chips by row and filter out rows with fewer chips than the preset threshold for the number of chips in a row.

[0065] For example, S442. Based on the total number of rows of chips remaining after filtering and the preset row block size parameters, the chip array is divided into several row blocks along the row direction.

[0066] S443. Within each row block, based on the column index distribution of the chips in that row block and the preset column block size parameters, the current row block is divided into several column blocks along the column direction.

[0067] S444. The rectangular area covered by each column block is taken as a chip block. All chips within the rectangular area constitute a chip block. Different chip blocks do not overlap and are independent of each other.

[0068] For example, firstly, all chips are grouped by row based on the initial grid coordinates. If a row has fewer than 3 chips, it is discarded as noise. Similarly, after grouping by column, columns with fewer than 3 chips are discarded as noise. Then, a block size parameter (e.g., 30 or 20) is set, dividing the chip array into approximately 30×30 or 20×20 blocks. Specifically, the total number of rows in the chip array is first determined based on the initial grid coordinates, and then the chip array is divided into multiple row blocks along the row direction according to the block size parameter. Within each row block, the number of columns covered by that row block is calculated, and then further divided into multiple column blocks along the column direction according to the block size parameter, thus obtaining individual chip blocks. Through this division method, the number of blocks within each row block adaptively changes with the actual shape of the chip array, keeping the number of chips within each chip block roughly balanced. (Reference) Figure 2 As shown, since the angle of the chip array has been calculated in step S200 and the preliminary grid coordinates of the chip have been obtained in step S300, the above block division method can still be applied normally even if the chip array has a certain rotation angle.

[0069] S500: Based on the preliminary grid coordinates, obtain the local grid coordinates of the chip in the corresponding chip block, and then combine the coordinate offset relationship between the chip block and the preset reference block to convert the local grid coordinates of all chips into chip array grid coordinates under the global coordinate origin.

[0070] In this embodiment, local grid coordinates are first calculated independently within each chip block. Then, a reference block is found for each chip block. Based on the coordinate offset relationship with the reference block, the local coordinates are converted into global coordinates, and finally, unified array image grid coordinates are synthesized. This block-based strategy divides the large-size wafer into multiple small regions for separate processing, and then fuses them block by block using the reference block, effectively avoiding coordinate offset problems caused by the accumulation of long-distance coordinate errors. Specifically, step S500 may include the following sub-steps S510 to S560: S510. Based on the coordinate direction vector, establish a local coordinate system for each chip block with the central chip of the chip block as the local coordinate origin, and combine it with the preliminary grid coordinates of the chips in the chip block to obtain the local grid coordinates of the chips in the corresponding local coordinate system.

[0071] S520. Based on the local coordinate origin of the chip block, select the nearest adjacent chip block, and from the adjacent chip block, select the chip block with the fewest row blocks and / or column blocks as the reference block, and determine the local coordinate system of the reference block as the reference coordinate system.

[0072] S530. Select at least one chip point in the chip block that is closest to the local coordinate origin of the reference block, and calculate the coordinate offset of the current chip block relative to the reference block by obtaining the local grid coordinates of the chip point in the current chip block and the reference grid coordinates in the reference coordinate system.

[0073] Further, calculate the offset (offsetX, offset) of the chip block's origin relative to the reference block's origin. Within the current chip block, select the chip point closest to the reference block's origin, denoted as nearstPt, whose grid coordinates in the current chip block are (i2, j2). Calculate the grid coordinates of nearstPt in the reference block, denoted as (i3, j3). Then, the origin coordinate offsets of the current chip block are: offsetX = i3 - i2, offsetY = j3 - j2. If using only the nearest chip point is not stable enough, multiple nearest chip points can be calculated, and the coordinate offset is calculated for each chip point, then the average is taken.

[0074] S530. Based on the coordinate offset, convert the local grid coordinates of each chip in the current chip block into reference grid coordinates in the reference block coordinate system.

[0075] Furthermore, if the local grid coordinates of a certain chip in the chip block are (cur_i, cur_j), then the reference grid coordinates (ref_i, ref_j) of that chip in the reference block coordinate system are: ref_i = offsetX + cur_i, ref_j = offsetY + cur_j.

[0076] S540. Based on the transformation relationship between the local coordinate origin and the global coordinate origin of the reference block, convert the reference grid coordinates of each chip into global grid coordinates.

[0077] Furthermore, by querying the global grid coordinates (global_refX, global_refY) of the origin of the reference block, the global grid coordinates (global_i, global_j) of the chip are: global_i = global_refX + ref_i, global_j = global_refY + ref_j.

[0078] S550: Based on the minimum row index and minimum column index of the global grid coordinates of all chips, subtract the minimum index value from the global grid coordinates of each chip to obtain the image grid coordinates of the chip array.

[0079] Furthermore, after calculating the global grid coordinates of all chip points, the minimum value of the global grid coordinates (minX, minY) is calculated. Then the array image grid coordinates (grid_i, grid_j) of that point are: grid_i = global_i - minX, grid_j = global_j - minY. Figure 3 This diagram illustrates the conversion of each chip's coordinates to array image grid coordinates. The chip array is divided into six smaller arrays. The block enclosed by the dashed box represents the current chip block, while the block to its left is the reference block. The black origin within each block is its coordinate origin. The straight arrows show the coordinate transformation process: from the current block's grid coordinates to the reference block's grid coordinates, to the global grid coordinates, and finally to the array image grid coordinates. The pentagram chip has grid coordinates of (-2,1) in the current block, (3,1) in the reference block, (8,1) in the global grid, and (10,3) in the array image grid.

[0080] Furthermore, this embodiment also provides a system for calculating the angle and grid coordinates of a large-size chip array, including: The pixel coordinate extraction module is used to extract the pixel coordinates of each chip from the input wafer image.

[0081] The orientation parameter calculation module is used to obtain the connection relationship between each chip and its neighboring chips based on pixel coordinates, and to identify the main orientation and calculate the cyclic angle through a preset chip angle histogram, so as to obtain the mean cyclic angle and mean distance of the chip array in the two main orientations.

[0082] The array angle calculation module is used to construct two coordinate direction vectors of the chip array based on the mean of the cyclic angle and the mean of the distance, and to obtain the array angle of the chip array based on how close the coordinate direction vector is to 90 degrees.

[0083] The preliminary mesh and block segmentation module is used to construct the preliminary mesh coordinates of each chip based on the coordinate direction vector and the preset global coordinate origin, and to segment the chip array according to the preliminary mesh coordinates to obtain several independent chip blocks.

[0084] The global coordinate transformation module is used to obtain the local grid coordinates of the chip in the corresponding chip block based on the preliminary grid coordinates, and then combine the coordinate offset relationship between the chip block and the preset reference block to convert the local grid coordinates of all chips into chip array grid coordinates under the global coordinate origin.

[0085] In summary, the method and system for calculating the angle and grid coordinates of a large-size chip array provided by this invention constructs an adjacent chip query structure and uses histograms to statistically analyze the connection angles and distances between adjacent chips. It then extracts two principal direction parameters by combining the cyclic angle difference and the cyclic angle mean, effectively eliminating interference from peripheral noisy chips. This provides a stable and accurate determination of the chip array's deflection angle and two direction vectors, solving the angle calculation deviation problem caused by noise in traditional methods. Furthermore, this invention supports real-world scenarios where the two direction vectors are not perpendicular. It constructs preliminary grid coordinates through floating-point coordinate projection and secondary verification, and further employs a block-based strategy to divide the large-size array into multiple small regions. Local grid coordinates are calculated separately, and then coordinate offset fusion is performed based on a reference block. This effectively suppresses the long-distance propagation of coordinate errors and avoids coordinate drift phenomena of distant chips in large-size wafers. Therefore, this invention has significant advantages in the robustness of chip array angle calculation and the accuracy of large-size wafer grid coordinates, and can be widely applied in the field of automated optical inspection of chips.

[0086] Since the systems / devices described in the above embodiments of the present invention are systems / devices used to implement the methods of the above embodiments of the present invention, those skilled in the art can understand the specific structure and modifications of the systems / devices based on the methods described in the above embodiments of the present invention, and therefore will not be repeated here. All systems / devices used in the methods of the above embodiments of the present invention fall within the scope of protection of the present invention.

[0087] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0088] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, as well as combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions.

[0089] It should be noted that in the description of this invention, the word "a" or "an" preceding a component does not exclude the existence of multiple such components. This invention can be implemented by means of hardware comprising several different components and by means of a suitably programmed computer. The use of terms such as first, second, third, etc., is merely for convenience and does not indicate any order. These terms can be understood as part of the component names.

[0090] Furthermore, it should be noted that in the description of this specification, the terms "one embodiment," "some embodiments," "embodiment," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Furthermore, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0091] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning of the basic inventive concept, can make other changes and modifications to these embodiments.

[0092] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from the spirit and scope of the invention.

Claims

1. A method for calculating the angle and grid coordinates of a large-size chip array, characterized in that, include: Extract the pixel coordinates of each chip from the input wafer image; The connection relationship between each chip and its neighboring chips is obtained based on the pixel coordinates. The main direction is identified and the cyclic angle is calculated by using a preset chip angle histogram. The mean cyclic angle and mean distance of the chip array in the two main directions are obtained. Based on the mean of the cyclic angle and the mean of the distance, two coordinate direction vectors of the chip array are constructed, and the array angle of the chip array is obtained according to the degree of proximity of the coordinate direction vectors to 90 degrees. Based on the coordinate direction vector and the preset global coordinate origin, the preliminary grid coordinates of each chip are constructed, and the chip array is divided into blocks according to the preliminary grid coordinates to obtain several independent chip blocks. Based on the preliminary grid coordinates, the local grid coordinates of the chip in the corresponding chip block are obtained. Then, combined with the coordinate offset relationship between the chip block and the preset reference block, the local grid coordinates of all chips are converted into chip array grid coordinates under the global coordinate origin.

2. The method as described in claim 1, characterized in that, Extracting the pixel coordinates of each chip from the input wafer image includes: The input wafer image with a chip array larger than 100×100 is binarized, and the initial binarized image is subjected to closing and opening operations to obtain the optimal binarized image. Connectivity analysis is performed on the optimal binarized image to extract the contour of each chip; Draw the smallest bounding rectangle on the outline of the chip, and use the center point of the bounding rectangle as the pixel coordinates of the current chip.

3. The method as described in claim 1, characterized in that, The connection relationship between each chip and its adjacent chips is obtained based on pixel coordinates. Then, the main direction is identified and the cyclic angle is calculated using a preset chip angle histogram. This yields the mean cyclic angle and mean distance of the chip array in the two main directions, including: A neighboring chip query structure is constructed for each chip based on pixel coordinates, so as to query the adjacent chips of the current chip based on the pixel coordinates of each chip; Based on the pixel coordinates of each chip and its neighboring chips, the distance between the connecting lines is obtained, and the angle between the chip and its neighboring chips is calculated using the atan2 function. A chip angle histogram is established based on the angle between the chip and adjacent chips, and two peak angles are obtained from the chip angle histogram; In the chip angle histogram, the average of the angles whose cyclic angle difference with the peak angle is within 2 degrees is calculated to obtain the average of the two cyclic angles. The average distances of the lines connecting the angles whose cyclic angle difference with the peak angle is within 2 degrees are calculated to obtain two average distances. The two peak angles correspond to the two main directions of the chip array.

4. The method as described in claim 3, characterized in that, In the chip angle histogram, the average value of the cyclic angles within 2 degrees of the peak angle is calculated, resulting in the following average cyclic angle values: Convert all angles to be averaged into radians; The sum of the sine and cosine values ​​of all radian values ​​is obtained and denoted as the sum sine and sum cosine, respectively. The average radian is calculated based on the sum of the sine and cosine, and the resulting average radian is converted into an angle value, which is then output as the average value of the cyclic angle.

5. The method as described in claim 3, characterized in that, Based on the mean of the cyclic angle and the mean of the distance, two coordinate direction vectors of the chip array are constructed. Then, based on the proximity of these coordinate direction vectors to 90 degrees, the array angles of the chip array are obtained, including: Based on the average of two cyclic angles and the average of two distances, construct two coordinate direction vectors; The difference between the two mean cyclic angles and 90 degrees is calculated. The coordinate direction vector corresponding to the mean cyclic angle with the smaller difference is selected as the column coordinate direction vector of the chip array, and the coordinate direction vector corresponding to the mean cyclic angle is selected as the row coordinate direction vector. Subtract 90 degrees from the mean of the cyclic angles corresponding to the column coordinate direction vectors, and output the difference angle as the array angle of the chip array.

6. The method as described in claim 1, characterized in that, Based on the coordinate direction vector and a preset global coordinate origin, the initial grid coordinates of each chip are constructed. The chip array is then divided into blocks according to these initial grid coordinates, resulting in several independent chip blocks, including: Based on the center position of the chip array, the chip closest to the center position is selected as the global coordinate origin, and the coordinate direction vector is used as the direction basis vector to establish a global coordinate system; Based on the pixel coordinates of each chip, the coordinate difference of each chip relative to the global coordinate origin is obtained, and floating-point coordinates are projected based on the difference to obtain the floating-point coordinates of each chip. The floating-point coordinates of each chip are rounded and double-checked to obtain the preliminary grid coordinates of each chip; Based on the row and column indices of the initial grid coordinates, the chip array is divided into multiple rectangular regions according to the preset row and column intervals. All chips within each rectangular region constitute a chip block, and different chip blocks do not overlap and are independent of each other.

7. The method as described in claim 6, characterized in that, The floating-point coordinates of each chip are rounded and double-checked to obtain the preliminary grid coordinates of each chip, including: The floating-point coordinates of each chip are rounded down to obtain the integer grid coordinates of that chip; Obtain the difference between the floating-point coordinates and the integer grid coordinates of each chip. If the difference is less than a preset threshold, use the integer grid coordinates as the initial grid coordinates of the current chip and assign the current chip to the preset coordinate set. If the difference is greater than or equal to a preset threshold, the chip closest to the current chip is selected from the coordinate set as a temporary origin. Based on this temporary origin and the coordinate direction vector, the integer grid coordinates of the current chip are recalculated to obtain the preliminary grid coordinates of the current chip.

8. The method as described in claim 6, characterized in that, Based on the row and column indices of the initial grid coordinates, the chip array is divided into multiple rectangular regions according to preset row and column intervals, including: Based on the row index in the initial grid coordinates of each chip, all chips are grouped by row, and rows with fewer chips than a preset threshold number of chips in a row are filtered out. Based on the total number of rows of chips remaining after filtering and the preset row block size parameters, the chip array is divided into several row blocks along the row direction; Within each row block, based on the column index distribution of the chips in that row block and the preset column block size parameters, the current row block is divided into several column blocks along the column direction; Each column block covers a rectangular area as a chip block, and all chips within that rectangular area constitute a chip block. Different chip blocks do not overlap and are independent of each other.

9. The method as described in claim 1, characterized in that, Based on the preliminary grid coordinates, the local grid coordinates of the chip within the corresponding chip block are obtained. Then, combined with the coordinate offset relationship between the chip block and the preset reference block, the local grid coordinates of all chips are converted into chip array grid coordinates at the global coordinate origin, including: Based on the coordinate direction vector, a local coordinate system is established for each chip block with the central chip as the local coordinate origin. Combined with the preliminary grid coordinates of the chips within the chip block, the local grid coordinates of the chips in the corresponding local coordinate system are obtained. Based on the local coordinate origin of the chip block, the nearest adjacent chip block is selected, and the chip block with the fewest row blocks and / or column blocks is selected from the adjacent chip blocks as the reference block, and the local coordinate system of the reference block is determined as the reference coordinate system. Select at least one chip point in the chip block that is closest to the local coordinate origin of the reference block, and calculate the coordinate offset of the current chip block relative to the reference block by obtaining the local grid coordinates of the chip point in the current chip block and the reference grid coordinates in the reference coordinate system. Based on the coordinate offset, the local grid coordinates of each chip within the current chip block are converted into reference grid coordinates in the reference block coordinate system; Based on the transformation relationship between the local coordinate origin and the global coordinate origin of the reference block, the reference grid coordinates of each chip are converted into global grid coordinates; Based on the minimum row index and minimum column index of the global grid coordinates of all chips, the minimum index value is subtracted from the global grid coordinates of each chip to obtain the image grid coordinates of the chip array.

10. A system for calculating the angle and grid coordinates of a large-size chip array, characterized in that, include: The pixel coordinate extraction module is used to extract the pixel coordinates of each chip from the input wafer image; The orientation parameter calculation module is used to obtain the connection relationship between each chip and its neighboring chips based on pixel coordinates, and to identify the main orientation and calculate the cyclic angle through a preset chip angle histogram, so as to obtain the mean cyclic angle and mean distance of the chip array in the two main orientations. The array angle calculation module is used to construct two coordinate direction vectors of the chip array based on the average cyclic angle and the average distance, and to obtain the array angle of the chip array based on how close the coordinate direction vectors are to 90 degrees. The preliminary mesh and block segmentation module is used to construct the preliminary mesh coordinates of each chip based on the coordinate direction vector and the preset global coordinate origin, and to segment the chip array according to the preliminary mesh coordinates to obtain several independent chip blocks. The global coordinate transformation module is used to obtain the local grid coordinates of the chip in the corresponding chip block based on the preliminary grid coordinates, and then combine the coordinate offset relationship between the chip block and the preset reference block to convert the local grid coordinates of all chips into chip array grid coordinates under the global coordinate origin.

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