An in-situ method for fabricating nanotube array supercapacitor electrodes integrated on a chip

Abstract

This invention relates to the field of micro / nanomaterial fabrication and micro energy storage device technology. The invention discloses an in-situ fabrication method for on-chip integrated nanotube array supercapacitor electrodes, comprising the following steps: in-situ construction of an on-chip patterned template; in-situ electrochemical growth of a metal nanotube array; in-situ conversion of a metal / metal oxide composite structure; and the forming of an integrated electrode. This invention directly constructs a patterned anodic aluminum oxide template on a chip substrate with a pre-prepared patterned conductive layer (non-aluminum material) and completes material growth. The resulting nanotube array electrode and the current collector on the chip are grown in situ and integrally formed, avoiding complex material transfer and secondary bonding steps. This achieves perfect compatibility with planar microelectronic processes and can be mass-produced on 4-inch and larger wafers.

Description

Technical Field

[0001] This invention relates to the field of micro / nanomaterial fabrication and micro energy storage device technology, and particularly to an in-situ fabrication method for an on-chip integrated nanotube array supercapacitor electrode, a metal / metal oxide composite nanotube array electrode, and an on-chip integrated micro supercapacitor. Background Technology

[0002] With the rapid development of fields such as the Internet of Things, micro-sensing nodes, implantable medical devices, wearable electronics, and aerospace microsystems, the demand for miniaturized, integrated, and high-performance energy storage units is becoming increasingly urgent. Micro supercapacitors are considered one of the most promising on-chip integrated micro energy solutions due to their high power density, long cycle life, and fast charge-discharge characteristics. The performance of micro supercapacitors is highly dependent on the structure and properties of electrode materials. Among them, one-dimensional nano-ordered array materials (such as nanowire and nanotube arrays) have become a research hotspot for electrode materials due to their high specific surface area, efficient ion / electron transport paths, and good structural stability.

[0003] Currently, the fabrication of electrodes for on-chip integrated micro supercapacitors mainly faces the following technical bottlenecks: (a) Limitations of traditional slurry coating processes: Traditional electrode fabrication employs a slurry coating process, where active materials are mixed with binders and conductive agents and then coated onto the surface of the current collector. This process has several drawbacks: First, the active material and the current collector only have physical contact, resulting in high interfacial resistance and low charge transport efficiency, which affects the rate performance and cycle stability of the electrode. Second, it is difficult to achieve precise patterning and high loading at the micrometer scale, limiting the miniaturization of the device. Third, the presence of binders reduces the effective specific surface area and ion transport efficiency of the electrode. These limitations make it difficult for traditional slurry coating processes to meet the high-performance requirements of on-chip integrated micro supercapacitors for electrode materials.

[0004] (II) Preparation method of nanoarray based on anodic aluminum oxide template: The anodic aluminum oxide (AAO) template method has attracted widespread attention due to its ability to prepare highly ordered one-dimensional nanoarrays. In the existing technology, there are schemes for preparing specific patterned arrays using patterned aluminum substrates. For example, in his master's thesis, Shao Zengjun disclosed that patterned AAO templates were prepared on pre-patterned aluminum sheets by combining photolithography and constant current oxidation, and then patterned metal nanowire arrays were obtained by electrodeposition (Shao Zengjun. Preparation and application of patterned AAO templates by constant current method [D]. Qingdao University, 2009.).

[0005] However, this approach and similar technologies have fundamental limitations: First, the entire process substrate and current collector are made of aluminum itself, and the obtained nanostructure array is attached to the aluminum substrate, making it difficult to peel off and transfer; Second, aluminum is not a commonly used interconnect material in standard semiconductor processes, and its own oxide layer is insulating, and this method cannot achieve direct electrical connection and in-situ integration with patterned conductive lines such as gold and platinum prefabricated on chip substrates such as silicon and glass; the incompatibility of the process makes it impossible to use it to prepare high-performance microelectrodes integrated with microelectronic systems.

[0006] (III) The complexity of the AAO template transfer method: To address these issues, researchers attempted to transfer AAO templates onto silicon substrates. Scisco et al. reported a method for bonding thick AAO templates to silicon wafers via Al-Si eutectic bonding, and used this method to fabricate electrodes. The process flow of this method includes: first, preparing an AAO template on an aluminum wafer; then, transferring the AAO template to the silicon wafer via eutectic bonding; and finally, removing the residual aluminum layer. Although this method achieves the bonding between the AAO template and the silicon substrate, it still has the following drawbacks: the bonding process requires high temperature and high pressure conditions, resulting in a narrow process window; additional steps are needed to remove residual aluminum and the barrier layer after template transfer; and the electrical contact between the active material and the current collector depends on the bonding interface rather than in-situ growth, making it difficult to optimize the interface resistance.

[0007] Other studies have employed a template transfer combined with vacuum deposition, for example, by chemically etching away residual aluminum under the AAO template, using vacuum-deposited gold as a bonding layer to attach the AAO template to the substrate, and then removing the barrier layer by ion etching. Such methods involve multi-step transfer and etching processes, which are cumbersome, and the brittle AAO template is easily broken during the transfer process, resulting in low yield and difficulty in large-scale production.

[0008] (iv) Existing technologies have not achieved in-situ integrated integration: Existing research has also attempted to deposit other active materials in AAO templates to achieve on-chip energy storage. For example, Chinese patent CN110415988A discloses a method for preparing graphene oxide / yttrium cobalt oxide nanoarray electrode materials. This method involves electrochemically depositing graphene oxide quantum dots into the pores of an AAO template, followed by vacuum spin-coating of a yttrium cobalt oxide sol precursor, and then calcining to obtain a coaxial heterostructure nanoarray. However, this method still requires transferring the AAO template or preparing it directly on an aluminum substrate, and the electrical contact between the active material and the current collector depends on subsequent electrode preparation steps after template removal, failing to achieve true in-situ integrated processing.

[0009] In addition to the AAO template method, researchers have also explored other on-chip integration technologies. For example, Chinese patent CN101950685A uses MEMS technology to prepare SU-8 adhesive columnar arrays on the surface of a copper substrate, and then covers them with polypyrrole functional films to form three-dimensional microelectrodes. Although this method can improve the specific surface area, the size and morphology control of the columnar array are limited, and the cycling stability of polypyrrole materials is poor.

[0010] (v) Existing technologies lack sufficient ability to control nanotube structures: In terms of the structural control of nanoarrays, existing technologies mostly use direct current electrodeposition to prepare solid nanowires, which has limited ability to prepare nanotube structures. Compared with nanowires, nanotubes have double surfaces, providing higher specific surface area and shorter ion diffusion paths, making them an ideal structure for improving electrode performance. However, existing on-chip integration technologies lack effective methods for in-situ preparation of metal / metal oxide composite nanotube arrays on pre-patterned conductive current collectors on chips. How to achieve "preferential growth of metal ions on the pore walls" rather than "filling of the pore bottom" within nanopores to form hollow nanotube structures remains a technical challenge that urgently needs to be solved in this field.

[0011] (vi) Technological gaps that urgently need to be addressed in the existing technology: In summary, existing technologies have not yet solved the following key problems: how to fabricate one-dimensional ordered nanoarray electrodes with nanotube structures in situ on a non-aluminum patterned conductive current collector prefabricated on a chip using a fully compatible micro-nano fabrication process, so as to achieve the integrated integration of active materials and current collectors, thereby avoiding complex template transfer, secondary alignment and material bonding steps; this technological gap has become the core bottleneck restricting the practical application of on-chip micro supercapacitors. Summary of the Invention

[0012] The purpose of this invention is to provide an in-situ fabrication method for on-chip integrated nanotube array supercapacitor electrodes, a metal / metal oxide composite nanotube array electrode, and an on-chip integrated micro supercapacitor, so as to solve the problems mentioned in the background art.

[0013] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is: an in-situ fabrication method for electrodes of an on-chip integrated nanotube array supercapacitor, comprising the following steps: Step S1: In-situ construction of on-chip graphical template: A chip substrate is provided, on which a patterned conductive layer is formed; A metallic aluminum film is deposited on the patterned conductive layer, and the metallic aluminum film is patterned to form an aluminum structure corresponding to the pattern of the patterned conductive layer. The aluminum structure is anodized to transform it into a patterned anodized aluminum template, wherein the bottom of the anodized aluminum template is in direct contact with the patterned conductive layer. The anodized aluminum template is subjected to a hole-enlarging treatment; Step S2: In-situ electrochemical growth of metal nanotube arrays: Using the patterned conductive layer as the working electrode, an ordered array of metal nanotubes is grown in the nanopores of the anodic aluminum oxide template by electrochemical deposition, wherein the metal nanotubes are hollow structures. Step S3: In-situ transformation of the metal / metal oxide composite structure: The ordered array of metal nanotubes is subjected to oxidation treatment to form a metal oxide layer on the metal surface in situ, resulting in an ordered array of metal / metal oxide composite nanotubes. Step S4: Molding of the integrated electrode: The anodic aluminum oxide template is removed, exposing the ordered array of metal / metal oxide composite nanotubes and maintaining direct bonding with the patterned conductive layer to form an on-chip integrated electrode.

[0014] Preferably, in step S2, the electrochemical deposition method employs pulsed electrodeposition, wherein the pulse on-time Ton is 0.05-0.5s, the pulse off-time Toff is 0.1-1.0s, and the pulse deposition potential is -0.8V to -1.2V (relative to a saturated calomel electrode); by adjusting the ratio of the pulse on-time Ton to the pulse off-time Toff, the wall thickness and surface morphology of the metal nanotube are controlled.

[0015] Preferably, in step S2, the electrochemical deposition method employs constant potential deposition, with a deposition potential of -0.9V to -1.1V (relative to a saturated calomel electrode) and a deposition time of 10-30 min; by adjusting the deposition potential, the wall thickness and surface morphology of the metal nanotubes are controlled.

[0016] Preferably, the chip substrate is a silicon wafer, a glass wafer, or a polymer wafer; the material of the patterned conductive layer is gold, platinum, titanium, chromium, copper, or a combination thereof.

[0017] Preferably, the metal is at least one of nickel (Ni), iron (Fe), cobalt (Co), and manganese (Mn), or an alloy containing at least two of the above metals; the metal oxide is the corresponding oxide or composite oxide of nickel, iron, cobalt, and manganese.

[0018] Preferably, in step S1, the voltage of the anodizing is 20-60V, the temperature is 0-10℃, and the electrolyte is oxalic acid or phosphoric acid solution; the pore-expanding treatment uses phosphoric acid solution, and the pore-expanding treatment time is 5-20min.

[0019] Preferably, in step S3, the oxidation treatment is one of thermal oxidation, electrochemical oxidation, or oxygen plasma treatment; the thermal oxidation method has an oxidation temperature of 200-400℃ and an oxidation time of 0.5-4h; the electrochemical oxidation method is achieved in an alkaline electrolyte by cyclic voltammetry or constant potential oxidation.

[0020] This application also discloses an on-chip integrated metal / metal oxide composite nanotube array electrode, comprising: Chip substrate; A patterned conductive layer is formed on the chip substrate, and the material of the patterned conductive layer is a non-aluminum conductive material; Furthermore, an ordered array of metal / metal oxide composite nanotubes directly grown on the patterned conductive layer via in-situ electrochemical deposition; The ordered array of metal / metal oxide composite nanotubes consists of metal nanotubes and a metal oxide shell layer that covers the inner and outer surfaces of the metal nanotubes in situ, forming a hollow core-shell structure. The ordered array of metal / metal oxide composite nanotubes forms a metallurgical bond or ohmic contact with the patterned conductive layer, and has the same planar pattern as the patterned conductive layer.

[0021] Preferably, the wall thickness of the metal nanotube is 20-100 nm, the thickness of the metal oxide shell is 2-20 nm, and the length of the metal nanotube is 0.5-5 μm.

[0022] The present invention further provides an on-chip integrated micro supercapacitor comprising a pair of on-chip integrated metal / metal oxide composite nanotube array electrodes, wherein the pair of electrodes are arranged in an interdigitated manner on the same plane and immersed in a solid or gel electrolyte.

[0023] As can be seen from the above description of the structure of the present invention, compared with the prior art, the present invention has the following advantages: 1. This invention directly constructs a patterned anode aluminum oxide template on a chip substrate with a pre-prepared patterned conductive layer (non-aluminum material) and completes material growth. The resulting nanotube array electrodes and current collectors on the chip are grown in situ and integrally formed. This is different from the scheme of Shao Zengjun et al., which prepares AAO templates on patterned aluminum substrates (the products are attached to the aluminum substrate and cannot be integrated with silicon-based chips), and also different from the scheme of Scisco et al., which uses Al-Si eutectic bonding to transfer AAO templates to silicon wafers (involving multiple complex processes such as high-temperature bonding, template transfer, and residual aluminum removal). This invention can avoid complex material transfer and secondary bonding steps, achieve perfect compatibility with planar microelectronics processes, and can be mass-produced on 4-inch and larger wafers.

[0024] 2. In this invention, the active material (metal / metal oxide composite nanotube array) is electrochemically grown directly from the current collector, with an ohmic contact or a strong metallurgical bond between the two. This differs from the physical contact interface of traditional slurry coating processes and the bonding interface of template transfer methods. The interface resistance formed by this invention is extremely low (below 2.0 Ω·cm²), with high charge transport efficiency, and the mechanical stability and electrochemical reliability of the electrode are greatly improved. The cycling stability of the electrode of this invention (retention rate >90% after 1000 cycles) is significantly better than that of the transfer method electrode.

[0025] 3. This invention controls the electrochemical deposition conditions (deposition potential, pulse parameters, electrolyte composition) to enable metal ions to achieve "preferential growth on the pore walls" rather than "filling of the pore bottom" in the AAO template channels, thereby obtaining a hollow nanotube structure. Compared with solid nanowires prepared by DC electrodeposition in the prior art, the nanotubes prepared by this invention have double surfaces, which can provide a larger specific surface area, higher active material loading, and shorter ion diffusion path, thereby simultaneously improving the mass specific capacitance, areal specific capacitance, and power density of the electrode. The areal capacitance of the composite nanotube array reaches 48 mF / cm², and the capacitance retention rate exceeds 90% after 1000 cycles.

[0026] 4. This invention allows for flexible control of the size, wall thickness, composition, crystal phase, and shell thickness of composite nanotubes by adjusting the parameters of the anodic alumina template (pore size, depth), electrochemical deposition conditions (Ton / pulse off-time Toff ratio, potential, time), and oxidation process (temperature, time, potential). It is applicable to various transition metals and their oxide systems, such as nickel, iron, cobalt, and manganese. Unlike the existing graphene oxide / yttrium cobalt oxide coaxial heterostructure disclosed in CN110415988A (which requires multiple steps such as spin coating and calcination), this invention adopts a process route combining all-electrochemical and thermal oxidation. The process is simple, the parameters are controllable, and the repeatability is good, providing a general platform for customizing high-performance electrodes for on-chip micro-energy storage devices with different needs.

[0027] 5. The substrate materials (silicon, glass, etc.), conductive layer materials (gold, platinum, chromium, etc.), and processing technologies (photolithography, sputtering, electrodeposition, thermal oxidation) used in this invention are all mature technologies in standard microelectronics manufacturing. The process temperature is low (≤400°C) and is highly compatible with standard CMOS back-end processes. This lays the technological foundation for the synergistic integration of on-chip micro supercapacitors with sensing, computing, and communication circuit units, and has good prospects for industrial application. Attached Figure Description

[0028] The accompanying drawings, which form part of this application, are used to provide a further understanding of the invention. The illustrative embodiments of the invention and their descriptions are used to explain the invention and do not constitute an undue limitation of the invention. In the drawings: Figure 1 This is a process flow diagram of the present invention; Figure 2 This is a schematic diagram of the interdigitated electrode structure; Figure 3 The image shown is an electron microscope image of the ordered array of metal / metal oxide composite nanotubes prepared in this invention, used to demonstrate its morphological characteristics. Detailed Implementation

[0029] To better understand the technical solution of the present invention, the technical solution of the present invention will be described in detail below with reference to the accompanying drawings and specific embodiments.

[0030] like Figure 1 , Figure 2 and Figure 3 As shown, an in-situ fabrication method for an on-chip integrated metal / metal oxide composite nanotube array electrode includes the following steps: Step 1: In-situ construction of on-chip graphical templates: A chip substrate is provided, on which a patterned conductive layer is formed. The material of the patterned conductive layer is a non-aluminum conductive material. The chip substrate is preferably a silicon wafer, a glass wafer, or a polymer wafer. The material of the patterned conductive layer is preferably gold, platinum, titanium, chromium, copper, or a combination thereof. A metallic aluminum film is deposited on a patterned conductive layer; specifically, a high-purity aluminum film can be deposited by electron beam evaporation or magnetron sputtering, with the deposition temperature controlled below 50°C to reduce thermal stress between the aluminum film and the substrate. The aluminum film is patterned to form an aluminum structure corresponding to the pattern of the patterned conductive layer. Specifically, photolithography and etching processes can be used to define a pattern on the aluminum film that completely overlaps with the pattern of the underlying conductive layer, and excess aluminum is removed by wet or dry etching. The aluminum structure is anodized to transform it into a patterned anodized aluminum template, with the bottom of the anodized aluminum template in direct contact with the patterned conductive layer. The preferred process parameters for anodizing are: voltage 20-60V, temperature 0-10℃, and electrolyte is oxalic acid or phosphoric acid solution. The anodic aluminum oxide template is enlarged to reduce or eliminate the barrier layer between the bottom of the anodic aluminum oxide template and the patterned conductive layer. The enlargement process is preferably carried out with phosphoric acid solution, and the enlargement time is 5-20 minutes. This step is crucial to ensure uniform current conduction during the subsequent electrodeposition process and to achieve direct electrical contact between the active material and the current collector.

[0031] Step 2: In-situ electrochemical growth of metal nanotube arrays: An ordered array of metal nanotubes was grown in the nanopores of an anodic aluminum oxide template using a patterned conductive layer as the working electrode and an electrochemical deposition method. Electrochemical deposition, by controlling the deposition potential and / or pulse parameters, enables metal ions to preferentially nucleate on the pore walls of nanopores and grow along the pore walls, forming hollow metal nanotubes; specifically, one of the following methods can be used: Pulsed electrodeposition was employed, with pulse parameters including: on-time Ton of 0.05-0.5 s, off-time pulse off-time Toff of 0.1-1.0 s, and deposition potential of -0.8 V to -1.2 V (relative to a saturated calomel electrode). Constant potential deposition was used, with a deposition potential of -0.9V to -1.1V (relative to a saturated calomel electrode) and a deposition time of 10-30 min. Optionally, a surfactant may be added to the electrolyte to further promote the preferential growth of metal ions on the pore walls; During the deposition process, metal ions are reduced at the bottom of the nanopores (on the patterned conductive layer) of the anodic aluminum oxide template. However, due to the control of deposition parameters, the metal preferentially nucleates on the pore wall and grows along the wall to form a hollow tubular structure. By adjusting the deposition time, pulse parameters and electroplating solution composition, the wall thickness, length and filling rate of the nanotubes can be precisely controlled. The metal is preferably nickel, iron, cobalt, manganese or their alloys.

[0032] Step 3: In-situ transformation of metal / metal oxide composite structures: An ordered array of metal nanotubes was oxidized to form a metal oxide layer on the metal surface in situ, resulting in a metal / metal oxide composite nanotube ordered array. The oxidation treatment can be one of thermal oxidation, electrochemical oxidation, or oxygen plasma treatment. By controlling the temperature, time, or potential of the oxidation treatment, the surface of the metal nanotube is transformed in situ and uniformly into a metal oxide layer with pseudocapacitive activity, forming a core-shell structure of metal core / metal oxide shell. The metal oxide is preferably an oxide or composite oxide of nickel, iron, cobalt, or manganese. When using thermal oxidation, the preferred oxidation temperature is 200-400℃, and the preferred oxidation time is 0.5-4h. When using electrochemical oxidation, it can be achieved in an alkaline electrolyte by cyclic voltammetry or constant potential oxidation. During the oxidation process, the thickness (preferably 2-20nm), crystal form, and interfacial bonding strength with the metal substrate of the metal oxide layer can be precisely controlled by process parameters.

[0033] Step 4: Molding of the integrated electrode: Selectively removing the anodic aluminum oxide template wrapped around the composite nanotube array exposes the ordered array of metal / metal oxide composite nanotubes directly grown on the patterned conductive layer of the chip substrate, forming an on-chip integrated electrode; Template removal can be achieved by selectively dissolving the anodic aluminum oxide template with an alkaline solution (such as sodium hydroxide solution), while the metal / metal oxide composite nanotube structure remains unaffected. After template removal, the active material and the patterned conductive layer maintain the metallurgical bond or ohmic contact formed in situ during growth, resulting in extremely low interfacial resistance, and the active material completely replicates the preset planar pattern.

[0034] The present invention also provides an on-chip integrated metal / metal oxide composite nanotube array electrode; the electrode includes: a chip substrate; a patterned conductive layer formed on the chip substrate, the patterned conductive layer being made of a non-aluminum conductive material; and an ordered array of metal / metal oxide composite nanotubes directly grown on the patterned conductive layer by in-situ electrochemical deposition; the ordered array of composite nanotubes consists of metal nanotubes and a metal oxide shell layer in-situ covering the inner and outer surfaces of the metal nanotubes, forming a hollow core-shell structure; the ordered array of composite nanotubes forms a metallurgical bond or ohmic contact with the patterned conductive layer, and has the same planar pattern as the patterned conductive layer; preferably, the wall thickness of the metal nanotubes is 20-100 nm, the thickness of the metal oxide shell layer is 2-20 nm, and the length of the metal nanotubes is 0.5-5 μm.

[0035] The present invention provides an on-chip integrated micro supercapacitor comprising a pair of on-chip integrated metal / metal oxide composite nanotube array electrodes, wherein the pair of electrodes are arranged in an interdigitated manner on the same plane and immersed in a solid or gel electrolyte; preferably, the interdigitated electrodes have a finger width of 5-10 μm, a finger spacing of 5-10 μm, and a finger length to finger width ratio of 10:1 to 50:1.

[0036] The following specific embodiments demonstrate the effectiveness of the method proposed in this invention.

[0037] Example 1: In-situ fabrication of on-chip integrated nickel / nickel oxide composite nanotube array electrodes: This embodiment demonstrates how to fabricate interdigitated nickel / nickel oxide composite nanotube array electrodes in situ on a silicon-based chip. This method fully follows the technical route of this invention: "in-situ construction of on-chip patterned template - in-situ electrochemical growth of metal nanotube array - in-situ conversion of metal / metal oxide composite structure - integrated electrode forming".

[0038] Step 1: In-situ construction of on-chip graphical templates: 1) Select a 4-inch silicon wafer with a silicon dioxide insulating layer (approximately 300nm thick) thermally oxidized on the surface as the substrate; 2) Using a magnetron sputtering device, a 10 nm thick chromium adhesion layer and a 100 nm thick gold layer are sequentially deposited on the silicon wafer. The chromium layer is used to enhance the adhesion between the gold layer and the silicon substrate, and the gold layer, as a non-aluminum patterned conductive current collector, forms an in-situ bonding interface with the subsequently grown active material. 3) Using standard ultraviolet lithography, an interdigitated electrode pattern (5µm finger width, 5µm spacing) is defined on the gold layer; subsequently, wet etching is performed using gold and chromium etching solutions to obtain patterned chromium / gold interdigitated electrodes as current collectors; such as Figure 2 As shown, the width and spacing of the interdigitated electrodes are both at the micrometer level, with high patterning precision, and they are tightly bonded to the underlying silicon substrate. 4) Using an electron beam evaporation apparatus, a high-purity aluminum film with a thickness of approximately 1 μm is deposited at a low temperature (below 50°C) on the substrate with the gold interdigitated electrodes. Low-temperature deposition can reduce the thermal stress between the aluminum film and the silicon substrate, and avoid delamination in subsequent processes. 5) Use photolithography again to define a pattern on the aluminum film that completely overlaps with the gold cross-finger electrode below; remove excess aluminum by wet or dry etching of aluminum to form an aluminum structure consistent with the gold cross-finger pattern.

[0039] 6) Using the above substrate as the anode and the platinum sheet as the cathode, the substrate was placed in a 0.3M oxalic acid electrolyte and anodized at a constant voltage of 40V and a temperature of 4°C. During the oxidation process, the aluminum regions not protected by the photoresist were transformed into porous anodic aluminum oxide, with the channels growing perpendicular to the substrate. Since the aluminum film was pre-patterned, the final AAO template naturally exhibited an interdigitated pattern, and the bottom of the template maintained direct contact with the underlying gold conductive layer. The oxidation time was controlled at 10 minutes, forming channels with a depth of approximately 500nm and a pore diameter of approximately 40-50nm. 7) After oxidation, the template is enlarged with a 5wt% phosphoric acid solution (about 10 min) to reduce the barrier layer between the bottom of the template and the gold current collector below, so as to facilitate the uniform conduction of current in the subsequent electrodeposition process; this enlargement step is the key to ensuring that the active material and the current collector form a direct electrical contact.

[0040] Step 2: In-situ electrochemical growth of metal nanotube arrays: 1) Preparation of the electroplating solution: The solution is a mixed aqueous solution of 0.1M nickel sulfate and 0.2M boric acid, with the pH adjusted to 3.5. Boric acid acts as a buffer to stabilize the pH of the electroplating solution; 2) Pulse electrodeposition using a three-electrode system: using a gold current collector on the chip as the working electrode, a saturated calomel electrode as the reference electrode, and a platinum sheet as the counter electrode; setting the pulse parameters: on-time (Ton) is 0.1s, potential is -1.0V (vs. SCE); off-time (pulse off-time Toff) is 0.5s, potential is -0.2V (vs. SCE); 3) Deposition at room temperature for about 20 minutes; under this pulse parameter, nickel ions are reduced at the bottom of the nanopores of the AAO template (on the gold electrode), but due to the presence of pulse intervals, nickel preferentially nucleates on the pore wall and grows along the wall to form hollow nickel nanotubes; by adjusting the deposition time, the length and wall thickness of the nanotubes can be precisely controlled; in this embodiment, the nickel nanotubes formed after 20 minutes of deposition are about 500 nm long and about 50 nm thick.

[0041] Step 3: In-situ transformation of metal / metal oxide composite structures: 1) Remove the chip with deposited nickel nanotubes from the electrolyte, wash it with deionized water and blow it dry; 2) Place it in a tube furnace and heat it to 300°C in air at a rate of 2°C / min, then maintain the temperature for 2 hours for thermal oxidation treatment; 3) After cooling in the furnace, a uniform nickel oxide active layer grows in situ on the surface of the nickel nanotube, forming a core-shell structured nickel / nickel oxide composite nanotube; the thickness of the oxide layer can be adjusted by controlling the oxidation temperature and time. In this embodiment, the oxide layer thickness is about 5-10 nm.

[0042] Step 4: Molding of the integrated electrode: 1) The chip was immersed in a 5 wt% sodium hydroxide solution for 10 min to selectively dissolve the AAO template, while the nickel / nickel oxide composite nanotube structure remained unaffected. 2) After repeated rinsing and drying with deionized water, the final product can be obtained: an ordered array of nickel / nickel oxide composite nanotubes directly and firmly grown on the gold interdigitated current collector, which completely replicates the preset interdigitated pattern and forms an on-chip integrated electrode. Characterization and Effects: Observed by scanning electron microscopy (see...) Figure 3 The highly ordered, vertically oriented nanotube arrays are precisely distributed on each golden finger. The outer diameter of the nanotubes is consistent with the pore size of the AAO template (about 50 nm), and the wall thickness is uniform. Transmission electron microscopy analysis confirms that the nanotubes have a clear hollow structure and a uniform NiO shell with a shell thickness of about 5-10 nm. Electrochemical tests showed that in 1M KOH electrolyte, the electrode had an areal capacitance of 42 mF / cm² at a current density of 1A / g, an interfacial resistance of less than 2.0 Ω·cm², and a capacitance retention of over 88% after 1000 cycles.

[0043] Example 2: In-situ fabrication of on-chip integrated cobalt / cobalt tetroxide composite nanotube array electrodes: This embodiment demonstrates the in-situ preparation of cobalt / cobalt tetroxide composite nanotube arrays using a constant potential electrodeposition method combined with an electrochemical oxidation method, showcasing the universality of this invention in different metal systems and with different oxidation methods.

[0044] Step 1: In-situ construction of on-chip graphical templates: Similar to Example 1, a silicon substrate with a patterned gold conductive layer and a patterned AAO template were prepared. Specifically: a 4-inch silicon wafer with a silicon dioxide insulating layer (approximately 300 nm thick) thermally oxidized on the surface was selected as the substrate. A 10 nm chromium adhesion layer and a 100 nm gold layer were deposited by magnetron sputtering. The interdigitated pattern (5 μm wide and 5 μm pitch) was formed by photolithography and wet etching. A 1 μm high-purity aluminum film was deposited at low temperature using electron beam evaporation. The aluminum structure was formed with the same pattern as the gold interdigitated pattern by photolithography and etching. Using 0.3 M oxalic acid as the electrolyte, the template was anodized for 10 min at a constant voltage of 40 V and a temperature of 4°C to form a patterned AAO template with a depth of approximately 500 μm and a pore size of approximately 40-50 μm. After oxidation, the template was treated with a 5 wt% phosphoric acid solution for 10 min to reduce the barrier layer between the bottom of the template and the gold current collector.

[0045] Step 2: In-situ electrochemical growth of metal nanotube arrays: 1) Preparation of electroplating solution: The solution is 0.1M cobalt sulfate. A mixed aqueous solution of boric acid and 0.2M boric acid was prepared, and the pH value was adjusted to 4.0; boric acid acts as a buffer to stabilize the pH value of the electroplating solution.

[0046] 2) A three-electrode system was used for constant potential deposition: the gold current collector on the chip was used as the working electrode, the saturated calomel electrode was used as the reference electrode, and the platinum sheet was used as the counter electrode; the deposition potential was set to -1.0V (vs. SCE), and the deposition time was 20min; 3) Under constant potential deposition conditions, cobalt ions are reduced at the bottom of the nanopores of the AAO template. By precisely controlling the deposition potential and the composition of the electroplating solution, cobalt preferentially nucleates on the pore wall and grows along the wall to form hollow cobalt nanotubes. In this embodiment, the cobalt nanotubes formed after 20 minutes of deposition are approximately 500 μm long and have a wall thickness of approximately 40-60 μm.

[0047] Step 3: In-situ transformation of metal / metal oxide composite structures: 1) Remove the chip with deposited cobalt nanotubes from the electrolyte, wash it with deionized water and blow it dry; 2) Place the chip in 1M KOH electrolyte and perform electrochemical oxidation using cyclic voltammetry: potential range 0 to 0.6V (vs. Hg / HgO), scan rate 20 mV / s, 50 cycles; 3) During this process, the surface of cobalt nanotubes is transformed in situ into cobalt tetroxide. An active layer forms a core-shell structure of cobalt / cobalt tetroxide composite nanotubes; electrochemical oxidation can be completed at room temperature, avoiding the damage to the interface caused by thermal stress that may be caused by thermal oxidation, making it particularly suitable for heat-sensitive applications.

[0048] Step 4: Molding of the integrated electrode: 1) The chip was immersed in a 5 wt% sodium hydroxide solution for 10 min to selectively dissolve the AAO template, while the cobalt / cobalt tetroxide composite nanotube structure remained unaffected. 2) After repeated rinsing and drying with deionized water, the final product can be obtained: an ordered array of cobalt / cobalt tetroxide composite nanotubes directly and firmly grown on the gold interdigitated current collector, which completely replicates the preset interdigitated pattern and forms an on-chip integrated electrode.

[0049] Characterization and Effects: Scanning electron microscopy revealed highly ordered, vertically oriented nanotube arrays precisely distributed on each of the golden interdigitates. The outer diameter of the nanotubes matched the pore size of the AAO template (approximately 50 μm), and the tube walls exhibited uniform thickness. Transmission electron microscopy confirmed that the nanotubes possessed a clear hollow structure and uniformity. The shell has a thickness of approximately 5-8 μm.

[0050] Electrochemical tests show that, due to the double surface of the nanotube structure, which provides a larger specific surface area and a shorter ion diffusion path, the electrode achieves an areal capacitance of 48 mF / cm² at a current density of 1 A / g, an interfacial resistance of less than 2.0 Ω·cm², and a capacitance retention rate of over 90% after 1000 cycles, demonstrating excellent electrochemical performance and stability.

[0051] Example 3: In-situ fabrication of on-chip integrated manganese / manganese oxide composite nanotube array electrodes: This embodiment demonstrates the in-situ preparation of manganese / manganese oxide composite nanotube arrays using a potentiostatic deposition method with added surfactants combined with thermal oxidation, showcasing the flexibility of this invention in controlling nanotube morphology and employing different oxidation methods.

[0052] Step 1: In-situ construction of on-chip graphical templates: Similar to Example 1, a silicon substrate with a patterned gold conductive layer and a patterned AAO template were prepared. The template parameters were: aperture 50 μm, depth 500 μm, and the barrier layer was thinned after the via enlargement process.

[0053] Step 2: In-situ electrochemical growth of metal nanotube arrays: 1) Preparation of electroplating solution: containing 0.1M manganese sulfate 0.1M sodium sulfate A mixed aqueous solution of sodium dodecyl sulfate (SDS) and 0.05% was prepared, with the pH adjusted to 6.5. Sodium sulfate provides ionic conductivity, while SDS acts as a surfactant to promote the preferential growth of manganese ions on the pore walls. 2) Potential constant deposition method was used: the potential was set to -1.2V (vs. SCE), and the deposition time was 15 min. This parameter optimized the nucleation rate of manganese. With the assistance of SDS, manganese preferentially nucleated on the pore walls and grew along the walls to form hollow manganese nanotubes.

[0054] Step 3: In-situ transformation of metal / metal oxide composite structures: The deposited chip was heated to 250°C in air at a rate of 2°C / min and held at that temperature for 1 hour for thermal oxidation treatment. This process transformed the surface of the manganese nanotubes into an amorphous MnO2 shell, forming a core-shell structured Mn / MnO2 composite nanotube. The oxide layer thickness was controlled to be 5-8 nanometers.

[0055] Step 4: Molding of the integrated electrode: Similar to Example 1, the AAO template was dissolved in an alkaline solution to obtain a Mn / MnO2 composite nanotube array directly grown on the gold interdigitated electrode.

[0056] Characterization and Effects: Morphological analysis showed that the nanotube array maintained a one-dimensional ordered structure with a uniform MnO2 shell. A clear core-shell interface could be observed through transmission electron microscopy, with no cracks or detachment. The addition of SDS made the nanotube walls more uniform and the surface smoother.

[0057] Excellent electrochemical performance: At a current density of 0.5 A / g, the areal capacitance reaches 55 mF / cm², and the capacity retention rate is 90% after 2000 cycles, which is attributed to the high ionic conductivity of MnO2 and the in-situ ohmic contact interface.

[0058] Example 4: Regulation of nanotube morphology by different pulse parameters: This embodiment illustrates how adjusting pulse electrodeposition parameters can further optimize the morphology and structure of nanotubes, demonstrating the flexibility of this invention in morphology control.

[0059] Using the same substrate and AAO template as in Example 1, comparative experiments were conducted with different pulse parameters: 1) Pulse parameter A (Ton=0.05s, pulse off time Toff=0.1s, potential -1.0V): Short conduction time generates tiny hydrogen bubbles, forming nickel nanotubes with dense walls and smooth surfaces.

[0060] 2) Pulse parameter B (Ton=0.2s, pulse off time Toff=0.5s, potential -1.0V): Moderate conduction time generates appropriate hydrogen bubbles, forming nickel nanotubes with microporous structures in the tube wall, resulting in a larger specific surface area.

[0061] 3) Pulse parameters C (Ton=0.5s, pulse off time Toff=1.0s, potential -1.0V): Long conduction time generates a large number of hydrogen bubbles, forming nickel nanotubes with loose tube walls and porous secondary structures, resulting in the largest specific surface area.

[0062] Electrochemical tests showed that the nickel / nickel oxide composite nanotube electrode prepared with pulse parameter B had the best performance, with an areal capacitance of 45 mF / cm². This is because the moderate porous structure provides both a high specific surface area and good structural stability.

[0063] Example 5: Effect of different oxidation conditions on the properties of composite nanotubes: This embodiment illustrates how to control the thickness, crystal form, and electrochemical properties of a metal oxide shell by adjusting oxidation treatment conditions.

[0064] Using the same nickel nanotube sample as in Example 1, thermal oxidation treatment was performed at different temperatures: 1) Oxidation temperature 200°C, time 2 hours: a thin NiO shell layer (about 2-3 μm) is formed, with low specific capacitance (about 25 mF / cm²), but good conductivity.

[0065] 2) Oxidation temperature 300°C, time 2 hours: forms a NiO shell of moderate thickness (about 5-10 μm), with the highest specific capacitance (42 mF / cm²) and the lowest interfacial resistance (1.8 Ω·cm²).

[0066] 3) Oxidation temperature 400°C, time 2 hours: a thicker NiO shell (about 15-20 nanometers) is formed, the specific capacitance decreases slightly (38 mF / cm²), but the cycle stability is the best (92% retention rate after 1000 cycles).

[0067] The results above indicate that by optimizing the oxidation temperature and time, an optimal balance can be achieved between specific capacitance, interfacial resistance, and cycle stability.

[0068] Comparative Experiment 1: Comparison with the patterned aluminum substrate method: Following the method disclosed in Shao Zengjun's master's thesis, a nickel nanotube array was prepared on a patterned aluminum sheet and then transferred to a gold interdigitated electrode after being peeled off. The specific steps were as follows: a patterned AAO template was prepared on the aluminum sheet, nickel nanotubes were electrodeposited, the aluminum substrate was removed with a copper chloride solution, the free nickel nanotube film was transferred to the gold interdigitated electrode, and then fixed with conductive silver paste.

[0069] Electrochemical testing results showed that the electrode interface resistance after transfer was as high as 8.7 Ω·cm², and the capacitance retention rate was only 72% after 500 cycles. In contrast, the integrated electrode interface resistance of Example 1 of this invention was less than 2.0 Ω·cm², and the capacitance retention rate exceeded 88% after 1000 cycles. This indicates that the metallurgical bonding interface formed by in-situ growth in this invention has significantly better electrical properties than the physical contact interface formed by the template transfer method.

[0070] Comparative Experiment 2: Comparison with Template Transfer Method: Following the Al-Si eutectic bonding method reported by Scisco et al., an AAO template was transferred onto a silicon wafer and nickel nanotubes were electrodeposited. The specific steps were as follows: an AAO template was prepared on an aluminum wafer, Al-Si eutectic bonding was performed with the silicon wafer at 550°C, the residual aluminum layer was removed with a copper chloride solution, nickel nanotubes were electrodeposited in the pores of the AAO template, and finally the AAO template was removed with an alkaline solution.

[0071] This process requires high-temperature bonding at 550-650°C, and approximately 30% of the template breaks during the transfer process. The resulting electrode has an interface resistance of 2.3 Ω·cm², and a capacitance retention of 85% after 1000 cycles. The process temperature of this invention is only 400°C at most, making it compatible with CMOS back-end processes, eliminating the need for a template transfer step, and resulting in a high yield.

[0072] Comparative experiments fully demonstrate the significant advantages of this invention in terms of in-situ integration process compatibility, interface quality, structural stability, and electrochemical performance.

[0073] Comparative Experiment 3: Performance Comparison of Nanotubes and Nanowires: To verify the advantages of the nanotube structure, the same process conditions as in Example 1 were used, but the pulse parameters were adjusted to allow metal ions to grow in a "bottom-filling" mode, and a solid nickel nanowire array was prepared as a comparison.

[0074] Electrochemical test results show that, at the same current density, the areal capacitance of the nanotube electrode (42 mF / cm²) is significantly higher than that of the nanowire electrode (28 mF / cm²); the rate performance of the nanotube electrode (75% retention at 10 A / g) is also better than that of the nanowire electrode (62% retention at 10 A / g). This confirms that the nanotube structure, due to its double surface, can provide a larger specific surface area and a shorter ion diffusion path, thus achieving superior electrochemical performance.

[0075] Optimal range of process parameters: According to the method of the present invention, the following process parameters can be adjusted according to actual needs to achieve customized preparation with different structures and properties: ①AAO template parameters: Aluminum film thickness: 0.5-5μm; Anodizing voltage: 20-60V (oxalic acid system), 40-100V (phosphoric acid system); Oxidation temperature: 0-10°C; Pore ​​size: 20-200nm (adjustable by oxidation voltage and pore expansion time); Hole depth: 0.5-5μm; ② Electrochemical deposition parameters: Deposition methods: pulsed potential (Ton 0.05-0.5s, pulse off time Toff 0.1-1.0s) or constant potential (-0.8V to -1.2V vs. SCE); Deposition time: 10-30 min; Electroplating solution concentration: metal salt 0.05-0.5M, boric acid 0.1-0.5M; Surfactant concentration: 0.01-0.1wt% (optional); ③Oxidation treatment parameters: Thermal oxidation: temperature 200-400°C, time 0.5-4h Electrochemical oxidation: The potential range is determined according to the type of metal, and the number of cycles is 20-100. Oxygen plasma treatment: power 50-200W, time 10-60min.

[0076] The substrate materials (silicon, glass, etc.), conductive layer materials (gold, platinum, chromium, etc.), and processing technologies (photolithography, sputtering, electrodeposition, thermal oxidation) used in this invention are all mature technologies in standard microelectronics manufacturing. The process temperature is low (≤400°C), and it is highly compatible with standard CMOS back-end processes. This lays the technological foundation for the on-chip integration of micro supercapacitors with sensing, computing, and communication circuit units. It can be mass-produced on 4-inch and larger wafers, and has promising prospects for industrial application.

[0077] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for in-situ fabrication of electrodes for an on-chip integrated nanotube array supercapacitor, characterized in that, Includes the following steps: Step S1: In-situ construction of on-chip graphical template: A chip substrate is provided, on which a patterned conductive layer is formed; A metallic aluminum film is deposited on the patterned conductive layer, and the metallic aluminum film is patterned to form an aluminum structure corresponding to the pattern of the patterned conductive layer. The aluminum structure is anodized to transform it into a patterned anodized aluminum template, wherein the bottom of the anodized aluminum template is in direct contact with the patterned conductive layer. The anodized aluminum template is subjected to a hole-enlarging treatment; Step S2: In-situ electrochemical growth of metal nanotube arrays: Using the patterned conductive layer as the working electrode, an ordered array of metal nanotubes is grown in the nanopores of the anodic aluminum oxide template by electrochemical deposition, wherein the metal nanotubes are hollow structures. Step S3: In-situ transformation of the metal / metal oxide composite structure: The ordered array of metal nanotubes is subjected to oxidation treatment to form a metal oxide layer on the metal surface in situ, resulting in an ordered array of metal / metal oxide composite nanotubes. Step S4: Molding of the integrated electrode: The anodic aluminum oxide template is removed, exposing the ordered array of metal / metal oxide composite nanotubes and maintaining direct bonding with the patterned conductive layer to form an on-chip integrated electrode.

2. The in-situ fabrication method of on-chip integrated nanotube array supercapacitor electrodes according to claim 1, characterized in that: In step S2, the electrochemical deposition method employs pulsed electrodeposition, wherein the pulse on-time Ton is 0.05-0.5s, the pulse off-time Toff is 0.1-1.0s, and the pulse deposition potential is -0.8V to -1.2V.

3. The in-situ fabrication method of an on-chip integrated nanotube array supercapacitor electrode according to claim 1, characterized in that: In step S2, the electrochemical deposition method employs constant potential deposition, with a deposition potential of -0.9V to -1.1V and a deposition time of 10-30min.

4. The in-situ fabrication method of on-chip integrated nanotube array supercapacitor electrodes according to claim 1, characterized in that: The chip substrate is a silicon wafer, a glass wafer, or a polymer wafer; the material of the patterned conductive layer is gold, platinum, titanium, chromium, copper, or a combination thereof.

5. The in-situ fabrication method of an on-chip integrated nanotube array supercapacitor electrode according to claim 1, characterized in that: The metal is at least one of nickel, iron, cobalt, and manganese, or an alloy containing at least two of the above metals; the metal oxide is an oxide or composite oxide of the corresponding nickel, iron, cobalt, and manganese.

6. The in-situ fabrication method of an on-chip integrated nanotube array supercapacitor electrode according to claim 1, characterized in that: In step S1, the voltage for anodizing is 20-60V, the temperature is 0-10℃, and the electrolyte is oxalic acid or phosphoric acid solution; the pore-expanding treatment uses phosphoric acid solution and the pore-expanding treatment time is 5-20min.

7. The in-situ fabrication method of on-chip integrated nanotube array supercapacitor electrodes according to claim 1, characterized in that: In step S3, the oxidation treatment is one of thermal oxidation, electrochemical oxidation, or oxygen plasma treatment; the thermal oxidation method has an oxidation temperature of 200-400℃ and an oxidation time of 0.5-4h; the electrochemical oxidation method is achieved in an alkaline electrolyte by cyclic voltammetry or constant potential oxidation.

8. A method for fabricating an on-chip integrated metal / metal oxide composite nanotube array electrode using any one of claims 1-7, characterized in that, include: Chip substrate; A patterned conductive layer is formed on the chip substrate, and the material of the patterned conductive layer is a non-aluminum conductive material; Furthermore, an ordered array of metal / metal oxide composite nanotubes directly grown on the patterned conductive layer via in-situ electrochemical deposition; The ordered array of metal / metal oxide composite nanotubes consists of metal nanotubes and a metal oxide shell layer that covers the inner and outer surfaces of the metal nanotubes in situ, forming a hollow core-shell structure. The ordered array of metal / metal oxide composite nanotubes forms a metallurgical bond or ohmic contact with the patterned conductive layer, and has the same planar pattern as the patterned conductive layer.

9. The on-chip integrated metal / metal oxide composite nanotube array electrode according to claim 1, characterized in that: The metal nanotube has a wall thickness of 20-100 nm, the metal oxide shell has a thickness of 2-20 nm, and the metal nanotube has a length of 0.5-5 μm.

10. An on-chip integrated micro supercapacitor, characterized in that: It comprises a pair of on-chip integrated metal / metal oxide composite nanotube array electrodes as described in claim 8 or 9, wherein the pair of electrodes are arranged in an interdigitated manner on the same plane and immersed in a solid or gel electrolyte.

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