A high-speed encryption method and device based on an enhanced gallium nitride transistor

Abstract

This invention discloses a high-speed encryption method and apparatus based on enhanced gallium nitride transistors (GNTs), comprising: splitting an initial key using an XOR operation unit and XORing it with preset system parameters to obtain multiple sets of intermediate key variables with the same number of bits; iterating through the multiple sets of intermediate variables using a first core transformation function to obtain a round key sequence; iterating through multiple sets of split plaintext obtained from splitting the plaintext to be encrypted using a second core transformation function and the round key sequence to obtain an initial ciphertext; and outputting the initial ciphertext after reversing its order to obtain the output ciphertext. This invention solves the problems of large switching delays and difficulty in achieving nanosecond-level operational performance by using an XOR operation unit constructed with an enhanced gallium nitride transistor and a nonlinear substitution S-box in the core transformation function, thereby improving encryption speed and ensuring high throughput, meeting the real-time requirements of data encryption, enhancing anti-interference capabilities, and improving encryption security and operational reliability.

Description

Technical Field

[0001] This invention belongs to the field of information security and integrated circuit technology, specifically relating to a high-speed encryption method and device based on enhanced gallium nitride transistors. Background Technology

[0002] Existing encryption systems mostly rely on silicon-based semiconductor devices for their hardware. However, these devices have inherent limitations in high-frequency and high-speed scenarios. Silicon-based devices have low electron mobility and limited switching speed, making it difficult to support the real-time encryption requirements of data transmission. To improve encryption speed, traditional silicon-based chips need to increase their operating frequency or add parallel processing units, resulting in a surge in power consumption and high heat dissipation pressure. Furthermore, encryption algorithms are susceptible to interference. Traditional silicon-based semiconductor devices are greatly affected by temperature and noise, and their randomness is easily affected, reducing encryption security.

[0003] Existing encryption circuits are implemented using application-specific integrated circuits (ASICs). Taking AES128 as an example, the algorithm is directly embedded into a highly parallel custom hardware data path. A pipelined architecture is typically used to unfold ten rounds of operations, enabling continuous throughput of data blocks. Each round includes four key optimization steps: byte substitution, row shifting, column mixing, and round key addition. The most complex nonlinear byte substitution (S-box) does not simply use a lookup table; instead, it transforms the computation into a series of combinational logic gates through composite field arithmetic, significantly reducing area and power consumption. The column mixing operation is optimized in conjunction with key addition, achieving efficient processing through a limited number of XOR and shift operations. The entire data path is accompanied by a parallel key expansion module, ensuring that each pipeline stage obtains the corresponding round key in a timely manner. This fully hardened implementation completely eliminates the overhead of software decoding and scheduling, thus completing the entire encryption process within a very small clock cycle, achieving an optimal balance between throughput, energy efficiency, and physical security.

[0004] However, existing technologies have the following drawbacks: a bottleneck in computing speed, as traditional silicon-based encryption circuits are limited by the low channel electron mobility of silicon materials, resulting in large switching delays in their core logic units, making it difficult to achieve nanosecond-level computing performance and facing a fundamental limitation of insufficient throughput in ultra-high-speed real-time encryption scenarios; and limitations in security protection, as silicon-based devices are more sensitive to side-channel information leakage such as power consumption, timing, and electromagnetic radiation, and their physical structure is easily detected and analyzed. At the same time, they have a higher error rate in high-frequency or complex environments, resulting in inherent vulnerabilities in resisting side-channel attacks and ensuring system reliability. Summary of the Invention

[0005] To address the aforementioned problems in the prior art, this invention provides a high-speed encryption method and apparatus based on enhanced gallium nitride transistors.

[0006] The technical problem to be solved by this invention is achieved through the following technical solution: In a first aspect, the present invention provides a high-speed encryption method based on enhanced gallium nitride transistors, the method comprising: Split the plaintext to be encrypted into multiple groups of plaintext with the same number of bits; An XOR operation unit constructed using enhanced gallium nitride transistors splits the initial key and XORs it with preset system parameters to obtain multiple sets of intermediate key variables with the same number of bits. The round key sequence is obtained by iterating through the multiple sets of intermediate variables using the first core transformation function; The initial ciphertext is obtained by iterating through the multiple sets of split plaintexts using the second core transformation function and the round key sequence; wherein, both the first core transformation function and the second core transformation function include a nonlinear substitution S-box and a linear transformation L process; the nonlinear substitution S-box is constructed based on an enhancement gallium nitride transistor; The initial ciphertext is reversed and then output to obtain the output ciphertext.

[0007] Optionally, the step of iterating through the multiple sets of intermediate key variables using a first core transformation function to obtain the round key sequence includes: Substitute the multiple sets of intermediate key variables and round parameters into the first core transformation function for iterative looping; In each iteration, the current round key is generated based on the first four intermediate key variables obtained in the current iteration round and the round parameters of the current iteration round; The round key sequence is obtained based on the round key obtained in each iteration.

[0008] Optionally, the first core transformation function is expressed as follows: ; in, This represents the first core transformation function. This represents the first input data. This represents the linear transformation L process in the first core transformation function. This represents the nonlinear substitution S-box in the first core transformation function.

[0009] Optionally, the current round key is represented as follows: ; in, Indicates the first Round key for round iteration Indicates the first The first intermediate key variable in the round of iteration. Indicates the first The second intermediate key variable in the round of iteration. Indicates the first The third intermediate key variable in the round of iteration. Indicates the first The fourth intermediate key variable in the round of iteration, Indicates the first The round parameters of the round iteration, This represents the XOR operation.

[0010] Optionally, the step of iterating through the multiple sets of split plaintexts using the second core transformation function and the round key sequence to obtain the initial ciphertext includes: Substitute the multiple sets of split plaintext and round key sequences into the second core transformation function for iterative looping; In each iteration, the ciphertext for the current round is generated based on the first four intermediate plaintext variables obtained in the current iteration round and the round key for the current iteration round; The initial ciphertext is obtained based on the ciphertext obtained in each iteration.

[0011] The current round's ciphertext is represented as follows: ; in, Indicates the first Round ciphertext of round iteration, This represents the second core transformation function. Indicates the first The first intermediate ciphertext variable in the round of iteration, Indicates the first The second intermediate ciphertext variable in the round of iteration, Indicates the first The third intermediate ciphertext variable in the round iteration, Indicates the first The fourth intermediate ciphertext variable in the round of iteration, Indicates the first Round ciphertext of round iteration, This represents the XOR operation.

[0012] Optionally, the linear transformation L process in the second core transformation function is represented as follows: ; in, This represents the linear transformation L process in the second core transformation function. This represents the second input data. Represents 32-bit input data Circular left shift Bit, .

[0013] Secondly, the present invention provides a high-speed encryption device based on an enhanced gallium nitride transistor, the device comprising: The plaintext splitting module is used to split the plaintext to be encrypted into multiple sets of split plaintext with the same number of bits. The XOR module is used to split the initial key and XOR it with preset system parameters using an XOR operation unit built with enhanced gallium nitride transistors to obtain multiple sets of intermediate key variables with the same number of bits. The first iteration module is used to iterate the multiple sets of intermediate variables through the first core transformation function to obtain the round key sequence; The second iteration module is used to iterate the multiple sets of split plaintexts through the second core transformation function and the round key sequence to obtain the initial ciphertext; wherein, both the first core transformation function and the second core transformation function include a nonlinear replacement S-box and a linear transformation L process; the nonlinear replacement S-box is constructed based on an enhancement gallium nitride transistor; The ciphertext output module is used to reverse the order of the initial ciphertext and output it to obtain the output ciphertext.

[0014] The technical solutions provided by the embodiments of the present invention may include the following beneficial effects: In the above technical solution, the present invention solves the problems of large switching delay and difficulty in achieving nanosecond-level operation performance caused by low channel electron mobility in silicon-based encryption circuits by constructing an XOR operation unit using enhanced gallium nitride transistors and a nonlinear replacement S-cell. It improves the encryption operation speed by leveraging the high mobility characteristics of enhanced gallium nitride transistors, ensuring high throughput in ultra-high-speed real-time encryption scenarios, and meeting the real-time requirements of data encryption. It overcomes the inherent vulnerability of silicon-based devices to side-channel information leakage, easy detection and analysis of physical structure, and high error rate in complex environments. It utilizes the physical advantages of low side-channel attack sensitivity and low error encryption rate of eGaN (enhanced gallium nitride) devices to enhance the anti-interference capability and anti-attack performance of the encryption system, thereby improving encryption security and operational reliability.

[0015] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0016] Figure 1 This is a flowchart of a high-speed encryption method based on enhanced gallium nitride transistors provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of the structure of an XOR operation unit provided in an embodiment of the present invention; Figure 3 This is a flowchart of a round key sequence processing method provided in an embodiment of the present invention; Figure 4 This is a structural detail diagram of an XOR unit provided in an embodiment of the present invention; Figure 5This is a schematic diagram of a nonlinear replacement S-cell constructed using an enhanced gallium nitride transistor, provided by an embodiment of the present invention; Figure 6 This is a GF(((2) provided in the embodiments of the present invention. 2 ) 2 ) 2 The principle diagram for inverse calculation in (). Figure 7 This is a schematic diagram of a conventional inverter structure provided by an embodiment of the present invention; Figure 8 This is a schematic diagram of an encryption process provided by an embodiment of the present invention; Figure 9 This is a block diagram of a high-speed encryption device based on an enhanced gallium nitride transistor provided in an embodiment of the present invention. Detailed Implementation

[0017] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0018] Figure 1 This is a flowchart of a high-speed encryption method based on enhanced gallium nitride transistors provided in an embodiment of the present invention, as shown below. Figure 1 As shown, the method includes the following steps: S101. Split the plaintext to be encrypted into multiple sets of plaintext with the same number of bits.

[0019] For example, the 128-bit plaintext to be encrypted is split into four groups of 32 bits each, and the four plaintext groups are stored in four 32-bit registers.

[0020] S102. The XOR operation unit constructed using enhanced gallium nitride transistors splits the initial key and performs an XOR operation with preset system parameters to obtain multiple sets of intermediate key variables with the same number of bits.

[0021] Understandably, the key can be split similarly based on the plaintext to be encrypted, dividing the 128-bit key into four 32-bit subkeys, while fixing a 32-bit constant as the initial key for the initial XOR of key expansion.

[0022] Figure 2 This is a schematic diagram of the structure of an XOR operation unit provided in an embodiment of the present invention, as shown below. Figure 2As shown, the XOR operation unit adopts a differential input XOR gate circuit based on gallium nitride technology. The whole adopts a complementary structure of core logic unit + push-pull output driver stage: with a pair of differential signals A and A' as input, the core logic unit is composed of complementary PMOS and NMOS transistors, and the right side is composed of push-pull output stage through stacked PMOS and NMOS transistors, finally realizing the XOR logic function of Y1=A⊕A'. In this circuit, A is the first logic input signal; A' is the second logic input signal; Y1 is the XOR logic output signal; VDD is the positive power supply (high level) for the CMOS circuit; VSS is the ground (low level) for the CMOS circuit; PMOS transistor (labeled 1) has its gate connected to input A, its source connected to VDD, and its drain connected to the intermediate node and the drain of NMOS transistor 2; NMOS transistor (labeled 2) has its gate connected to input A', its source connected to VSS, and its drain connected to the drain of PMOS 1 and the intermediate node. Node 1 is an enhancement-mode gallium nitride (pMOS) transistor, and Node 2 is an enhancement-mode gallium nitride (nMOS) transistor. The combination of these two transistors creates complementary GaN (gallium nitride) logic, simultaneously achieving the low static power consumption and good noise margin of CMOS, while also incorporating the advantages of GaN's high voltage, high temperature, radiation resistance, lower parasitics, and higher energy efficiency. In high-voltage, harsh environments, it offers higher speed and energy efficiency compared to silicon CMOS. In high-voltage, high-speed mixed-signal, driving, and ruggedized logic applications, it offers a comprehensive advantage over silicon in terms of speed, resilience, and energy saving.

[0023] S103. The first core transformation function is used to iterate through multiple sets of intermediate variables to obtain the round key sequence.

[0024] Optionally, S103 may include: Substitute multiple sets of intermediate key variables and round parameters into the first core transformation function for iterative looping; In each iteration, the current round key is generated based on the first four intermediate key variables obtained in the current iteration round and the round parameters of the current iteration round; The round key sequence is obtained based on the round key obtained in each iteration.

[0025] Understandable, Figure 3 This is a flowchart of a round key sequence processing method provided in an embodiment of the present invention, such as... Figure 3 As shown, the initial 128-bit key is processed using a fixed algorithm to generate 32 round key sequences of 32 bits each. The entire process requires presetting system parameters, round parameters, a nonlinear substitution S-box, and a linear transformation L. The initial key length is 128 bits (16 bytes), divided into four groups of 32 bits (4 bytes each). Each grouped key is a 32-bit hexadecimal number. The preset system parameters are fixed values, and the key is XORed with the original key to achieve initial confusion and prevent the original key from directly participating in the iteration. There are 32 round parameters, each 32 bits, constructed byte-by-byte. The nonlinear and linear transformations applied to the first core transformation function are represented as follows: ; in, This represents the first core transformation function. This represents the first input data. This represents the linear transformation L process in the first core transformation function. This represents the nonlinear substitution S-box in the first core transformation function.

[0026] The key expansion step can be broken down into two parts: initialization and 32 rounds of iterative generation. The initialization step is the "first mixing" of the initial key with preset system parameters. Its purpose is to break the regularity of the original key and generate four 32-bit intermediate key variables, as follows: ; in, Indicates the first A 32-bit intermediate key variable. Indicates the first A 32-bit initial key Indicates the first Preset system parameters.

[0027] Figure 4 This is a structural detail diagram of an XOR unit provided in an embodiment of the present invention. This method employs... Figure 4 The XOR operation unit of the complementary logic structure built by the designed enhanced gallium nitride transistor is used for operation. After receiving the 128-bit initial key, based on the key expansion rule of the SM4 algorithm, it is split into 4 groups of 32 bits each, and then XORed with the preset system parameters to obtain the intermediate key variable, such as... Figure 4 The diagram shows multiple sets of parallel eGaN XOR units that enable parallel XOR processing of 128-bit data. GaN's high electron mobility allows for faster key expansion than traditional silicon-based devices. This is crucial for high-speed encryption systems, reducing the time required to generate intermediate variables for SM4 encryption. Simultaneously, GaN's high channel mobility significantly improves switching speed, resulting in faster key expansion and superior throughput compared to silicon-based systems.

[0028] Then, 32 rounds of iteration are performed. Through 32 loop iterations, the current round key is generated by combining the first four intermediate key variables and the round parameters of the current iteration round. The current round key is the round key for this round, as shown below: ; in, Indicates the first Round key for round iteration Indicates the first The first intermediate key variable in the round of iteration. Indicates the first The second intermediate key variable in the round of iteration. Indicates the first The third intermediate key variable in the round of iteration. Indicates the first The fourth intermediate key variable in the round of iteration, Indicates the first The round parameters of the round iteration, This represents the XOR operation.

[0029] The complete round key sequence can be obtained by substituting the intermediate key variables and round parameters from the initialization step into the first core transformation function. The first core transformation function includes a nonlinear substitution S-box and a linear transformation L process.

[0030] Nonlinear substitution is a nonlinear substitution operation based on a lookup table (S-box). The S-box, the only nonlinear logic unit in the SM4 algorithm, is a crucial guarantee of the algorithm's safety and is often considered a key research focus. Each input element is replaced with another output element. Each element S in the input matrix is ​​read sequentially, mapped to the S-box, and then the data in the S-box is extracted using the mapped row and column values ​​and placed into the replaced output matrix. The nonlinear substitution S-box operation process is represented as follows: ; in, Represents an isomorphic mapping matrix. Describe an 8×8 matrix over GF(2). Indicates the input of the S-box. This represents a matrix (11010011)′, where ′ denotes transpose; when selected back, and They can then be merged into constant matrices. It becomes a constant vector. Through careful selection This can significantly reduce computation. When performing nonlinear substitution of the S-box using the composite domain method, two affine transformations and one GF(((2)) operation are required. 2 ) 2 ) 2 The inverse operation is performed in the context of [the data type]. This method aims to perform non-linear obfuscation, disrupt the linear correlation of data, and resist linear attacks.

[0031] Figure 5 This invention provides a schematic diagram of a conventional nonlinear replacement S-cell constructed using an enhanced gallium nitride transistor, involving two affine transformations and one GF(((2)) transformation. 2 ) 2 ) 2 The inverse in ) Figure 5 In the middle, the two parts correspond to two affine transformations respectively. Figure 6 This is a GF(((2) provided in the embodiments of the present invention. 2 ) 2 ) 2 The principle diagram for inverse finding in ( ) is as follows: Figure 6 As shown, through this high-speed encryption circuit based on enhanced gallium nitride transistors, each element input is eventually replaced with another element output. Figure 5 With GF(2) 8 The left and right sides of the inverse computation in a finite field are separated, with each side representing an affine operation, and the middle GF(2)... 8 Inverse calculation in a finite field is as follows: Figure 6 As shown, GF(2) 8 The inverse calculation under finite fields is decomposed into the inverse calculation under GF(24) finite fields. Figure 7 This is a schematic diagram of a conventional inverter structure provided by an embodiment of the present invention, which adopts... Figure 7 In the inverter structure constructed from GaN enhancement-mode GaN transistors shown, 1 is a GaN pMOS transistor, 2 is a GaN nMOS transistor, VDD is the power supply, VSS is ground, Vi is the input power supply, and Vo is the output voltage. Each S-cell unit is implemented using an XOR logic AND inverter composed of multiple GaN enhancement-mode transistors. The lookup structure composed of these GaN devices achieves byte substitution through high-speed voltage level switching. Due to the extremely fast switching speed of GaN devices, byte lookup and output are almost instantaneous. The GaN logic array allows each S-cell module to operate in complete parallel, with each S-cell corresponding to an independent GaN logic array. There is no dependency between the S-cells. The high-speed and low-latency characteristics of GaN ensure the balance and high-speed output of each stage of the pipeline. The high electron mobility of GaN greatly reduces latency and improves real-time performance. At the same time, the use of GaN devices can reduce electromagnetic leakage and improve resistance to side-channel attacks.

[0032] The linear transformation step is a crucial part of the SM4 encryption algorithm. It is responsible for performing in-line cyclic shifts on the 32-bit data after the input S-box replacement. The linear transformation process is as follows: Figure 3 As shown, the first core transformation function is: ; in, Represents 32-bit input data Circular left shift Bit, When using enhanced gallium nitride (GaN) transistors to implement the SM4 high-speed encryption circuit, the specific implementation of the row shifting step differs from that of traditional silicon-based implementations, especially in terms of speed, parallelism, and stability, where GaN material offers significant advantages. In traditional hardware implementations, shifting rows is typically accomplished using multiplexers and shift registers. However, in GaN implementations, due to its high mobility and low power consumption, this operation can be achieved more efficiently and quickly: for each row of data, the high-speed switching of GaN transistors controls the flow of bytes. These bytes switch very quickly within the GaN device, making the row shifting operation almost instantaneous. Compared to silicon-based materials, enhanced gallium nitride transistors offer lower power consumption and higher energy efficiency, making them suitable for large-scale parallel encryption tasks; furthermore, all row shifting operations can be executed in parallel, avoiding the serial latency present in traditional silicon-based implementations. Therefore, using GaN material not only significantly improves the performance of the SM4 encryption circuit but also enhances the overall reliability and applicability of the system. GaN's low-latency response characteristics enable efficient processing of multiple parallel data blocks, simultaneous format conversion, and key expansion in a very short time. This reduces the overall latency of the encryption process and ensures rapid data transmission during encryption. After key expansion, a round of key sequence is performed, and subsequent encryption processes rely on this round of key sequence, plaintext blocks, and SM4 core transformations, resulting in a total of 32 rounds of Feistel iterations + 1 round of output transformation.

[0033] S104. The initial ciphertext is obtained by iterating through multiple sets of split plaintexts using the second core transformation function and the round key sequence. The first and second core transformation functions both include a nonlinear replacement S-box and a linear transformation L process. The nonlinear replacement S-box is constructed based on an enhancement gallium nitride transistor.

[0034] Optionally, S104 may include: Substitute multiple sets of split plaintext and round key sequences into the second core transformation function for iterative looping; In each iteration, the ciphertext for the current round is generated based on the first four intermediate plaintext variables obtained in the current iteration round and the round key for the current iteration round; The initial ciphertext is obtained from the round ciphertext obtained in each iteration.

[0035] Understandable, Figure 8 This is a schematic diagram of an encryption process provided by an embodiment of the present invention. Figure 8 The encryption steps show that four plaintext blocks are stored in four 32-bit registers as initial values ​​for the iteration: X0=P0, X1=P1, X2=P2, X3=P3. The same round transformation is performed for 32 rounds of encryption iterations, and the ciphertext for the current round is represented as follows: ; in, Indicates the first Round ciphertext of round iteration, This represents the second core transformation function. Indicates the first The first intermediate ciphertext variable in the round of iteration, Indicates the first The second intermediate ciphertext variable in the round of iteration, Indicates the first The third intermediate ciphertext variable in the round iteration, Indicates the first The fourth intermediate ciphertext variable in the round of iteration, Indicates the first Round ciphertext of round iteration, This represents the XOR operation. The linear transformation L process of the second core transformation function differs from that of the first core transformation function in key expansion. The 32 rounds of encryption iterations are consistent with the nonlinear substitution in key expansion, both employing... Figure 5 The S-cell constructed using the enhanced gallium nitride transistor is shown. The linear transformation L process in the second core transformation function is represented as follows: ; in, This represents the linear transformation L process in the second core transformation function. This represents the second input data. Represents 32-bit input data Circular left shift Bit, .

[0036] The initial value is XORed with the key for each round to obtain X for each round. The iterative cycle is as follows: in round 0, X1, X2, X3, and RK0 are substituted to obtain X4; in round 1 (i=1), X2, X3, X4, and RK1 are substituted to obtain X5. After 32 rounds of iteration, the final four register values ​​are obtained: X 32 X 33 X 34 X 35 .

[0037] S105. Reverse the initial ciphertext and output the output ciphertext.

[0038] Understandably, after 32 rounds of encryption iterations, the initial ciphertext is obtained. Due to the iterative nature of the round function, these four registers need to be reversed to obtain the output ciphertext. The final state matrix is ​​then converted into ciphertext data and output in reverse order. This data format corresponds to the plaintext input format and is transmitted using the same blocks as during encryption. The ciphertext data is output at high speed through GaN-based output buffer units. GaN hardware can output the encryption result in a very short time, adapting to the needs of high-speed data processing and communication. GaN's high-speed switching capability makes the ciphertext output speed far exceed that of traditional silicon-based devices, especially in applications requiring high-speed processing or real-time encryption, where GaN's high output rate ensures smooth system operation. Through optimization of GaN devices, the output of ciphertext is not only accelerated but also ensures data accuracy and consistency.

[0039] The SM4 encryption process used in this invention is set to 32 rounds of iteration. The processing steps from the first to the thirty-second round are completely identical, with no special processing in the final round. The core of each iteration is the transformation of the core transformation function, which sequentially performs nonlinear substitution and linear transformation operations. The round function transformation uses a circuit designed with enhanced gallium nitride transistors (GaN transistors) to meet the algorithm requirements of all rounds and optimize path delay, greatly improving the throughput of encryption operations. At the same time, GaN transistors have high electron mobility, enabling them to complete calculations in a shorter time, with performance far exceeding that of silicon-based devices.

[0040] Figure 9 This is a block diagram of a high-speed encryption device based on an enhanced gallium nitride transistor provided in an embodiment of the present invention, such as... Figure 9 As shown, the device 900 includes: Plaintext splitting module 901 is used to split the plaintext to be encrypted into multiple sets of split plaintext with the same number of bits. The XOR module 902 is used to split the initial key and XOR it with preset system parameters using an XOR operation unit constructed with enhanced gallium nitride transistors to obtain multiple sets of intermediate key variables with the same number of bits. The first iteration module 903 is used to iterate through multiple sets of intermediate variables using the first core transformation function to obtain the round key sequence; The second iteration module 904 is used to iterate through multiple sets of split plaintexts using the second core transformation function and the round key sequence to obtain the initial ciphertext; wherein, both the first core transformation function and the second core transformation function include a nonlinear substitution S-box and a linear transformation L process; the nonlinear substitution S-box is constructed based on an enhancement gallium nitride transistor; The ciphertext output module 905 is used to reverse the order of the initial ciphertext and output the ciphertext.

[0041] It is understood that the device embodiments are basically similar to the method embodiments, so the description is relatively simple, and relevant parts can be referred to in the description of the method embodiments.

[0042] It should be noted that the terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention. Rather, they are merely examples of apparatuses and methods consistent with some aspects of the invention.

[0043] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Furthermore, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0044] Although the invention has been described herein in conjunction with various embodiments, those skilled in the art will understand and implement other variations of the disclosed embodiments by reviewing the accompanying drawings and the disclosure in carrying out the claimed invention. In the description of the invention, the word "comprising" does not exclude other components or steps, "a" or "an" does not exclude a plurality, and "a plurality" means two or more, unless otherwise explicitly specified. Furthermore, while different embodiments may describe certain measures, this does not mean that these measures cannot be combined to produce good results.

[0045] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A high speed encryption method based on enhanced gallium nitride transistor, characterized in that, The method includes: Split the plaintext to be encrypted into multiple groups of plaintext with the same number of bits; An XOR operation unit constructed using enhanced gallium nitride transistors splits the initial key and XORs it with preset system parameters to obtain multiple sets of intermediate key variables with the same number of bits. The round key sequence is obtained by iterating through the multiple sets of intermediate variables using the first core transformation function; The initial ciphertext is obtained by iterating through the multiple sets of split plaintexts using the second core transformation function and the round key sequence; wherein, both the first core transformation function and the second core transformation function include a nonlinear substitution S-box and a linear transformation L process; the nonlinear substitution S-box is constructed based on an enhancement gallium nitride transistor; The initial ciphertext is reversed and then output to obtain the output ciphertext.

2. The high speed encryption method based on an enhanced gallium nitride transistor according to claim 1, characterized in that, The step of iterating through the multiple sets of intermediate key variables using the first core transformation function to obtain the round key sequence includes: Substitute the multiple sets of intermediate key variables and round parameters into the first core transformation function for iterative looping; In each iteration, the current round key is generated based on the first four intermediate key variables obtained in the current iteration round and the round parameters of the current iteration round; The round key sequence is obtained based on the round key obtained in each iteration.

3. The high speed encryption method based on an enhanced gallium nitride transistor according to claim 2, characterized by, The first core transformation function is expressed as follows: ； wherein, denotes the first core transformation function, denotes a first input data, denotes a linear transformation L process in the first core transformation function, denotes a non-linear substitution S-box in the first core transformation function.

4. The high speed encryption method based on an enhanced gallium nitride transistor according to claim 3, characterized in that, The current round key is represented as follows: ； in, Indicates the first Round key for round iteration Indicates the first The first intermediate key variable in the round of iteration. Indicates the first The second intermediate key variable in the round of iteration. Indicates the first The third intermediate key variable in the round of iteration. Indicates the first The fourth intermediate key variable in the round of iteration, Indicates the first The round parameters of the round iteration, This represents the XOR operation.

5. The high-speed encryption method based on enhanced gallium nitride transistors according to claim 1, characterized in that, The initial ciphertext is obtained by iterating through the multiple sets of split plaintexts using the second core transformation function and the round key sequence, including: Substitute the multiple sets of split plaintext and round key sequences into the second core transformation function for iterative looping; In each iteration, the ciphertext for the current round is generated based on the first four intermediate plaintext variables obtained in the current iteration round and the round key for the current iteration round; The initial ciphertext is obtained based on the ciphertext obtained in each iteration.

6. The high-speed encryption method based on enhanced gallium nitride transistors according to claim 5, characterized in that, The current round's ciphertext is represented as follows: ； in, Indicates the first Round ciphertext of round iteration, This represents the second core transformation function. Indicates the first The first intermediate ciphertext variable in the round of iteration, Indicates the first The second intermediate ciphertext variable in the round iteration, Indicates the first The third intermediate ciphertext variable in the round iteration, Indicates the first The fourth intermediate ciphertext variable in the round of iteration, Indicates the first Round ciphertext of round iteration, This represents the XOR operation.

7. The high-speed encryption method based on enhanced gallium nitride transistors according to claim 6, characterized in that, The linear transformation L process in the second core transformation function is represented as follows: ； in, This represents the linear transformation L process in the second core transformation function. This represents the second input data. Represents 32-bit input data Circular left shift Bit, .

8. A high-speed encryption device based on enhanced gallium nitride transistors, characterized in that, The device includes: The plaintext splitting module is used to split the plaintext to be encrypted into multiple sets of split plaintext with the same number of bits. The XOR module is used to split the initial key and XOR it with preset system parameters using an XOR operation unit built with enhanced gallium nitride transistors to obtain multiple sets of intermediate key variables with the same number of bits. The first iteration module is used to iterate the multiple sets of intermediate variables through the first core transformation function to obtain the round key sequence; The second iteration module is used to iterate the multiple sets of split plaintexts through the second core transformation function and the round key sequence to obtain the initial ciphertext; wherein, both the first core transformation function and the second core transformation function include a nonlinear replacement S-box and a linear transformation L process; the nonlinear replacement S-box is constructed based on an enhancement gallium nitride transistor; The ciphertext output module is used to reverse the order of the initial ciphertext and output it to obtain the output ciphertext.

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