Audio output optimization method and related equipment based on PBTL biamp master-slave collaboration

Abstract

This invention relates to the field of audio processing technology, and discloses an audio output optimization method and related equipment based on PBTL dual power amplifier master-slave collaboration, used to improve the output consistency, stability, and sound quality performance when dual power amplifiers are driven in parallel. The method includes: configuring a first power amplifier module as the master power amplifier module and a second power amplifier module as the slave power amplifier module, establishing a PBTL output connection relationship; starting the master power amplifier module and monitoring its clock locking, bias establishment, and protection self-test states; determining the start-up delay and enable start-up time of the slave power amplifier module based on the synchronization reference state; starting the slave power amplifier module and locking the master synchronization signal source of the master power amplifier module; acquiring the output spectrum characteristics of the master and slave power amplifier modules and coordinating the switching frequency adjustment; monitoring the output consistency state and performing amplitude and phase compensation.

Description

Technical Field

[0001] This invention relates to the field of audio processing technology, and in particular to an audio output optimization method and related equipment based on PBTL dual power amplifier master-slave collaboration. Background Technology

[0002] Existing audio equipment using PBTL amplifier architecture typically focuses only on increasing output power and enhancing load capacity. While such designs can meet basic power output and distortion requirements under laboratory conditions, in real-world applications, factors such as simultaneous operation of dual amplifier modules, inconsistent drive timing, switching noise coupling, and power supply disturbances can easily lead to channel performance degradation, noticeable spikes in the spectrum, a rough listening experience, and even decreased system stability. Summary of the Invention

[0003] This invention provides an audio output optimization method and apparatus based on PBTL dual power amplifier master-slave collaboration, to solve the problems of poor output consistency, severe beat frequency interference, and degraded sound quality caused by the independent operation of dual power amplifier modules, asynchronous timing, and inconsistent switching frequencies.

[0004] The first aspect of this invention provides an audio output optimization method based on PBTL dual-amplifier master-slave collaboration, comprising: configuring a first power amplifier module as a master power amplifier module and a second power amplifier module as a slave power amplifier module, and establishing a PBTL output connection relationship so that the master power amplifier module and the slave power amplifier module jointly drive a target load; starting the master power amplifier module and monitoring its synchronization reference state, the synchronization reference state including a clock-locked state, an offset establishment state, and a protection self-test state; determining the start-up delay of the slave power amplifier module based on the synchronization reference state, and calculating the enable start-up time of the slave power amplifier module based on the start-up delay, wherein the enable start-up time is located at the start-up time of the master power amplifier module. After clock locking, bias establishment, and protection self-test are completed; the slave power amplifier module is started according to the enabled start time, and the slave power amplifier module is controlled to lock the master synchronization signal source of the master power amplifier module; the output spectrum characteristics of the master power amplifier module and the slave power amplifier module are acquired, and the switching frequency of the master power amplifier module and / or the slave power amplifier module is coordinated and adjusted according to the output spectrum characteristics to obtain the adjusted switching frequency parameters; the audio signals of the master power amplifier module and the slave power amplifier module are controlled according to the adjusted switching frequency parameters, and the output consistency status of the master power amplifier module and the slave power amplifier module is monitored; the amplitude and phase compensation of the output of the slave power amplifier module is performed according to the monitoring results.

[0005] In one feasible implementation, configuring the first power amplifier module as the master power amplifier module and the second power amplifier module as the slave power amplifier module, and establishing a PBTL output connection relationship, includes: configuring the first power amplifier module to operate in master mode and the second power amplifier module to operate in slave mode through hardware pin configuration or register configuration; connecting the non-inverting and inverting output terminals of the master power amplifier module and the non-inverting and inverting output terminals of the slave power amplifier module in parallel according to the PBTL topology, and connecting them together to both ends of the target load; configuring the master power amplifier module as the master clock source, and electrically connecting the clock input pin of the slave power amplifier module to the clock output pin of the master power amplifier module.

[0006] In one feasible implementation, starting the main power amplifier module and monitoring its synchronization reference state includes: sending a power-on start command to the main power amplifier module and starting a status monitoring timer; reading the clock lock flag of the main power amplifier module and confirming that the clock lock state has been achieved when the clock lock flag is valid; reading the bias establishment flag of the main power amplifier module and confirming that the bias establishment state has been achieved when the bias establishment flag is valid; and reading the protection self-test flag of the main power amplifier module and confirming that the protection self-test state has passed when the protection self-test flag is normal.

[0007] In one feasible implementation, determining the startup delay of the slave power amplifier module based on the synchronization reference state and calculating the enable startup time of the slave power amplifier module based on the startup delay includes: acquiring the first duration required for the main power amplifier module to complete clock locking, the second duration required to complete bias establishment, and the third duration required to complete protection self-test; using the maximum value among the first duration, the second duration, and the third duration as the reference delay, or summing the first duration, the second duration, and the third duration and adding a preset safety margin as the startup delay; taking the startup time of the main power amplifier module as the time zero point, and determining the result of adding the startup delay to the time zero point as the enable startup time.

[0008] In one feasible implementation, the step of obtaining the first duration required for the main power amplifier module to complete clock locking, the second duration required to complete bias establishment, and the third duration required to complete protection self-test includes: reading the historical startup timestamps recorded in the internal registers of the main power amplifier module; extracting the first difference between the clock locking completion time and the startup time, the second difference between the bias establishment completion time and the clock locking completion time, and the third difference between the protection self-test completion time and the bias establishment completion time during the most recent successful startup process; multiplying the first difference, the second difference, and the third difference by a preset safety factor to obtain the estimated first duration, the second duration, and the third duration; when the main power amplifier module is starting for the first time or historical startup records are missing, using the default values ​​of typical durations preset in the firmware as the first duration, the second duration, and the third duration.

[0009] In one feasible implementation, the step of using the maximum value among the first duration, the second duration, and the third duration as the baseline delay, or summing the first duration, the second duration, and the third duration and adding a preset safety margin as the startup delay, includes: comparing the values ​​of the first duration, the second duration, and the third duration, selecting the maximum value as the minimum safety delay baseline, ensuring that the main power amplifier module has completed the most time-consuming state establishment when the power amplifier module starts; dynamically adjusting the value of the safety margin according to the startup history fluctuation amplitude of the main power amplifier module, the larger the fluctuation amplitude, the larger the safety margin; using the sum of the baseline delay and the safety margin as the startup delay, or using the sum of the first duration, the second duration, and the third duration and the safety margin as the startup delay, selecting the appropriate calculation method according to the system's priority between startup speed and safety.

[0010] In one feasible implementation, the step of activating the slave power amplifier module according to the enable start time and controlling the slave power amplifier module to lock the master synchronization signal source of the master power amplifier module includes: sending an enable signal to the slave power amplifier module when the enable start time arrives to activate the slave power amplifier module; causing the phase-locked loop circuit of the slave power amplifier module to use the master clock signal output by the master power amplifier module as a reference input to perform a frequency locking process; monitoring the phase-locked loop locking flag bit of the slave power amplifier module until the phase-locked loop locking flag bit is valid to confirm that the slave power amplifier module has successfully locked the master synchronization signal source.

[0011] In one feasible implementation, the step of acquiring the output spectrum characteristics of the main power amplifier module and the slave power amplifier module, and coordinating the switching frequency of the main power amplifier module and / or the slave power amplifier module according to the output spectrum characteristics to obtain the adjusted switching frequency parameters includes: acquiring the first spectrum data from the output of the main power amplifier module and the second spectrum data from the output of the slave power amplifier module respectively; extracting the switching ripple frequency component and harmonic distortion component from the first spectrum data and the second spectrum data; calculating the switching frequency deviation value of the main power amplifier module and the slave power amplifier module according to the switching ripple frequency component, and determining whether the current switching frequency setting causes excessive distortion according to the amplitude of the harmonic distortion component; when the switching frequency deviation value exceeds a preset beat frequency suppression threshold, or the amplitude of the harmonic distortion component exceeds a preset distortion tolerance threshold, adjusting the switching frequency of the slave power amplifier module to the reference based on the switching frequency of the main power amplifier module; and writing the adjusted switching frequency value as the adjusted switching frequency parameter into the switching frequency configuration register of the slave power amplifier module.

[0012] In one feasible implementation, the step of separately acquiring the first spectrum data from the output of the main power amplifier module and the second spectrum data from the output of the slave power amplifier module includes: coupling isolation attenuation networks between the outputs of the main power amplifier module and the slave power amplifier module and the target load, respectively, to attenuate the high-power output signal to a preset input range; acquiring the spectrum data of the two output signals sequentially or simultaneously with the same center frequency, sweep width, and resolution bandwidth, and pausing the input audio signal or injecting a preset single-tone test signal during the acquisition process to eliminate interference from the audio content on the switching ripple spectrum measurement; using the acquired spectrum data from the output of the main power amplifier module as the first spectrum data, and the spectrum data from the output of the slave power amplifier module as the second spectrum data.

[0013] In one feasible implementation, the step of calculating the switching frequency deviation value of the main power amplifier module and the slave power amplifier module based on the switching ripple frequency component, and determining whether the current switching frequency setting causes excessive distortion based on the amplitude of the harmonic distortion component; when the switching frequency deviation value exceeds a preset beat frequency suppression threshold, or the amplitude of the harmonic distortion component exceeds a preset distortion tolerance threshold, adjusting the switching frequency of the slave power amplifier module towards the reference, using the switching frequency of the main power amplifier module as the reference, includes: The frequency value corresponding to the largest switching ripple peak is extracted from the first spectrum data as the actual switching frequency of the main power amplifier module. The frequency value corresponding to the largest switching ripple peak is extracted from the second spectrum data as the actual switching frequency of the slave power amplifier module. Simultaneously, the amplitude values ​​of each harmonic distortion component are extracted from both the first and second spectrum data. The difference between the actual switching frequency of the slave power amplifier module and the actual switching frequency of the main power amplifier module is calculated, and its absolute value is taken as the switching frequency deviation value. The extracted amplitude values ​​of each harmonic distortion component are compared with a preset distortion tolerance threshold. When... When the switching frequency deviation exceeds a preset beat frequency suppression threshold, or the amplitude of any of the harmonic distortion components exceeds a preset distortion tolerance threshold, the switching frequency control word of the power amplifier module is gradually adjusted according to a preset step size. After each adjustment, the spectrum data is re-acquired and the switching ripple frequency component and harmonic distortion component are re-extracted. The switching frequency deviation is recalculated and the harmonic distortion amplitude is re-compared with the distortion tolerance threshold to verify whether the switching frequency deviation has decreased and whether the harmonic distortion amplitude has decreased, until the switching frequency deviation converges to within the beat frequency suppression threshold and the amplitude of all harmonic distortion components has decreased to below the corresponding distortion tolerance threshold.

[0014] In one feasible implementation, controlling the output audio signals of the main power amplifier module and the slave power amplifier module according to the adjusted switching frequency parameters, and monitoring the output consistency status of the main power amplifier module and the slave power amplifier module, includes: simultaneously writing the adjusted switching frequency parameters into the switching frequency configuration registers of the main power amplifier module and the slave power amplifier module to keep their nominal switching frequencies consistent, and synchronously sending audio playback start commands to both; coupling voltage detection circuits at the output terminals of the main power amplifier module and the slave power amplifier module respectively, synchronously acquiring the main power amplifier output voltage signal and the slave power amplifier output voltage signal at a preset sampling frequency, and performing analog-to-digital conversion respectively to obtain the main power amplifier digital feedback signal and the slave power amplifier digital feedback signal; using the main power amplifier digital feedback signal as a reference, calculating the amplitude difference value and phase difference value of the slave power amplifier digital feedback signal relative to the main power amplifier digital feedback signal, as a quantitative indicator of the output consistency status.

[0015] In one feasible implementation, the step of performing amplitude and phase compensation on the output of the slave power amplifier module based on the monitoring results includes: comparing the amplitude difference value with a preset amplitude tolerance range; when the amplitude difference value exceeds the amplitude tolerance range, generating an amplitude compensation gain coefficient based on the deviation between the amplitude difference value and the target amplitude reference, and applying the amplitude compensation gain coefficient to the multiplier node in the digital signal processing link of the slave power amplifier module; comparing the phase difference value with a preset phase tolerance range; when the absolute value of the phase difference value exceeds the phase tolerance range, generating a phase compensation delay amount based on the positive and negative direction and magnitude of the phase difference value, and applying the phase compensation delay amount to the all-pass filter or delay line node in the digital signal processing link of the slave power amplifier module; after applying the amplitude compensation gain coefficient and the phase compensation delay amount, re-acquiring the output voltage signal of the slave power amplifier module and comparing it with the output voltage signal of the main power amplifier module for a second time to verify whether the compensated amplitude difference value and phase difference value fall within the corresponding tolerance range; if so, locking the current compensation parameter as the steady-state compensation parameter.

[0016] The second aspect of the present invention provides an audio output optimization device based on PBTL dual power amplifier master-slave collaboration, comprising: a connection module, configured to configure a first power amplifier module as a master power amplifier module, configure a second power amplifier module as a slave power amplifier module, and establish a PBTL output connection relationship, so that the master power amplifier module and the slave power amplifier module jointly drive the target load; The startup module is used to start the main power amplifier module and monitor the synchronization reference state of the main power amplifier module. The synchronization reference state includes clock lock state, bias establishment state and protection self-test state. The calculation module is used to determine the startup delay of the slave power amplifier module according to the synchronization reference state, and to calculate the enable startup time of the slave power amplifier module according to the startup delay, wherein the enable startup time is located after the master power amplifier module completes clock locking, bias establishment and protection self-test; A locking module is used to activate the slave power amplifier module according to the enable start time, and control the slave power amplifier module to lock the master synchronization signal source of the master power amplifier module; The processing module is used to acquire the output spectrum characteristics of the main power amplifier module and the slave power amplifier module, and to perform coordinated adjustment processing on the switching frequency of the main power amplifier module and / or the slave power amplifier module according to the output spectrum characteristics to obtain the adjusted switching frequency parameters. The monitoring module is used to control the output audio signals of the main power amplifier module and the slave power amplifier module according to the adjusted switching frequency parameters, and to monitor the output consistency status of the main power amplifier module and the slave power amplifier module. The compensation module is used to perform amplitude and phase compensation on the output of the power amplifier module based on the monitoring results.

[0017] A third aspect of the present invention provides an electronic device, comprising: a memory and at least one processor, wherein the memory stores instructions; the at least one processor invokes the instructions in the memory to cause the electronic device to execute the above-described audio output optimization method based on PBTL dual power amplifier master-slave collaboration.

[0018] A fourth aspect of the present invention provides a computer-readable storage medium storing instructions that, when executed on a computer, cause the computer to perform the above-described audio output optimization method based on PBTL dual amplifier master-slave collaboration.

[0019] In the technical solution provided by this invention, a first power amplifier module is configured as a master power amplifier module, a second power amplifier module is configured as a slave power amplifier module, and a PBTL output connection is established so that the master power amplifier module and the slave power amplifier module jointly drive the target load; the master power amplifier module is started and its synchronization reference state is monitored, the synchronization reference state including clock lock state, bias establishment state, and protection self-test state; the start-up delay of the slave power amplifier module is determined according to the synchronization reference state, and the enable start-up time of the slave power amplifier module is calculated according to the start-up delay, wherein the enable start-up time is when the master power amplifier module completes clock lock, bias establishment, and protection self-test. After self-test, the slave power amplifier module is started according to the enabled start time, and the slave power amplifier module is controlled to lock the master synchronization signal source of the master power amplifier module; the output spectrum characteristics of the master power amplifier module and the slave power amplifier module are acquired, and the switching frequency of the master power amplifier module and / or the slave power amplifier module is coordinated and adjusted according to the output spectrum characteristics to obtain the adjusted switching frequency parameters; the audio signal output of the master power amplifier module and the slave power amplifier module is controlled according to the adjusted switching frequency parameters, and the output consistency status of the master power amplifier module and the slave power amplifier module is monitored; the amplitude and phase compensation of the output of the slave power amplifier module is performed according to the monitoring results. In this embodiment of the invention, by configuring the first power amplifier module as the master power amplifier module and the second power amplifier module as the slave power amplifier module and establishing a PBTL output connection, the master power amplifier module is first started and its clock locking, bias establishment, and protection self-test synchronization reference states are monitored in real time. This determines the start-up delay and enable start-up time of the slave power amplifier module, ensuring that the slave power amplifier starts and locks the master synchronization signal source only after the master power amplifier completes the establishment of key states. This effectively avoids channel performance degradation caused by inconsistent driving timing of the two power amplifiers. Furthermore, by acquiring the output spectrum characteristics of the master and slave power amplifiers and coordinating the switching frequencies of the two, the spectral spikes and beat frequency interference caused by switching noise coupling and power supply disturbances can be significantly suppressed. On this basis, the output consistency status of the master and slave power amplifiers is continuously monitored, and the amplitude and phase compensation of the slave power amplifier is performed according to the monitoring results. This greatly improves the output consistency, system stability, and audio fidelity when the two power amplifiers are driven in parallel, ultimately improving the problems of rough listening and degraded sound quality, and achieving high-fidelity and high-stability audio output. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of an embodiment of the audio output optimization method based on PBTL dual power amplifier master-slave collaboration in this invention. Figure 2 This is a schematic diagram of another embodiment of the audio output optimization method based on PBTL dual power amplifier master-slave collaboration in this invention. Figure 3This is a schematic diagram of another embodiment of the audio output optimization method based on PBTL dual power amplifier master-slave collaboration in the present invention. Figure 4 This is a schematic diagram of an embodiment of the audio output optimization device based on PBTL dual power amplifier master-slave collaboration in this invention. Figure 5 This is a schematic diagram of another embodiment of the audio output optimization device based on PBTL dual power amplifier master-slave collaboration in this invention. Figure 6 This is a schematic diagram of one embodiment of the electronic device in this invention. Detailed Implementation

[0021] This invention provides an audio output optimization method and related equipment based on PBTL dual power amplifier master-slave collaboration. By coordinating the timing of the master and slave power amplifier modules, coordinating the spectrum adjustment of the switching frequency, and compensating for the consistency of the output amplitude and phase, accurate synchronous output is achieved when the dual power amplifiers are driven in parallel.

[0022] The terms "first," "second," "third," "fourth," etc. (if present) in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" or "having" and any variations thereof are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0023] It is understood that the executing entity of this invention can be an audio output optimization device based on PBTL dual power amplifier master-slave collaboration, or it can be a terminal or a server; the specific implementation is not limited here. This embodiment of the invention will be described using a server as an example.

[0024] For ease of understanding, the specific process of the embodiments of the present invention is described below. Please refer to [link / reference]. Figure 1 One embodiment of the audio output optimization method based on PBTL dual power amplifier master-slave collaboration in this invention includes: 101. Configure the first power amplifier module as the master power amplifier module and the second power amplifier module as the slave power amplifier module, and establish a PBTL output connection relationship so that the master power amplifier module and the slave power amplifier module can jointly drive the target load. The first power amplifier module is set to master mode and the second power amplifier module is set to slave mode via hardware pins or I²C / SPI interface; the non-inverting output terminals and inverting output terminals of the master and slave power amplifier modules are interconnected and connected to both ends of the target load to form a PBTL topology, thereby achieving output current multiplication.

[0025] 102. Start the main power amplifier module and monitor the synchronization reference status of the main power amplifier module. The synchronization reference status includes clock lock status, bias establishment status and protection self-test status. A power-on start command is sent to the main power amplifier module, followed by the start of an internal status monitoring timer. The initialization process is tracked by continuously reading various flag bits in the main power amplifier module's internal status register: first, the clock lock flag is checked to confirm that the main power amplifier module's internal oscillator or phase-locked loop has been successfully locked to the reference clock source; then, the bias setup flag is checked to confirm that its internal DC bias voltage has been stably established to the preset value; finally, the protection self-test flag is read to confirm that no faults such as overcurrent, overtemperature, or DC offset are detected during the main power amplifier module's startup, thus determining that the main power amplifier module has completed all the prerequisites for safe startup.

[0026] 103. Determine the startup delay of the slave power amplifier module based on the synchronization reference state, and calculate the enable startup time of the slave power amplifier module based on the startup delay. The enable startup time is located after the master power amplifier module completes clock locking, bias establishment and protection self-test. The startup rhythm of the main power amplifier module is evaluated by statistically analyzing the time required for the main power amplifier module to complete each of the three states (clock lock, bias establishment, and protection self-test) from receiving the startup command. To prevent potential shocks or erroneous lockouts caused by the slave power amplifier module starting prematurely before the main power amplifier module is fully stable, a safe waiting window is determined based on these time lengths. The end time of this window is set as the enable startup time of the slave power amplifier module. This enable startup time must occur after the main power amplifier module has completed the establishment of all critical states, thus ensuring that the main power amplifier module is already in a stable and followable operating state when the slave power amplifier module starts.

[0027] 104. Start the slave power amplifier module according to the enable start time, and control the slave power amplifier module to lock the master synchronization signal source of the master power amplifier module; When the internal timer reaches the calculated enable start-up moment, an enable signal is immediately sent to the slave power amplifier module, triggering its power-on and initialization process. During the slave power amplifier module's startup, its internal phase-locked loop (PLL) circuit is forced to connect its input clock pin to the master clock signal line output by the master power amplifier module, using this master clock as the sole frequency and phase reference. Subsequently, the lock flag of the slave power amplifier module's internal PLL is continuously monitored until it becomes valid, confirming that the slave power amplifier module has successfully locked onto the synchronization signal source of the master power amplifier module, achieving precise time base alignment between the two.

[0028] 105. Obtain the output spectrum characteristics of the main power amplifier module and the slave power amplifier module, and perform coordinated adjustment of the switching frequency of the main power amplifier module and / or the slave power amplifier module based on the output spectrum characteristics to obtain the adjusted switching frequency parameters. With a stable output test signal or in a silent state with no audio input, the voltage signals at the output terminals of the main power amplifier module and the slave power amplifier module are acquired by connecting a spectrum analysis module in the output circuit or utilizing the integrated analog-to-digital converter and digital signal processing capabilities of the power amplifier module. Fast Fourier Transform is then performed to obtain their respective spectrum data. Ripple spike components related to the switching frequency are extracted from these two sets of spectrum data, and the frequency deviation between them is calculated. If this deviation exceeds a set beat frequency suppression threshold, the system will use the actual switching frequency of the main power amplifier module as the sole reference. By writing a new control word to the switching frequency configuration register of the slave power amplifier module, the switching frequency of the slave power amplifier module is gradually adjusted in small steps to continuously bring it closer to the switching frequency of the main power amplifier module, thereby suppressing audible beat frequency interference caused by frequency differences.

[0029] 106. Control the output audio signals of the main power amplifier module and the slave power amplifier module according to the adjusted switching frequency parameters, and monitor the output consistency status of the main power amplifier module and the slave power amplifier module. After coordinated adjustment, the consistent switching frequency parameters are simultaneously written into the corresponding registers of both the main and slave power amplifier modules, ensuring their nominal switching frequencies are completely identical. Then, an audio playback start command is synchronously sent to both. During playback, voltage detection circuits coupled to the outputs of the main and slave power amplifier modules simultaneously acquire the two output voltage signals at the same sampling frequency, and convert them into digital feedback signals via analog-to-digital converters. Using the digital feedback signal from the main power amplifier module as a reference, the amplitude difference and phase lead / lag difference of the digital feedback signal from the slave power amplifier module relative to the digital feedback signal from the main power amplifier module are calculated point-by-point or frame-by-frame. These differences are used as the core indicators for quantifying the output consistency status.

[0030] 107. Perform amplitude and phase compensation on the output of the power amplifier module based on the monitoring results.

[0031] The calculated amplitude difference value is compared with a preset acceptable tolerance range. If it exceeds the range, a corresponding amplitude compensation gain coefficient is generated based on the direction and magnitude of the difference. This coefficient is then multiplied by the multiplier node on the audio data path in the digital signal processing link of the power amplifier module, thereby adjusting the output amplitude of the power amplifier module in real time. Simultaneously, the phase difference value is compared with a preset phase tolerance range. If it exceeds the range, a corresponding compensation delay is applied to the power amplifier module at the all-pass filter or variable delay line node based on the direction and degree of phase lag, adjusting the phase of its output signal. After compensation, output consistency monitoring is performed again to verify whether the compensation effect has brought the difference value back to the tolerance range. If the requirements are met, the current compensation parameters are locked as the steady-state operating point, maintaining synchronous output between the main and slave power amplifier modules.

[0032] To further improve the accuracy of amplitude and phase compensation in the master-slave power amplifier module and avoid compensation oscillations caused by amplitude and phase coupling effects, this embodiment also provides an adaptive amplitude and phase joint iterative compensation algorithm based on error coupling awareness. This algorithm uses amplitude compensation and phase compensation as two dimensions for joint optimization, dynamically adjusts the iteration step size of both through a coupling awareness factor, and employs a weighted joint convergence criterion to lock the steady-state parameters.

[0033] First, calculate the normalized magnitude error using the following formula: ,when

[0034] in, To compensate for the iteration count index, For the first In the next iteration, the ADC sampling root mean square estimate of the amplitude output by the main power amplifier module is... For the first The output amplitude after compensation is applied from the power amplifier module in the next iteration. This represents the normalized amplitude error; a positive value indicates that the amplitude from the power amplifier module is too low. When the output amplitude of the main power amplifier is lower than the minimum effective threshold, skip the current compensation iteration and wait for the output of the main power amplifier to stabilize before recalculating.

[0035] The phase error is calculated using the cross-correlation argument estimation method:

[0036] in, and These are the nth sampling points of the digital feedback signals of the output voltages from the main power amplifier module and the slave power amplifier module, respectively. for The complex conjugate of , where N is the sampling window length. This represents the phase error, measured in radians. A positive value indicates phase lag from the power amplifier module.

[0037] A coupling sensing factor is introduced to jointly update the amplitude compensation gain and phase compensation delay.

[0038] The iterative update formula for the amplitude compensation gain is:

[0039] in, For the first The amplitude compensation gain coefficient for the next iteration, initial value ; This is the amplitude adaptive step size factor, with a value range of 0.05 to 0.3; It is the amplitude-phase coupling factor, which automatically suppresses amplitude updates when the phase error is large, thus avoiding erroneous amplitude compensation caused by phase deviation.

[0040] The iterative update formula for phase compensation delay is:

[0041] in, For the first The phase compensation delay amount for the next iteration, in units of the number of sampling points, initial value. ; This is the phase adaptive step size factor, with a value range of 0.1 to 0.5; It is the amplitude-phase coupling factor. When the amplitude error is large, it automatically suppresses phase updates to prevent the introduction of erroneous phase shifts before the amplitude correction is completed.

[0042] Calculate the joint error energy criterion:

[0043] in, and These are the weighting coefficients for amplitude and phase in the joint convergence criterion, respectively, satisfying... ; This is the joint error energy value. If... Then the steady-state compensation parameters are locked:

[0044] in, The joint convergence threshold is set based on the system's amplitude tolerance and phase tolerance. These are the steady-state amplitude gain and phase delay compensation parameters locked after convergence, respectively.

[0045] In this embodiment of the invention, by configuring the first power amplifier module as the master power amplifier module and the second power amplifier module as the slave power amplifier module and establishing a PBTL output connection, the master power amplifier module is first started and its clock locking, bias establishment, and protection self-test synchronization reference states are monitored in real time. This determines the start-up delay and enable start-up time of the slave power amplifier module, ensuring that the slave power amplifier starts and locks the master synchronization signal source only after the master power amplifier completes the establishment of key states. This effectively avoids channel performance degradation caused by inconsistent driving timing of the two power amplifiers. Furthermore, by acquiring the output spectrum characteristics of the master and slave power amplifiers and coordinating the switching frequencies of the two, the spectral spikes and beat frequency interference caused by switching noise coupling and power supply disturbances can be significantly suppressed. On this basis, the output consistency status of the master and slave power amplifiers is continuously monitored, and the amplitude and phase compensation of the slave power amplifier is performed according to the monitoring results. This greatly improves the output consistency, system stability, and audio fidelity when the two power amplifiers are driven in parallel, ultimately improving the problems of rough listening and degraded sound quality, and achieving high-fidelity and high-stability audio output.

[0046] Please see Figure 2 Another embodiment of the audio output optimization method based on PBTL dual power amplifier master-slave collaboration in this invention includes: 201. Configure the first power amplifier module as the master power amplifier module and the second power amplifier module as the slave power amplifier module, and establish a PBTL output connection relationship so that the master power amplifier module and the slave power amplifier module can jointly drive the target load. Configure the first power amplifier module to master mode and the second power amplifier module to slave mode via hardware pin configuration or register configuration. Connect the non-inverting and inverting output terminals of the master power amplifier module and the slave power amplifier module in parallel according to the PBTL topology, and connect them together to the two ends of the target load. Configure the master power amplifier module as the master clock source, and electrically connect the clock input pin of the slave power amplifier module to the clock output pin of the master power amplifier module.

[0047] 202. Start the main power amplifier module and monitor the synchronization reference status of the main power amplifier module. The synchronization reference status includes clock lock status, bias establishment status and protection self-test status. Send a power-on start command to the main power amplifier module and start the status monitoring timer; read the clock lock flag of the main power amplifier module, and confirm that the clock lock status is achieved when the clock lock flag is valid; read the bias establishment flag of the main power amplifier module, and confirm that the bias establishment status is achieved when the bias establishment flag is valid; read the protection self-test flag of the main power amplifier module, and confirm that the protection self-test status is passed when the protection self-test flag is normal.

[0048] During startup, the various flag bits in the main power amplifier module's internal status register are periodically read: First, the clock lock flag is read. When this flag is active, it indicates that the oscillator circuit or phase-locked loop circuit inside the main power amplifier module has successfully locked to the reference clock source, and the clock signal has stabilized. Next, the bias setup flag is read. When this flag is active, it indicates that the DC bias voltage of each stage of the amplifier circuit inside the main power amplifier module has been established and stabilized at the preset operating point. Finally, the protection self-test flag is read. When this flag displays a normal value, it indicates that the main power amplifier module has not detected any abnormal faults such as overcurrent, overtemperature, output DC offset, or short circuit during the power-on self-test, and is ready for safe output. By sequentially confirming the active status of these three flag bits, it is possible to accurately determine whether the main power amplifier module has completed all the prerequisites for safe startup.

[0049] 203. Obtain the first duration required for the main power amplifier module to complete clock locking, the second duration required to complete bias establishment, and the third duration required to complete protection self-test, respectively; Read the historical startup timestamps recorded in the internal registers of the main power amplifier module, and extract the first difference between the clock lock completion time and the startup time, the second difference between the bias establishment completion time and the clock lock completion time, and the third difference between the protection self-test completion time and the bias establishment completion time during the most recent successful startup process. Multiply the first, second, and third differences by a preset safety factor to obtain the estimated first, second, and third durations. When the main power amplifier module is starting for the first time or the historical startup record is missing, use the default typical duration preset in the firmware as the first, second, and third durations.

[0050] The timestamp information for each stage of the most recent successful startup is read from the register group inside the main power amplifier module, which is dedicated to recording startup history data. Specifically, the time difference between receiving the startup command and the time when the clock lock flag is valid is extracted as the first duration required for clock lock; the time difference between the time when clock lock is completed and the time when the bias establishment flag is valid is extracted as the second duration required for bias establishment; and the time difference between the time when bias establishment is completed and the time when the protection self-test flag shows normal is extracted as the third duration required for protection self-test. To prevent uncertainty caused by startup time fluctuations due to component aging and environmental changes, these three time differences are multiplied by a preset safety factor greater than one to obtain the estimated duration of the safety margin. If the main power amplifier module is powered on for the first time since leaving the factory, or if valid data in the historical startup record register is lost due to power failure or reset, the historical record is not read, and the default value of the typical duration pre-embedded in the system firmware is used as the basis for the values ​​of the first, second, and third durations mentioned above.

[0051] 204. Use the maximum value among the first duration, the second duration, and the third duration as the baseline delay, or sum the first duration, the second duration, and the third duration and add a preset safety margin as the start delay; Compare the values ​​of the first, second, and third durations, and select the maximum value as the minimum safe delay benchmark to ensure that the main power amplifier module has completed the most time-consuming state establishment when it starts up. Dynamically adjust the safety margin value based on the historical fluctuation range of the main power amplifier module's startup; the larger the fluctuation range, the larger the safety margin. Use the sum of the benchmark delay and the safety margin as the startup delay, or use the sum of the first, second, and third durations and the safety margin as the startup delay, and select the appropriate calculation method according to the system's priority between startup speed and safety.

[0052] The maximum value among the first, second, and third durations is identified. Since this maximum value represents the time required for the main power amplifier module to complete the longest state establishment process, it is used as the minimum safe delay benchmark to ensure that the main power amplifier module has at least completed the longest-running state upon startup. Simultaneously, the stability of the startup process is dynamically evaluated based on the fluctuation range of each stage duration in multiple historical startup records of the main power amplifier module: if the historical records show large fluctuations in the completion time of each stage, a preset safety margin value is dynamically increased; conversely, if the fluctuations are small, the safety margin value can be appropriately decreased. Subsequently, based on the different priority requirements of startup speed and startup safety in the current application scenario, one of two delay calculation methods is selected: in scenarios with high startup speed requirements, the maximum benchmark delay is added to the safety margin to obtain the final startup delay; in scenarios with high startup safety requirements, the first, second, and third durations are all added together before adding to the safety margin to obtain a more conservative startup delay.

[0053] 205. Taking the startup time of the main power amplifier module as the zero point of time, the result of adding the startup delay to the zero point of time is determined as the enable startup time. The enable startup time is located after the main power amplifier module completes clock locking, bias establishment and protection self-test. The moment the main power amplifier module receives the start command is defined as time zero, serving as the time reference for the entire master-slave collaborative start process. Subsequently, the calculated start delay is input into the calculation: starting from time zero, this start delay length is shifted backward; the resulting moment is determined as the enable start time of the slave power amplifier module. Since the start delay design ensures that this delay length is greater than or equal to the time required for the main power amplifier module to complete clock locking, bias establishment, and protection self-test (this condition is satisfied regardless of whether a maximum value reference or a summation reference is used), this enable start time must occur after the main power amplifier module has completed the establishment of these three key states. This ensures that when the slave power amplifier module starts, the main power amplifier module is already in a completely stable and safe operating state.

[0054] 206. Start the slave power amplifier module according to the enable start time, and control the slave power amplifier module to lock the master synchronization signal source of the master power amplifier module; When the enable start time arrives, an enable signal is sent to the slave power amplifier module to start it. The phase-locked loop (PLL) circuit of the slave power amplifier module uses the master clock signal output by the master power amplifier module as a reference input to perform a frequency locking process, including: the PLL circuit of the slave power amplifier module compares the frequency difference and phase difference between the master clock signal and the signal after frequency division by its own voltage-controlled oscillator (VCO) through its internal frequency and phase detector, generating an error voltage. This error voltage is filtered by a loop filter to remove high-frequency noise and then controls the output frequency of the VCO. The output of the VCO is sent back to the frequency and phase detector through a feedback divider to form a negative feedback closed loop, so that the output frequency of the VCO gradually approaches and finally locks to the frequency of the master clock signal. The PLL lock flag of the slave power amplifier module is monitored until the PLL lock flag is valid, confirming that the slave power amplifier module has successfully locked the master synchronization signal source.

[0055] 207. Obtain the output spectrum characteristics of the main power amplifier module and the slave power amplifier module, and perform coordinated adjustment of the switching frequency of the main power amplifier module and / or the slave power amplifier module based on the output spectrum characteristics to obtain the adjusted switching frequency parameters. 208. Control the output audio signals of the main power amplifier module and the slave power amplifier module according to the adjusted switching frequency parameters, and monitor the output consistency status of the main power amplifier module and the slave power amplifier module. The adjusted switching frequency parameters are simultaneously written into the switching frequency configuration registers of both the main power amplifier module and the slave power amplifier module to ensure that their nominal switching frequencies are consistent. Audio playback start commands are then sent to both synchronously. Voltage detection circuits are coupled to the output terminals of the main power amplifier module and the slave power amplifier module respectively. The output voltage signals of the main power amplifier and the slave power amplifier are synchronously acquired at a preset sampling frequency and then converted from analog to digital to obtain the digital feedback signals of the main power amplifier and the slave power amplifier. Using the digital feedback signal of the main power amplifier as a reference, the amplitude difference and phase difference values ​​of the digital feedback signal of the slave power amplifier relative to the digital feedback signal of the main power amplifier are calculated as quantitative indicators of the output consistency status.

[0056] The final confirmed switching frequency parameters are written into the switching frequency configuration registers inside the main power amplifier module and the slave power amplifier module respectively via I²C or SPI digital communication bus, ensuring that the nominal switching frequencies of the two power amplifier modules are exactly the same. Then, an audio playback start command is simultaneously sent to both the main and slave power amplifier modules via a synchronous trigger signal line or by sending commands within the same bus cycle, causing both to begin amplifying the audio signal at the same time. During audio playback, voltage detection circuits consisting of a high-precision resistor divider network and an isolation buffer amplifier are coupled between the output of the main power amplifier module and the target load, and between the output of the slave power amplifier module and the target load, respectively, to obtain low-voltage sampling signals proportional to the output voltage. These two voltage sampling signals are simultaneously acquired by a multi-channel synchronous sampling analog-to-digital converter at a pre-set fixed sampling frequency much higher than the highest audio frequency, and converted into digital feedback signals for the main power amplifier module and the slave power amplifier module, respectively. In the digital domain, using the digital feedback signal from the main power amplifier module as a reference, the amplitudes of the two signals are compared point by point. The amplitude ratio or difference at each corresponding sampling point is calculated to obtain the amplitude difference value. Simultaneously, cross-correlation or phase difference detection algorithms are performed on the two signals to estimate the time offset by finding the optimal alignment position between the two signal waveforms. This time offset is then converted into a phase angle difference at the corresponding frequency to obtain the phase difference value. The calculated amplitude difference value and phase difference value are used as core indicators to quantitatively characterize the output consistency between the main power amplifier module and the slave power amplifier module.

[0057] 209. Perform amplitude and phase compensation on the output of the power amplifier module based on the monitoring results.

[0058] The amplitude difference value is compared with the preset amplitude tolerance range. When the amplitude difference value exceeds the amplitude tolerance range, an amplitude compensation gain coefficient is generated based on the deviation between the amplitude difference value and the target amplitude reference, and the amplitude compensation gain coefficient is applied to the multiplier node in the digital signal processing link of the power amplifier module. The phase difference value is compared with the preset phase tolerance range. When the absolute value of the phase difference value exceeds the phase tolerance range, a phase compensation delay is generated based on the positive and negative direction and magnitude of the phase difference value, and the phase compensation delay is applied to the all-pass filter or delay line node in the digital signal processing link of the power amplifier module. After applying the amplitude compensation gain coefficient and the phase compensation delay, the output voltage signal of the power amplifier module is re-acquired and compared with the output voltage signal of the main power amplifier module to verify whether the compensated amplitude difference value and phase difference value fall within the corresponding tolerance range. If so, the current compensation parameter is locked as the steady-state compensation parameter.

[0059] The calculated amplitude difference value is compared with a pre-set amplitude tolerance range. If the amplitude difference value exceeds this tolerance range, a corresponding amplitude compensation gain coefficient is generated based on the deviation direction and magnitude between the amplitude difference value and the target amplitude reference. This coefficient, greater than 1, is used to increase the output amplitude of the power amplifier module, and less than 1, it is used to decrease the output amplitude. This gain coefficient is then written to the multiplier node on the audio data channel in the digital signal processing link of the power amplifier module, so that each frame of audio data is multiplied by this coefficient before entering the pulse width modulation stage, thereby achieving real-time correction of the output amplitude. Simultaneously, the absolute value of the phase difference value is compared with a pre-set phase tolerance range. If it exceeds this tolerance range, a corresponding phase compensation gain coefficient is generated based on the positive or negative direction (leading or lagging) and absolute value of the phase difference value, with the number of sampling periods as the threshold. The phase compensation delay is applied to a configurable all-pass filter or variable delay line node in the digital signal processing link of the power amplifier module. This delay is used to compensate for the phase deviation of the output signal by directional shifting of the audio data stream. After applying the amplitude compensation gain coefficient and phase compensation delay, the output voltage signal acquisition process is restarted. The output voltage signals from the power amplifier module and the main power amplifier module are acquired synchronously again, and the compensated amplitude difference and phase difference values ​​are recalculated. These two new values ​​are then compared and verified with the corresponding tolerance range. If both fall within the tolerance range, the currently used amplitude compensation gain coefficient and phase compensation delay are locked and remain in effect as fixed compensation parameters during steady-state operation. They are not dynamically adjusted until the next system restart or recalibration is triggered.

[0060] In this embodiment of the invention, by establishing a master-slave power amplifier module working mode, and obtaining the time required for clock locking, bias establishment, and protection self-test based on historical startup timestamps or firmware default values, and then flexibly selecting the maximum value as the base delay or the sum of the three plus a dynamically adjusted safety margin as the startup delay according to the priority of startup speed and security, the optimal balance between startup speed and security is achieved while ensuring that the master power amplifier module is completely stable when the slave power amplifier module starts up. This provides a differentiated collaborative startup strategy for different application scenarios (such as fast startup requirements or high reliability requirements).

[0061] Please see Figure 3 Another embodiment of the audio output optimization method based on PBTL dual power amplifier master-slave collaboration in this invention includes: The specific execution process of steps 301 and 304 is similar to steps 101-104 in the aforementioned embodiments, and will not be repeated here.

[0062] 305. Collect the first spectrum data from the output of the main power amplifier module and the second spectrum data from the output of the power amplifier module respectively; Isolation attenuation networks are coupled between the output terminals of the main power amplifier module and the slave power amplifier module and the target load, respectively, to attenuate the high-power output signal to a preset input range. The spectrum data of the two output signals are acquired sequentially or simultaneously with the same center frequency, sweep width, and resolution bandwidth. During the acquisition process, the input audio signal is paused or a preset single-tone test signal is injected to eliminate the interference of audio content on the switching ripple spectrum measurement. The spectrum data acquired from the output terminal of the main power amplifier module is used as the first spectrum data, and the spectrum data from the output terminal of the slave power amplifier module is used as the second spectrum data.

[0063] A voltage divider attenuation network composed of high-precision non-inductive resistors is connected in series between the output of the main power amplifier module and the target load, and between the output of the slave power amplifier module and the target load. A broadband isolation transformer is connected after this attenuation network to safely attenuate the high-power BTL output signal to a voltage range allowed by the preset input range, while simultaneously achieving electrical isolation between the front and rear stages to eliminate common-mode noise interference. To avoid the music or speech frequency components in the normally played audio signal masking or interfering with the switching ripple spectrum measurement, the audio input channel is temporarily muted or paused from supplying effective audio content to the two power amplifier modules before acquiring the spectrum data. This ensures that the power amplifier modules output only a pure switching carrier signal without audio modulation. Alternatively, a single-tone test signal with constant amplitude and a frequency outside the range of human hearing is simultaneously injected into both power amplifier modules as a unified excitation source, ensuring that the operating state of the two power amplifier modules is consistent and the spectral characteristics are clearly distinguishable during the measurement. After completing the above preparations, the two attenuated signals are acquired separately. During acquisition, the center frequency, frequency sweep width, and resolution bandwidth parameters of the two signals are set exactly the same. The time domain data of the two signals are acquired simultaneously by time multiplexing or by using multi-channel parallel acquisition hardware. The same windowing processing and fast Fourier transform are performed on each data. Finally, the spectrum data obtained by the transformation at the output of the main power amplifier module is recorded as the first spectrum data, and the spectrum data obtained by the transformation at the output of the power amplifier module is recorded as the second spectrum data.

[0064] 306. Extract the switching ripple frequency component and harmonic distortion component from the first and second spectrum data; The acquired time-domain signals are windowed (e.g., using a Hanning or Blackman window) to suppress spectral leakage. Then, the two signals are converted to the frequency domain using a Fast Fourier Transform (FFT) to obtain the corresponding power or amplitude spectra. In the obtained spectral data, an amplitude threshold is set that is a certain decibel higher than the background noise floor, and all peaks exceeding this threshold are searched across the entire analysis frequency range. Since the amplitude of the fundamental frequency component of the switching ripple is usually much larger than its harmonic components and noise, the frequency corresponding to the peak with the largest amplitude is identified as the main switching ripple frequency component, and its amplitude is recorded as the main switching ripple amplitude. Building upon this, a narrow-band search window is set near integer multiples (i.e., second, third, fourth, etc.) of the main frequency. Within each window, peaks exceeding a second-order threshold are detected. If such peaks exist, they are identified as harmonic distortion components of the corresponding order, and the frequency and amplitude of each harmonic are recorded. Simultaneously, to eliminate interference peaks unrelated to harmonics, the ratio between the detected peak frequency and the main switching frequency is verified to be within a preset integer multiple tolerance range (e.g., a relative error of 0.1% to 0.5%). Only when the integer multiple relationship is satisfied is it confirmed as a harmonic distortion component. By combining peak detection with integer multiple verification, the switching ripple frequency component and its harmonic distortion components can be reliably extracted from complex spectral data.

[0065] 307. Calculate the switching frequency deviation between the main power amplifier module and the slave power amplifier module based on the switching ripple frequency component, and determine whether the current switching frequency setting causes excessive distortion based on the amplitude of the harmonic distortion component; when the switching frequency deviation exceeds the preset beat frequency suppression threshold, or the amplitude of the harmonic distortion component exceeds the preset distortion tolerance threshold, adjust the switching frequency of the slave power amplifier module to the reference based on the switching frequency of the main power amplifier module. The frequency corresponding to the largest switching ripple peak is extracted from the first spectrum data as the actual switching frequency of the main power amplifier module. Similarly, the frequency corresponding to the largest switching ripple peak is extracted from the second spectrum data as the actual switching frequency of the slave power amplifier module. Simultaneously, the amplitude values ​​of each harmonic distortion component are extracted from both the first and second spectrum data. The difference between the actual switching frequency of the slave power amplifier module and the actual switching frequency of the main power amplifier module is calculated, and the absolute value is taken as the switching frequency deviation. The extracted amplitude values ​​of each harmonic distortion component are compared with a preset distortion tolerance threshold. When the switching frequency deviates... When the difference exceeds the preset beat frequency suppression threshold, or the amplitude of any harmonic distortion component exceeds the preset distortion tolerance threshold, the switching frequency control word of the power amplifier module is gradually adjusted according to the preset step size. After each adjustment, the spectrum data is re-acquired and the switching ripple frequency component and harmonic distortion component are re-extracted. The switching frequency deviation value is recalculated and the harmonic distortion amplitude is re-compared with the distortion tolerance threshold to verify whether the switching frequency deviation value has decreased and whether the harmonic distortion amplitude has decreased, until the switching frequency deviation value converges to within the beat frequency suppression threshold and the amplitude of all harmonic distortion components has dropped to below the corresponding distortion tolerance threshold.

[0066] Peak search algorithms are performed on both spectrum streams: The largest peak is identified across the entire analysis frequency range. The frequency value corresponding to this peak is determined as the actual switching frequency of the main and slave power amplifier modules, respectively, and the amplitude of this peak is recorded as the fundamental frequency switching ripple amplitude. Subsequently, a narrow-band search window is set near integer multiples of each actual switching frequency (second harmonic, third harmonic, up to the preset highest harmonic order, e.g., fifth harmonic). Within each window, it is checked whether there is a peak exceeding the background noise threshold. If so, the amplitude value of this peak is recorded as the harmonic distortion component amplitude of the corresponding order. After obtaining the above data, the absolute value of the difference between the actual switching frequency of the slave power amplifier module and the actual switching frequency of the main power amplifier module is calculated as the switching frequency deviation value. Simultaneously, the extracted harmonic distortion component amplitudes are compared one by one with preset distortion tolerance thresholds that may be adjusted with frequency variations. When the judgment result indicates that the switching frequency deviation exceeds the preset beat frequency suppression threshold (e.g., 50Hz to 200Hz), or the amplitude of any harmonic distortion component exceeds the corresponding distortion tolerance threshold, an iterative adjustment process is initiated: the switching frequency control word of the power amplifier module is adjusted in a pre-set small step (e.g., a change in switching frequency from 10Hz to 50Hz) in the direction of reducing the deviation. After each adjustment operation, the entire process of spectrum acquisition, peak search, and harmonic extraction is immediately repeated, the updated switching frequency deviation value is recalculated, and the relationship between the amplitude of each harmonic distortion component and the corresponding threshold is re-compared. After each iteration, the changing trends of two key indicators are verified: whether the switching frequency deviation value has decreased compared to before the adjustment, and whether the amplitude of each harmonic distortion component has decreased. If both indicators are developing in a positive direction, the next step adjustment is continued in the same direction; if the deviation value increases or the amplitude of a certain harmonic deteriorates, the adjustment is immediately reversed or the step size is reduced for correction. The above iterative process continues until two convergence conditions are met simultaneously: the switching frequency deviation value has dropped to within the beat frequency suppression threshold, and the amplitude of all monitored harmonic distortion components has dropped to below the corresponding distortion tolerance threshold. At this point, the iteration is terminated and the final switching frequency value is used as the adjusted switching frequency parameter.

[0067] 308. Use the adjusted switching frequency value as the adjusted switching frequency parameter and write it into the switching frequency configuration register of the power amplifier module. The final confirmed switching frequency value after iterative convergence is used as the adjusted switching frequency parameter. This parameter is written into the switching frequency configuration register inside the slave power amplifier module via the I²C or SPI digital communication bus in the form of a register write instruction. This enables the slave power amplifier module to generate switching signals according to this frequency value in subsequent operations, thereby maintaining frequency synchronization with the main power amplifier module.

[0068] The specific execution process of steps 309 and 310 is similar to steps 106-107 in the aforementioned embodiments, and will not be repeated here.

[0069] In this embodiment of the invention, by coupling an attenuation network consisting of a high-precision non-inductive resistor and a broadband isolation transformer between the output of the power amplifier module and the target load, and by pausing the input audio or injecting a single-tone test signal, the interference of audio content and common-mode noise on the switching ripple spectrum measurement is effectively eliminated, ensuring the purity and accuracy of the spectrum acquisition. On this basis, not only are the switching ripple frequency components extracted to calculate the switching frequency deviation value, but the amplitude of each harmonic distortion component is also extracted and compared with the distortion tolerance threshold. The degree of harmonic distortion is used as an independent judgment condition to trigger the switching frequency adjustment, and a dual convergence target of switching frequency deviation and harmonic distortion amplitude is set. Thus, while suppressing beat frequency interference, the harmonic distortion component in the output signal is effectively reduced, significantly improving the purity and listening fineness of the audio output.

[0070] The above describes the audio output optimization method based on PBTL dual-amp master-slave collaboration in the embodiments of the present invention. The following describes the audio output optimization device based on PBTL dual-amp master-slave collaboration in the embodiments of the present invention. Please refer to [link to relevant documentation]. Figure 4 One embodiment of the audio output optimization device based on PBTL dual power amplifier master-slave collaboration in this invention includes: The connection module 401 is used to configure the first power amplifier module as the master power amplifier module, configure the second power amplifier module as the slave power amplifier module, and establish a PBTL output connection relationship so that the master power amplifier module and the slave power amplifier module can jointly drive the target load. The startup module 402 is used to start the main power amplifier module and monitor the synchronization reference status of the main power amplifier module. The synchronization reference status includes clock lock status, bias establishment status and protection self-test status. The calculation module 403 is used to determine the start-up delay of the slave power amplifier module according to the synchronization reference state, and to calculate the enable start-up time of the slave power amplifier module according to the start-up delay. The enable start-up time is located after the master power amplifier module completes clock locking, bias establishment and protection self-test. The locking module 404 is used to start the slave power amplifier module according to the enable start time and control the slave power amplifier module to lock the main synchronization signal source of the main power amplifier module. The processing module 405 is used to acquire the output spectrum characteristics of the main power amplifier module and the slave power amplifier module, and to perform coordinated adjustment processing on the switching frequency of the main power amplifier module and / or the slave power amplifier module according to the output spectrum characteristics to obtain the adjusted switching frequency parameters. The monitoring module 406 is used to control the output audio signals of the main power amplifier module and the slave power amplifier module according to the adjusted switching frequency parameters, and to monitor the output consistency status of the main power amplifier module and the slave power amplifier module. The compensation module 407 is used to perform amplitude and phase compensation on the output of the power amplifier module based on the monitoring results.

[0071] Please see Figure 5 Another embodiment of the audio output optimization device based on PBTL dual power amplifier master-slave collaboration in this invention includes, in addition to the aforementioned... Figure 4 In addition to the modules in the document, it also includes: Optionally, the connection module 401 can be specifically used for: Configure the first power amplifier module to master mode and the second power amplifier module to slave mode via hardware pin configuration or register configuration. Connect the non-inverting and inverting output terminals of the master power amplifier module and the slave power amplifier module in parallel according to the PBTL topology, and connect them together to the two ends of the target load. Configure the master power amplifier module as the master clock source, and electrically connect the clock input pin of the slave power amplifier module to the clock output pin of the master power amplifier module.

[0072] Optionally, the startup module 402 can be specifically used for: Send a power-on start command to the main power amplifier module and start the status monitoring timer; read the clock lock flag of the main power amplifier module, and confirm that the clock lock status is achieved when the clock lock flag is valid; read the bias establishment flag of the main power amplifier module, and confirm that the bias establishment status is achieved when the bias establishment flag is valid; read the protection self-test flag of the main power amplifier module, and confirm that the protection self-test status is passed when the protection self-test flag is normal.

[0073] Optionally, the computing module 403 includes: The acquisition unit 4031 is used to acquire the first time required for the main power amplifier module to complete clock locking, the second time required to complete bias establishment, and the third time required to complete protection self-test, respectively. The processing unit 4032 is used to take the maximum value among the first duration, the second duration and the third duration as the reference delay, or to sum the first duration, the second duration and the third duration and add a preset safety margin as the start delay; The determination unit 4033 is used to determine the enable start time by taking the start time of the main power amplifier module as the time zero point and adding the start delay to the time zero point.

[0074] Optionally, the acquisition unit 4031 can be specifically used for: Read the historical startup timestamps recorded in the internal registers of the main power amplifier module, and extract the first difference between the clock lock completion time and the startup time, the second difference between the bias establishment completion time and the clock lock completion time, and the third difference between the protection self-test completion time and the bias establishment completion time during the most recent successful startup process. Multiply the first, second, and third differences by a preset safety factor to obtain the estimated first, second, and third durations. When the main power amplifier module is starting for the first time or the historical startup record is missing, use the default typical duration preset in the firmware as the first, second, and third durations.

[0075] Optionally, the processing unit 4032 may be specifically used for: Compare the values ​​of the first, second, and third durations, and select the maximum value as the minimum safe delay benchmark to ensure that the main power amplifier module has completed the most time-consuming state establishment when it starts up. Dynamically adjust the safety margin value based on the historical fluctuation range of the main power amplifier module's startup; the larger the fluctuation range, the larger the safety margin. Use the sum of the benchmark delay and the safety margin as the startup delay, or use the sum of the first, second, and third durations and the safety margin as the startup delay, and select the appropriate calculation method according to the system's priority between startup speed and safety.

[0076] Optionally, the locking module 404 can be specifically used for: When the enable start time arrives, an enable signal is sent to the slave power amplifier module to start the slave power amplifier module; the phase-locked loop circuit of the slave power amplifier module uses the master clock signal output by the master power amplifier module as the reference input to perform the frequency locking process; the phase-locked loop locking flag bit of the slave power amplifier module is monitored until the phase-locked loop locking flag bit is valid, confirming that the slave power amplifier module has successfully locked the master synchronization signal source.

[0077] Optionally, the processing module 405 includes: Acquisition unit 4051 is used to acquire the first spectrum data from the output of the main power amplifier module and the second spectrum data from the output of the power amplifier module, respectively. Extraction unit 4052 is used to extract the switching ripple frequency component and harmonic distortion component from the first spectrum data and the second spectrum data; The adjustment unit 4053 is used to calculate the switching frequency deviation between the main power amplifier module and the slave power amplifier module based on the switching ripple frequency component, and to determine whether the current switching frequency setting causes excessive distortion based on the amplitude of the harmonic distortion component. When the switching frequency deviation exceeds the preset beat frequency suppression threshold, or the amplitude of the harmonic distortion component exceeds the preset distortion tolerance threshold, the switching frequency of the slave power amplifier module is adjusted towards the reference based on the switching frequency of the main power amplifier module. The write unit 4054 is used to take the adjusted switching frequency value as the adjusted switching frequency parameter and write it to the switching frequency configuration register of the power amplifier module.

[0078] Optionally, the acquisition unit 4051 can be specifically used for: Isolation attenuation networks are coupled between the output terminals of the main power amplifier module and the slave power amplifier module and the target load, respectively, to attenuate the high-power output signal to a preset input range. The spectrum data of the two output signals are acquired sequentially or simultaneously with the same center frequency, sweep width, and resolution bandwidth. During the acquisition process, the input audio signal is paused or a preset single-tone test signal is injected to eliminate the interference of audio content on the switching ripple spectrum measurement. The spectrum data acquired from the output terminal of the main power amplifier module is used as the first spectrum data, and the spectrum data from the output terminal of the slave power amplifier module is used as the second spectrum data.

[0079] Optionally, the adjustment unit 4053 can be specifically used for: The frequency corresponding to the largest switching ripple peak is extracted from the first spectrum data as the actual switching frequency of the main power amplifier module. Similarly, the frequency corresponding to the largest switching ripple peak is extracted from the second spectrum data as the actual switching frequency of the slave power amplifier module. Simultaneously, the amplitude values ​​of each harmonic distortion component are extracted from both the first and second spectrum data. The difference between the actual switching frequency of the slave power amplifier module and the actual switching frequency of the main power amplifier module is calculated, and the absolute value is taken as the switching frequency deviation. The extracted amplitude values ​​of each harmonic distortion component are compared with a preset distortion tolerance threshold. When the switching frequency deviates... When the difference exceeds the preset beat frequency suppression threshold, or the amplitude of any harmonic distortion component exceeds the preset distortion tolerance threshold, the switching frequency control word of the power amplifier module is gradually adjusted according to the preset step size. After each adjustment, the spectrum data is re-acquired and the switching ripple frequency component and harmonic distortion component are re-extracted. The switching frequency deviation value is recalculated and the harmonic distortion amplitude is re-compared with the distortion tolerance threshold to verify whether the switching frequency deviation value has decreased and whether the harmonic distortion amplitude has decreased, until the switching frequency deviation value converges to within the beat frequency suppression threshold and the amplitude of all harmonic distortion components has dropped to below the corresponding distortion tolerance threshold.

[0080] Optionally, the monitoring module 406 can be specifically used for: The adjusted switching frequency parameters are simultaneously written into the switching frequency configuration registers of both the main power amplifier module and the slave power amplifier module to ensure that their nominal switching frequencies are consistent. Audio playback start commands are then sent to both synchronously. Voltage detection circuits are coupled to the output terminals of the main power amplifier module and the slave power amplifier module respectively. The output voltage signals of the main power amplifier and the slave power amplifier are synchronously acquired at a preset sampling frequency and then converted from analog to digital to obtain the digital feedback signals of the main power amplifier and the slave power amplifier. Using the digital feedback signal of the main power amplifier as a reference, the amplitude difference and phase difference values ​​of the digital feedback signal of the slave power amplifier relative to the digital feedback signal of the main power amplifier are calculated as quantitative indicators of the output consistency status.

[0081] Optionally, the compensation module 407 can be specifically used for: The amplitude difference value is compared with the preset amplitude tolerance range. When the amplitude difference value exceeds the amplitude tolerance range, an amplitude compensation gain coefficient is generated based on the deviation between the amplitude difference value and the target amplitude reference, and the amplitude compensation gain coefficient is applied to the multiplier node in the digital signal processing link of the power amplifier module. The phase difference value is compared with the preset phase tolerance range. When the absolute value of the phase difference value exceeds the phase tolerance range, a phase compensation delay is generated based on the positive and negative direction and magnitude of the phase difference value, and the phase compensation delay is applied to the all-pass filter or delay line node in the digital signal processing link of the power amplifier module. After applying the amplitude compensation gain coefficient and the phase compensation delay, the output voltage signal of the power amplifier module is re-acquired and compared with the output voltage signal of the main power amplifier module to verify whether the compensated amplitude difference value and phase difference value fall within the corresponding tolerance range. If so, the current compensation parameter is locked as the steady-state compensation parameter.

[0082] above Figure 4 and Figure 5 The audio output optimization device based on PBTL dual power amplifier master-slave collaboration in this embodiment of the invention will be described in detail from the perspective of modular functional entities. The electronic device in this embodiment of the invention will be described in detail from the perspective of hardware processing.

[0083] See Figure 6 As shown, the electronic device includes a processor 600 and a memory 601. The memory 601 stores machine-executable instructions that can be executed by the processor 600. The processor 600 executes the machine-executable instructions to implement the above-mentioned audio output optimization method based on PBTL dual power amplifier master-slave collaboration.

[0084] Furthermore, Figure 6 The electronic device shown also includes a bus 602 and a communication interface 603. The processor 600, the communication interface 603 and the memory 601 are connected via the bus 602.

[0085] The memory 601 may include high-speed random access memory (RAM) and may also include non-volatile memory, such as at least one disk storage device. Communication between this system network element and at least one other network element is achieved through at least one communication interface 603 (which can be wired or wireless), such as the Internet, wide area network, local area network, metropolitan area network, etc. The bus 602 may be an ISA bus, PCI bus, or EISA bus, etc. The bus can be divided into address bus, data bus, control bus, etc. For ease of representation, Figure 6 The symbol is represented by a single double-headed arrow, but this does not mean that there is only one bus or one type of bus.

[0086] The processor 600 may be an integrated circuit chip with signal processing capabilities. In implementation, each step of the above method can be completed by the integrated logic circuitry in the hardware of the processor 600 or by instructions in software form. The processor 600 may be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it may also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this disclosure. The general-purpose processor may be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this disclosure can be directly embodied in the execution of a hardware decoding processor, or executed by a combination of hardware and software modules in the decoding processor. The software modules may reside in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. The storage medium is located in memory 601. Processor 600 reads the information in memory 601 and, in conjunction with its hardware, completes the method steps of the aforementioned embodiment.

[0087] The present invention also provides an electronic device, the computer device including a memory and a processor, wherein the memory stores computer-readable instructions, and when the computer-readable instructions are executed by the processor, the processor performs the steps of the audio output optimization method based on PBTL dual-amplifier master-slave collaboration described in the above embodiments. The present invention also provides a computer-readable storage medium, which can be a non-volatile computer-readable storage medium or a volatile computer-readable storage medium, wherein the computer-readable storage medium stores instructions, and when the instructions are executed on a computer, the computer performs the steps of the audio output optimization method based on PBTL dual-amplifier master-slave collaboration.

[0088] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0089] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0090] The above-described embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. An audio output optimization method based on PBTL dual power amplifier master-slave collaboration, characterized in that, The method includes: Configure the first power amplifier module as the master power amplifier module and the second power amplifier module as the slave power amplifier module, and establish a PBTL output connection relationship so that the master power amplifier module and the slave power amplifier module jointly drive the target load. Start the main power amplifier module and monitor the synchronization reference status of the main power amplifier module. The synchronization reference status includes clock lock status, bias establishment status and protection self-test status. The startup delay of the slave power amplifier module is determined based on the synchronization reference state, and the enable startup time of the slave power amplifier module is calculated based on the startup delay, wherein the enable startup time is located after the master power amplifier module completes clock locking, bias establishment and protection self-test; The slave power amplifier module is started according to the enabled start time, and the slave power amplifier module is controlled to lock the master synchronization signal source of the master power amplifier module; The output spectrum characteristics of the main power amplifier module and the slave power amplifier module are obtained, and the switching frequency of the main power amplifier module and / or the slave power amplifier module is coordinated and adjusted according to the output spectrum characteristics to obtain the adjusted switching frequency parameters. The main power amplifier module and the slave power amplifier module are controlled to output audio signals according to the adjusted switching frequency parameters, and the output consistency status of the main power amplifier module and the slave power amplifier module is monitored. Amplitude and phase compensation are performed on the output of the power amplifier module based on the monitoring results.

2. The audio output optimization method based on PBTL dual power amplifier master-slave collaboration according to claim 1, characterized in that, The step of configuring the first power amplifier module as the master power amplifier module, configuring the second power amplifier module as the slave power amplifier module, and establishing a PBTL output connection includes: The first power amplifier module is configured to operate in master mode and the second power amplifier module is configured to operate in slave mode by means of hardware pin configuration or register configuration. The non-inverting and inverting output terminals of the main power amplifier module are connected in parallel with the non-inverting and inverting output terminals of the slave power amplifier module according to a PBTL topology, and are connected together to the two ends of the target load. Configure the main power amplifier module as the main clock source, and electrically connect the clock input pin of the slave power amplifier module to the clock output pin of the main power amplifier module.

3. The audio output optimization method based on PBTL dual power amplifier master-slave collaboration according to claim 1, characterized in that, The step of starting the main power amplifier module and monitoring the synchronization reference status of the main power amplifier module includes: Send a power-on start command to the main power amplifier module and start the status monitoring timer; Read the clock lock flag of the main power amplifier module, and confirm that the clock lock state has been achieved when the clock lock flag is valid; Read the bias establishment flag of the main power amplifier module, and confirm that the bias establishment state has been achieved when the bias establishment flag is valid; Read the protection self-test flag of the main power amplifier module, and confirm that the protection self-test status is passed when the protection self-test flag is normal.

4. The audio output optimization method based on PBTL dual power amplifier master-slave collaboration according to claim 1, characterized in that, The step of determining the startup delay of the slave power amplifier module based on the synchronization reference state, and calculating the enable startup time of the slave power amplifier module based on the startup delay, includes: The first time required for the main power amplifier module to complete clock locking, the second time required to complete bias establishment, and the third time required to complete protection self-test are obtained respectively. The maximum value among the first duration, the second duration, and the third duration is used as the base delay, or the sum of the first duration, the second duration, and the third duration is added to a preset safety margin as the start delay; The start-up time of the main power amplifier module is taken as the zero point of time, and the result of adding the start-up delay to the zero point of time is determined as the enable start-up time.

5. The audio output optimization method based on PBTL dual power amplifier master-slave collaboration according to claim 4, characterized in that, The process of obtaining the first time required for the main power amplifier module to complete clock locking, the second time required to complete bias establishment, and the third time required to complete protection self-test includes: Read the historical startup timestamps recorded in the internal registers of the main power amplifier module, and extract the first difference between the clock lock completion time and the startup time, the second difference between the bias establishment completion time and the clock lock completion time, and the third difference between the protection self-test completion time and the bias establishment completion time during the most recent successful startup process; The first difference, the second difference, and the third difference are multiplied by a preset safety factor to obtain the estimated first duration, the second duration, and the third duration, respectively. When the main power amplifier module is starting for the first time or when historical startup records are missing, the default value of the typical duration preset in the firmware is used as the first duration, the second duration, and the third duration.

6. The audio output optimization method based on PBTL dual power amplifier master-slave collaboration according to claim 4, characterized in that, The step of using the maximum value among the first duration, the second duration, and the third duration as a baseline delay, or summing the first duration, the second duration, and the third duration and adding a preset safety margin as the start-up delay, includes: Compare the values ​​of the first duration, the second duration, and the third duration, and select the maximum value as the minimum safe delay benchmark to ensure that the main power amplifier module has completed the most time-consuming state establishment when the power amplifier module is started. The safety margin is dynamically adjusted based on the historical fluctuation range of the main power amplifier module's startup. The larger the fluctuation range, the larger the safety margin. The startup delay can be calculated by summing the baseline delay and the safety margin, or by summing the first duration, the second duration, and the third duration with the safety margin. The appropriate calculation method can be selected based on the system's priority between startup speed and safety.

7. The audio output optimization method based on PBTL dual power amplifier master-slave collaboration according to claim 1, characterized in that, The step of starting the slave power amplifier module according to the enabled start time and controlling the slave power amplifier module to lock the master synchronization signal source of the master power amplifier module includes: When the enable start time arrives, an enable signal is sent to the slave power amplifier module to start the slave power amplifier module; The phase-locked loop circuit of the slave power amplifier module uses the main clock signal output by the main power amplifier module as a reference input to perform a frequency locking process; Monitor the phase-locked loop (PLL) lock flag of the slave power amplifier module until the PLL lock flag is valid, confirming that the slave power amplifier module has successfully locked the master synchronization signal source.

8. The audio output optimization method based on PBTL dual power amplifier master-slave collaboration according to claim 1, characterized in that, The step of acquiring the output spectrum characteristics of the main power amplifier module and the slave power amplifier module, and performing coordinated adjustment processing on the switching frequency of the main power amplifier module and / or the slave power amplifier module based on the output spectrum characteristics to obtain the adjusted switching frequency parameters includes: The first spectrum data from the output of the main power amplifier module and the second spectrum data from the output of the slave power amplifier module are collected respectively. Extract the switching ripple frequency component and harmonic distortion component from the first and second spectrum data; The switching frequency deviation between the main power amplifier module and the slave power amplifier module is calculated based on the switching ripple frequency component, and the amplitude of the harmonic distortion component is used to determine whether the current switching frequency setting causes excessive distortion. When the switching frequency deviation exceeds a preset beat frequency suppression threshold or the amplitude of the harmonic distortion component exceeds a preset distortion tolerance threshold, the switching frequency of the slave power amplifier module is adjusted to the reference based on the switching frequency of the main power amplifier module. The adjusted switching frequency value is used as the adjusted switching frequency parameter and written into the switching frequency configuration register of the power amplifier module.

9. The audio output optimization method based on PBTL dual power amplifier master-slave collaboration according to claim 8, characterized in that, The process of acquiring the first spectrum data from the output of the main power amplifier module and the second spectrum data from the output of the slave power amplifier module includes: An isolation attenuation network is coupled between the output terminals of the main power amplifier module and the slave power amplifier module and the target load, respectively, to attenuate the high-power output signal to a preset input range. The spectrum data of the two output signals are acquired sequentially or simultaneously with the same center frequency, sweep width and resolution bandwidth. During the acquisition process, the input audio signal is paused or a preset single-tone test signal is injected to eliminate the interference of audio content on the switch ripple spectrum measurement. The collected spectrum data from the main power amplifier module output is used as the first spectrum data, and the spectrum data from the power amplifier module output is used as the second spectrum data.

10. The audio output optimization method based on PBTL dual power amplifier master-slave collaboration according to claim 8, characterized in that, The step of calculating the switching frequency deviation between the main power amplifier module and the slave power amplifier module based on the switching ripple frequency component, and determining whether the current switching frequency setting causes excessive distortion based on the amplitude of the harmonic distortion component; when the switching frequency deviation exceeds a preset beat frequency suppression threshold, or the amplitude of the harmonic distortion component exceeds a preset distortion tolerance threshold, adjusting the switching frequency of the slave power amplifier module towards the reference, using the switching frequency of the main power amplifier module as the reference, includes: The frequency value corresponding to the largest switching ripple peak is extracted from the first spectrum data as the actual switching frequency of the main power amplifier module. The frequency value corresponding to the largest switching ripple peak is extracted from the second spectrum data as the actual switching frequency of the slave power amplifier module. At the same time, the amplitude values ​​of each harmonic distortion component are extracted from the first spectrum data and the second spectrum data respectively. Calculate the difference between the actual switching frequency of the slave power amplifier module and the actual switching frequency of the main power amplifier module, take the absolute value as the switching frequency deviation value, and compare the amplitude values ​​of each harmonic distortion component extracted with the preset distortion tolerance threshold. When the switching frequency deviation exceeds the preset beat frequency suppression threshold, or the amplitude of any of the harmonic distortion components exceeds the preset distortion tolerance threshold, the switching frequency control word of the power amplifier module is gradually adjusted according to the preset step size. After each adjustment, the spectrum data is re-acquired and the switching ripple frequency component and harmonic distortion component are re-extracted. The switching frequency deviation is recalculated and the harmonic distortion amplitude is re-compared with the distortion tolerance threshold to verify whether the switching frequency deviation has decreased and whether the harmonic distortion amplitude has decreased, until the switching frequency deviation converges to within the beat frequency suppression threshold and the amplitude of all harmonic distortion components has decreased to below the corresponding distortion tolerance threshold.

11. The audio output optimization method based on PBTL dual power amplifier master-slave collaboration according to claim 1, characterized in that, The step of controlling the output audio signals of the main power amplifier module and the slave power amplifier module according to the adjusted switching frequency parameters, and monitoring the output consistency status of the main power amplifier module and the slave power amplifier module, includes: The adjusted switching frequency parameters are simultaneously written into the switching frequency configuration registers of the main power amplifier module and the slave power amplifier module to keep their nominal switching frequencies consistent, and audio playback start commands are sent to both synchronously. Voltage detection circuits are coupled to the output terminals of the main power amplifier module and the slave power amplifier module respectively. The main power amplifier output voltage signal and the slave power amplifier output voltage signal are synchronously acquired at a preset sampling frequency, and analog-to-digital conversion is performed respectively to obtain the main power amplifier digital feedback signal and the slave power amplifier digital feedback signal. Using the main power amplifier digital feedback signal as a reference, the amplitude difference and phase difference values ​​of the slave power amplifier digital feedback signal relative to the main power amplifier digital feedback signal are calculated as quantitative indicators of output consistency.

12. The audio output optimization method based on PBTL dual power amplifier master-slave collaboration according to claim 11, characterized in that, The step of performing amplitude and phase compensation on the output of the power amplifier module based on the monitoring results includes: The amplitude difference value is compared with a preset amplitude tolerance range. When the amplitude difference value exceeds the amplitude tolerance range, an amplitude compensation gain coefficient is generated based on the deviation between the amplitude difference value and the target amplitude reference, and the amplitude compensation gain coefficient is applied to the multiplier node in the digital signal processing link of the power amplifier module. The phase difference value is compared with a preset phase tolerance range. When the absolute value of the phase difference value exceeds the phase tolerance range, a phase compensation delay is generated according to the positive and negative direction and magnitude of the phase difference value, and the phase compensation delay is applied to the all-pass filter or delay line node in the digital signal processing link from the power amplifier module. After applying the amplitude compensation gain coefficient and the phase compensation delay, the output voltage signal of the slave power amplifier module and the output voltage signal of the main power amplifier module are re-acquired and compared for the second time to verify whether the compensated amplitude difference value and phase difference value fall within the corresponding tolerance range. If so, the current compensation parameter is locked as the steady-state compensation parameter.

13. An audio output optimization device based on PBTL dual power amplifier master-slave collaboration, characterized in that, The audio output optimization device based on PBTL dual power amplifier master-slave collaboration includes: The connection module is used to configure the first power amplifier module as the master power amplifier module, configure the second power amplifier module as the slave power amplifier module, and establish a PBTL output connection relationship so that the master power amplifier module and the slave power amplifier module jointly drive the target load. The startup module is used to start the main power amplifier module and monitor the synchronization reference state of the main power amplifier module. The synchronization reference state includes clock lock state, bias establishment state and protection self-test state. The calculation module is used to determine the startup delay of the slave power amplifier module according to the synchronization reference state, and to calculate the enable startup time of the slave power amplifier module according to the startup delay, wherein the enable startup time is located after the master power amplifier module completes clock locking, bias establishment and protection self-test; A locking module is used to activate the slave power amplifier module according to the enable start time, and control the slave power amplifier module to lock the master synchronization signal source of the master power amplifier module; The processing module is used to acquire the output spectrum characteristics of the main power amplifier module and the slave power amplifier module, and to perform coordinated adjustment processing on the switching frequency of the main power amplifier module and / or the slave power amplifier module according to the output spectrum characteristics to obtain the adjusted switching frequency parameters. The monitoring module is used to control the output audio signals of the main power amplifier module and the slave power amplifier module according to the adjusted switching frequency parameters, and to monitor the output consistency status of the main power amplifier module and the slave power amplifier module. The compensation module is used to perform amplitude and phase compensation on the output of the power amplifier module based on the monitoring results.

14. An electronic device, characterized in that, The electronic device includes: a memory and at least one processor, wherein the memory stores instructions; The at least one processor invokes the instructions in the memory to cause the electronic device to execute the audio output optimization method based on PBTL dual amplifier master-slave collaboration as described in any one of claims 1-12.

15. A computer-readable storage medium storing instructions thereon, characterized in that, When the instruction is executed by the processor, it implements the audio output optimization method based on PBTL dual power amplifier master-slave collaboration as described in any one of claims 1-12.

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