A high aspect ratio rivet deep trench capacitor and method of making same

Abstract

This invention provides a high aspect ratio riveted deep trench capacitor and its fabrication method. A high aspect ratio riveted deep trench capacitor includes: a substrate; an arrayed deep trench structure formed on the substrate, the arrayed deep trench structure comprising a plurality of periodically arranged minimum structural units; each minimum structural unit comprising a plurality of first supports, a plurality of second supports, and a plurality of riveting pillars, forming a riveting structure, the plurality of riveting structures being interconnected and / or spaced apart, defining interconnected trench spaces; and a lower electrode layer, a dielectric layer, and an upper electrode layer sequentially deposited on the arrayed deep trench structure. The fabrication method includes: depositing a metal layer on the surface of the arrayed deep trench structure, and generating a metal silicide as the lower electrode layer through a two-stage annealing process. This invention achieves improved trench structure strength, wafer-wide stress relief, improved process gas flow, and reduced lower electrode resistivity in the deep trench capacitor.

Description

Technical Field

[0001] This invention relates to a deep trench capacitor, specifically to a high aspect ratio riveted deep trench capacitor and its manufacturing method, belonging to the field of microelectronic device manufacturing technology. Background Technology

[0002] In the field of micro-nano electronics, as electronic products develop towards higher performance and higher integration, the performance requirements for silicon capacitors are becoming increasingly stringent. Silicon capacitors possess unique advantages in high-frequency characteristics, high reliability, and miniaturization, and are widely used in high-end communications, automotive electronics, high-performance computing chips, aerospace, and other fields, providing functions such as decoupling, filtering, DC blocking, and power supply matching. To meet the demands of miniaturization and high capacitance in end products, the industry commonly adopts three-dimensional high aspect ratio silicon capacitor structures, which increase capacitance density per unit area by etching high aspect ratio deep trenches or using high aspect ratio nanopillars on silicon substrates.

[0003] However, traditional high aspect ratio silicon capacitors employ an independent array layout. During etching and dielectric deposition processes, the sidewalls of deep trenches or pillars are prone to directional residual stress between the silicon substrate and the silicon matrix due to thermal expansion coefficient mismatch and lattice damage. This can lead to defects such as wafer warping and deep trench sidewall cracking, severely reducing device production yield and lifespan. Simulations show that at a 100:1 aspect ratio, the maximum internal stress of a non-riveted pillar under a 1 MPa shear force reaches 34772 MPa, far exceeding the material's tolerance limit, severely restricting the realization of high aspect ratio (>50:1) structures and product yield.

[0004] Traditional deep tanks are mostly closed structures, with no connection between tanks. When using gas-solid reaction-based processes like atomic layer deposition (ALD), this closed structure leads to uneven distribution of the reaction precursor gas at the bottom of the tank, resulting in insufficient purging. This directly causes uneven thickness and composition of the deposited dielectric or electrode layers at the top, middle, and bottom of the deep tank, insufficient step coverage, and an inability to leverage the atomic-level uniformity advantage of ALD, ultimately affecting the insulation performance and capacitance consistency of the capacitor. Simulations show that the mass flow rate transfer efficiency of gas from top to bottom in a traditional closed deep tank is only 0.047%.

[0005] Furthermore, silicon capacitors typically use low-resistivity monocrystalline silicon substrates or heavily doped polycrystalline silicon deposited via chemical vapor deposition as the bottom electrode. This traditional structure results in a relatively large parasitic resistance at the bottom electrode because the resistivity of low-resistivity monocrystalline silicon or heavily doped polycrystalline silicon (typically on the order of hundreds to thousands of μΩ·cm) is much higher than that of metallic materials. This large electrode series resistance (ESR) leads to a decrease in the capacitor's quality factor and a drop in its self-resonant frequency. For radio frequency circuits operating at high frequencies, this can severely degrade circuit performance, causing signal loss and inefficiency.

[0006] While directly filling deep trenches with metal might seem to solve the resistance problem, it faces several challenges. First, there may be poor adhesion or severe interdiffusion between the metal and the silicon substrate, leading to gaps at the internal interface and affecting device reliability. Second, filling high aspect ratio trenches with metal can easily create voids, causing electrode discontinuities. Finally, due to the requirements of high aspect ratio trenches and production efficiency, the metal electrode layer filled in the trenches is generally thin (below 50nm), which increases the series resistance of the electrodes.

[0007] Therefore, there is an urgent need for a novel high aspect ratio deep trench capacitor structure and a suitable fabrication method to solve the problems of easy trench structure collapse, easy wafer warping, poor film coverage uniformity, and high electrode resistivity in existing high aspect ratio deep trench capacitors. Summary of the Invention

[0008] Based on the above background, the purpose of this invention is to provide a high aspect ratio riveted deep trench capacitor and its fabrication method. By introducing unique riveting structural units and arranging them periodically, an internally connected trench network is constructed, thereby improving the trench structure strength of the deep trench capacitor, offsetting global wafer stress, and facilitating process gas flow. At the same time, combined with optimized atomic layer deposition and metal silicide fabrication processes, a high-performance, high-reliability, high aspect ratio riveted deep trench capacitor with electrodes under low resistivity is fabricated.

[0009] To achieve the above-mentioned objectives, the present invention provides the following technical solution:

[0010] A high aspect ratio riveted deep groove capacitor includes:

[0011] Substrate;

[0012] An arrayed deep trench structure is formed on the substrate, the arrayed deep trench structure comprising a plurality of periodically arranged minimum structural units; each minimum structural unit comprises a plurality of first supports, a plurality of second supports, and a plurality of riveting posts, the first supports, the second supports, and the riveting posts all extending upward in a direction perpendicular to the substrate, at least one riveting post being disposed between at least one first support and at least one second support to form a riveting structure, the plurality of riveting structures being interconnected and / or spaced apart and defining interconnected trench spaces;

[0013] The lower electrode layer, dielectric layer, and upper electrode layer are sequentially deposited on the arrayed deep trench structure.

[0014] By incorporating riveted posts, the previously isolated first and second supports are rigidly connected. When a single support is subjected to external force, the stress can be transferred and dispersed to the connected support through the riveted posts, preventing excessive stress concentration locally, especially at the connection between the support bottom and the substrate. This significantly enhances the overall structure's shear and collapse resistance. Multiple such riveted structures are interconnected and / or spaced apart within the smallest structural unit. They, along with other parts of the first and second supports, define interconnected trench spaces. This design creates an open network of trench spaces that runs from top to bottom and is internally interconnected, providing an excellent gas dynamics environment for subsequent atomic layer deposition processes. Reactive gases can flow smoothly, diffuse, and fill the entire trench network, and be efficiently purged, ensuring the uniformity and consistency of the deposited thin film across the entire complex three-dimensional structure surface. The lower electrode layer, dielectric layer, and upper electrode layer are sequentially deposited on all exposed surfaces of the arrayed deep trench structure, thereby utilizing the entire internal surface area of ​​the interconnected trench network to form a capacitor and maximize capacitance density.

[0015] Preferably, the first support and the second support extend parallel to the substrate in a first direction and are parallel to each other. The riveting post is fixedly connected to one end of the first support and one end of the second support in a second direction parallel to the substrate and perpendicular to the first direction. The first or second support constituting a riveting structure is configured to be connected to the riveting post of an adjacent riveting structure, or is configured as the riveting post of an adjacent riveting structure.

[0016] The aforementioned structural design allows the first support, second support, and riveted pillars to collectively form a continuous mesh structure on the substrate. In this structure, the roles of the walls are relative; that is, a support in one structural unit may simultaneously serve as a connecting point for adjacent structural units, thus forming a mechanically interlocking network structure. Furthermore, the riveted structures can be arranged in a mirror-alternating pattern, resulting in a high degree of symmetry and periodicity in the plane. This creates conditions for stress cancellation within the plane, helping to suppress wafer warpage.

[0017] Preferably, the non-connecting end of the first support or the non-connecting end of the second support is further provided with an extended wall segment, the extended wall segment extending along the second direction, and the extended wall segments of adjacent riveted structures are arranged at intervals to form an interdigitated structure.

[0018] By setting extended wall segments to form an interdigitated structure, the surface area of ​​the vertical sidewalls that can be used to form capacitors can be further increased without significantly increasing the floor area of ​​the structural unit, thereby effectively improving the capacitance density per unit area.

[0019] Preferably, the first or second support body constituting a riveting structure is shared by adjacent riveting structures.

[0020] By sharing a support structure, isolated structural features can be reduced, the overall mechanical strength and rigidity of the structure can be enhanced, and the structure can be simplified, reducing the difficulty of etching to a certain extent.

[0021] Preferably, the number of riveting structures is even, and the riveting structures in each minimum structural unit are arranged in a centrally symmetrical manner with respect to the geometric center of the minimum structural unit.

[0022] The strict central symmetry arrangement ensures that the thermal stress generated by temperature changes during processing can cancel each other out in all directions within the centrally symmetric pattern, making it difficult to form a net stress torque that causes overall wafer deformation, thus solving the wafer warping problem caused by structural asymmetry.

[0023] Preferably, the aspect ratio of the groove space is not less than 100:1. The riveted structure design is particularly suitable for such extremely high aspect ratio scenarios, and its mechanical support and gas flow capabilities make it possible to process and uniformly fill grooves with aspect ratios of 100:1 or even higher.

[0024] A method for manufacturing a high aspect ratio riveted deep trench capacitor as described above, the method comprising the following steps:

[0025] S1. Photolithography, etching and resist removal are performed on the silicon substrate to form an arrayed deep trench structure on the silicon substrate, which is composed of multiple minimum structural units arranged periodically.

[0026] S2. Using atomic layer deposition (ALD) technology, a metal layer is conformally deposited on the exposed surface of the arrayed deep trench structure. The metal layer is made of one or more of nickel, cobalt, platinum, and titanium.

[0027] S3. The silicon substrate on which the metal layer is deposited is subjected to a two-stage annealing process in a reducing atmosphere. The first stage is held at a first temperature for a first duration to allow metal atoms to diffuse into the silicon lattice and form a metal-rich phase. The second stage is held at a second temperature higher than the first temperature for a second duration to allow the metal-rich phase to further react with silicon to generate metal silicides and form a metal silicide lower electrode layer.

[0028] S4. A dielectric layer and an upper electrode layer are sequentially deposited on the lower electrode layer forming the metal silicide.

[0029] Step S1 utilizes deep reactive ion etching (DRIE) and other processes to fabricate a high aspect ratio three-dimensional structure. Because the trench spaces formed in Step S1 are interconnected open networks, the ALD reactive gas in Step S2 can diffuse uniformly and rapidly to all areas, ensuring excellent conformability and uniformity of the deposited metal layer across the entire complex structure surface. Step S3 precisely controls the temperature and time in two stages to ensure the formation of a single, uniform, and stable metal silicide phase, avoiding the formation of high-resistivity or unstable phases. Step S4 further stacks the dielectric layer and the top electrode layer, ultimately completing the fabrication of the capacitor device.

[0030] Preferably, in step S2, when the metal layer is made of nickel, the atomic layer deposition process uses nickel-ceramic and ammonia plasma as reactants, the substrate temperature is 250-300°C, the source temperature of the nickel-ceramic is 60-100°C, and the single-cycle pulse sequence of the atomic layer deposition process is as follows: nickel-ceramic vapor is introduced in a pulsed manner with nitrogen as the carrier gas for 1.5-3 seconds, nitrogen is introduced to purge to remove excess nickel-ceramic, then ammonia is introduced in a pulsed manner for 15-30 seconds, and then nitrogen is introduced again to purge to remove excess ammonia and reaction byproducts.

[0031] Preferably, in step S3, the reducing atmosphere is an Ar / H2 mixed atmosphere, the first temperature is 300-350°C, the first duration is 30-60s, the second temperature is 500-600°C, and the second duration is 30-60s.

[0032] Preferably, in step S4, the dielectric layer is one or more of hafnium oxide, zirconium oxide, silicon oxide, aluminum oxide, titanium oxide, lanthanum oxide, yttrium oxide, and silicon nitride, and the upper electrode layer is one or more of titanium nitride, tantalum nitride, niobium nitride, ruthenium, and nickel.

[0033] Compared with the prior art, the present invention has the following advantages:

[0034] The present invention discloses a high aspect ratio riveted deep slot capacitor, which connects discrete support bodies into an integral network by riveting columns. Simulation results show that the maximum internal stress of the structure under 1MPa shear force can be reduced by 86% (i.e. from 34772 MPa to 4759.2 MPa), which greatly reduces the risk of collapse and cracking of high aspect ratio structures during processing and use, and improves product yield and reliability life.

[0035] The centrally symmetrical design and periodic arrangement of the smallest structural unit in this invention enable the thermal stress of the process to cancel each other out in the plane, solving the wafer warpage problem caused by structural asymmetry. The further designed riveting structure and interdigitated design provide a larger effective sidewall surface area in the same footprint, opening up an effective path to improve capacitance density.

[0036] The unique interconnected trench space design of this invention increases the gas diffusion efficiency to 28 times that of traditional closed deep trenches (i.e., from 0.047% to 1.335%), creating an ideal gas dynamic environment for the ALD process and ensuring atomic-level uniform coverage of the electrode layer and dielectric layer throughout the deep trench, resulting in excellent capacitance consistency.

[0037] This invention utilizes metal silicides instead of traditional heavily doped silicon as the bottom electrode, reducing its resistivity by one to two orders of magnitude compared to traditional doped silicon. This directly leads to a significant decrease in the capacitor's series resistance. The low-resistance electrode ensures uniform current distribution within the deep trench, maximizing the effective area of ​​the capacitor and improving the efficiency of capacitance density. This significantly enhances the capacitor's Q value and self-resonant frequency, making it highly suitable for high-frequency applications. Attached Figure Description

[0038] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0039] Figure 1 This is a top view schematic diagram of a high aspect ratio riveted deep groove capacitor according to the present invention;

[0040] Figure 2 This is a top view of the smallest structural unit of Embodiment 1 of the present invention;

[0041] Figure 3 This is the structural model of a high aspect ratio riveted deep trench capacitor used for mass transfer rate simulation in this invention. In the figure, the "0" face is the bottom of the trench, the "50" face is 50 (m) away from the bottom of the trench, and the "100" face is 100 (m) away from the bottom of the trench.

[0042] Figure 4 This is a schematic diagram of the cross-sectional structure of a high aspect ratio riveted deep groove capacitor according to the present invention;

[0043] Figure 5 This is a top view schematic diagram of a minimum structural unit structural variation according to Embodiment 2 of the present invention;

[0044] Figure 6 This is a top view schematic diagram of another minimum structural unit structural variation of Embodiment 2 of the present invention;

[0045] Figure 7This is a top view schematic diagram of another minimum structural unit structural variation of Embodiment 2 of the present invention;

[0046] Figure 8 This is a top view of the smallest structural unit of the traditional closed deep trench structure in Comparative Example 1 of the present invention.

[0047] Figure 9 This is a top view of the smallest structural unit of the non-riveted columnar deep groove structure of Comparative Example 2 of the present invention;

[0048] Figure 10 This is a diagram showing the internal stress distribution of a column under top pressure according to Embodiment 1 of the present invention.

[0049] Figure 11 This is a stress distribution diagram inside the column of Comparative Example 2 of the present invention when subjected to top pressure;

[0050] Figure 12 This is a diagram showing the stress distribution inside the column when subjected to shear force according to Embodiment 1 of the present invention.

[0051] Figure 13 This is a stress distribution diagram inside the column of Comparative Example 2 of the present invention when subjected to shear force;

[0052] Figure 14 This is a comparison diagram of the gas mass flow rate at different positions from the bottom of the deep trenches with different structures in Embodiment 1, Comparative Example 1 and Comparative Example 2 of the present invention (the depth-to-width ratio of the trench structure is 100:1).

[0053] In the figure: 100, substrate; 200, arrayed deep trench structure; 210, minimum structural unit; 211, first support; 212, second support; 213, riveted pillar; 214, riveted structure; 215, extended wall segment; 216, interdigitated structure; 220, trench space; 310, lower electrode layer; 320, dielectric layer; 330, upper electrode layer. Detailed Implementation

[0054] The technical solution of the present invention will be further described in detail below through specific embodiments and in conjunction with the accompanying drawings. It should be understood that the implementation of the present invention is not limited to the following embodiments, and any modifications and / or alterations made to the present invention will fall within the protection scope of the present invention.

[0055] In this invention, unless otherwise specified, all parts and percentages are by weight, and the equipment and raw materials used are commercially available or commonly used in the art. Unless otherwise specified, the methods in the following embodiments are conventional methods in the art. Unless otherwise specified, the components or equipment in the following embodiments are general standard parts or components known to those skilled in the art, and their structures and principles can be learned by those skilled in the art through technical manuals or conventional experimental methods.

[0056] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings. In this detailed description, numerous specific details are set forth to facilitate explanation and provide a thorough understanding of the embodiments of the present invention. However, one or more embodiments may be practiced by those skilled in the art without these specific details.

[0057] Example 1

[0058] This embodiment provides a high aspect ratio riveted deep trench capacitor, including a substrate, an arrayed deep trench structure formed on the substrate, and a lower electrode layer, a dielectric layer and an upper electrode layer sequentially disposed on the arrayed deep trench structure.

[0059] The arrayed deep trench structure comprises a plurality of periodically arranged minimum structural units. Each minimum structural unit includes a plurality of first supports, a plurality of second supports, and a plurality of riveting posts. The first supports, second supports, and riveting posts all extend upward in a direction perpendicular to the substrate. At least one riveting post is disposed between at least one first support and at least one second support to form a riveting structure. The plurality of riveting structures are interconnected and / or spaced apart, defining interconnected trench spaces.

[0060] Specifically, such as Figure 1 As shown, the capacitor is fabricated on a silicon substrate 100, which can be single-crystal silicon or silicon-on-insulator (SOI), etc. An arrayed deep trench structure 200 is formed on the silicon substrate 100 using photolithography and deep reactive ion etching (DRIE) processes. This arrayed deep trench structure 200 is composed of nine minimum structural units 210 arranged periodically in the X and Y directions.

[0061] like Figure 2 and Figure 3As shown, each minimum structural unit 210 comprises eight riveting structures perpendicular to the substrate surface and extending in a vertical direction (Z-direction). Each riveting structure specifically includes a first support 211, a second support 212, and a riveting post 213. The first support 211 and the second support 212 are elongated strips in the top view, extending in a first direction (X-direction) parallel to the substrate and parallel to each other. The riveting post 213 extends in a second direction (Y-direction) parallel to the substrate and perpendicular to the first direction.

[0062] One end of each riveted post 213 is integrally connected to the end of a first support 211 (i.e., it is continuously constructed of silicon material itself without interfaces), and the other end of each post is integrally connected to the end of a second support 212. In this way, a first support 211, a second support 212, and a riveted post 213 connecting them together constitute a stable "U"-shaped three-dimensional frame, which is defined in this invention as a riveting structure 214.

[0063] It should be noted that in the array design of this embodiment, the first support 211, the second support 212, and the riveting post 213 together form a continuous grid structure on the substrate 100. In this structure, the functional roles of the walls are relative. For example, the first support 211 or the second support 212 constituting a riveting structure 214 can be configured to be connected to the riveting post 213 of an adjacent riveting structure 214, or directly used as the riveting post 213 of an adjacent riveting structure 214. This design achieves mechanical interlocking between structural units.

[0064] In this unit, eight riveting structures 214 are arranged alternately in a mirror-flip manner, so that the smallest structural unit 210 has good symmetry in the plane.

[0065] The gaps between all the first supports 211, 212, and riveted posts 213 collectively define an interconnected trench space 220. The trench space 220 is not an independent, closed pit, but rather a crisscrossing network of channels that extends completely from the substrate surface to the bottom of the etching. This structure offers two major advantages:

[0066] First, when a first support 211 is subjected to lateral process shear force, this force is transmitted to the second support 212 through the riveted column 213 connected to it, or to the support of the adjacent unit shared with it. This disperses the concentrated stress between the two supports, preventing stress concentration at the root of a single support from causing fracture. Simulation data shows that under a shear force of 1 MPa, the maximum internal stress of this riveted structure is only 4759.2 MPa, far lower than the 34772 MPa of the non-riveted structure, a reduction of 86%.

[0067] Secondly, during atomic layer deposition (ALD), the reactive gas can diffuse rapidly and unimpeded through the interconnected trench space 220 to the deepest part of the entire structure, and is effectively removed by the subsequent purge gas. Simulation data shows that the gas mass flow rate transfer efficiency from top to bottom of this structure is as high as 1.335%, which is 28 times that of traditional closed deep trenches, laying a physical foundation for subsequent uniform film formation.

[0068] The aspect ratio (ratio of depth D to feature width W) of the groove space 220 is not less than 100:1. The riveting design of this invention makes it possible to achieve and maintain structural stability at such a high aspect ratio.

[0069] like Figure 4 As shown, a lower electrode layer 310, a dielectric layer 320, and an upper electrode layer 330 are conformally deposited sequentially on all exposed silicon surfaces of the arrayed deep trench structure 200 (i.e., the inner walls of the trench space 220 and the unetched top surface). The lower electrode layer 310 is specifically a metal silicide (such as nickel silicide) formed through subsequent annealing. Because the connectivity of the trench space 220 ensures the uniformity of ALD deposition, these films can perfectly cover all complex three-dimensional surfaces, forming a huge effective capacitance area.

[0070] Example 2

[0071] Based on Embodiment 1, this embodiment further discloses several structural variations of the minimum structural unit 210. These structural variations are achieved by changing the shape and / or planar arrangement of the first support 211, the second support 212, and the riveted column 213.

[0072] like Figure 5 As shown, an extended wall segment 215 is added to the other end (i.e., the non-connected end) of each second support 212 that is not connected to the riveted post 213. This extended wall segment 215 extends along the second direction (Y direction) and its length is less than that of the riveted post 213. By setting the extended wall segment 215, the following effect is achieved: two adjacent riveted structures 214, with their extended wall segments 215 parallel to each other and spaced apart, form an interdigitated structure 216 within the cell. The introduction of the interdigitated structure 216 adds multiple pairs of parallel, substrate-perpendicular sidewalls without significantly increasing the overall size of the minimum cell 210. The area of ​​these newly added sidewalls can also be covered by the lower electrode layer 310, the dielectric layer 320, and the upper electrode layer 330, thereby directly increasing the effective capacitor area per unit chip area and improving capacitance density. Simultaneously, the extended wall segment 215 also slightly enhances the rigidity of the local structure.

[0073] Meanwhile, the first support 211 at the boundary of adjacent riveted structures 214 spaced apart along the second direction (Y direction) is shared by the adjacent smallest structural unit 210. By sharing the support, isolated structural features can be reduced, the mechanical strength and rigidity of the overall structure can be enhanced, the structure can be simplified, and the etching difficulty can be reduced to a certain extent.

[0074] like Figure 6 As shown, the smallest structural unit 210 is further adjusted to a comb-tooth grid structure. (As...) Figure 7 As shown, the minimum structural unit 210 is further adjusted into a multi-stage bent arm structure.

[0075] Other parts of this embodiment, such as the mirror arrangement of the riveting structure 214 and the connecting groove space 220, are the same as those in Embodiment 1, so that they also have excellent mechanical stability and gas flow.

[0076] Example 3

[0077] This embodiment provides a method for manufacturing a high aspect ratio riveted deep trench capacitor, the method comprising the following steps:

[0078] Step S1: Deep Trench Etching. A clean single-crystal silicon substrate (i.e., silicon substrate 100) is provided. First, photoresist is coated on the substrate, and then exposed using a photolithography process to define a riveted topological structure pattern (i.e., a periodic arrangement of the minimum structural units 210) as described in Example 1 or Example 2. Then, anisotropic deep etching is performed on the silicon substrate using a deep reactive ion etching (DRIE) process, such as a Bosch-based process. By controlling the number of etching cycles, an arrayed deep trench structure 200 with a depth (D) much larger than the feature width (W) is formed, while retaining the designed first support 211, second support 212, and riveted pillars 213, and simultaneously forming a longitudinally and transversely connected trench space 220. After etching, the photoresist is removed and standard cleaning is performed. The goal of this step is to ensure that the aspect ratio (D / W) of the trench space 220 is not less than 100:1.

[0079] Step S2: ALD deposition of the metal layer. The etched substrate is placed in the ALD reaction chamber. In order to achieve uniform and conformal metal layer deposition in the ultra-high aspect ratio and complex interconnected trench space 220, the following optimized process is adopted. This embodiment uses nickel (Ni) as an example for illustration, but the present invention is not limited thereto. The material of the metal layer can also be selected from one or more of cobalt (Co), platinum (Pt), and titanium (Ti).

[0080] Nickel-ceramic (NiCp2) was used as the nickel-metal-organic precursor source, and its container was heated to 60–100 °C to obtain a stable vapor pressure. Ammonia (NH3) plasma was used as the reducing reaction gas. The substrate temperature was controlled at 250–300 °C. A standard deposition cycle pulse sequence is as follows:

[0081] A pulse of NiCp2 vapor is introduced for 1.5 to 3 seconds, causing NiCp2 molecules to adsorb on all surfaces, including the bottom of the deepest trenches.

[0082] High-purity nitrogen (N2) is introduced for purging for a sufficient time to thoroughly remove excess precursors and reaction byproducts that are physically adsorbed.

[0083] A pulse of NH3 plasma is introduced for 15 to 30 seconds, and the plasma reduces the chemically adsorbed NiCp2 to metallic nickel atoms.

[0084] N2 was introduced again to purge and remove reaction byproducts.

[0085] Repeating this cycle yields a uniformly thick, shape-preserving amorphous or microcrystalline nickel layer across the entire three-dimensional structure surface. Since the trench space 220 formed in step S1 is interconnected, allowing for smooth flow of reactant and purge gases, this step achieves uniform deposition within the deep trench.

[0086] Step S3: Two-step annealing to form a metal silicide (e.g., NiSi) electrode. The silicon substrate with the deposited metal layer is transferred to a rapid thermal annealing (RTP) apparatus. An Ar / H2 mixed gas is introduced as a reducing protective atmosphere to prevent oxidation of the metal at high temperatures. Subsequently, a two-stage annealing process is performed. It should be noted that the specific temperature and time parameters for the two-stage annealing need to be adjusted adaptively according to the type of metal deposited. The following details the specific preparation conditions using nickel as the metal layer (i.e., preparing nickel silicide) as an example:

[0087] In the first stage, the substrate temperature is raised to 300–350°C at a rapid heating rate of 50–100°C / s and held at this temperature for 30–60 seconds. At this relatively mild temperature, nickel atoms begin to diffuse into the silicon lattice in contact with them, forming a nickel-rich silicide (Ni2Si) precursor, preparing for the subsequent phase transition;

[0088] In the second stage, the temperature is further increased to a specific window of 500–600°C and held for 30–60 seconds. This temperature window is crucial for generating nickel silicide (NiSi) with low resistivity and high thermal stability. At this temperature, the nickel-rich phase formed in the first stage completes atomic rearrangement and is completely transformed into uniform nickel silicide (NiSi). If the temperature is too low, the reaction will be incomplete; if the temperature is too high, it may transform into a phase with higher resistivity (NiSi2). Through this specific process, a high-performance metal silicide under-electrode layer 310 is obtained.

[0089] It is understandable that if other metals such as cobalt, platinum or titanium are used as the metal layer, those skilled in the art can adjust the temperature and time parameters of the first and second stages accordingly based on the phase transition characteristics of the corresponding metal silicide.

[0090] Step S4: Stacking of the dielectric layer and the upper electrode layer. On the formed metal silicide lower electrode layer 310, a dielectric layer 320 is deposited using atomic layer deposition (ALD). The material of the dielectric layer 320 can be selected from one, two, or a combination of multiple materials chosen from hafnium oxide, zirconium oxide, silicon oxide, aluminum oxide, titanium oxide, lanthanum oxide, yttrium oxide, and silicon nitride. The deposition temperature can be selected between 200 and 300°C depending on the material properties. Finally, an upper electrode layer 330 is deposited on the dielectric layer 320 using ALD or physical vapor deposition (PVD). The material can be one or a combination of titanium nitride, tantalum nitride, niobium nitride, ruthenium, and nickel. At this point, the complete MIM (metal / insulator / metal) capacitor structure is fabricated. Depending on the circuit design requirements, steps S2-S4 can be repeated and the materials adjusted to stack multiple layers, forming a parallel capacitor structure. For example, a MIM stack can achieve two capacitors in parallel, and a MIM stack can achieve three capacitors in parallel.

[0091] In order to objectively and quantitatively evaluate the technical advantages of the high aspect ratio riveted deep trench capacitor of the present invention, especially the mechanical properties, process compatibility and electrical performance potential brought about by its structural design, the present invention also set up comparative experiments and obtained the following simulation and calculation results.

[0092] To highlight the technical effects of the riveting structure and connecting groove of the present invention, two typical comparative structures were designed.

[0093] Comparative Example 1 is a traditional closed deep trench structure, such as Figure 8 As shown, this structure simulates the most common deep-trench capacitor design in existing technology. It consists of a series of rectangular deep trenches etched into a silicon substrate, completely isolated from each other. Each trench is separated by a thick silicon wall, with no physical connection between trenches and closed gas channels. This structure represents a typical technological state facing the dual challenges of mechanical fragility and ALD mass transfer difficulties when pursuing high aspect ratios.

[0094] Comparative Example 2 is a non-riveted column structure, as requested... Figure 9As shown. This structure is a degenerate variant of the present invention, used for evaluating the riveting effect separately. It retains an array of pillars (i.e., with a first support and a second support) similar to that in Embodiment 1 of the present invention on a silicon substrate, but completely omits the riveted pillars connecting these pillars. Therefore, while this structure also provides a large sidewall area, all pillars are isolated from each other and have no mechanical connection. This structure helps to distinguish whether the performance improvement of the present invention is due to the increased surface area alone or to the unique riveted interconnect design.

[0095] Using finite element analysis (FEA) software, static simulations were performed on the structures of Embodiment 1, Comparative Example 1, and Comparative Example 2 of the present invention under the same boundary conditions (100:1 aspect ratio, silicon material properties).

[0096] After applying a vertical pressure of 1 MPa, Figure 10 and Figure 11 Simulation results show that the maximum internal stress in the riveted structure of Embodiment 1 of the present invention occurs at the connection between the riveted column and the support, with a value of 1.3956 MPa. In contrast, the maximum stress in the non-riveted structure of Comparative Example 2 is concentrated at the root of the isolated column, reaching a value as high as 2.7737 MPa. The maximum stress in the structure of Embodiment 1 of the present invention is reduced by approximately 50% compared to Comparative Example 2. This result clearly demonstrates that by setting riveted columns to connect isolated supports into a network, the locally borne pressure can be effectively transferred and redistributed through connecting beams, avoiding fatal stress concentration at the root of the column, thereby significantly improving the structural load-bearing capacity and crush resistance in the vertical direction.

[0097] After applying an in-plane shear force of 1 MPa, Figure 12 and Figure 13 Simulation results show that the maximum shear stress of the riveted structure in Embodiment 1 of the present invention is 4759.2 MPa, while the maximum shear stress of the non-riveted structure in Comparative Example 2 increases to 34772 MPa. The maximum shear stress of the structure in Embodiment 1 of the present invention is reduced by 86% compared with Comparative Example 2. The stress value of Comparative Example 2 far exceeds the yield strength of monocrystalline silicon, indicating that structural collapse will inevitably occur in actual processes. Although the stress level of the structure in Embodiment 1 of the present invention is high, the actual failure risk is greatly reduced due to its good stress transmission path. This strongly demonstrates the core role of the riveted column in resisting shear force. It changes the stress mode of the structure, transforming the shear force from the bending deformation of a single column into a composite deformation of tension, compression, and shear of the entire riveted structure, thereby utilizing more material to dissipate energy and enhancing shear resistance.

[0098] The steady-state diffusion process of precursor gas in a deep trench structure during atomic layer deposition (ALD) was simulated using computational fluid dynamics (CFD) software. The simulation conditions were set to the same inlet pressure, gas type, and 100:1 aspect ratio.

[0099] like Figure 14 As shown, the gas mass flow rate distribution curve along the depth of the deep trench reflects the mass transfer capabilities of different structures. The mass flow rate transfer efficiency from top to bottom is defined as the percentage of the average mass flow rate at the bottom cross-section to the mass flow rate at the top inlet. Calculations show that the transfer efficiency of Comparative Example 1 is only 0.047%. This is because gas exchange at the bottom of the closed structure is extremely difficult, forming a severe diffusion barrier, making it difficult for precursors to reach the site and for reaction byproducts to be discharged, inevitably leading to uneven film deposition. The transfer efficiency of Comparative Example 2 is 0.699%. Although this is an improvement over the closed deep trench, the gas flow path is still not optimized due to the lack of lateral connections. The riveted structure of Embodiment 1 of this invention achieves a transfer efficiency as high as 1.335%. This efficiency is 1.9 times that of Comparative Example 2 and 28 times that of Comparative Example 1. The high transfer efficiency of the structure of this invention directly stems from its interconnected trench space design. This design creates two advantages: First, it provides multiple parallel diffusion paths, allowing gas to flow from multiple directions to the bottom of the deep trench, reducing flow resistance; second, it forms an efficient purge channel, enabling the purge gas after each ALD cycle to quickly remove residual reactants, preparing a clean surface for the next reaction cycle. This demonstrates that the interconnected trench design of this invention is not a simple shape change, but a targeted optimization of the gas dynamics characteristics of the ALD process, fundamentally solving the technical challenge of achieving uniform film deposition at high aspect ratios.

[0100] Capacitance density is proportional to the effective electrode area, which in turn depends directly on the specific surface area of ​​the three-dimensional structure (the total sidewall area per unit projected area). Theoretical calculations were performed on three structures, with the characteristic size of the smallest structural unit set as 'a' and the trench depth as 'H'.

[0101] The specific surface area of ​​Comparative Example 1 is (16a×a×H×16+17a×a×17) / (17a×17a)=0.886H+1.

[0102] The specific surface area of ​​Comparative Example 2 is (16a×a×H×16+15a×a×15) / (15a×15a)=1.138H+1.

[0103] The specific surface area of ​​Embodiment 1 of the present invention is (32a×a×H×8+15a×a×15) / (15a×15a)=1.138H+1.

[0104] Calculations show that the specific surface area of ​​both Embodiment 1 and Comparative Example 2 is approximately 1.138H+1. This indicates that the present invention, by introducing the riveted pillars, does not sacrifice valuable sidewall area, i.e., it does not trade mechanical strength for reduced capacitance density. The present invention and Comparative Example 2 possess the same capacitance density potential. Simultaneously, Embodiment 1 of the present invention achieves advantages in mechanical stability and process gas transport. Furthermore, the calculation formula also reveals that by adjusting parameters such as the width of the first support, the width of the second support, the size of the riveted pillars, and their spacing, the specific value of the specific surface area can be flexibly controlled, thereby providing circuit designers with the freedom to customize designs according to specific capacitance density and reliability requirements.

[0105] This article uses specific examples to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of the present invention. It should be noted that those skilled in the art can make several improvements and modifications to the present invention without departing from the principles of the present invention, and these improvements and modifications also fall within the protection scope of the claims of the present invention.

Claims

1. A high aspect ratio riveted deep groove capacitor, characterized in that: This high aspect ratio riveted deep-groove capacitor includes: Substrate (100); An arrayed deep trench structure (200) is formed on the substrate (100), the arrayed deep trench structure (200) comprising a plurality of periodically arranged minimum structural units (210); each minimum structural unit (210) comprises a plurality of first supports (211), a plurality of second supports (212) and a plurality of riveting posts (213), the first supports (211), the second supports (212) and the riveting posts (213) all extending upward in a direction perpendicular to the substrate (100), at least one riveting post (213) is disposed between at least one first support (211) and at least one second support (212) to form a riveting structure (214), the plurality of riveting structures (214) are interconnected and / or spaced apart and define interconnected trench spaces (220). The lower electrode layer (310), the dielectric layer (320) and the upper electrode layer (330) are sequentially deposited on the arrayed deep trench structure (200).

2. The high aspect ratio riveted deep slot capacitor according to claim 1, characterized in that: The first support (211) and the second support (212) extend in a first direction parallel to the substrate (100) and are parallel to each other. The riveting post (213) is fixedly connected to one end of the first support (211) and one end of the second support (212) in a second direction parallel to the substrate (100) and perpendicular to the first direction. The first support (211) or the second support (212) constituting a riveting structure (214) is configured to be connected to the riveting post (213) of the adjacent riveting structure (214), or is configured as the riveting post (213) of the adjacent riveting structure (214).

3. A high aspect ratio riveted deep slot capacitor according to claim 2, characterized in that: The non-connecting end of the first support (211) or the non-connecting end of the second support (212) is further provided with an extended wall section (215), the extended wall section (215) extends along the second direction, and the extended wall sections (215) of adjacent riveting structures (214) are arranged at intervals to form an interdigitated structure (216).

4. A high aspect ratio riveted deep groove capacitor according to claim 3, characterized in that: A first support (211) or a second support (212) constituting a riveting structure (214) is shared by adjacent riveting structures (214).

5. A high aspect ratio riveted deep slot capacitor according to claim 1, characterized in that: The number of the riveting structures (214) is even, and the riveting structures (214) in each of the minimum structural units (210) are arranged in a centrally symmetrical manner with respect to the geometric center of the minimum structural unit (210).

6. A method for manufacturing a high aspect ratio riveted deep trench capacitor as described in any one of claims 1-5, characterized in that: The method includes the following steps: S1. Photolithography, etching and resist removal are performed on the silicon substrate (100) to form an arrayed deep trench structure (200) formed by a periodic arrangement of multiple minimum structural units (210) on the silicon substrate (100). S2. Using atomic layer deposition (ALD) technology, a metal layer is conformally deposited on the exposed surface of the arrayed deep trench structure (200), wherein the material of the metal layer is selected from one or more of nickel, cobalt, platinum, and titanium. S3. The silicon substrate (100) on which the metal layer is deposited is subjected to a two-stage annealing process in a reducing atmosphere. In the first stage, the substrate is held at a first temperature for a first duration to allow metal atoms to diffuse into the silicon lattice and form a metal-rich phase. In the second stage, the substrate is held at a second temperature higher than the first temperature for a second duration to allow the metal-rich phase to further react with silicon to generate metal silicide and form a metal silicide lower electrode layer (310). S4. A dielectric layer (320) and an upper electrode layer (330) are sequentially deposited on the lower electrode layer (310) of the metal silicide.

7. A high aspect ratio riveted deep slot capacitor according to claim 6, characterized in that: In step S2, when the metal layer is made of nickel, the atomic layer deposition process uses nickel diacene and ammonia plasma as reactants, the substrate (100) temperature is 250-300°C, the source temperature of the nickel diacene is 60-100°C, and the single-cycle pulse sequence of the atomic layer deposition process is as follows: nickel diacene vapor is introduced in a pulsed manner with nitrogen as the carrier gas for 1.5-3 seconds, nitrogen is introduced to purge to remove excess nickel diacene, then ammonia is introduced in a pulsed manner for 15-30 seconds, and then nitrogen is introduced to purge to remove excess ammonia and reaction byproducts.

8. A high aspect ratio riveted deep groove capacitor according to claim 6, characterized in that: In step S3, the reducing atmosphere is an Ar / H2 mixed atmosphere, the first temperature is 300-350°C, the first duration is 30-60s, the second temperature is 500-600°C, and the second duration is 30-60s.

9. A high aspect ratio riveted deep slot capacitor according to claim 6, characterized in that: In step S4, the dielectric layer (320) is one or more of hafnium oxide, zirconium oxide, silicon oxide, aluminum oxide, titanium oxide, lanthanum oxide, yttrium oxide, and silicon nitride, and the upper electrode layer (330) is one or more of titanium nitride, tantalum nitride, niobium nitride, ruthenium, and nickel.

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