Light emitting chip, method of manufacturing the same, and optical communication system

Abstract

This invention discloses a light-emitting chip and its fabrication method, as well as an optical communication system. The light-emitting chip includes at least two light-emitting units. When the at least two light-emitting units are arranged horizontally, the light-emitting chip also includes a connecting electrode disposed on one side of the backlight surface of the light-emitting unit, which is used to connect two adjacent light-emitting units in series. And / or, when the at least two light-emitting units are arranged vertically, the light-emitting chip also includes a tunneling junction disposed between two adjacent light-emitting units, used to connect the two adjacent light-emitting units in series. This allows the light-emitting chip to form a series high-voltage chip, enabling high-voltage driving. Furthermore, the light-emitting chip exhibits a low RC constant, long carrier lifetime, and high parasitic effect. When used in optical communication, the light-emitting chip can improve the communication speed, facilitating high-speed communication.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of communication technology, and in particular to a light-emitting chip and its manufacturing method, and an optical communication system. Background Technology

[0002] Micro-LED, as a new generation of core display devices, possesses excellent characteristics such as low power consumption, high integration, high display effect, and long lifespan, and is showing a vigorous development trend. Micro-LED is applied to optical communication through co-packaged optoelectronics (CPO) technology, solving the bandwidth and energy consumption dilemma with a combination of low power consumption, high density, and easy integration. In optical communication, Micro-LED achieves high bandwidth through array parallelism: hundreds or thousands of chips ranging from a few micrometers to tens of micrometers (approximately 2Gbps per channel) are stacked in parallel, easily aggregating to a total bandwidth of Tbps. The energy consumption per bit of Micro-LED is as low as 1–2 pJ / bit; the power consumption of a 1.6Tbps optical module is reduced from 30W to 1.6W, a reduction of approximately 95%, directly solving the heat dissipation and energy consumption pain points of optical communication clusters. Micro-LED also has advantages in high-density integration, high reliability and long-distance operation, easy integration, and cost reduction. In existing technologies, when Micro-LED is applied to the field of optical communication, it suffers from high RC constant, short carrier lifetime, high parasitic effects, and driving methods unsuitable for high speeds. Summary of the Invention

[0003] This invention provides a light-emitting chip and its manufacturing method, as well as an optical communication system, to achieve high-voltage driving of the light-emitting chip. When the light-emitting chip is applied in optical communication, it can improve the communication speed.

[0004] In a first aspect, embodiments of the present invention provide a light-emitting chip for optical communication; the light-emitting chip includes at least two light-emitting units;

[0005] When at least two of the light-emitting units are arranged horizontally, the light-emitting chip further includes a connecting electrode, which is disposed on one side of the back surface of the light-emitting unit and is used to connect two adjacent light-emitting units in series.

[0006] And / or, when at least two of the light-emitting units are arranged vertically, the light-emitting chip further includes a tunneling junction, which is disposed between two adjacent light-emitting units for connecting the two adjacent light-emitting units in series.

[0007] Optionally, each of the light-emitting units includes a first semiconductor layer, a quantum well layer, and a second semiconductor layer stacked together;

[0008] When at least two light-emitting units are arranged horizontally, the surface of the second semiconductor layer of the light-emitting unit away from the quantum well layer serves as the light-emitting surface; the light-emitting unit includes a first electrode and a second electrode disposed on one side of the backlight surface, the first electrode is connected to the first semiconductor layer of one of the light-emitting units, the second electrode is connected to the second semiconductor layer of the adjacent light-emitting unit, and the connecting electrode is connected to the first electrode of one light-emitting unit and the second electrode of the other light-emitting unit.

[0009] And / or, when at least two of the light-emitting units are arranged vertically, the surface of the last second semiconductor layer away from the quantum well layer serves as the light-emitting surface; the light-emitting chip further includes a third electrode and a fourth electrode disposed on one side of the backlight surface, the third electrode being connected to the first semiconductor layer of the first light-emitting unit, and the fourth electrode being connected to the second semiconductor layer of the last light-emitting unit.

[0010] Optionally, the light-emitting unit further includes a sidewall insulating layer, which is disposed on one side of the backlight surface and covers the platform and sidewall of the light-emitting unit. A through hole is provided on the sidewall insulating layer, through which the electrode of the light-emitting unit and / or the electrode of the light-emitting chip passes. The connecting electrode is disposed on the side of the sidewall insulating layer away from the light-emitting surface.

[0011] Optionally, the light-emitting chip is circular.

[0012] Optionally, when at least two of the light-emitting units are arranged horizontally, the at least two light-emitting units are evenly distributed circumferentially.

[0013] Optionally, the light-emitting chip further includes a first lens, which is disposed on the light-emitting surface of the light-emitting unit.

[0014] In a second aspect, embodiments of the present invention provide a method for manufacturing a light-emitting chip, used to manufacture the light-emitting chip described in the first aspect; when at least two of the light-emitting units are arranged horizontally, the method for manufacturing the light-emitting chip includes:

[0015] A first epitaxial layer is formed on the substrate;

[0016] The first epitaxial layer is patterned to form at least two first mesa structures;

[0017] A first electrode, a second electrode, and a connecting electrode are formed on the platform of the first platform structure. One end of the connecting electrode is connected to a first electrode on the first platform structure, and the other end of the connecting electrode is connected to a second electrode on another adjacent first platform structure.

[0018] Remove the substrate;

[0019] Alternatively, when at least two of the light-emitting units are arranged vertically, the method for manufacturing the light-emitting chip includes:

[0020] A second epitaxial layer is formed on a substrate; the second epitaxial layer includes symmetrically periodically arranged light-emitting functional layers and tunneling junctions; the tunneling junctions are disposed between adjacent light-emitting functional layers;

[0021] The second epitaxial layer is patterned to form a second mesa structure;

[0022] A third electrode and a fourth electrode are formed on the mesa of the second mesa structure;

[0023] Remove the substrate;

[0024] Alternatively, when at least two of the light-emitting units are arranged horizontally, and when at least two of the light-emitting units are arranged vertically, the method for manufacturing the light-emitting chip includes:

[0025] A second epitaxial layer is formed on a substrate; the second epitaxial layer includes symmetrically periodically arranged light-emitting functional layers and tunneling junctions; the tunneling junctions are disposed between adjacent light-emitting functional layers;

[0026] The second epitaxial layer is patterned to form at least two second mesa structures;

[0027] A third electrode, a fourth electrode, and the connecting electrode are formed on the platform of the second platform structure. One end of the connecting electrode is connected to a third electrode on a second platform structure, and the other end of the connecting electrode is connected to a fourth electrode on another adjacent second platform structure.

[0028] Remove the substrate.

[0029] Optionally, after patterning the first epitaxial layer and / or the second epitaxial layer, the method further includes:

[0030] A sidewall insulation layer is formed on the tabletop and sidewall of the first tabletop structure and / or the second tabletop structure;

[0031] The sidewall insulating layer is patterned to form vias; the first via and the second via on the first mesa structure expose the first semiconductor layer and the second semiconductor layer in the first epitaxial layer, respectively; the third via and the fourth via on the second mesa structure expose the first semiconductor layer of the first light-emitting functional layer and the second semiconductor layer of the last light-emitting functional layer, respectively.

[0032] A first electrode and a second electrode are formed on the platform of the first mesa structure, including:

[0033] The first electrode is formed at the first via, and the second electrode is formed at the second via;

[0034] Alternatively, a third and fourth electrode may be formed on the mesa of the second mesa structure, including:

[0035] The third electrode is formed at the third via, and the fourth electrode is formed at the fourth via.

[0036] Thirdly, embodiments of the present invention provide an optical communication system, including optical fiber ports, a lens structure, and an array of light-emitting chips arranged in sequence;

[0037] The array of light-emitting chips includes a driving substrate and a plurality of light-emitting chips as described in the first aspect disposed on the driving substrate. The driving substrate is connected to the light-emitting chips, and the plurality of light-emitting chips are arranged in an array. The lens structure is used to focus the light emitted by the array of light-emitting chips into the optical fiber port.

[0038] Optionally, the lens structure includes a second lens, the orthographic projection of the second lens on the driving substrate covering the orthographic projection of any of the light-emitting chips on the driving substrate; or, the lens structure includes a plurality of microlenses arranged in an array, each of the microlenses being disposed opposite to one of the light-emitting chips.

[0039] The technical solution of this invention, by setting the light-emitting chip to include at least two light-emitting units, allows the light-emitting chips to form a series high-voltage chip by either horizontally arranged and connected in series via connecting electrodes or vertically arranged and connected in series via tunnel junctions. This enables the light-emitting chip to achieve high-voltage driving, and the chip exhibits a low RC constant, long carrier lifetime, and high parasitic effect. When used in optical communication, this light-emitting chip can improve the communication speed, facilitating high-speed communication. Attached Figure Description

[0040] Figure 1 A cross-sectional structural diagram of a light-emitting chip provided in an embodiment of the present invention;

[0041] Figure 2 A cross-sectional structural diagram of another light-emitting chip provided in an embodiment of the present invention;

[0042] Figure 3 for Figure 1 A top view schematic diagram of the provided light-emitting chip;

[0043] Figure 4 for Figure 2 A top view schematic diagram of the provided light-emitting chip;

[0044] Figure 5A top view of another light-emitting chip provided in an embodiment of the present invention;

[0045] Figure 6 A top view of another light-emitting chip provided in an embodiment of the present invention;

[0046] Figure 7 A cross-sectional structural diagram of another light-emitting chip provided in an embodiment of the present invention;

[0047] Figure 8 A cross-sectional structural diagram of another light-emitting chip provided in an embodiment of the present invention;

[0048] Figure 9 A schematic flowchart illustrating a method for fabricating a light-emitting chip according to an embodiment of the present invention;

[0049] Figure 10 A schematic flowchart illustrating another method for fabricating a light-emitting chip according to an embodiment of the present invention;

[0050] Figure 11 A schematic flowchart illustrating another method for fabricating a light-emitting chip according to an embodiment of the present invention;

[0051] Figure 12 This is a schematic diagram of the structure of an optical communication system provided in an embodiment of the present invention;

[0052] Figure 13 A cross-sectional structural diagram of an optical fiber port provided in an embodiment of the present invention;

[0053] Figure 14 This is a schematic diagram of another optical communication system provided in an embodiment of the present invention. Detailed Implementation

[0054] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, the accompanying drawings show only the parts relevant to the present invention, and not all of the structures.

[0055] This invention provides a light-emitting chip comprising at least two light-emitting units connected in series, making it a series-connected high-voltage light-emitting chip. This series-connected high-voltage light-emitting chip is driven by high voltage. Compared to conventional voltage-driven light-emitting chips, the series-connected high-voltage light-emitting chip has a lower RC constant, longer carrier lifetime, and higher parasitic effects. When the series-connected high-voltage light-emitting chip is applied to optical communication, it can improve communication speed and facilitate high-speed communication. Specifically, Figure 1 This is a cross-sectional structural diagram of a light-emitting chip provided in an embodiment of the present invention. Figure 1As shown, the light-emitting chip includes at least two light-emitting units 10; when the at least two light-emitting units 10 are arranged horizontally, the light-emitting chip also includes a connecting electrode 20, which is disposed on one side of the backlight surface of the light-emitting unit 10, and the connecting electrode 20 is used to connect two adjacent light-emitting units 10 in series.

[0056] Specifically, such as Figure 1 As shown, the light-emitting chip includes two horizontally arranged light-emitting units 10. The connecting electrode 20 can be a metal wire, metal layer, or metal block, and is disposed on one side of the backlight surface of the light-emitting unit 10. This prevents the connecting electrode 20 from blocking the light emitting side of the light-emitting unit 10, ensuring the light emission effect of the light-emitting unit 10. Simultaneously, the connecting electrode 20 connects two adjacent light-emitting units 10 in series, forming a series high-voltage chip. This allows the light-emitting chip to achieve high-voltage driving, and it exhibits a low RC constant, long carrier lifetime, and high parasitic effect. When used in optical communication, the light-emitting chip can improve the communication speed, facilitating high-speed communication.

[0057] Figure 2 This is a schematic cross-sectional view of another light-emitting chip provided in an embodiment of the present invention. Figure 2 As shown, when at least two light-emitting units 10 are arranged vertically, the light-emitting chip also includes a tunnel junction 30, which is disposed between two adjacent light-emitting units 10 for connecting the two adjacent light-emitting units 10 in series.

[0058] Specifically, such as Figure 2 As shown, the light-emitting chip includes two vertically arranged light-emitting units 10, each with the same structural arrangement. For example, when the light-emitting unit 10 includes a stacked P-type semiconductor layer, a quantum well layer, and an N-type semiconductor layer, the arrangement of each light-emitting unit 10 is the same; that is, the P-type semiconductor layer of the next light-emitting unit 10 is adjacent to the N-type semiconductor layer of the previous light-emitting unit 10, or the N-type semiconductor layer of the next light-emitting unit 10 is adjacent to the P-type semiconductor layer of the previous light-emitting unit 10. A tunnel junction 30 is provided between adjacent light-emitting units 10. In this case, the tunnel junction 30 can connect two adjacent light-emitting units 10 in series, forming a series high-voltage chip. This allows the light-emitting chip to achieve high-voltage driving, and it exhibits a low RC constant, long carrier lifetime, and high parasitic effect. When the light-emitting chip is used in the field of optical communication, it can improve the communication speed of optical communication, which is beneficial for achieving high-speed communication. For example, the P-type semiconductor layer of the next light-emitting unit 10 is electrically connected to the N-type semiconductor layer of the previous light-emitting unit 10 through a tunnel junction 30, or the N-type semiconductor layer of the next light-emitting unit 10 is electrically connected to the P-type semiconductor layer of the previous light-emitting unit 10 through a tunnel junction 30.

[0059] In some embodiments, the light-emitting chip includes multiple light-emitting units 10, with at least two light-emitting units 10 arranged vertically. A tunnel junction 30 is provided between adjacent light-emitting units 10, enabling the two vertically arranged light-emitting units 10 to be connected in series to form a light-emitting unit group. Then, adjacent light-emitting unit groups are connected in series via connecting electrodes 20, further increasing the driving voltage of the light-emitting chip. When the light-emitting chip is used in optical communication, it can further improve the communication speed, facilitating high-speed communication.

[0060] The technical solution of this embodiment, by setting the light-emitting chip to include at least two light-emitting units, allows the light-emitting chips to form a series high-voltage chip by means of either horizontal arrangement via connecting electrodes or vertical arrangement via tunnel junctions. This enables the light-emitting chip to achieve high-voltage driving, and results in a low RC constant, long carrier lifetime, and high parasitic effect. When used in optical communication, this light-emitting chip can improve communication speed and facilitate high-speed communication.

[0061] Continue to refer to Figure 1 and Figure 2 Each light-emitting unit 10 includes a first semiconductor layer 11, a quantum well layer 12, and a second semiconductor layer 13 stacked together;

[0062] When at least two light-emitting units 10 are arranged horizontally, the surface of the second semiconductor layer 13 of the light-emitting unit 10 away from the quantum well layer 12 serves as the light-emitting surface; the light-emitting unit 10 includes a first electrode 14 and a second electrode 15 disposed on one side of the backlight surface, the first electrode 14 is connected to the first semiconductor layer 11 of one of the light-emitting units 10, the second electrode 15 is connected to the second semiconductor layer 13 of the adjacent light-emitting unit 10, and the connecting electrode 20 is connected to the first electrode 14 of one light-emitting unit 10 and the second electrode 15 of the other light-emitting unit 10.

[0063] And / or, when at least two light-emitting units 10 are arranged vertically, the surface of the last second semiconductor layer 13 away from the quantum well layer 12 serves as the light-emitting surface; the light-emitting chip also includes a third electrode 16 and a fourth electrode 17 disposed on one side of the backlight surface, the third electrode 16 being connected to the first semiconductor layer 11 of the first light-emitting unit 10, and the fourth electrode 17 being connected to the second semiconductor layer 13 of the last light-emitting unit 10.

[0064] Specifically, the first semiconductor layer 11 can be a P-type semiconductor layer, and the second semiconductor layer 13 can be an N-type semiconductor layer. Alternatively, the first semiconductor layer 11 can be an N-type semiconductor layer, and the second semiconductor layer 13 can be a P-type semiconductor layer. Figure 1As shown, when at least two light-emitting units 10 are arranged horizontally, each light-emitting unit 10 further includes a current spreading layer 18 to improve the current spreading performance of the first semiconductor layer 11. The current spreading layer 18 can be a transparent conductive layer. For example, the material of the current spreading layer 18 can be ITO. When the first semiconductor layer 11 can be a P-type semiconductor layer and the second semiconductor layer 13 can be an N-type semiconductor layer, the current spreading layer 18 can be disposed on the side of the first semiconductor layer 11 away from the quantum well layer 12. In this case, the first electrode 14 is connected to the first semiconductor layer 11 through the current spreading layer 18. Figure 2 As shown, when at least two light-emitting units 10 are arranged vertically, along the direction from the backlight surface of the light-emitting chip to the light-emitting surface of the light-emitting chip, the first light-emitting unit 10 can also have a current spreading layer 18, which is connected to the first semiconductor layer 11. When the third electrode 16 is connected to the first semiconductor layer 11 of the first light-emitting unit 10, it can be connected to the first semiconductor layer 11 of the first light-emitting unit 10 through the current spreading layer 18.

[0065] The first electrode 14 and the second electrode 15 are disposed on the back surface of the light-emitting chip, which can prevent the first electrode 14 and the second electrode 15 from blocking the light emission of the light-emitting chip, thus ensuring the light emission effect of the light-emitting chip. For example, Figure 1 As shown, the light-emitting unit 10 has a mesa structure, which includes a first mesa formed by a first semiconductor layer 11 and a second mesa formed by a second semiconductor layer 13. A first electrode 14 is disposed on the side of the first mesa away from the light-emitting surface, and a second electrode 15 is disposed on the second mesa. In this case, both the first electrode 14 and the second electrode 15 are located on the back surface of the light-emitting chip, allowing the light-emitting chip to function as a flip-chip structure. Furthermore, when multiple light-emitting units 10 are connected in series, the second electrode 15, serving as an electrode of the light-emitting chip, extends from the second mesa to the first mesa, ensuring that both electrodes of the light-emitting chip are located on the first mesa. This reduces the difficulty of flip-chip connection of the light-emitting chip and guarantees the light-emitting effect of the chip. For example, as... Figure 1 As shown, the second electrode 15 of the left light-emitting unit 10 is connected to the first electrode 14 of the right light-emitting unit 10. The second electrode 15 of the right light-emitting unit 10 extends to the first platform, and both it and the first electrode 14 of the left light-emitting unit 10 are located on the first platform. When the first semiconductor layer 11 is a P-type semiconductor layer and the second semiconductor layer 13 can be an N-type semiconductor layer, the first electrode 14 is a P-electrode and the second electrode 15 is an N-electrode. When connecting two adjacent light-emitting units 10 in series with the connecting electrode 20, the P-electrode of one light-emitting unit 10 can be connected, and then the N-electrode of the other light-emitting unit 10 can be connected, thus realizing the series connection of the light-emitting units 10. At this time, the N-electrode of one light-emitting unit 10 serves as the N-electrode of the light-emitting chip, and the P-electrode of the other light-emitting unit 10 serves as the P-electrode of the light-emitting chip.

[0066] The third electrode 16 and the fourth electrode 17 are also disposed on the back surface of the light-emitting chip, which can prevent the third electrode 16 and the fourth electrode 17 from blocking the light emission of the light-emitting chip and ensure the light emission effect of the light-emitting chip. For example, Figure 2 As shown, along the direction from the backlight surface of the light-emitting chip to the light-emitting surface, the mesa structure includes a third mesa formed by the first first semiconductor layer 11 and a fourth mesa formed by the last second semiconductor layer 13. The third electrode 16 is disposed on the side of the third mesa away from the light-emitting surface, and the fourth electrode 17 is disposed on the fourth mesa and extends to the third mesa. This arrangement, with both the third electrode 16 and the fourth electrode 17 located on the third mesa, helps reduce the difficulty of flip-chip bonding of the light-emitting chip and ensures the light-emitting effect of the chip. When the first semiconductor layer 11 is a P-type semiconductor layer and the second semiconductor layer 13 can be an N-type semiconductor layer, the third electrode 16 is a P-electrode and the fourth electrode 17 is an N-electrode. A tunnel junction 30 is disposed between the second semiconductor layer 13 of the previous light-emitting unit 10 and the first semiconductor layer 11 of the next light-emitting unit 10, used to realize the series connection of two adjacent light-emitting units 10.

[0067] Continue to refer to Figure 1 and Figure 2 The light-emitting unit 10 also includes a sidewall insulating layer 19, which is disposed on one side of the backlight surface and covers the platform and sidewall of the light-emitting unit 10. A through hole is provided on the sidewall insulating layer 19, through which the electrodes of the light-emitting unit 10 and / or the electrodes of the light-emitting chip pass. The connecting electrode 20 is disposed on the side of the sidewall insulating layer 19 away from the light-emitting surface.

[0068] Specifically, the sidewall insulating layer 19 can be formed using an atomic layer deposition process. When the light-emitting unit 10 includes a current spreading layer 18, the sidewall insulating layer 19 is disposed on the side of the current spreading layer 18 away from the first semiconductor layer 11. The sidewall insulating layer 19 covers the current spreading layer 18 and extends along the mesa towards the sidewall until it covers all sidewalls of the light-emitting unit 10, thus insulating adjacent film layers of the light-emitting unit 10. Simultaneously, two vias are provided on the sidewall insulating layer 19, with an electrode corresponding to each via, allowing the electrode to connect to the corresponding semiconductor layer through the via. Then, the connecting electrode 20 is disposed on the side of the sidewall insulating layer 19 away from the light-emitting surface, preventing short-circuit connections between the connecting electrode 20 and other film layers. For example, as... Figure 1As shown, a first via and a second via are provided on the sidewall insulating layer 19. The first via is located on the first mesa and extends through to the current spreading layer 18. The first electrode 14 is connected to the current spreading layer 18 through the first via. The second via is located on the second mesa and extends through to the second semiconductor layer 13. The second electrode 15 is connected to the second semiconductor layer 13 through the second via. A connecting electrode 20 is disposed on the sidewall insulating layer 19 and connected to the first electrode 14 of one light-emitting unit 10 and the second electrode 15 of another light-emitting unit 10. While ensuring that the connecting electrode 20 is insulated from other film layers, a series connection between two adjacent light-emitting units 10 can be achieved. Figure 2 As shown, a third via and a fourth via are provided on the sidewall insulating layer 19. The third via is located on the third mesa and extends through to the current spreading layer 18. The third electrode 16 is connected to the current spreading layer 18 through the third via. The fourth via is located on the fourth mesa and extends through to the second semiconductor layer 13. The fourth electrode 17 is connected to the second semiconductor layer 13 through the fourth via. The fourth electrode 17 extends through the sidewall insulating layer 19 to the third mesa, facilitating flip-chip bonding of the light-emitting chip.

[0069] It should be noted that when at least two light-emitting units 10 are arranged horizontally, after the at least two light-emitting units 10 form a mesa structure, an insulating layer can be filled between the second semiconductor layers 13 of the at least two light-emitting units 10. Then, when forming the sidewall insulating layer 19, the sidewall insulating layer 19 can cover the insulating layer, which can ensure the insulation between adjacent light-emitting units 10. Alternatively, in other embodiments, after the at least two light-emitting units 10 form a mesa structure, the sidewall insulating layer 19 can be directly formed between the second semiconductor layers 13 of the at least two light-emitting units 10, which can also ensure the insulation between adjacent light-emitting units 10. This is not limited here.

[0070] Continue to refer to Figure 1 and Figure 2 The light-emitting unit 10 also includes a DBR reflective layer 110, which is disposed on the side of the sidewall insulating layer 19 away from the first semiconductor layer 11. The DBR reflective layer 110 can reflect the light emitted by the light-emitting unit 10 to the light-emitting surface, thereby improving the light extraction efficiency of the light-emitting chip. When at least two light-emitting units 10 are arranged horizontally, each light-emitting unit 10 may include a DBR reflective layer 110. When at least two light-emitting units 10 are arranged vertically, the first light-emitting unit 10 has a DBR reflective layer 110 in the direction from the backlight surface of the light-emitting chip to the light-emitting surface of the light-emitting chip, ensuring the light extraction efficiency of all light-emitting units 10.

[0071] It should be noted that when the light-emitting unit 10 includes a DBR reflective layer 110, the electrodes of the light-emitting chip are located on the side of the DBR reflective layer 110 away from the first semiconductor layer 11. In this case, the DBR reflective layer 110 also has vias, which at least partially overlap with the vias on the sidewall insulating layer 19, so that the electrodes of the light-emitting chip are connected to the semiconductor layer through the vias on the DBR reflective layer 110 and the vias on the sidewall insulating layer 19.

[0072] Figure 3 for Figure 1 A top view schematic diagram of the provided light-emitting chip structure. Figure 4 for Figure 2 A top-view structural diagram of the provided light-emitting chip. (See diagram below.) Figure 3 and Figure 4 As shown, the light-emitting chip is circular.

[0073] Specifically, Figure 3 The example illustrates a light-emitting chip comprising two horizontally arranged light-emitting units 10, each of which is semi-circular and positioned opposite each other, forming a circular shape. This facilitates lens fabrication and improves the matching degree between the shape of the light-emitting units 10 and the lens when a lens is subsequently placed. Specifically, in Figure 3 In the diagram, the dashed semicircle on the left represents the edge L1 of the second mesa of the left light-emitting unit 10. At this point, a portion of the second mesa is etched at the second electrode 15 of the left light-emitting unit 10, causing the edge L1 of the second mesa to be concave inwards towards the semicircle. The dashed semicircle on the right represents the edge L2 of the second mesa of the right light-emitting unit 10. The second electrode 15 of the left light-emitting unit 10 is connected to the first electrode 14 of the right light-emitting unit 10 via the connecting electrode 20. The first electrode 14 of the left light-emitting unit 10 and the second electrode 15 of the right light-emitting unit 10 are located on the left and right sides of the light-emitting chip, respectively, serving as the two electrodes of the chip. Figure 4 The illustration exemplifies a light-emitting chip comprising two vertically arranged light-emitting units 10, each of which is circular and overlaps in the vertical direction. The dashed line L3 surrounding the circle represents the portion of the fourth electrode 17 extending from the fourth platform to the third platform. This electrode can be positioned around the sidewall of the light-emitting unit 10, improving the connection reliability of the fourth electrode 17 and simultaneously reducing its impedance. The solid semicircle L4 on the left and the solid line L5 on the right represent the fourth electrode 17 and the third electrode 16 on the first platform, respectively, serving as electrodes of the light-emitting chip.

[0074] Continue to refer to Figure 3 When at least two light-emitting units 10 are arranged horizontally, at least two light-emitting units 10 are evenly distributed circumferentially.

[0075] Specifically, when the light-emitting chip includes two horizontally arranged light-emitting units 10, each light-emitting unit 10 is a semicircle and is evenly distributed along the circumference of the light-emitting chip, so that the semicircles of the two light-emitting units 10 form the circle of the light-emitting chip.

[0076] Figure 5 This is a top view schematic diagram of another light-emitting chip provided in an embodiment of the present invention, as shown below. Figure 5 As shown, the light-emitting chip may also include three light-emitting units 10. When the three light-emitting units 10 are arranged horizontally, they can be evenly distributed along the circumference of the light-emitting chip. In this case, the shape of each light-emitting unit 10 can be one-third of a circle, forming the circle of the light-emitting chip. When the light-emitting units 10 are connected in series, the first electrode 14 of the first light-emitting unit 10 can be connected to the second electrode 15 of the second light-emitting unit 10, and the first electrode 14 of the second light-emitting unit 10 can be connected to the second electrode 15 of the third light-emitting unit 10. The second electrode 15 of the first light-emitting unit 10 and the first electrode 14 of the third light-emitting unit 10 serve as electrodes of the light-emitting chip.

[0077] Figure 6 This is a top view schematic diagram of another light-emitting chip provided in an embodiment of the present invention, as shown below. Figure 6 As shown, the light-emitting chip may also include four light-emitting units 10. When the four light-emitting units 10 are arranged horizontally, they can be evenly distributed along the circumference of the light-emitting chip. In this case, the shape of each light-emitting unit 10 can be a quarter circle, forming the circle of the light-emitting chip. When the light-emitting units 10 are connected in series, the first electrode 14 of the first light-emitting unit 10 can be connected to the second electrode 15 of the second light-emitting unit 10, the first electrode 14 of the second light-emitting unit 10 can be connected to the second electrode 15 of the third light-emitting unit 10, and the first electrode 14 of the third light-emitting unit 10 can be connected to the second electrode 15 of the fourth light-emitting unit 10. The second electrode 15 of the first light-emitting unit 10 and the first electrode 14 of the fourth light-emitting unit 10 serve as electrodes of the light-emitting chip.

[0078] It should be noted that the number of light-emitting units 10 in the above-described light-emitting chip is merely an example and is not limited here. In other embodiments, the number of light-emitting units 10 in the light-emitting chip can be arbitrary. The more light-emitting units 10 in the light-emitting chip, the higher the driving voltage of the light-emitting chip, which is more conducive to improving the transmission speed of optical communication.

[0079] Figure 7 This is a cross-sectional structural diagram of another light-emitting chip provided in an embodiment of the present invention. Figure 8 This is a schematic cross-sectional view of another light-emitting chip provided in an embodiment of the present invention. Figure 7 and Figure 8As shown, the light-emitting chip also includes a first lens 40, which is disposed on the light-emitting surface of the light-emitting unit 10.

[0080] Specifically, the first lens 40 has a light-converging function. The first lens 40 is disposed on the light-emitting surface of the light-emitting unit 10, which allows the light emitted by the light-emitting unit 10 to be converged and coupled after passing through the first lens 40, which is beneficial to improving the transmission quality of optical communication.

[0081] This invention also provides a method for manufacturing a light-emitting chip, which is used to manufacture the light-emitting chip provided in any embodiment of this invention. Figure 9 This is a schematic flowchart illustrating a method for fabricating a light-emitting chip according to an embodiment of the present invention. The method for fabricating a light-emitting chip includes at least two horizontally arranged light-emitting units. Figure 9 As shown, the method for manufacturing this light-emitting chip includes:

[0082] S110, Form a first epitaxial layer on the substrate.

[0083] Specifically, the first epitaxial layer may include a second semiconductor layer, a quantum well layer, and a first semiconductor layer sequentially stacked on a substrate. When the light-emitting unit includes a current spreading layer, the first epitaxial layer may also include a current spreading layer. The current spreading layer is disposed on the side of the first semiconductor layer away from the quantum well layer.

[0084] S120. Pattern the first epitaxial layer to form at least two first mesa structures.

[0085] Specifically, an inductively coupled plasma (ICP) etching process can be used to etch the first epitaxial layer to form at least two first mesa structures. Each first mesa structure includes a first mesa and a second mesa. The first mesa exposes the surface of the current spreading layer, and the second mesa is larger than the first mesa, thus exposing the surface of the second semiconductor layer. Furthermore, the second semiconductor layer is disconnected, thus insulating adjacent first mesa structures.

[0086] S130. A first electrode, a second electrode, and a connecting electrode are formed on the platform of the first platform structure. One end of the connecting electrode is connected to the first electrode on a first platform structure, and the other end of the connecting electrode is connected to the second electrode on another adjacent first platform structure.

[0087] Specifically, after forming the first mesa structure, a first electrode can be formed on one side of the first mesa, and a second electrode can be formed on one side of the second mesa. Simultaneously, a connecting electrode is formed, such that the connecting electrode contacts and connects with the second electrode of one first mesa structure and with the first electrode of the other first mesa structure, thus achieving a series connection between two adjacent light-emitting units. Furthermore, the second electrode on one first mesa structure can extend to the first mesa, so that the two electrodes of the light-emitting chip are located on the same plane.

[0088] S140, Remove substrate.

[0089] Figure 10 This is a schematic flowchart illustrating another method for fabricating a light-emitting chip according to an embodiment of the present invention. The method for fabricating a light-emitting chip includes at least two vertically arranged light-emitting units. Figure 10 As shown, the method for manufacturing this light-emitting chip includes:

[0090] S210. A second epitaxial layer is formed on the substrate; the second epitaxial layer includes symmetrically periodically arranged light-emitting functional layers and tunneling junctions; the tunneling junctions are disposed between adjacent light-emitting functional layers.

[0091] Specifically, when at least two light-emitting units are arranged vertically, the second epitaxial layer includes symmetrically periodically arranged light-emitting functional layers and tunneling junctions. Each light-emitting functional layer includes a second semiconductor layer, a quantum well layer, and a first semiconductor layer sequentially stacked on the substrate. Tunneling junctions are disposed between adjacent light-emitting functional layers, enabling series connection between them. When the light-emitting unit includes a current spreading layer, the second epitaxial layer may also include a current spreading layer. The current spreading layer is disposed on the side of the first semiconductor layer furthest from the substrate.

[0092] S220. Pattern the second epitaxial layer to form the second mesa structure.

[0093] Specifically, the second epitaxial layer can be etched using an inductively coupled plasma (ICP) etching process to form a second mesa structure. The second mesa structure includes a third mesa and a fourth mesa. The third mesa exposes the surface of the current spreading layer, and the fourth mesa is larger than the third mesa, thus exposing the surface of the second semiconductor layer closest to the substrate.

[0094] S230, the third and fourth electrodes are formed on the platform of the second platform structure.

[0095] Specifically, after the second mesa structure is formed, a third electrode can be formed on one side of the third mesa and a fourth electrode can be formed on one side of the fourth mesa. The fourth electrode can extend to the third mesa, so that the two electrodes of the light-emitting chip are located on the same plane.

[0096] S240, Remove substrate.

[0097] Figure 11 This is a schematic flowchart illustrating another method for fabricating a light-emitting chip according to an embodiment of the present invention. The method includes at least two horizontally arranged light-emitting units and at least two vertically arranged light-emitting units. For example... Figure 11 As shown, the method for manufacturing this light-emitting chip includes:

[0098] S310. A second epitaxial layer is formed on the substrate; the second epitaxial layer includes symmetrically periodically arranged light-emitting functional layers and tunneling junctions; the tunneling junctions are disposed between adjacent light-emitting functional layers.

[0099] Specifically, a tunnel junction is disposed between adjacent light-emitting functional layers, enabling series connection between them. Each light-emitting functional layer can form a light-emitting unit along the vertical direction. When the light-emitting unit includes a current spreading layer, the second epitaxial layer can also include a current spreading layer. The current spreading layer is disposed on the side of the first semiconductor layer furthest from the substrate.

[0100] S320. Pattern the second epitaxial layer to form at least two second mesa structures.

[0101] Specifically, at least two second mesa structures include a third mesa and a fourth mesa. The third mesa exposes the surface of the current spreading layer, and the fourth mesa is larger than the third mesa and exposes the surface of the second semiconductor layer closest to the substrate. The second semiconductor layer closest to the substrate is disconnected, thus insulating adjacent second mesa structures.

[0102] S330. A third electrode, a fourth electrode, and a connecting electrode are formed on the platform of the second platform structure. One end of the connecting electrode is connected to the third electrode on a second platform structure, and the other end of the connecting electrode is connected to the fourth electrode on another adjacent second platform structure.

[0103] Specifically, after forming the second mesa structure, a third electrode can be formed on one side of the third mesa and a fourth electrode on one side of the fourth mesa. Simultaneously, a connecting electrode is formed, making contact with the fourth electrode of one second mesa structure and with the third electrode of another second mesa structure, thus achieving series connection of the light-emitting units in adjacent second mesa structures. Furthermore, the fourth electrode on one second mesa structure can extend to the third mesa, so that the two electrodes of the light-emitting chip are located on the same plane.

[0104] S340, Remove substrate.

[0105] The technical solution of this embodiment, by setting the light-emitting chip to include at least two light-emitting units, allows the light-emitting chips to form a series high-voltage chip by means of either horizontal arrangement via connecting electrodes or vertical arrangement via tunnel junctions. This enables the light-emitting chip to achieve high-voltage driving, and results in a low RC constant, long carrier lifetime, and high parasitic effect. When used in optical communication, this light-emitting chip can improve communication speed and facilitate high-speed communication.

[0106] In some embodiments, when the light-emitting unit includes a sidewall insulating layer and a DBR reflective layer, after patterning the first epitaxial layer and / or the second epitaxial layer, the method further includes:

[0107] A sidewall insulation layer is formed on the tabletop and sidewall of the first tabletop structure and / or the second tabletop structure.

[0108] Specifically, when patterning the first epitaxial layer to form the first mesa structure, a sidewall insulating layer can be formed on the mesa and sidewalls of the first mesa structure. When patterning the second epitaxial layer to form the second mesa structure, a sidewall insulating layer can be formed on the mesa and sidewalls of the second mesa structure. When the light-emitting unit includes a DBR reflective layer, the DBR reflective layer can be formed after the sidewall insulating layer is formed, and the DBR reflective layer covers the sidewall insulating layer.

[0109] The sidewall insulating layer is patterned to form vias; the first via and the second via on the first mesa structure expose the first semiconductor layer and the second semiconductor layer in the first epitaxial layer, respectively; the third via and the fourth via on the second mesa structure expose the first semiconductor layer of the first light-emitting functional layer and the second semiconductor layer of the last light-emitting functional layer, respectively.

[0110] Specifically, after forming the sidewall insulating layer, the sidewall insulating layer can be etched to form vias. When the light-emitting unit includes a DBR reflective layer, vias can be formed simultaneously by etching the sidewall insulating layer and the DBR reflective layer after forming the DBR reflective layer. In this case, the vias can penetrate both the sidewall insulating layer and the DBR reflective layer. When an electrode is formed on the side of the DBR reflective layer away from the substrate, the electrode can be connected to the semiconductor layer through the vias. For example, when at least two first mesa structures are formed after the first epitaxial layer is patterned, a first via can be formed on the first mesa of the first mesa structure and a second via can be formed on the second mesa when the sidewall insulating layer is patterned. The first via exposes the first semiconductor layer in the first epitaxial layer. Alternatively, when the first epitaxial layer includes a current spreading layer, the first via exposes the current spreading layer. The second via exposes the second semiconductor layer in the first epitaxial layer. When a second mesa structure is formed after the second epitaxial layer is patterned, a third via can be formed on the third mesa of the second mesa structure and a fourth via can be formed on the fourth mesa when the sidewall insulating layer is patterned. The third via exposes the first semiconductor layer or current spreading layer furthest from the substrate in the second epitaxial layer, and the fourth via exposes the second semiconductor layer closest to the substrate in the second epitaxial layer. The sidewall insulating layer prevents short-circuit connections between the electrodes and connecting electrodes and other film layers. The DBR reflective layer reflects the light emitted by the light-emitting unit, improving the light extraction efficiency of the light-emitting unit.

[0111] A first electrode and a second electrode are formed on the mesa of the first mesa structure, including:

[0112] A first electrode is formed at the first via, and a second electrode is formed at the second via;

[0113] Alternatively, a third and fourth electrode may be formed on the mesa of the second mesa structure, including:

[0114] A third electrode is formed at the third via, and a fourth electrode is formed at the fourth via.

[0115] Specifically, when forming a first electrode at a first via and a second electrode at a second via, the first electrode can be connected to a first semiconductor layer through the first via, and the second electrode can be connected to a second semiconductor layer through the second via. When forming a third electrode at a third via and a fourth electrode at a fourth via, the third electrode can be connected to the first semiconductor layer furthest from the substrate through the third via, and the fourth electrode can be connected to the second semiconductor layer closest to the substrate through the fourth via.

[0116] This invention also provides an optical communication system. Figure 12 This is a schematic diagram of the structure of an optical communication system provided in an embodiment of the present invention. Figure 12As shown, the optical communication system includes an optical fiber port 100, a lens structure 200, and an array of light-emitting chips 300 arranged in sequence. The array of light-emitting chips 300 includes a driving substrate 301 and a plurality of light-emitting chips 302 provided in any embodiment of the present invention disposed on the driving substrate 301. The driving substrate 301 is connected to the light-emitting chips 302, and the plurality of light-emitting chips 302 are arranged in an array. The lens structure 200 is used to focus the light emitted by the array of light-emitting chips 300 into the optical fiber port 100.

[0117] Specifically, fiber optic port 100 has multiple optical fibers. For example, Figure 13 This is a cross-sectional structural diagram of an optical fiber port provided in an embodiment of the present invention. Figure 13 As shown, the fiber optic port 100 is an array port with an array of optical fibers. The driving substrate 301 has a driving circuit and driving electrodes. The driving electrodes are connected to the electrodes of the light-emitting chip 302, enabling the driving circuit to drive the light-emitting chip 302 to emit light. The lens structure 200 is disposed between the light-emitting surface of the array light-emitting chip 300 and the end face of the fiber optic port 100. When the array light-emitting chip 300 emits light, the light emitted by the array light-emitting chip 300 is focused by the lens structure 200 and then perpendicularly enters the fiber optic port 100, which can improve the communication transmission quality of the optical communication system.

[0118] Since the optical communication system provided in this embodiment of the invention has the light-emitting chip provided in any embodiment of the invention, it has the same beneficial effects as the light-emitting chip provided in any embodiment of the invention, and is not limited here.

[0119] Continue to refer to Figure 12 The lens structure 200 includes a second lens 201. The orthographic projection of the second lens 201 on the driving substrate 301 covers the orthographic projection of any light-emitting chip 302 on the driving substrate 301. At this time, the size of the second lens 201 is relatively large, which can converge the light emitted by all the light-emitting chips 302 and improve the communication transmission quality of the optical communication system.

[0120] Figure 14 This is a schematic diagram of another optical communication system provided in an embodiment of the present invention. Figure 14 As shown, the lens structure 200 includes a plurality of microlenses 202 arranged in an array, each microlens 202 being disposed opposite to a light-emitting chip 302. In this case, each microlens 202 can converge the light emitted by the oppositely disposed light-emitting chip 302, thereby improving the communication transmission quality of the optical communication system.

[0121] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, the scope of which is determined by the scope of the appended claims.

Claims

1. A light-emitting chip, characterized in that, Used for optical communication; the light-emitting chip includes at least two light-emitting units; When at least two of the light-emitting units are arranged horizontally, the light-emitting chip further includes a connecting electrode, which is disposed on one side of the back surface of the light-emitting unit and is used to connect two adjacent light-emitting units in series. And / or, when at least two of the light-emitting units are arranged vertically, the light-emitting chip further includes a tunneling junction, which is disposed between two adjacent light-emitting units for connecting the two adjacent light-emitting units in series.

2. The light-emitting chip according to claim 1, characterized in that, Each of the light-emitting units includes a first semiconductor layer, a quantum well layer, and a second semiconductor layer stacked together; When at least two light-emitting units are arranged horizontally, the surface of the second semiconductor layer of the light-emitting unit away from the quantum well layer serves as the light-emitting surface; the light-emitting unit includes a first electrode and a second electrode disposed on one side of the backlight surface, the first electrode is connected to the first semiconductor layer of one of the light-emitting units, the second electrode is connected to the second semiconductor layer of the adjacent light-emitting unit, and the connecting electrode is connected to the first electrode of one light-emitting unit and the second electrode of the other light-emitting unit. And / or, when at least two of the light-emitting units are arranged vertically, the surface of the last second semiconductor layer away from the quantum well layer serves as the light-emitting surface; the light-emitting chip further includes a third electrode and a fourth electrode disposed on one side of the backlight surface, the third electrode being connected to the first semiconductor layer of the first light-emitting unit, and the fourth electrode being connected to the second semiconductor layer of the last light-emitting unit.

3. The light-emitting chip according to claim 2, characterized in that, The light-emitting unit further includes a sidewall insulating layer, which is disposed on one side of the backlight surface and covers the platform and sidewall of the light-emitting unit. A through hole is provided on the sidewall insulating layer, through which the electrode of the light-emitting unit and / or the electrode of the light-emitting chip pass. The connecting electrode is disposed on the side of the sidewall insulating layer away from the light-emitting surface.

4. The light-emitting chip according to claim 1, characterized in that, The light-emitting chip is circular.

5. The light-emitting chip according to claim 4, characterized in that, When at least two of the light-emitting units are arranged horizontally, the at least two light-emitting units are evenly distributed circumferentially.

6. The light-emitting chip according to any one of claims 1-5, characterized in that, It also includes a first lens, which is disposed on the light-emitting surface of the light-emitting unit.

7. A method for manufacturing a light-emitting chip, characterized in that, Used to manufacture the light-emitting chip according to any one of claims 1-6; the method for manufacturing the light-emitting chip includes: An epitaxial layer is formed on a substrate; when at least two of the light-emitting units are arranged vertically, the epitaxial layer includes a symmetrically periodically arranged light-emitting functional layer and a tunneling junction; the tunneling junction is disposed between adjacent light-emitting functional layers; The epitaxial layer is patterned to form at least one mesa structure; when at least two light-emitting units are arranged horizontally, the epitaxial layer forms at least two mesa structures. An electrode is formed on the platform of the platform structure; when at least two light-emitting units are arranged horizontally, the electrode includes a first electrode, a second electrode, and a connecting electrode; one end of the connecting electrode is connected to a first electrode on one of the platform structures, and the other end of the connecting electrode is connected to a second electrode on another adjacent platform structure; when at least two light-emitting units are arranged vertically, the electrode includes a third electrode and a fourth electrode. Remove the substrate.

8. The method for manufacturing a light-emitting chip according to claim 7, characterized in that, After patterning the epitaxial layer, the process further includes: A sidewall insulation layer is formed on the table surface and sidewalls of the table structure; The sidewall insulating layer is patterned to form vias; when at least two light-emitting units are arranged horizontally, the first via and the second via on the mesa structure expose the first semiconductor layer and the second semiconductor layer in the epitaxial layer, respectively; when at least two light-emitting units are arranged vertically, the third via and the fourth via on the mesa structure expose the first semiconductor layer of the first light-emitting functional layer and the second semiconductor layer of the last light-emitting functional layer, respectively. An electrode is formed on the mesa of the mesa structure, including: The first electrode is formed at the first via, and the second electrode is formed at the second via; Alternatively, the third electrode may be formed at the third via, and the fourth electrode may be formed at the fourth via.

9. An optical communication system, characterized in that, It includes fiber optic ports, lens structures, and arrayed light-emitting chips arranged in sequence; The array of light-emitting chips includes a driving substrate and a plurality of light-emitting chips as described in any one of claims 1-6 disposed on the driving substrate, wherein the driving substrate is connected to the light-emitting chips and the plurality of light-emitting chips are arranged in an array. The lens structure is used to focus the light emitted by the array of light-emitting chips into the optical fiber port.

10. The optical communication system according to claim 9, characterized in that, The lens structure includes a second lens, the orthographic projection of which on the driving substrate covers the orthographic projection of any of the light-emitting chips on the driving substrate; or, the lens structure includes a plurality of microlenses arranged in an array, each of the microlenses being disposed opposite to one of the light-emitting chips.

Images