Display device

Abstract

A display device includes a base layer having a display area and a non-display area including a pad area, first, second, third, fourth, and fifth insulating layers sequentially stacked on the base layer, and a first pad on the first insulating layer in the pad area, wherein the first pad includes a first pad pattern on the first insulating layer, a second pad pattern on the first pad pattern with the second insulating layer interposed between the second pad pattern and the first pad pattern, a third pad pattern on the second pad pattern with the third insulating layer interposed between the third pad pattern and the second pad pattern, a fourth pad pattern on the third pad pattern and the fourth insulating layer, and a fifth pad pattern on the fourth pad pattern, and the first to fifth pad patterns are electrically connected to each other.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2019-0139761, filed on November 4, 2019, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] This disclosure generally relates to a display panel and a display device including the display panel. Background Technology

[0004] With the development of multimedia, display devices have become increasingly important. Therefore, various types of display devices, such as organic light-emitting diode (OLED) displays and liquid crystal displays (LCDs), can be used for a variety of purposes.

[0005] Display panels, such as organic light-emitting display panels or liquid crystal display panels, can be included in display devices for displaying images. The display panel can be a light-emitting display panel and can include a light-emitting element. The light-emitting element can be a light-emitting diode (LED). Examples of LEDs include organic light-emitting diodes (OLEDs) that use organic materials as fluorescent materials, and inorganic light-emitting diodes that use inorganic materials as fluorescent materials.

[0006] Compared to organic light-emitting diodes (OLEDs), inorganic light-emitting diodes (LEDs) using inorganic semiconductors as fluorescent materials exhibit durability even at high temperatures and can provide highly efficient blue light. Furthermore, a transfer method using dielectric electrophoresis (DEP) technology has been developed to address the limitations of existing inorganic LED manufacturing processes. Therefore, research on inorganic LEDs with superior durability and efficiency compared to OLEDs has been ongoing. Moreover, using DEP technology to overcome the limitations of existing inorganic LED manufacturing processes may be a viable approach. Summary of the Invention

[0007] An exemplary embodiment of this disclosure provides a display device including a nanoscale or microscale light-emitting element and a pad having a conductive layer, wherein the conductive layer comprises the same material as an alignment electrode for aligning the light-emitting element and a contact electrode for electrically connecting the alignment electrode and the light-emitting element.

[0008] According to one aspect of this disclosure, a display panel is provided, comprising: a base layer having a display area and a non-display area, the non-display area including a pad area; a plurality of transistors located on the base layer; a first protective layer covering the plurality of transistors; a conductive layer located on the first protective layer; a second protective layer located on the conductive layer; a first electrode and a second electrode located on the second protective layer, the first electrode and the second electrode being spaced apart from each other; a plurality of light-emitting elements located between the first electrode and the second electrode; a first contact electrode located on the first electrode and a second contact electrode located on the second electrode, the first contact electrode contacting one end of at least one of the plurality of light-emitting elements, the second contact electrode contacting the other end of at least one of the plurality of light-emitting elements; and a first pad located in a pad area, the first pad having a plurality of conductive pad patterns, wherein the pad pattern at the uppermost part of the first pad comprises the same material as the first contact electrode or the second contact electrode.

[0009] The first pad may include: a first pad pattern; a second pad pattern located on the first pad pattern; a third pad pattern located on the second pad pattern; a fourth pad pattern located on the third pad pattern; and a fifth pad pattern located on the fourth pad pattern.

[0010] The fourth pad pattern may include the same material as the first electrode and the second electrode, and the fifth pad pattern may include the same material as the first contact electrode or the second contact electrode.

[0011] The first pad pattern may include the same material as the gate electrode of each of the plurality of transistors, the second pad pattern may include the same material as the source and drain electrodes of each of the plurality of transistors, and the third pad pattern may include the same material as the conductive layer.

[0012] The conductive layer may include a connection pattern that electrically connects the source or drain electrode of a driving transistor among a plurality of transistors to a first electrode or a second electrode.

[0013] The first, second, third, fourth, and fifth pad patterns can be electrically connected.

[0014] The second and fifth pad patterns can have the same width.

[0015] The first pad pattern, the third pad pattern, and the fourth pad pattern can have the same width.

[0016] The first pad may include a groove at the top of the first pad, and the width-to-depth ratio of the groove may be 20 or greater.

[0017] The width of the groove can be 20µm or greater, and the depth of the groove can be 1µm or less.

[0018] The pad pattern at the top of the first pad may include ITO, IZO or ITZO.

[0019] The first pad may be surrounded by adjacent insulating material. The step difference between the first pad and the insulating material may be from 0.6µm to 2.0µm.

[0020] The display panel may also include a second pad in the pad area. The first pad may be a gate pad, and the second pad may be a data pad.

[0021] A scan signal can be applied to the first pad from the outside, and the second pad is used to receive data signals from the outside.

[0022] The second pad can be adjacent to the first pad. The distance between the first pad and the second pad can be from 15µm to 25µm.

[0023] The display panel may also include an insulating layer above the first pad. The insulating layer may include an overlapping area that overlaps with the edge of the first pad.

[0024] The overlapping area can have a width of 2µm to 3µm.

[0025] The insulating layer can have a thickness of 6000 Å or less.

[0026] The display panel may also include an island electrode located on the same layer as the first and second electrodes. The island electrode may be located between the first and second electrodes.

[0027] Some of the multiple light-emitting elements may be located between the first electrode and the island electrode, and other light-emitting elements may be located between the island electrode and the second electrode.

[0028] Multiple light-emitting elements can be connected in series and / or in parallel.

[0029] The first contact electrode can be located on the second contact electrode.

[0030] Each of the multiple light-emitting elements may include: one end comprising an n-type semiconductor material; another end comprising a p-type semiconductor material; and an active layer located between the two ends in a quantum well structure. The multiple light-emitting elements may have diameters and lengths ranging from hundreds of nanometers to several micrometers.

[0031] According to another aspect of this disclosure, a display device is provided, comprising: a display panel having a plurality of pixels arranged therein; a scan driver configured to provide a scan signal to each of the plurality of pixels; and a data driver configured to provide a data signal to each of the plurality of pixels, wherein the display panel includes: a base layer having a display area and a non-display area, the non-display area including pad areas; a plurality of transistors located on the base layer, the plurality of transistors being included in each of the plurality of pixels; a first protective layer covering the plurality of transistors; a conductive layer located on the first protective layer; a second protective layer located on the conductive layer; a first electrode and a second electrode located on the second protective layer, the first electrode... The first electrode and the second electrode are spaced apart from each other; a plurality of light-emitting elements are located between the first electrode and the second electrode; a first contact electrode on the first electrode and a second contact electrode on the second electrode, the first contact electrode contacting one end of at least one of the plurality of light-emitting elements and the second contact electrode contacting the other end of at least one of the light-emitting elements; and a first pad and a second pad located in a pad region, the first pad and the second pad having a plurality of conductive pad patterns, wherein the first pad is electrically connected to a scan driver, wherein the second pad is electrically connected to a data driver, wherein the pad pattern at the uppermost part of each of the first pad and the second pad comprises the same material as the first contact electrode or the second contact electrode.

[0032] The scan driver and data driver can be located outside the display panel.

[0033] Each of the multiple pixels can include seven transistors. Attached Figure Description

[0034] Exemplary embodiments will now be described more fully below with reference to the accompanying drawings; however, these exemplary embodiments may be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of the exemplary embodiments to those skilled in the art.

[0035] In the accompanying drawings, dimensions may be exaggerated for clarity. It will be understood that when an element is referred to as "between" two elements, the element may be the only element between the two elements, or there may be one or more elements in between. The same reference numerals denote the same elements throughout.

[0036] Figure 1 and Figure 2 This is a perspective view and a cross-sectional view showing a light-emitting element according to some exemplary embodiments of the present disclosure.

[0037] Figure 3 and Figure 4This is a perspective view and a cross-sectional view showing a light-emitting element according to some exemplary embodiments of the present disclosure.

[0038] Figure 5 and Figure 6 This is a perspective view and a cross-sectional view showing a light-emitting element according to some exemplary embodiments of the present disclosure.

[0039] Figure 7 This is a conceptual diagram illustrating a display device according to some exemplary embodiments of the present disclosure.

[0040] Figure 8 This illustrates some exemplary embodiments according to this disclosure, including... Figure 7 The circuit diagram shows an example of a subpixel in an exemplary display panel.

[0041] Figures 9 to 12 This illustrates some exemplary embodiments that can be used as included in the present disclosure. Figure 8 The circuit diagram shows an example of a unit pixel in the sub-pixel.

[0042] Figure 13 This illustrates some exemplary embodiments according to this disclosure, including... Figure 7 A plan view showing an exemplary arrangement of some components in a subpixel of the display panel shown.

[0043] Figure 14 This is along some exemplary embodiments of the present disclosure. Figure 13 The line I-I' shown is a cross-sectional view of the display panel.

[0044] Figure 15 This is along some exemplary embodiments of the present disclosure. Figure 7 The cross-sectional view of the display panel is shown by line II-II'.

[0045] Figure 16 This is along some exemplary embodiments of the present disclosure. Figure 7 The cross-sectional view of the display panel is shown by line III-III'.

[0046] Figures 17 to 19 This is a cross-sectional view of a display panel according to some exemplary embodiments of the present disclosure.

[0047] Figure 20 and Figure 21 This is a cross-sectional view of a display panel according to some exemplary embodiments of the present disclosure.

[0048] Figure 22 This is a cross-sectional view of a display panel according to some exemplary embodiments of the present disclosure.

[0049] Figures 23 to 26 This is an exemplary circuit diagram that can be used as a unit pixel included in a sub-pixel of a display panel according to some exemplary embodiments of this disclosure.

[0050] Figure 27 This is a plan view illustrating the arrangement of some components in a sub-pixel of a display panel according to some exemplary embodiments of the present disclosure.

[0051] Figure 28 This is along some exemplary embodiments of the present disclosure. Figure 27 The cross-sectional view of the display panel is shown by line IV-IV'.

[0052] Figure 29 This is a cross-sectional view of a display panel according to some exemplary embodiments of the present disclosure. Detailed Implementation

[0053] The effects and features of this disclosure, as well as the methods for achieving these effects and features, will become clear from the detailed description of the embodiments described below in conjunction with the accompanying drawings. However, this disclosure is not limited to the embodiments disclosed herein, but can be implemented in various forms. The embodiments are provided by way of example only to enable those skilled in the art to fully understand the features and scope of this disclosure. Therefore, this disclosure may be defined by the scope of the appended claims.

[0054] The term "on" used to indicate that an element or layer is located on another element or layer includes both cases where the element or layer is located directly on another element or layer, and cases where the element or layer is located on another element or layer via yet another element or layer. Throughout the description of this disclosure, the same reference numerals are used for the same elements in the various figures.

[0055] Although the terms "first," "second," etc., are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from other components. Therefore, according to the technical concept of this disclosure, a first component can be a second component, or a second component can be a first component.

[0056] For ease of description, spatial relative terms such as “below,” “under,” “down,” “below,” “above,” and “above” are used herein to describe the relationship of one element or feature to another element(s) as shown in the accompanying drawings. It will be understood that, in addition to the orientations depicted in the drawings, such spatial relative terms are intended to include different orientations of the device in use or operation. For example, if the device in the drawings is flipped, an element described as “below,” “under,” or “below” other elements or features will subsequently be oriented “above” other elements or features. Thus, the exemplary terms “below” and “below” can include both above and below orientations. The device may be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein should be interpreted accordingly. Furthermore, it will be understood that when a layer is referred to as being located “between” two layers, the layer may be the only layer between the two layers, or there may be one or more layers in between.

[0057] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the inventive concept. As used herein, the terms “substantially,” “about,” and similar terms are used as approximate terms rather than terms of degree and are intended to allow for inherent deviations in measurements or calculations that will be recognized by those skilled in the art.

[0058] As used herein, unless the context clearly indicates otherwise, the singular forms “a” and “an” are intended to include the plural forms as well. It will also be understood that, when used in this specification, the terms “comprising” and / or “comprising of” specify the presence of stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or collections thereof. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. When a statement such as “at least one of…” follows a list of elements, it modifies the entire list of elements and does not modify any individual element of the list. Furthermore, when “may” is used to describe embodiments of the inventive concept, it means “one or more embodiments of the invention.” Additionally, the term “exemplary” is intended to indicate an example or illustration. As used herein, the terms “use,” “using,” and “used” may be considered synonymous with the terms “utilize,” “utilizing,” and “utilized,” respectively.

[0059] It will be understood that when a component or layer is referred to as being "on," "connected to," "linked to," or "adjacent to" another component or layer, the component or layer may be directly on, directly connected to, directly linked to, or directly adjacent to the other component or layer, or there may be one or more intermediate components or layers. Conversely, when a component or layer is referred to as being "directly on," "directly connected to," "directly linked to," or "directly adjacent to," there are no intermediate components or layers.

[0060] Any numerical ranges listed herein are intended to include all subranges with the same numerical precision contained within the listed range. For example, the range "1.0 to 10.0" is intended to include all subranges between the listed minimum value 1.0 and the listed maximum value 10.0 (and inclusive of both the minimum value 1.0 and the maximum value 10.0) (i.e., a minimum value equal to or greater than 1.0 and a maximum value equal to or less than 10.0), such as 2.4 to 7.6. Any maximum numerical limits listed herein are intended to include all smaller numerical limits contained therein, and any minimum numerical limits listed in this specification are intended to include all higher numerical limits contained therein.

[0061] In the following description, exemplary embodiments will be referenced to the accompanying drawings. Throughout the drawings, the same reference numerals are used for the same elements.

[0062] Figure 1 and Figure 2 This shows a perspective view and a cross-sectional view of a light-emitting element according to an embodiment of the present disclosure. Although in Figure 1 and Figure 2 The diagram shows a rod-type light-emitting element (LD) with a cylindrical shape, but the type and / or shape of the light-emitting element (LD) according to this disclosure are not limited thereto.

[0063] Reference Figure 1 and Figure 2 The light-emitting element (LD) may include a first conductive electrode layer 11, a second conductive electrode layer 13, and an active layer 12 interposed between the first conductive electrode layer 11 and the second conductive electrode layer 13. In an example, the light-emitting element (LD) may be configured as a stacked structure in which the first conductive electrode layer 11, the active layer 12, and the second conductive electrode layer 13 are sequentially stacked along one direction.

[0064] In some embodiments, the light-emitting element (LD) can be configured as a rod shape extending in one direction. The light-emitting element (LD) can have one end and another end along one direction.

[0065] In some embodiments, one of the first conductive electrode layer 11 and the second conductive electrode layer 13 may be disposed at one end of the light-emitting element LD, and the other of the first conductive electrode layer 11 and the second conductive electrode layer 13 may be disposed at the other end of the light-emitting element LD.

[0066] In some embodiments, the light-emitting element (LD) can be a rod-shaped light-emitting diode. The rod shape can include a rod-like shape or a similar rod shape, such as a cylinder or a polygonal prism, which is long in its length direction (i.e., its length-to-width ratio is greater than 1), and the shape of the cross-section of the rod shape is not particularly limited. For example, the length L of the light-emitting element LD can be greater than the diameter D (or the width of the cross-section) of the light-emitting element LD.

[0067] In some embodiments, the light-emitting element (LD) may have a diameter D and / or a length L, having dimensions as small as the micrometer or nanometer scale, for example, ranging from hundreds of nanometers to several micrometers. However, the size of the light-emitting element (LD) is not limited to this. For example, the size of the light-emitting element (LD) may vary depending on the design conditions of various types of devices (e.g., display devices, etc.) that use lighting devices utilizing the light-emitting element (LD) as light-emitting units.

[0068] The first conductive electrode layer 11 may include at least one n-type semiconductor material. For example, the first conductive electrode layer 11 may include one of the semiconductor materials selected from InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and may include an n-type semiconductor material doped with a first conductive dopant (such as Si, Ge, or Sn). However, the materials constituting the first conductive electrode layer 11 are not limited to these. Furthermore, the first conductive electrode layer 11 may be composed of different materials.

[0069] The active layer 12 is located (e.g., formed on) the first conductive electrode layer 11 and can be formed as a single or multiple quantum well structures. In embodiments, a cladding layer (not shown) doped with a conductive dopant can be located (e.g., formed on) the top and / or bottom of the active layer 12. In examples, the cladding layer can be implemented as an AlGaN layer or an InAlGaN layer. In some embodiments, materials such as AlGaN or AlInGaN can be used to form the active layer 12. Furthermore, the active layer 12 can be made of different materials.

[0070] When a voltage equal to or greater than the threshold voltage is applied across the light-emitting element (LD), the LD emits light due to the combination of electron-hole pairs in the active layer 12. This principle can be used to control the emission of the LD, and therefore, the LD can be used as a light-emitting unit in various lighting devices, including pixels of a display device.

[0071] The second conductive electrode layer 13 is located (e.g., formed on) the active layer 12 and may include a semiconductor layer of a different type than the first conductive electrode layer 11. In an example, the second conductive electrode layer 13 may include at least one p-type semiconductor material. For example, the second conductive electrode layer 13 may include at least one semiconductor material selected from InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and may include a p-type semiconductor material doped with a second conductive dopant (such as Mg). However, the materials constituting the second conductive electrode layer 13 are not limited to these. Furthermore, the second conductive electrode layer 13 may be composed of different materials.

[0072] In some embodiments, the light-emitting element (LD) may further include an insulating film INF located on its surface. For example, the insulating film INF may be located on the outer surface of the light-emitting element (LD). The insulating film INF may be located (e.g., formed on) the surface of the light-emitting element (LD) to surround at least the outer periphery of the active layer 12. Furthermore, the insulating film INF may also surround at least one region of the first conductive electrode layer 11 and the second conductive electrode layer 13. However, the insulating film INF may expose the two ends of the light-emitting element (LD) with different polarities. For example, the insulating film INF may expose both ends of the light-emitting element (LD) without covering at least one end of each of the first conductive electrode layer 11 and the second conductive electrode layer 13 located at both ends of the light-emitting element (LD) in the longitudinal direction, for example, without covering the two planes (i.e., the upper and lower surfaces) of the cylinder. For example, in some embodiments, the insulating film INF may not cover the ends of the light-emitting element (LD) adjacent to the first conductive electrode layer 11 and the second conductive electrode layer 13.

[0073] In some embodiments, the insulating film INF may include at least one insulating material selected from silicon dioxide (SiO2), silicon nitride (Si3N4), aluminum oxide (Al2O3), and titanium dioxide (TiO2), but this disclosure is not limited thereto. That is, there are no particular limitations on the materials constituting the insulating film INF, and the insulating film INF can be made from a variety of insulating materials currently known in the art.

[0074] In some embodiments, the light-emitting element (LD) may further include additional components besides the first conductive electrode layer 11, the active layer 12, the second conductive electrode layer 13, and / or the insulating film INF. For example, the light-emitting element (LD) may also include at least one of a phosphor layer, an active layer, a semiconductor layer, and / or an electrode layer, which may be disposed at one end of the first conductive electrode layer 11, the active layer 12, and / or the second conductive electrode layer 13.

[0075] Figure 3 and Figure 4 This is a perspective view and a cross-sectional view showing a light-emitting element according to another exemplary embodiment of the present disclosure. Figure 5 and Figure 6 This is a perspective view and a cross-sectional view showing a light-emitting element according to some exemplary embodiments of the present disclosure.

[0076] Reference Figure 3 and Figure 4 The light-emitting element LD may also include at least one electrode layer 14 located at one end of the second conductive electrode layer 13.

[0077] Reference Figure 5 and Figure 6 The light-emitting element LD may also include at least another electrode layer 15 located at one end of the first conductive electrode layer 11.

[0078] Each of electrode layers 14 and 15 may be an ohmic contact electrode, but this disclosure is not limited thereto. Furthermore, each of electrode layers 14 and 15 may include a metal or a conductive metal oxide. In examples, each of electrode layers 14 and 15 may include one or a mixture of chromium (Cr), titanium (Ti), aluminum (Al), gold (Au), nickel (Ni), their oxides or alloys, transparent electrode materials (such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium tin zinc oxide (ITZO)). Electrode layers 14 and 15 may be substantially transparent or translucent. Therefore, light generated in the light-emitting element LD can be transmitted through electrode layers 14 and 15 and then emitted to the outside of the light-emitting element LD.

[0079] In some embodiments, the insulating film INF may at least partially surround or may not surround the outer periphery of electrode layers 14 and 15. That is, the insulating film INF may be selectively located (e.g., formed on) the surfaces (e.g., side surfaces) of electrode layers 14 and 15. Furthermore, the insulating film INF may be located (e.g., formed on) the two ends of the light-emitting element LD with different polarities. In some exemplary embodiments, the insulating film INF may expose at least one region of electrode layers 14 and 15. However, this disclosure is not limited thereto, and the insulating film INF may not be provided.

[0080] The insulating film INF is located on the surface of the light-emitting element LD, for example, on the surface of the active layer 12, thereby preventing (or substantially preventing) a short circuit between the active layer 12 and at least one electrode layer 14 or 15 (e.g., at least one of electrode layers 14 and 15 connected to a corresponding end of the light-emitting element LD) (or reducing the chance of a short circuit). Therefore, the electrical stability of the light-emitting element LD can be substantially ensured. For example, because the insulating film INF insulates the active layer 12 from at least one electrode layer 14 or 15, the chance of a short circuit is reduced, thereby improving the electrical stability of the light-emitting element LD.

[0081] Furthermore, the insulating film INF is located (e.g., formed on) the surface of the light-emitting element LD, thereby minimizing or reducing surface defects of the light-emitting element LD and improving the lifespan and efficiency of the light-emitting element LD. Additionally, the insulating film INF is located (e.g., formed on) the light-emitting element LD, so that even when multiple light-emitting elements LD are close to each other (or very close to each other), unwanted short circuits between multiple light-emitting elements LD can be prevented (or the chance of short circuits can be reduced).

[0082] In this implementation, the light-emitting element (LD) can be manufactured using a surface treatment process (e.g., coating). For example, when multiple LDs are mixed in a liquid solution (or solvent) to provide light to each emitting area (e.g., the emitting area of ​​each pixel), the LDs do not aggregate unevenly in the solution, but are instead uniformly dispersed. The emitting area is the region in which light is emitted by the LD and can be distinguished from the non-emitting area in which no light is emitted.

[0083] In some embodiments, the insulating film INF itself may be formed as a hydrophobic layer made of a hydrophobic material, or a hydrophobic layer made of a hydrophobic material may be additionally located (e.g., formed on) the insulating film INF. In some embodiments, the hydrophobic material may be a fluorinated material to exhibit hydrophobicity. Furthermore, in some embodiments, the hydrophobic material may be applied to the light-emitting element LD in the form of a self-assembled monolayer (SAM). The hydrophobic material may include octadecyltrichlorosilane, fluoroalkyltrichlorosilane, perfluoroalkyltriepoxysilane, etc. Additionally, the hydrophobic material may be such as Teflon. TM Or Cytop TM Commercially available fluorinated materials, or materials corresponding to them.

[0084] Lighting devices including light-emitting elements (LDs) can be used in various types of devices (including display devices) that require light-emitting units. For example, at least one micro-light-emitting element (LD) (e.g., multiple micro-light-emitting elements (LDs) each having a nanometer-scale or micrometer-scale size) can be located in a pixel area of ​​a display panel, and the micro-light-emitting elements (LDs) can be used to configure the light-emitting units of each pixel. However, in the exemplary embodiments of this disclosure, the application of light-emitting elements (LDs) is not limited to display devices. For example, light-emitting elements (LDs) can be used in other types of devices (such as lighting devices) that require light-emitting units.

[0085] Figure 7 This is a conceptual diagram illustrating a display device according to an embodiment of the present disclosure. In some embodiments, Figure 7 The reference shows that it can be used Figures 1 to 6 The described light-emitting element LD is a display device that uses light-emitting units as light-emitting elements. In some embodiments, based on the display area DA, in Figure 7 The structure of the display device is briefly shown. However, in some embodiments, the display device may further include at least one driving circuit (e.g., at least one of a scan driver and a data driver) and multiple lines (not shown).

[0086] Reference Figure 7 The display device may include a display panel 21, a scan driver 30, and a data driver 40. Figure 7 In the diagram, display panel 21 is shown in a schematic plan view, and scan driver 30 and data driver 40 are shown in a block diagram.

[0087] In one embodiment, the scan driver 30 and the data driver 40 may be located outside (or outside) the display panel 21. Each of the scan driver 30 and the data driver 40 may be connected by multiple signal lines, but this disclosure is not limited thereto. In another embodiment, the scan driver 30 and the data driver 40 may be located inside the display panel 21.

[0088] The display panel 21 can be configured in a rectangular shape, which is longer in the second direction DR2 than in the first direction DR1. The thickness direction of the display panel 21 is indicated by the third direction DR3. However, the directions indicated by the first direction DR1, the second direction DR2, and the third direction DR3 are relative concepts and can be changed to other directions. In the following, the first direction DR1, the second direction DR2, and the third direction DR3 are the directions indicated by the first direction DR1, the second direction DR2, and the third direction DR3, respectively, and are indicated by the same reference numerals. Furthermore, the shape of the display panel 21 is not limited to the shape shown in the figures, and the display panel 21 can have various shapes. In addition, the shown positions of the blocks representing the concepts of the scan driver 30 and the data driver 40 do not specify their relative positions with respect to the display panel 21.

[0089] The display panel 21 may include a base layer SUB1 (or substrate) and pixels PXL disposed on the base layer SUB1. Specifically, the base layer SUB1 may include a display area DA in which an image is displayed and a non-display area NDA (the area of ​​the base layer SUB1 other than the display area DA).

[0090] The display area DA and the non-display area NDA can be defined within the base layer SUB1. In some embodiments, the display area DA can be located in the central area of ​​the display panel 21, and the non-display area NDA can be positioned along the edge of the display panel 21 to surround the display area DA. However, the positions of the display area DA and the non-display area NDA are not limited to this and can be changed.

[0091] The base layer SUB1 can form the basic component of the display panel 21. For example, the base layer SUB1 can form the basic component of the lower panel (e.g., the lower plate of the display panel 21).

[0092] In some embodiments, the base layer SUB1 may be a rigid substrate or a flexible substrate, and the material or properties of the base layer SUB1 are not particularly limited. In examples, the base layer SUB1 may be a rigid substrate configured using glass or tempered glass, or a flexible substrate configured using a thin film made of a metallic material. Furthermore, the base layer SUB1 may be a transparent substrate, but this disclosure is not limited thereto. In examples, the base layer SUB1 may be a translucent substrate, an opaque substrate, or a reflective substrate.

[0093] The area in the base layer SUB1 where pixel PXL is located is defined as display area DA, and other areas on the base layer SUB1 are defined as non-display areas NDA. In the example, the base layer SUB1 may include display area DA and non-display area NDA located on the periphery of display area DA, wherein display area DA includes multiple light-emitting areas, and pixel PXL is located (e.g., formed in) said multiple light-emitting areas. Various types of lines and / or built-in circuitry connecting pixel PXL to display area DA may be located in non-display area NDA.

[0094] Each of the pixels PXL may include at least one light-emitting element (LD) driven by a corresponding scan signal and a corresponding data signal (e.g., according to...). Figures 1 to 6 (At least one rod-shaped light-emitting diode in any of the embodiments shown). For example, a pixel PXL may include multiple rod-shaped light-emitting diodes having dimensions as small as the nanometer or micrometer scale, and connected in parallel with each other. Multiple rod-shaped light-emitting diodes may constitute the light-emitting unit of the pixel PXL.

[0095] Furthermore, pixel PXL may include multiple sub-pixels. In an example, pixel PXL may include a first sub-pixel SPX1, a second sub-pixel SPX2, and a third sub-pixel SPX3. In some implementations, the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 may emit different colors of light. In an example, the first sub-pixel SPX1 may be a red sub-pixel emitting red light, the second sub-pixel SPX2 may be a green sub-pixel emitting green light, and the third sub-pixel SPX3 may be a blue sub-pixel emitting blue light. However, there are no particular limitations on the color, type, and / or number of the sub-pixels constituting pixel PXL. In an example, the color of light emitted by each of sub-pixels SPX1, SPX2, and SPX3 may be varied differently. Although in Figure 7The illustration shows an embodiment in which pixels PXL are arranged in a stripe pattern in the display area DA, but this disclosure is not limited thereto. For example, pixels PXL can be arranged in various pixel arrangements.

[0096] In the implementation, sub-pixels SPX1, SPX2, and SPX3 may each include multiple unit pixels SSPX1, SSPX2 to SSPXk (e.g., ...). Figure 8 As shown in the image).

[0097] The non-display area NDA may include a pad area PDA in which multiple pads PAD1 and PAD2 are arranged. That is, the pad area PDA can be further defined in the base layer SUB1.

[0098] In some implementations, the pad region PDA can be positioned within the non-display region NDA adjacent to one edge of the display region DA. However, although the accompanying drawings show the pad region PDA positioned adjacent to the lower edge of the display region DA, the arrangement of the pad region PDA is not limited to that shown in the drawings. The pad region PDA can also be positioned within the non-display region NDA adjacent to the upper edge, lower edge, left edge, and / or right edge of the display region DA.

[0099] In this implementation, the plurality of pads PAD1 and PAD2 may include a first pad PAD1 and a second pad PAD2. For example, the first pad PAD1 may be a gate pad, and the second pad PAD2 may be a data pad. The first pad PAD1 may be connected to a scan driver 30 located outside the display panel 21. Therefore, a scan signal applied from the scan driver 30 can be transmitted to a scan line through the first pad PAD1.

[0100] The second pad PAD2 can be connected to the data driver 40 located outside the display panel 21. Therefore, data signals applied from the data driver 40 can be transmitted to the data line through the second pad PAD2.

[0101] Figure 8 It shows that it includes Figure 7 The circuit diagram shows an example of a sub-pixel in the display panel. Figure 8 In, it is shown that includes Figure 7 The first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 in the display panel 21 shown.

[0102] Except that the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 are connected to the corresponding data lines Dj, Dj+1, and Dj+2 respectively, the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 are identical to each other, and therefore, the first sub-pixel SPX1 will be mainly described.

[0103] The first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 can be arranged in the region defined by scan lines Si-1 and Si (i is a natural number) and data lines Dj, Dj+1, and Dj+2 (j is a natural number), respectively. For example, the first sub-pixel SPX1 can be located in the region defined by the (i-1)th scan line Si-1 and the ith scan line Si, as well as the jth data line Dj and the (j+1)th data line Dj+1. However, the arrangement of the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 is not limited to this.

[0104] The first sub-pixel SPX1 can be connected to the i-th scan line Si and the j-th data line Dj, and can also be connected to a first power line and a second power line. A first power supply VDD can be applied to the first power line, and a second power supply VSS can be applied to the second power line. Each of the first and second power lines can be a common line connecting multiple sub-pixels. The first power supply VDD and the second power supply VSS can have different potentials, allowing the first sub-pixel SPX1 to emit light, and the first power supply VDD can have a higher voltage level than the second power supply VSS.

[0105] In some implementations, the first sub-pixel SPX1 (or the second sub-pixel SPX2 or the third sub-pixel SPX3) may include at least one unit pixel SSPX1 to SSPXk (k is a natural number).

[0106] Each of the unit pixels SSPX1 to SSPXk included in the first sub-pixel SPX1 can be connected to the i-th scan line Si and the j-th data line Dj, and can also be connected to the first power supply VDD and the second power supply VSS. Each of the unit pixels SSPX1 to SSPXk can emit light with a brightness corresponding to the data signal transmitted through the j-th data line Dj in response to the scan signal transmitted through the i-th scan line Si. The unit pixels SSPX1 to SSPXk can have substantially the same pixel structure or pixel circuitry.

[0107] That is, the first sub-pixel SPX1 may include unit pixels SSPX1 to SSPXk that emit light independently of each other in response to a scan signal and a data signal.

[0108] In implementations, each of the unit pixels SSPX1 to SSPXk (or sub-pixels SPX1 to SPX3) can be configured as an active pixel. However, there are no particular limitations on the type, structure, and / or driving method of the unit pixels applicable to the display panel 21 of this disclosure. For example, a unit pixel can be configured as a pixel of the display panel 21 having a passive or active structure currently known in the art.

[0109] Figures 9 to 12 It shows that it can be used as included in Figure 8 The circuit diagram shows an example of a unit pixel in the sub-pixel.

[0110] For each attached figure, one unit pixel will be described primarily, and... Figure 8 The content shown can be applied to pixels SSPX1 through SSPXk, representing the first unit pixel. Therefore, similar content will not be discussed in detail. Figure 8 The first unit pixel SSPX1 to the kth unit pixel SSPXk shown have substantially the same or similar structures to each other. Figures 9 to 12 The shown with Figure 8 The first unit pixels SSPX1, SSPX1_1, SSPX1_2, and SSPX1_3 shown are illustrative only and can be applied in the same or similar way to any of the first unit pixels SSPX1 to the k-th unit pixel SSPXk.

[0111] First, refer to Figure 9 The first unit pixel SSPX1 may include a light-emitting unit LSU that emits light with a brightness corresponding to the data signal. Furthermore, the first unit pixel SSPX1 may optionally include pixel circuitry for driving the light-emitting unit LSU.

[0112] In some embodiments, the light-emitting unit (LSU) may include a plurality of light-emitting elements (LDs) electrically connected between a first power supply (VDD) and a second power supply (VSS). In some embodiments, the light-emitting elements (LDs) may be connected in parallel with each other, but this disclosure is not limited thereto. For example, the plurality of light-emitting elements (LDs) may be connected in series with each other between the first power supply (VDD) and the second power supply (VSS).

[0113] The first power supply VDD and the second power supply VSS can have different potentials, allowing the light-emitting element LD to emit light. For example, the first power supply VDD can be set to a high potential power supply, and the second power supply VSS can be set to a low potential power supply. During the light emission cycle of the first sub-pixel SPX1, the potential difference between the first power supply VDD and the second power supply VSS can be set to the threshold voltage of the light-emitting element LD or set to a value greater than the threshold voltage of the light-emitting element LD.

[0114] At the same time, although Figure 9The illustration shows an embodiment where light-emitting elements (LDs) are connected in parallel with each other in the same direction (e.g., forward) between a first power supply VDD and a second power supply VSS, but the disclosure is not limited thereto. In the example, some of the LDs are connected in the forward direction between the first power supply VDD and the second power supply VSS to form each effective light-emitting unit (LSU), while other LDs may be connected in the reverse direction. In another example, the first unit pixel SSPX1 may consist of only a single LD (e.g., a single effective light-emitting unit LSU connected in the forward direction between the first power supply VDD and the second power supply VSS).

[0115] In some embodiments, one end of each of the light-emitting elements (LDs) can be connected to a corresponding pixel circuit (PXC) via a first electrode, and can be connected to a first power supply (VDD) via the pixel circuit (PXC) and a first power line. The other end of each of the light-emitting elements (LDs) can be connected to a second power supply (VSS) via a second electrode and a second power line.

[0116] The light-emitting unit (LSU) can emit light with a brightness corresponding to the driving current provided through the corresponding pixel circuit (PXC). Therefore, light can be emitted in the display area DA (see...). Figure 7 The set image or the scheduled image is displayed in the ) section.

[0117] The pixel circuit PXC can be connected to the i-th scan line Si and the j-th data line Dj, which correspond to the respective sub-pixel (i.e., the first sub-pixel SPX1). For example, when the first sub-pixel SPX1 is located in the i-th row and j-th column of the display area DA, the pixel circuit PXC of the first unit pixel SPX1 can be connected to the i-th scan line Si and the j-th data line Dj in the display area DA.

[0118] The pixel circuit PXC may include a first transistor T1, a second transistor T2, and a storage capacitor Cst.

[0119] The first transistor T1 (or driving transistor) can be connected between the first power supply VDD and the light-emitting unit LSU. The gate electrode of the first transistor T1 can be connected to the first node N1. The first transistor T1 can provide the driving current to the light-emitting unit LSU in accordance with the voltage control of the first node N1.

[0120] The second transistor T2 (or switching transistor) can be connected between the j-th data line Dj and the first node N1. The gate electrode of the second transistor T2 can be connected to the i-th scan line Si.

[0121] The second transistor T2 can be turned on in response to a scan signal from the gate turn-on voltage (e.g., low voltage) of the i-th scan line Si to electrically connect the j-th data line Dj and the first node N1.

[0122] For each frame period, the data signal of the corresponding frame can be provided to the j-th data line Dj. The data signal can be transmitted to the first node N1 via the second transistor T2. Therefore, the storage capacitor Cst can be charged to the voltage corresponding to the data signal.

[0123] One electrode of the storage capacitor Cst can be connected to the first power supply VDD, while the other electrode of the storage capacitor Cst can be connected to the first node N1. The storage capacitor Cst can be charged with a voltage corresponding to the data signal supplied to the first node N1 during each frame period, and the charged voltage is maintained until the data signal of the next frame is provided.

[0124] Although Figure 9 The illustration shows a case where all transistors included in the pixel circuit PXC (e.g., first transistor T1 and second transistor T2) are P-type transistors, but this disclosure is not limited thereto. For example, at least one of the first transistor T1 and the second transistor T2 may be an N-type transistor.

[0125] For example, such as Figure 10 As shown, both the first transistor T1 and the second transistor T2 can be N-type transistors. For each frame period, the gate turn-on voltage that allows the data signal supplied to the j-th data line Dj to be written into the first unit pixel SSPX1_1 can be a high-level voltage. Similarly, the voltage used to turn on the data signal of the first transistor T1 can be a voltage with a voltage similar to that of the second transistor. Figure 9 The voltage of the waveform opposite to the waveform of the embodiment shown (e.g., its voltage may have the same waveform as the one described above). Figure 9 The embodiments shown have opposite polarities. In the example, in Figure 10 In the embodiment shown, as the grayscale value to be represented becomes larger, a data signal with a higher voltage level can be provided. In other words, in Figure 10 In this implementation, the voltage level of the data signal increases as the gray level to be displayed by the pixel increases.

[0126] Apart from the fact that the connection positions of some circuit elements and the voltage levels of control signals (e.g., scan signals and data signals) change due to the change in transistor type, Figure 10 The configuration and operation of the first unit pixel SSPX1_1 shown are basically similar to Figure 9 The configuration and operation of the first unit pixel SSPX1 shown are illustrated. Therefore, the details regarding... Figure 10The detailed description of the first unit pixel SSPX1_1 shown is provided because those skilled in the art will be able to understand it from... Figure 9 The detailed description is understood.

[0127] Meanwhile, the structure of the pixel circuit PXC is not limited to Figure 9 and Figure 10 The implementation shown is illustrated. That is, the pixel circuit PXC can be configured as a pixel circuit using various structures and / or various driving methods known to those skilled in the art. For example, the pixel circuit PXC can be as follows: Figure 11 The implementation shown is configured as illustrated.

[0128] Reference Figure 11 In addition to the corresponding i-th scan line Si, the pixel circuit PXC in the first unit pixel SSPX1_2 can also be connected to at least another scan line (or control line). For example, the pixel circuit PXC of a sub-pixel (or a unit pixel included therein) located in the i-th row of the display area DA can be further connected to the (i-1)-th scan line Si-1 and / or the (i+1)-th scan line Si+1. Furthermore, in some embodiments, in addition to the first power supply VDD and the second power supply VSS, the pixel circuit PXC can also be connected to another power supply. For example, the pixel circuit PXC can also be connected to the initialization power supply Vint.

[0129] In some implementations, the pixel circuit PXC may include seven transistors T1 to T7. The pixel circuit PXC may include a first transistor T1 to a seventh transistor T7 and a storage capacitor Cst.

[0130] A first transistor T1 can be connected between a first power supply VDD and a light-emitting unit LSU. One electrode of the first transistor T1 (e.g., the source electrode) can be connected to the first power supply VDD via a fifth transistor T5, and the other electrode of the first transistor T1 (e.g., the drain electrode) can be connected to an electrode of the light-emitting unit LSU (e.g., the first electrode of the corresponding sub-pixel) via a sixth transistor T6. The gate electrode of the first transistor T1 can be connected to a first node N1. The first transistor T1 can provide a drive current to the light-emitting unit LSU in accordance with the voltage control of the first node N1.

[0131] The second transistor T2 can be connected between the j-th data line Dj and one electrode of the first transistor T1. The gate electrode of the second transistor T2 can be connected to the corresponding i-th scan line Si. The second transistor T2 can be turned on when a scan signal providing a gate turn-on voltage from the i-th scan line Si is applied, so as to electrically connect the j-th data line Dj to one electrode of the first transistor T1. Therefore, when the second transistor T2 is turned on, the data signal provided from the j-th data line Dj can be transmitted to the first transistor T1.

[0132] The third transistor T3 can be connected between the other electrode (e.g., the drain electrode) of the first transistor T1 and the first node N1. The gate electrode of the third transistor T3 can be connected to the corresponding i-th scan line Si. The third transistor T3 can be turned on when a scan signal providing a gate turn-on voltage from the i-th scan line Si is applied, allowing the first transistor T1 to be diode-connected.

[0133] The fourth transistor T4 can be connected between the first node N1 and the initialization power supply Vint. The gate electrode of the fourth transistor T4 can be connected to the previous scan line, such as the (i-1)th scan line Si-1. The fourth transistor T4 can be turned on when a scan signal with a gate on-voltage is provided to the (i-1)th scan line Si-1 to transmit the voltage of the initialization power supply Vint to the first node N1. The voltage of the initialization power supply Vint can be equal to or less than the minimum voltage of the data signal.

[0134] The fifth transistor T5 can be connected between the first power supply VDD and the first transistor T1. The gate electrode of the fifth transistor T5 can be connected to a corresponding emitter control line, such as the i-th emitter control line Ei. The fifth transistor T5 can be turned off when an emitter control signal with a gate cutoff voltage (e.g., a high voltage) is provided to the i-th emitter control line Ei, and turned on under other conditions.

[0135] The sixth transistor T6 can be connected between the first transistor T1 and the first electrode of the light-emitting unit LSU. The gate electrode of the sixth transistor T6 can be connected to a corresponding emission control line, such as the i-th emission control line Ei. The sixth transistor T6 can be turned off when an emission control signal with a gate cutoff voltage is provided to the i-th emission control line Ei, and turned on under other conditions.

[0136] The seventh transistor T7 can be connected between the first electrode of the light-emitting unit LSU and the initialization power supply Vint (or the third power line used to transmit the initialization power supply Vint). The gate electrode of the seventh transistor T7 can be connected to any one of the scan lines of the next stage, for example, the (i+1)th scan line Si+1. The seventh transistor T7 can be turned on when the scan signal with the gate on-state voltage is provided to the (i+1)th scan line Si+1, so as to provide the voltage of the initialization power supply Vint to one electrode of the light-emitting unit LSU.

[0137] The storage capacitor Cst can be connected between the first power supply VDD and the first node N1. The storage capacitor Cst can store the voltage corresponding to the data signal supplied to the first node N1 and the threshold voltage of the first transistor T1 in each frame period.

[0138] Although Figure 11The illustration shows a case where all transistors included in the pixel circuit PXC (e.g., first transistor T1 through seventh transistor T7) are P-type transistors, but this disclosure is not limited thereto. In the example, at least one of the first transistor T1 through seventh transistor T7 can be changed to an N-type transistor.

[0139] In some implementations, the pixel circuit PXC can be connected to another line in addition to the j-th data line Dj.

[0140] Reference Figure 12 The pixel circuit PXC in the first unit pixel SSPX1_3 can be connected to the sensing line SENj. The pixel circuit PXC may include a first transistor T1 to a third transistor T3 and a storage capacitor Cst. The first transistor T1, the second transistor T2, and the storage capacitor Cst are connected to a reference... Figure 10 The first transistor T1 and the second transistor T2, as well as the storage capacitor Cst, are substantially the same or similar, and therefore, overlapping descriptions will not be repeated.

[0141] The third transistor T3 can be connected between the sensing line SENj and the second node N2. The gate electrode of the third transistor T3 can be connected to a second scan line S2, which is different from the first scan line S1, wherein the first scan line S1 is connected to the gate electrode of the second transistor T2.

[0142] The light-emitting unit LSU can be connected between the second node N2 and the second electric line (i.e., the electric line to which the second power supply VSS is applied).

[0143] The third transistor T3 can be turned on in response to a scan signal of the gate turn-on voltage transmitted from the second scan line S2, so as to electrically connect the sensing line SENj and the second node N2.

[0144] For example, when the third transistor T3 is turned on with a drive current corresponding to the reference voltage flowing through the first transistor T1, the drive current flowing through the first transistor T1 can be provided to an external sensing device through the third transistor T3 and the sensing line SENj, and a signal corresponding to the characteristics of the first transistor T1 (e.g., the threshold voltage Vth) can be output to the outside through the sensing line SENj based on the drive current.

[0145] Furthermore, the structure of a unit pixel applicable to this disclosure is not limited to... Figures 9 to 12The embodiments shown are illustrated, and the unit pixel can have various structures currently known in the art. For example, the pixel circuit PXC included in the unit pixel can be configured as a pixel circuit using various structures and / or various driving methods. Furthermore, the unit pixel can be configured in a passive light-emitting display panel, etc. In some embodiments, the pixel circuit PXC can be omitted, and each of the first and second electrodes of the light-emitting unit LSU can be directly connected to the i-th scan line Si, the j-th data line Dj, the power line, and / or the control line.

[0146] Figure 13 It is shown in Figure 7 The diagram shows a planar layout of some components within a sub-pixel of the display panel. Figure 13 In this context, the light-emitting unit LSU (see SSPX1 to SSPX3) included in the unit pixels is used. Figures 9 to 12 (or light-emitting element layer), showing the structure of unit pixels SSPX1 to SSPX3. The first unit pixels SSPX1 to the third unit pixels SSPX3 are substantially identical to each other, and therefore, the light-emitting unit will be described based on the first unit pixel SSPX1.

[0147] Reference Figure 13 The first unit pixel SSPX1 may include a first electrode ETL1 and a second electrode ETL21 (or a second electrode ETL22 (in the case of the second unit pixel SSPX2) or a second electrode ETL23 (in the case of the third unit pixel SSPX3)) spaced apart from each other, and at least one light-emitting element LD connected between the first electrode ETL1 and the second electrode ETL21 (or the second electrode ETL22, or the second electrode ETL23).

[0148] In some embodiments, light-emitting elements (LDs) included in the same unit pixels SSPX1 to SSPX3 can emit light of the same color. In some embodiments, the first unit pixels SSPX1 to the third unit pixels SSPX3 can define light-emitting regions that emit different colors of light. In one example, the first unit pixel SSPX1 may include a light-emitting element LD that emits red light, the second unit pixel SSPX2 may include a light-emitting element LD that emits green light, and the third unit pixel SSPX3 may include a light-emitting element LD that emits blue light. In another example, all of the first unit pixels SSPX1 to the third unit pixels SSPX3 may include light-emitting elements LD that emit blue light. To form a full-color pixel PXL, a light conversion layer and / or a color filter for converting the color of light emitted from the respective unit pixels may be located on top of at least some of the first unit pixels SSPX1 to the third unit pixels SSPX3.

[0149] In some embodiments, the first electrode ETL1 may be an electrode shared by the first unit pixel SSPX1 to the third unit pixel SSPX3. The first unit pixel SSPX1 to the third unit pixel SSPX3 may be arranged along the first direction DR1.

[0150] The second electrodes ETL21, ETL22, and ETL23 of the first unit pixel SSPX1 to the third unit pixel SSPX3 can be spaced apart from the first electrode ETL1 in the second direction DR2. The second electrodes ETL21, ETL22, and ETL23 of the first unit pixel SSPX1 to the third unit pixel SSPX3 can be arranged in the first direction DR1.

[0151] The first electrode ETL1 and the second electrodes ETL21, ETL22 and ETL23 can be positioned side by side (parallel) to be spaced apart from each other by a set distance or a predetermined distance.

[0152] In some embodiments, the first electrode ETL1 may be a cathode electrode electrically connected to a second power supply VSS. Each of the second electrodes ETL21, ETL22, and ETL23 may be an anode electrode electrically connected to a first power supply VDD. Light-emitting elements LD, each having one end electrically connected to the first electrode ETL1 and the other end of the second electrodes ETL21, ETL22, and ETL23 respectively, are located at the first electrode ETL1 and the second electrodes ETL21, ETL22, and ETL23, such that the first electrode ETL1 can be electrically connected to each of the second electrodes ETL21, ETL22, and ETL23 respectively.

[0153] In some implementations, each unit pixel (e.g., SSPX1) may define a light-emitting region. The light-emitting region may be defined by a non-light-emitting region. Although not explicitly shown, a pixel-defining layer (e.g., a dam or light-blocking pattern) used to block light emitted from the light-emitting element LD from passing through another region, etc., may overlap with the non-light-emitting region. In this specification, the term "overlap" means that two components overlap each other in the thickness direction (e.g., third direction DR3) of the display panel 21, unless otherwise specifically defined.

[0154] Figure 14 This is along some exemplary embodiments of the present disclosure. Figure 13 The line I-I' shown is a cross-sectional view of the display panel. Figure 15 This is along some exemplary embodiments of the present disclosure. Figure 7 The cross-sectional view of the display panel is shown by line II-II'. Figure 16 This is along some exemplary embodiments of the present disclosure. Figure 7The image shows a cross-sectional view of the display panel taken by line III-III'. The display panel will be described below based on the first pad PAD1.

[0155] Reference Figures 14 to 16 The display panel 21 may include a base layer SUB1 located at the bottom of the display panel 21. The base layer SUB1 has already been described above, and therefore, overlapping descriptions are unnecessary.

[0156] The first buffer layer 111 is located on the base layer SUB1. The first buffer layer 111 smooths the surface of the base layer SUB1 and serves to prevent or reduce the penetration of moisture or external air into the components of the display panel 21. The first buffer layer 111 may be an inorganic layer. The first buffer layer 111 may be a single layer or multiple layers.

[0157] Multiple transistors Tdr and Tsw are located on the first buffer layer 111. Each of transistors Tdr and Tsw can be a thin-film transistor. Two transistors Tdr and Tsw can be a driving transistor and a switching transistor, respectively.

[0158] Transistors Tdr and Tsw may include semiconductor patterns ACT1 and ACT2, gate electrodes GE1 and GE2, source electrodes SDE2 and SDE4, and drain electrodes SDE1 and SDE3. For example, the first transistor Tdr can be used as a driving transistor and may include a first semiconductor pattern ACT1, a first gate electrode GE1, a first source electrode SDE2, and a first drain electrode SDE1. The second transistor Tsw can be used as a switching transistor and may include a second semiconductor pattern ACT2, a second gate electrode GE2, a second source electrode SDE4, and a second drain electrode SDE3.

[0159] In some embodiments, a semiconductor layer is located on the first buffer layer 111. The semiconductor layer may include the first semiconductor pattern ACT1 and the second semiconductor pattern ACT2 described above. In addition, the semiconductor layer may also include a third semiconductor pattern ACT3.

[0160] In some embodiments, the semiconductor layer may include amorphous silicon, polycrystalline silicon, cryogenic polycrystalline silicon, and organic semiconductors. In some embodiments, the semiconductor layer may be an oxide semiconductor. Although not explicitly shown, the semiconductor layer may include a channel region and source and drain regions located on corresponding sides of the channel region and doped with impurities.

[0161] The first gate insulating layer 112 is located above the semiconductor layer. The first gate insulating layer 112 can be an inorganic layer. The first gate insulating layer 112 can be a single layer or multiple layers.

[0162] The first conductive layer is located on the first gate insulating layer 112. The first conductive layer may include a first gate electrode GE1 and a second gate electrode GE2. Furthermore, the first conductive layer may also include a first low-power pattern VSSL1 and first pad patterns 201 and 211. The first conductive layer may be made of metal or a metal alloy, or may include a conductive metallic material (e.g., formed from a conductive metallic material). For example, the first conductive layer may include molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc. The first conductive layer may be a single layer or multiple layers.

[0163] The first low-power pattern VSSL1 can be electrically connected to the second power line. The first low-power pattern VSSL1 can contact the second low-power pattern VSSL2 through contact holes penetrating the second gate insulating layer 113 and the interlayer insulating layer 114. The first low-power pattern VSSL1 can be located in the display area DA and overlap with the third semiconductor pattern ACT3.

[0164] The first pad patterns 201 and 211 can be located in the pad area PDA. The first pad patterns 201 and 211 can be conductive layers located at the bottom of the first pad PAD1 and the second pad PAD2, respectively.

[0165] The second gate insulating layer 113 is located above the first conductive layer. The second gate insulating layer 113 may be an inorganic layer. The second gate insulating layer 113 may be a single layer or multiple layers.

[0166] The second conductive layer is located on the second gate insulating layer 113. The second conductive layer may include a third gate electrode GE3. The third gate electrode GE3 may be the gate electrode of a transistor (not shown), but this disclosure is not limited thereto. The second conductive layer may be made of metal or metal alloy, or may include a conductive metal material (e.g., formed of a conductive metal material). For example, the second conductive layer may include molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc. The second conductive layer may be a single layer or multiple layers.

[0167] Interlayer insulating layer 114 is located above the second conductive layer. Interlayer insulating layer 114 can be an organic layer or an inorganic layer. Interlayer insulating layer 114 can be a single layer or multiple layers.

[0168] In one embodiment, the interlayer insulating layer 114 may not be located in the pad area PDA. However, this is merely illustrative, and the interlayer insulating layer 114 may be located in the display area DA and the non-display area NDA, which includes the pad area PDA.

[0169] The third conductive layer is located on the interlayer insulating layer 114. The third conductive layer may include the source electrodes SDE2 and SDE4 and the drain electrodes SDE1 and SDE3 described above. Furthermore, the third conductive layer may also include a second low-power pattern VSSL2 and second pad patterns 202 and 212. The third conductive layer may be made of metal or a metal alloy, or may include a conductive metallic material (e.g., formed from a conductive metallic material). For example, the source electrodes SDE2 and SDE4 and the drain electrodes SDE1 and SDE3 may include aluminum (Al), copper (Cu), titanium (Ti), molybdenum (Mo), etc.

[0170] The second low-power pattern VSSL2 can be electrically connected to the second power line. The second low-power pattern VSSL2 can contact the first low-power pattern VSSL1 through contact holes penetrating the second gate insulating layer 113 and the interlayer insulating layer 114. The second low-power pattern VSSL2 can be located in the display area DA and overlap with the first low-power pattern VSSL1 and the third semiconductor pattern ACT3.

[0171] The second pad patterns 202 and 212 can be located in the pad area of ​​the PDA. In an embodiment, the second pad patterns 202 and 212 can be located directly on the first pad patterns 201 and 211.

[0172] The source electrodes SDE2 and SDE4 and the drain electrodes SDE1 and SDE3 can be electrically connected to the source and drain regions of the corresponding semiconductor patterns ACT1 and ACT2 respectively through contact holes penetrating the interlayer insulating layer 114, the second gate insulating layer 113 and the first gate insulating layer 112.

[0173] Although not shown separately, the display panel 21 may also include storage capacitors located on the base layer SUB1.

[0174] The first protective layer 121 is located above the third conductive layer. The first protective layer 121 is located at the circuit including transistors Tdr and Tsw. The first protective layer 121 may be located at least a portion of the non-display area NDA and a portion of the pad area PDA. The first protective layer 121 may be a passivation layer or a planarization layer. The passivation layer may include SiO2 or SiN. x The planarization layer may include materials such as acrolein or polyimide. The first protective layer 121 may include both a passivation layer and a planarization layer. The passivation layer may be located on the third conductive layer and the interlayer insulating layer 114, and the planarization layer may be located on the passivation layer. The upper surface of the first protective layer 121 may be planarized.

[0175] A fourth conductive layer may be located on the first protective layer 121. The fourth conductive layer may include several conductive patterns, such as power lines, signal lines, and connection electrodes. The accompanying drawings illustrate a case where the fourth conductive layer includes a first connection pattern CE1 located in the display area DA and third pad patterns 203 and 213 located in the pad area PDA. The fourth conductive layer may be made of metal or a metal alloy, or may include a conductive metallic material (e.g., formed from a conductive metallic material). For example, the fourth conductive layer may include aluminum (Al), copper (Cu), titanium (Ti), molybdenum (Mo), etc.

[0176] The first connection pattern CE1 can contact either the first source electrode SDE2 or the first drain electrode SDE1 of the first transistor Tdr through a contact hole penetrating the first protective layer 121.

[0177] In some implementations, the third pad patterns 203 and 213 can be directly disposed on the second pad patterns 202 and 212.

[0178] The second protective layer 122 is located above the fourth conductive layer. The second protective layer 122 can be a passivation layer or a planarization layer. The passivation layer can include SiO2 or SiN. x The planarization layer may include materials such as acrolein or polyimide. The second protective layer 122 may include both a passivation layer and a planarization layer.

[0179] Meanwhile, the second protective layer 122 may include an opening that exposes the upper portion of a portion of the conductive pattern included in the fourth conductive layer. For example, the second protective layer 122 may include an opening that exposes at least a portion of the first connection pattern CE1 and another opening that exposes at least a portion of the third pad patterns 203 and 213.

[0180] The base layer SUB1 to the second protective layer 122 can be referred to as the pixel circuit layer.

[0181] Based on the display area DA, the first partition wall PW1 and the second partition wall PW2, the first electrode ETL1 and the second electrode ETL21, the first insulating layer 131, the light-emitting element LD, the second insulating layer 132, the first contact electrode CNE1 and the second contact electrode CNE2, the third insulating layer 141 and the thin film encapsulation layer 151 can be sequentially positioned on the second protective layer 122.

[0182] The first separator wall PW1 and the second separator wall PW2 may be located on the pixel circuit layer (i.e., on the second protective layer 122). The first separator wall PW1 and the second separator wall PW2 may protrude on the pixel circuit layer in the thickness direction (e.g., the third direction DR3). In some embodiments, the first separator wall PW1 and the second separator wall PW2 may have substantially the same height, but this disclosure is not limited thereto. For example, the protrusion height of each of the first separator wall PW1 and the second separator wall PW2 may be about 1.0 µm to 1.5 µm.

[0183] In this implementation, the first partition wall PW1 may be located between the pixel circuit layer and the first electrode ETL1. The second partition wall PW2 may be located between the pixel circuit layer and the second electrodes ETL21, ETL22 and ETL23.

[0184] In some embodiments, the first partition wall PW1 and the second partition wall PW2 can have various shapes. In some embodiments, the first partition wall PW1 and the second partition wall PW2 can have a trapezoidal cross-sectional shape, the width of which becomes narrower as it approaches its top. Each of the first partition wall PW1 and the second partition wall PW2 can have an inclined surface on at least one side.

[0185] Although not shown, in another example, the first partition wall PW1 and the second partition wall PW2 may have a semi-circular or semi-elliptical cross-section, the width of which becomes narrower near its top. Each of the first partition wall PW1 and the second partition wall PW2 may have a curved surface on at least one side. That is, in this disclosure, the shape of the first partition wall PW1 and the second partition wall PW2 is not particularly limited and can be varied. In some embodiments, at least one of the first partition wall PW1 and the second partition wall PW2 may be omitted, and their positions may be changed.

[0186] The first separator wall PW1 and the second separator wall PW2 may comprise insulating materials having inorganic and / or organic materials. In the example, the first separator wall PW1 and the second separator wall PW2 may comprise various inorganic insulating materials currently known in the art (including SiN). x SiO x At least one inorganic layer (e.g., organic layer, inorganic layer, etc.). Optionally, the first separator PW1 and the second separator PW2 may comprise at least one organic layer having various organic insulating materials currently known in the art and / or at least one photoresist layer, or be configured as a single-layer or multi-layer insulating structure comprising organic materials and / or inorganic materials. That is, the materials constituting the first separator PW1 and the second separator PW2 can be varied.

[0187] In some implementations, the first partition wall PW1 and the second partition wall PW2 can be used as reflective members. In an example, the first partition wall PW1 and the second partition wall PW2, together with the first electrode ETL1 and the second electrode ETL21 on the first partition wall PW1 and the second partition wall PW2 (e.g., on top of them), can be used as reflective members, which can improve the light efficiency of the pixel PXL by guiding the light emitted from the respective light-emitting element LD in the desired direction.

[0188] The first electrode ETL1 and the second electrode ETL21 may be located on the first partition wall PW1 and the second partition wall PW2 (e.g., on their tops), respectively. The first electrode ETL1 and the second electrode ETL21 may be spaced apart from each other.

[0189] In some embodiments, the first electrode ETL1 and the second electrode ETL21 on the first partition wall PW1 and the second partition wall PW2 may have shapes corresponding to the shapes of the first partition wall PW1 and the second partition wall PW2, respectively. For example, the first electrode ETL1 and the second electrode ETL21 may protrude in the thickness direction of the display panel 21 and have inclined surfaces or curved surfaces corresponding to the first partition wall PW1 and the second partition wall PW2, respectively.

[0190] Each of the first electrode ETL1 and the second electrode ETL21 may include at least one conductive material. In the example, each of the first electrode ETL1 and the second electrode ETL21 may include at least one material selected from metals such as Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Ti or any metal alloy thereof, conductive oxides such as ITO, IZO, ZnO or ITZO, and conductive polymers such as PEDOT, but this disclosure is not limited thereto.

[0191] Furthermore, each of the first electrode ETL1 and the second electrode ETL21 can be configured as a single layer or multiple layers. In some embodiments, each of the first electrode ETL1 and the second electrode ETL21 may include at least one reflective electrode layer. Additionally, each of the first electrode ETL1 and the second electrode ETL21 may selectively include at least one transparent electrode layer located on top of and / or at the bottom of the reflective electrode layer, and at least one capping layer covering the top of the reflective electrode layer and / or the transparent electrode layer.

[0192] In some embodiments, the reflective electrode layer of each of the first electrode ETL1 and the second electrode ETL21 may be made of an electrode material having uniform reflectivity. In examples, the reflective electrode layer may include at least one of metals and metal alloys thereof, such as Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, and Cr, but this disclosure is not limited thereto. That is, the reflective electrode layer may be made of a variety of reflective electrode materials. When each of the first electrode ETL1 and the second electrode ETL21 includes a reflective electrode layer, the first electrode ETL1 and the second electrode ETL21 may allow light emitted from both ends (i.e., one end and the other end) of the respective light-emitting element LD to propagate further in the direction along which it displays the image (e.g., the third-direction DR3 or the forward direction). Specifically, when the first electrode ETL1 and the second electrode ETL21 face one end and the other end of the corresponding light-emitting element LD, and each has an inclined surface or a curved surface corresponding to the shape of the first partition wall PW1 and the second partition wall PW2, the light emitted at one end and the other end of the corresponding light-emitting element LD is reflected by the first electrode ETL1 and the second electrode ETL21 to further propagate in the forward direction of the display panel 21 (e.g., the third direction DR3 above the base layer SUB1). Therefore, the efficiency of light emitted from the light-emitting element LD can be improved.

[0193] Furthermore, the transparent electrode layer of each of the first electrode ETL1 and the second electrode ETL21 can be made of various transparent electrode materials. In some embodiments, the transparent electrode layer may include ITO, IZO, or ITZO, but this disclosure is not limited thereto. In some embodiments, each of the first electrode ETL1 and the second electrode ETL21 can be configured as a three-layer structure having an ITO / Ag / ITO stacked structure. When each of the first electrode ETL1 and the second electrode ETL21 is configured as a multilayer comprising at least two layers, the voltage drop caused by signal delay (RC delay) can be minimized or reduced. Therefore, the desired voltage can be efficiently delivered to the light-emitting element LD.

[0194] Additionally, when each of the first electrode ETL1 and the second electrode ETL21 includes a conductive capping layer covering the reflective electrode layer and / or the transparent electrode layer, damage to the reflective electrode layer, etc., of each of the first electrode ETL1 and the second electrode ETL21 due to defects occurring during the manufacturing process of the pixel PXL can be prevented (or the chance of damage can be reduced). However, the conductive capping layer can be optionally included in the first electrode ETL1 and the second electrode ETL21. In some embodiments, the conductive capping layer can be omitted. Furthermore, the conductive capping layer can be considered as a component of each of the first electrode ETL1 and the second electrode ETL21, or as a separate component located on each of the first electrode ETL1 and the second electrode ETL21.

[0195] In some embodiments, at least a portion of the second electrodes ETL21, ETL22, and ETL23 may overlap with the first connection pattern CE1. The second electrodes ETL21, ETL22, and ETL23 may contact the first connection pattern CE1 through the first contact hole CH penetrating the second protective layer 122.

[0196] In some embodiments, in the pad area PDA, the fourth pad patterns 204 and 214 may be directly located on the third pad patterns 203 and 213. The fourth pad patterns 204 and 214 may be formed to cover the third pad patterns 203 and 213 and a portion of the second protective layer 122. In some embodiments, the fourth pad patterns 204 and 214 may be disposed on the same layer as the first electrode ETL1 and the second electrode ETL21. That is, the fourth pad patterns 204 and 214 may comprise the same material as the first electrode ETL1 and the second electrode ETL21, and may be positioned (e.g., formed) simultaneously (e.g., synchronously) with the first electrode ETL1 and the second electrode ETL21 in the same manner.

[0197] The fourth pad patterns 204 and 214 can be used as a primary capping layer to prevent (or substantially prevent) damage to the top of the third pad patterns 203 and 213 during the manufacture of the display panel 21 (or reduce the chance of the third pad patterns 203 and 213 being damaged).

[0198] In some implementations, the first pad patterns 201 and 211, the third pad patterns 203 and 213, and the fourth pad patterns 204 and 214 may have the same width.

[0199] The first insulating layer 131 may be partially positioned on the first electrode ETL1 and the second electrode ETL21 in the display area DA. For example, the first insulating layer 131 may be formed to cover one or more areas of the first electrode ETL1 and the second electrode ETL21, and include an opening that exposes another area of ​​the first electrode ETL1 and the second electrode ETL21.

[0200] In some embodiments, the first insulating layer 131 may be initially positioned (e.g., formed) to completely cover the first electrode ETL1 and the second electrode ETL21. Once the light-emitting element LD is placed and aligned on the first insulating layer 131, the first insulating layer 131 may be partially opened to expose the first electrode ETL1 and the second electrode ETL21. Alternatively, once the light-emitting element LD is placed and aligned, the first insulating layer 131 may be patterned into a discrete pattern partially placed beneath the light-emitting element LD.

[0201] That is, the first insulating layer 131 is interposed between the first electrode ETL1 and the second electrode ETL21 and the light-emitting element LD, and can expose at least one area of ​​each of the first electrode ETL1 and the second electrode ETL21. Once the first electrode ETL1 and the second electrode ETL21 are formed, the first insulating layer 131 is formed to cover the first electrode ETL1 and the second electrode ETL21, thereby preventing damage or metal deposition of the first electrode ETL1 and the second electrode ETL21 in subsequent processes (or reducing the chance of damage). In addition, the first insulating layer 131 can stably support each of the light-emitting elements LD. In some embodiments, the first insulating layer 131 may be omitted.

[0202] The light-emitting element (LD) can be provided and aligned in the area of ​​the display panel 21 in which the first insulating layer 131 is disposed. In some embodiments, the light-emitting element (LD) can be provided by inkjet technology or the like, and can be aligned between the first electrode ETL1 and the second electrode ETL21 by applying a set or predetermined alignment voltage (or alignment signal) to the first electrode ETL1 and the second electrode ETL21.

[0203] In some embodiments, the first insulating layer 131 may have a thickness of about 2500 Å to 3500 Å.

[0204] The embankment BNK can be located on the first insulating layer 131. In some embodiments, the embankment BNK can be located (e.g., formed on) between two adjacent sub-pixels to surround the sub-pixel. Figure 8 As shown in SPX1 to SPX3, these constitute a pixel-defining layer that defines the light-emitting area.

[0205] In some embodiments, the embankment BNK may not be located between unit pixels SSPX1 to SSPXk in the same sub-pixels of sub-pixels SPX1 to SPX3, but this disclosure is not limited thereto.

[0206] In some embodiments, the first insulating layer 131 may not be located (e.g., formed in the pad area of ​​the PDA), but this disclosure is not limited thereto.

[0207] The second insulating layer 132 may be located on the light-emitting element LD (e.g., on top of it), for example, on the light-emitting element LD aligned between the first electrode ETL1 and the second electrode ETL21, and may expose both ends of the light-emitting element LD. For example, the second insulating layer 132 may be partially disposed on the light-emitting element LD without covering both ends of the light-emitting element LD. The second insulating layer 132 may be located as a separation pattern in (e.g., formed in) each light-emitting region, but this disclosure is not limited thereto. Furthermore, when there is a separation space between the first insulating layer 131 and the light-emitting element LD before the formation of the second insulating layer 132, the space may be as follows: Figure 14 The image shown is filled with a second insulating layer 132. Therefore, the light-emitting element LD can be supported more stably.

[0208] In some embodiments, the second insulating layer 132 may have a thickness of about 7,500 Å to 8,500 Å.

[0209] In some embodiments, the second insulating layer 132 may not be located (e.g., formed in) the pad area of ​​the PDA, but this disclosure is not limited thereto.

[0210] The first contact electrode CNE1 and the second contact electrode CNE2 can be located on one end and the other end of the light-emitting element LD. In some embodiments, the first contact electrode CNE1 and the second contact electrode CNE2 can be as follows: Figure 14 The electrodes shown are disposed in the same layer. The first contact electrode CNE1 and the second contact electrode CNE2 can be formed using the same electrode material in the same process, but this disclosure is not limited thereto.

[0211] The first contact electrode CNE1 and the second contact electrode CNE2 can respectively connect one end and the other end of the light-emitting element LD to the first electrode ETL1 and the second electrode ETL21.

[0212] For example, a first contact electrode CNE1 can be disposed on the first electrode ETL1 to contact the first electrode ETL1. In some embodiments, the first contact electrode CNE1 can contact the first electrode ETL1 in a region of the first electrode ETL1 not covered by the first insulating layer 131. Furthermore, the first contact electrode CNE1 can be located on one end of at least one light-emitting element LD; for example, multiple light-emitting elements LDs adjacent to the first electrode ETL1 can contact the first electrode ETL1 at one end of their respective light-emitting elements LDs. That is, the first contact electrode CNE1 can cover one end of at least one light-emitting element LD and at least one corresponding region of the first electrode ETL1. Therefore, one end of at least one light-emitting element LD can be electrically connected to the first electrode ETL1.

[0213] Similarly, the second contact electrode CNE2 can be located on the second electrodes ETL21, ETL22, and ETL23 to contact them. In some embodiments, the second contact electrode CNE2 can contact the second electrode ETL21 in a region not covered by the first insulating layer 131. Furthermore, the second contact electrode CNE2 can be located at the ends of at least two light-emitting elements LDs adjacent to the second electrode ETL21 to contact the ends of at least two light-emitting elements LDs. That is, the second contact electrode CNE2 can cover one or more ends of at least two light-emitting elements LDs and at least one corresponding region of the second electrode ETL21. Therefore, one and the other ends of at least two light-emitting elements LDs can be electrically connected to the second electrode ETL21.

[0214] That is, one end of the light-emitting element LD can contact the first contact electrode CNE1, and the other end of the light-emitting element LD can contact the second contact electrode CNE2.

[0215] In some embodiments, in the pad area PDA, fifth pad patterns 205 and 215 may be directly located on the fourth pad patterns 204 and 214. The fifth pad patterns 205 and 215 correspond to the pad patterns located at the uppermost part of each of pads PAD1 and PAD2. The fifth pad patterns 205 and 215 may be disposed on the same layer as the first contact electrode CNE1 and the second contact electrode CNE2. That is, the fifth pad patterns 205 and 215 may comprise the same material as the first contact electrode CNE1 and the second contact electrode CNE2, and may be positioned (e.g., formed) simultaneously (e.g., synchronously) in the same manner.

[0216] In an embodiment, the fifth pad patterns 205 and 215, as well as the first contact electrode CNE1 and the second contact electrode CNE2, can be made of a transparent conductive material such as ITO, IZO, or ITZO, so that light emitted from the light-emitting element LD can be transmitted through them.

[0217] In some embodiments, the fifth pad patterns 205 and 215 may include a groove at their upper portion. External terminals contacting the first pad PAD1 can contact the first pad PAD1 through the groove at the upper portion of the fifth pad patterns 205 and 215. In some embodiments, the groove may have a width w1 of about 20 µm or more and a depth h1 of about 1 µm or less. That is, the groove at the upper portion of the first pad PAD1 may have a width w1 to depth h1 ratio of 20 or more.

[0218] The fifth pad patterns 205 and 215 can function as a secondary capping layer to prevent damage to the tops of the third pad patterns 203 and 213 during the manufacturing process of the display panel 21. For example, the fifth pad patterns 205 and 215 can function as a secondary capping layer to reduce the chance of damage to the tops of the third pad patterns 203 and 213 during the manufacturing process of the display panel 21.

[0219] In some implementations, the width of the fifth pad patterns 205 and 215 may be equal to the width of the second pad patterns 202 and 212.

[0220] The third insulating layer 141 may be formed and / or disposed on the first partition wall PW1 and the second partition wall PW2, the first electrode ETL1 and the second electrode ETL21, the light-emitting element LD, the first contact electrode CNE1 and the second contact electrode CNE2, and the embankment BNK, to cover the first partition wall PW1 and the second partition wall PW2, the first electrode ETL1 and the second electrode ETL21, the light-emitting element LD, the first contact electrode CNE1 and the second contact electrode CNE2, and the embankment BNK.

[0221] In some embodiments, the third insulating layer 141 may have a thickness of about 2500 Å to 3500 Å.

[0222] In some embodiments, each of the first insulating layer 131, the second insulating layer 132, and the third insulating layer 141 may be configured as a single layer or multiple layers, and may comprise at least one inorganic insulating material and / or at least one organic insulating material. For example, each of the first insulating layer 131, the second insulating layer 132, and the third insulating layer 141 may comprise various types of organic / inorganic insulating materials (including SiN) known to those skilled in the art. xFurthermore, there are no particular limitations on the materials constituting each of the first insulating layer 131, the second insulating layer 132, and the third insulating layer 141. Additionally, the first insulating layer 131, the second insulating layer 132, and the third insulating layer 141 may comprise different insulating materials. Optionally, at least some of the first insulating layer 131, the second insulating layer 132, and the third insulating layer 141 may comprise the same insulating material.

[0223] A thin-film encapsulation layer 151, comprising at least one inorganic layer and / or at least one organic layer, may be located on the third insulating layer 141. The thin-film encapsulation layer 151 may be an insulating layer. In some embodiments, the thin-film encapsulation layer 151 may be omitted.

[0224] In some embodiments, the thin-film encapsulation layer 151 may be located (e.g., formed) over the entire display area DA. In some embodiments, the thin-film encapsulation layer 151 may be formed to expose the upper portion of the fifth pad patterns 205 and 215 in the pad area PDA, and thus expose each recess of pads PAD1 and PAD2.

[0225] The thin-film encapsulation layer 151 may overlap with a portion of the edges of the fifth pad patterns 205 and 215. In some embodiments, the width w2 of the region in which the thin-film encapsulation layer 151 overlaps with the fifth pad patterns 205 and 215 may be about 2µm to 3µm.

[0226] In some embodiments, the thickness h2 of the thin-film encapsulation layer 151 may be about 6000 Å or less.

[0227] The second pad PAD2 may be adjacent to the first pad PAD1. The second pad PAD2 may also be separate from the first pad PAD1, with insulating material inserted between the two pads. In one embodiment, the distance between the first pad PAD1 and the second pad PAD2 may be approximately 15µm to 25µm.

[0228] Each of pads PAD1 and PAD2 may be surrounded by an insulating material. In some embodiments, the step difference h3 between the top of each of pads PAD1 and PAD2 (i.e., the top of the fifth pad patterns 205 and 215) and the insulating material between pads PAD1 and PAD2 (i.e., the top of the thin film encapsulation layer 151) may be from about 0.6 µm to 2.0 µm.

[0229] The tops of pads PAD1 and PAD2 are positioned (e.g., formed) together with fourth pad patterns 204 and 214 and fifth pad patterns 205 and 215, thereby preventing oxide layers from being positioned (e.g., formed) on third pad patterns 203 and 213 during manufacturing, or reducing the chance of oxide layers forming on third pad patterns 203 and 213 during manufacturing. Therefore, the additional mask used to prevent oxide layers from being positioned (e.g., formed) on third pad patterns 203 and 213 can be minimized or reduced.

[0230] Next, a display panel according to another embodiment will be described. In the following text, with reference to... Figures 1 to 16 The same or similar parts are indicated by the same reference numerals, and overlapping descriptions may not be repeated.

[0231] Figures 17 to 19 This is a cross-sectional view of a display panel according to some embodiments of the present disclosure. Figures 17 to 19 According to some exemplary embodiments of this disclosure, corresponding to the... Figure 15 The modifications.

[0232] Reference Figure 17 According to this exemplary embodiment, the display panel 21_1 and Figure 15 The difference in the display panel 21 shown is that the first pad pattern 201_1 corresponds to the second conductive layer.

[0233] Reference Figure 18 According to this exemplary embodiment, the display panel 21_2 and Figure 15 The difference in the display panel 21 shown is that the fourth pad pattern 204 is omitted. The fifth pad pattern 205 can be placed directly on the third pad pattern 203.

[0234] Reference Figure 19 According to this embodiment, the display panel 21_3 and Figure 15 The difference in the display panel 21 shown is that the second pad pattern 202 is not directly located on the first pad pattern 201, and the third pad pattern 203 is not directly located on the second pad pattern 202. The second gate insulating layer 113 may be located on the first pad pattern 201, and the first protective layer 121 may be located on the second pad pattern 202. The second pad pattern 202 can contact the first pad pattern 201 through a second contact hole CNT2 located (e.g., formed in) the second gate insulating layer 113. The third pad pattern 203 can contact the second pad pattern 202 through a third contact hole CNT3 located (e.g., formed in) the first protective layer 121.

[0235] Although the accompanying drawings show a second contact hole CNT2 and a third contact hole CNT3 located (e.g., formed in) the second gate insulating layer 113 and the first protective layer 121, respectively, this disclosure is not limited thereto. Multiple second contact holes CNT2 and multiple third contact holes CNT3 may be located (e.g., formed in) the second gate insulating layer 113 and the first protective layer 121, respectively.

[0236] Figure 20 and Figure 21 This is a cross-sectional view of a display panel according to yet another embodiment of the present disclosure. Figure 20 and Figure 21 Corresponding to the pair Figure 14 and Figure 15 The modifications.

[0237] Reference Figure 20 and Figure 21 According to some embodiments of the present disclosure, the display panel 22 and Figure 15 The difference between the display panel 21 shown is that the display panel 22 also includes a fourth insulating layer 133, and the first contact electrode CNE1 and the second contact electrode CNE2 are located in different layers.

[0238] In some embodiments, the fourth insulating layer 133 may be located above the second contact electrode CNE2. The fourth insulating layer 133 may be formed to cover the second contact electrode CNE2.

[0239] After the second contact electrode CNE2 is formed, the first contact electrode CNE1 can be formed. The first contact electrode CNE1 can be partially disposed at the fourth insulating layer 133.

[0240] In some embodiments, the first contact electrode CNE1 may include a conductive material having a work function of less than about 4.1 eV, such as Al, Ti, Cr, etc. The second contact electrode CNE2 may include a conductive material having a work function of greater than about 7.5 eV, such as Ni, ITO, etc.

[0241] The fifth pad pattern 205_1 may be located (e.g., formed on) the same layer as the second contact electrode CNE2.

[0242] Figure 22 This is a cross-sectional view of a display panel according to yet another exemplary embodiment of the present disclosure. Figure 22 According to some exemplary embodiments of this disclosure, corresponding to Figure 21 The modifications.

[0243] Reference Figure 22 According to some embodiments of this disclosure, the display panel 22_1 and Figure 21The difference in the display panel 22 shown is that the fifth pad pattern 205_2 can be located (e.g., formed on) the same layer as the first contact electrode CNE1.

[0244] Figures 23 to 26 This is an exemplary circuit diagram of first unit pixels SSPX1_4, SSPX1_5, SSPX1_6 and SSPX1_7 in the sub-pixels of a display panel, according to yet another exemplary embodiment of this disclosure. Figures 23 to 26 Corresponding to Figures 9 to 12 The modifications.

[0245] Reference Figures 23 to 26 Multiple light-emitting elements (LDs) can be connected in series and / or in parallel.

[0246] Figure 27 This is a plan view showing the arrangement of some components in a first sub-pixel SPX1_1 of a display panel 23 according to yet another exemplary embodiment of the present disclosure. Figure 28 It is along Figure 27 The cross-sectional view of the display panel 23 is shown by line IV-IV'. Figure 27 and Figure 28 The display panel 23 shown corresponds to the application. Figures 23 to 26 The embodiment of the light-emitting element LD shown is illustrated. The first unit pixel SSPX1 to the third unit pixel SSPX3 are identical to each other, and therefore, the first unit pixel SSPX1 will be described primarily.

[0247] Reference Figure 27 and Figure 28 Display panel 23 and Figure 13 and Figure 14 The difference in the display panel 21 shown is that it includes an island electrode between the first electrode ETL1 and the second electrodes ETL21, ETL22 and ETL23.

[0248] The first electrode ETL1, second electrode ETL21, third electrode ETL31, and fourth electrode ETL41 in the first unit pixel SSPX1 can extend generally in the first direction DR1 and can be positioned side-by-side (parallel) to be spaced apart from each other in the second direction DR2 by a set distance or a predetermined distance. In some embodiments, the extension length of the first electrode ETL1 in the first direction DR1 can be longer than the extension lengths of the second electrode ETL21, third electrode ETL31, and fourth electrode ETL41 in the first direction DR1. The third electrode ETL31 and fourth electrode ETL41 can be located between the first electrode ETL1 and the second electrode ETL21. The third electrode ETL31 and fourth electrode ETL41 can be island electrodes separated from the first electrode ETL1 and the second electrode ETL21. Therefore, each of the third electrode ETL31 and the fourth electrode ETL41 can be referred to as an island electrode.

[0249] In some embodiments, the first electrode ETL1 may be an electrode shared by the first unit pixel SSPX1 to the third unit pixel SSPX3. The first unit pixel SSPX1 to the third unit pixel SSPX3 may be arranged along a first direction DR1. The first electrode ETL1, the second electrode ETL22, the third electrode ETL32, and the fourth electrode ETL42 in the second unit pixel SSPX2 may extend substantially along the first direction DR1 and may be positioned side-by-side (parallel) to be spaced apart from each other by a set distance or a predetermined distance in the second direction DR2. Similarly, the first electrode ETL1, the second electrode ETL23, the third electrode ETL33, and the fourth electrode ETL43 in the third unit pixel SSPX3 may extend substantially along the first direction DR1 and may be positioned side-by-side (parallel) to be spaced apart from each other by a set distance or a predetermined distance in the second direction DR2.

[0250] The light-emitting element (LD) can be placed between the first electrode ETL1 and the third electrode ETL31, between the second electrode ETL21 and the fourth electrode ETL41, and between the third electrode ETL31 and the fourth electrode ETL41.

[0251] The first transistor Tdr can be used as a driving transistor and may include a first semiconductor pattern ACT21, a first gate electrode GE21, a first source electrode SDE31, and a first drain electrode SDE41. The second transistor Tsw can be used as a switching transistor and may include a second semiconductor pattern ACT11, a second gate electrode GE11, a second source electrode SDE11, and a second drain electrode SDE21.

[0252] In the attached figures (e.g., Figure 28An example of a fourth conductive layer on a first protective layer 121, comprising first conductive patterns CE1 to fifth conductive patterns CE5, is shown in the figure.

[0253] The second conductive pattern CE2 can be connected to either the first source electrode SDE31 or the first drain electrode SDE41 of the first transistor Tdr through a contact hole penetrating the first protective layer 121, and the fifth conductive pattern CE5 can be connected to the other of the first source electrode SDE31 and the first drain electrode SDE41 of the first transistor Tdr through another contact hole penetrating the first protective layer 121.

[0254] The first partition wall PW1, the second partition wall PW21, the third partition wall PW31 and the fourth partition wall PW41, the first electrode ETL1, the second electrode ETL21, the third electrode ETL31 and the fourth electrode ETL41, the first insulating layer 131, the light-emitting element LD, the second insulating layer 132, the first contact electrode CNE1 to the fourth contact electrode CNE4, the third insulating layer 141 and the thin film encapsulation layer 151 can be sequentially positioned on the second protective layer 122.

[0255] The first partition wall PW1, the second partition wall PW21, the third partition wall PW31, and the fourth partition wall PW41 may be located on the pixel circuit layer (i.e., the second protective layer 122). The first partition wall PW1, the second partition wall PW21, the third partition wall PW31, and the fourth partition wall PW41 may protrude in the thickness direction (e.g., the third direction DR3) on the pixel circuit layer.

[0256] The first electrode ETL1, the second electrode ETL21, the third electrode ETL31, and the fourth electrode ETL41 can be located on the first partition wall PW1, the second partition wall PW21, the third partition wall PW31, and the fourth partition wall PW41, respectively. The first electrode ETL1, the second electrode ETL21, the third electrode ETL31, and the fourth electrode ETL41 can be spaced apart from each other.

[0257] In some embodiments, at least a portion of the first electrode ETL1 may overlap with the first conductive pattern CE1, at least a portion of the second electrode ETL21 may overlap with the fourth conductive pattern CE4 and the fifth conductive pattern CE5, at least a portion of the third electrode ETL31 may overlap with the second conductive pattern CE2, and at least a portion of the fourth electrode ETL41 may overlap with the third conductive pattern CE3.

[0258] The first electrode ETL1 can be electrically connected to the first conductive pattern CE1 through the first contact hole CNT11, and the second electrode ETL21 can be electrically connected to the fifth conductive pattern CE5 through the second contact hole CNT21. The fifth conductive pattern CE5 can correspond to... Figure 14 The first connection pattern CE1 is shown. The third electrode ETL31 can be insulated from the second conductive pattern CE2, the fourth electrode ETL41 can be insulated from the third conductive pattern CE3, and the second electrode ETL21 can be insulated from the fourth conductive pattern CE4.

[0259] The first contact electrodes CNE1 to the fourth contact electrodes CNE4 can be located on the first electrode ETL1, the second electrode ETL21, the third electrode ETL31, and the fourth electrode ETL41, as well as on one end of the light-emitting element LD and the other end of the adjacent light-emitting element LD. In some embodiments, the first contact electrodes CNE1 to the fourth contact electrodes CNE4 can be as follows: Figure 28 The surfaces shown are located in the same layer. The first contact electrode CNE1 to the fourth contact electrode CNE4 can be formed using the same electrode material in the same process, but this disclosure is not limited thereto.

[0260] The first contact electrode CNE1 may be located on the first electrode ETL1 to contact the first electrode ETL1. In some embodiments, the first contact electrode CNE1 may contact the first electrode ETL1 on a region of the first electrode ETL1 not covered by the first insulating layer 131. Furthermore, the first contact electrode CNE1 may be located on one end of at least one light-emitting element LD (e.g., a plurality of light-emitting elements LD adjacent to the first electrode ETL1) to contact one end of the light-emitting element LD. That is, the first contact electrode CNE1 may cover one end of at least one light-emitting element LD and at least one corresponding region of the first electrode ETL1. Therefore, one end of at least one light-emitting element LD may be electrically connected to the first electrode ETL1.

[0261] Similarly, the third contact electrode CNE3 can be located on the third electrode ETL31 to contact the third electrode ETL31. In some embodiments, the third contact electrode CNE3 can contact the third electrode ETL31 in a region of the third electrode ETL31 not covered by the first insulating layer 131. Furthermore, the third contact electrode CNE3 can be located on the ends of at least two light-emitting elements LDs adjacent to the third electrode ETL31 to contact the ends of at least two light-emitting elements LDs. That is, the third contact electrode CNE3 can cover one or the other end of at least two light-emitting elements LDs and at least one corresponding region of the third electrode ETL31. Therefore, one or the other end of at least two light-emitting elements LDs can be electrically connected to the third electrode ETL31.

[0262] Similarly, the fourth contact electrode CNE4 can be located on the fourth electrode ETL41 to contact the fourth electrode ETL41. In some embodiments, the fourth contact electrode CNE4 can contact the fourth electrode ETL41 in a region of the fourth electrode ETL41 not covered by the first insulating layer 131. Furthermore, the fourth contact electrode CNE4 can be located on the ends of at least two light-emitting elements LDs adjacent to the fourth electrode ETL41 to contact the ends of at least two light-emitting elements LDs. That is, the fourth contact electrode CNE4 can cover one or the other end of at least two light-emitting elements LDs and at least one corresponding region of the fourth electrode ETL41. Therefore, one or the other end of at least two light-emitting elements LDs can be electrically connected to the fourth electrode ETL41.

[0263] Similarly, the second contact electrode CNE2 can be located on the second electrode ETL21 to contact the second electrode ETL21. In some embodiments, the second contact electrode CNE2 can contact the second electrode ETL21 in a region of the second electrode ETL21 not covered by the first insulating layer 131. Furthermore, the second contact electrode CNE2 can be located on the other end of at least one light-emitting element LD adjacent to the second electrode ETL21 to contact the other end of the at least one light-emitting element LD. That is, the second contact electrode CNE2 can cover the other end of at least one light-emitting element LD and at least one corresponding region of the second electrode ETL21. Therefore, the other end of at least one light-emitting element LD can be electrically connected to the second electrode ETL21.

[0264] That is, one end of a light-emitting element LD can contact the first contact electrode CNE1, and the other end of a light-emitting element LD can contact the third contact electrode CNE3. One end of another light-emitting element LD can contact the third contact electrode CNE3, and the other end of another light-emitting element LD can contact the fourth contact electrode CNE4. Yet another light-emitting element LD can have one end contacting the fourth contact electrode CNE4, and the other end of yet another light-emitting element LD can contact the second contact electrode CNE2.

[0265] Since the unit pixels SSPX1 to SSPX3 according to the exemplary embodiment have the same structure as described above, the second partition wall PW22, the third partition wall PW32 and the fourth partition wall PW42 and the second contact hole CNT22 in the second unit pixel SSPX2, and the second partition wall PW23, the third partition wall PW33 and the fourth partition wall PW43 and the second contact hole CNT23 in the third unit pixel SSPX3 can respectively correspond to the second partition wall PW21, the third partition wall PW31 and the fourth partition wall PW41 and the second contact hole CNT21 in the first unit pixel SSPX1.

[0266] Figure 29 This is a cross-sectional view of a display panel according to yet another embodiment of the present disclosure. Figure 29 Corresponding to Figure 14 The modifications.

[0267] Reference Figure 29 The display panel 24 according to this exemplary embodiment and according to Figure 14 The difference between the display panel 21 in the embodiment shown is that the display panel 24 also includes a color conversion filter 160 and a wavelength conversion pattern 180.

[0268] In an implementation, the color conversion filter 160 may be a color filter. A color filter allows light of a specific color to selectively pass through and can block the advance of light of another color by absorbing light. Light passing through a color filter can display one of the three primary colors: red, green, and blue. However, the colors displayed by light passing through a color filter are not limited to the three primary colors, and the light can display any of the colors cyan, magenta, yellow, and white.

[0269] Because the color filter absorbs external light to a considerable extent, it can reduce the reflection of external light even when no additional polarizer or the like is placed in the display panel 24.

[0270] A first sealing layer 171 is located on the color conversion filter 160. The first sealing layer 171 prevents the color conversion filter 160 from being damaged or contaminated by external impurities such as moisture or air. For example, the first sealing layer 171 reduces the chance of the color conversion filter 160 being contaminated by external impurities (such as moisture or air from the atmosphere). Furthermore, the first sealing layer 171 prevents the colorant included in each filter from diffusing into another component (or reduces the chance of the colorant included in each filter diffusing into another component).

[0271] In some embodiments, the first capping layer 171 may be made of an inorganic material. For example, the first capping layer 171 may include silicon nitride, aluminum nitride, zirconium nitride, titanium nitride, hafnium nitride, tantalum nitride, silicon oxide, aluminum oxide, titanium oxide, tin oxide, cerium oxide, silicon oxynitride, etc.

[0272] A wavelength conversion pattern 180 is located on the first capping layer 171. The wavelength conversion pattern 180 can convert incident light with a peak wavelength into light with a specific peak wavelength and emit the converted light. The light passing through the wavelength conversion pattern 180 can display one of the three primary colors: red, green, and blue. However, the color displayed by the light passing through the wavelength conversion pattern 180 is not limited to the three primary colors, and the light can display any of the colors: cyan, magenta, yellow, and white.

[0273] Wavelength conversion pattern 180 can overlap with color conversion filter 160.

[0274] The wavelength conversion pattern 180 may include a base resin 181 and a wavelength conversion material 183 dispersed in the base resin 181. The wavelength conversion pattern 180 may also include a scattering material 185 dispersed in the base resin 181.

[0275] There are no particular limitations on the materials used in the base resin 181, as long as the base resin 181 includes materials that have high transmittance and excellent dispersion characteristics relative to the wavelength conversion material 183 and the scattering material 185. For example, the base resin 181 may include organic materials such as epoxy resins, acrylaldehyde resins, carbon-based resins, or imide-based resins.

[0276] Wavelength conversion material 183 can convert incident light with a peak wavelength into light with a specific peak wavelength. Examples of wavelength conversion material 183 can be quantum dots (QDs), quantum rods, fluorescent materials, etc.

[0277] Quantum dots can be semiconductor nanocrystalline materials. Quantum dots have a specific band gap that depends on their composition and size, and can emit light with an intrinsic band after absorbing light. Examples of semiconductor nanocrystals based on quantum dots can include group IV-based nanocrystals, group II-VI-based compound nanocrystals, group III-V-based compound nanocrystals, group IV-VI-based nanocrystals, or combinations thereof.

[0278] For example, group IV-based nanocrystals may include binary compounds such as silicon (Si), germanium (Ge), silicon carbide (SiC), and silicon-germanium (SiGe). However, this disclosure is not limited thereto.

[0279] Furthermore, II-VI group compound nanocrystals can include binary compounds (such as CdSe, CdTe, ZnS, ZnSe, ZnTe, ZnO, HgS, HgSe, HgTe, MgSe, MgS, and mixtures thereof), ternary compounds (such as CdSeS, CdSeTe, CdSTe, ZnSeS, ZnSeTe, ZnSTe, HgSeS, HgSeTe, HgSTe, CdZnS, CdZnSe), and so on. CdZnTe, CdHgS, CdHgSe, CdHgTe, HgZnS, HgZnSe, HgZnTe, MgZnSe, MgZnS, and mixtures thereof, as well as quaternary compounds (such as HgZnTeS, CdZnSeS, CdZnSeTe, CdZnSTe, CdHgSeS, CdHgSeTe, CdHgSTe, HgZnSeS, HgZnSeTe, HgZnSTe, and mixtures thereof). However, this disclosure is not limited thereto.

[0280] Furthermore, III-V group compound nanocrystals can include binary compounds (such as GaN, GaP, GaAs, GaSb, AlN, AlP, AlAs, AlSb, InN, InP, InAs, InSb, and mixtures thereof), ternary compounds (such as GaNP, GaNAs, GaNSb, GaPAs, GaPSb, AlNP, AlNAs, AlNSb, AlPAs, AlPSb, InNP, InNAs, InNSb, InPAs, InPSb, and mixtures thereof), or quaternary compounds (such as GaAlNAs, GaAlNSb, GaAlPAs, GaAlPSb, GaInNP, GaInNAs, GaInNSb, GaInPAs, GaInPSb, InAlNP, InAlNAs, InAlNSb, InAlPAs, InAlPSb, and mixtures thereof). However, this disclosure is not limited thereto.

[0281] Group IV-VI nanocrystals may include binary compounds (such as SnS, SnSe, SnTe, PbS, PbSe, PbTe, and mixtures thereof), ternary compounds (such as SnSeS, SnSeTe, SnSTe, PbSeS, PbSeTe, PbSTe, SnPbS, SnPbSe, SnPbTe, and mixtures thereof), or quaternary compounds (such as SnPbSSe, SnPbSeTe, SnPbSTe, and mixtures thereof). However, this disclosure is not limited thereto.

[0282] Quantum dots can have a core-shell structure, comprising a core of nanocrystals as described above and a shell surrounding the core. The shell of a quantum dot can serve as a protective layer to prevent or reduce chemical degradation of the core, thus maintaining semiconductor properties, and / or as a charging layer to impart electrophoretic properties to the quantum dot. The shell can be a single-layer or multi-layer structure. As an example, metal or non-metal oxides, semiconductor compounds, combinations thereof, etc., can be used as the shell of a quantum dot.

[0283] For example, the aforementioned metal or non-metal oxides may include binary compounds (such as SiO2, Al2O3, TiO2, ZnO, MnO, Mn2O3, Mn3O4, CuO, FeO, Fe2O3, Fe3O4, CoO, Co3O4, NiO, etc.) or ternary compounds (such as MgAl2O4, CoFe2O4, NiFe2O4, CoMn2O4, etc.). However, this disclosure is not limited thereto.

[0284] Furthermore, the aforementioned semiconductor compounds may include CdS, CdSe, CdTe, ZnS, ZnSe, ZnTe, GaAs, GaP, GaSb, HgS, HgSe, HgTe, InAs, InP, InSb, AlAs, AlP, AlSb, etc. However, this disclosure is not limited thereto.

[0285] The light emitted by the wavelength conversion material 183 can have a full width at half maximum (FWHM) of an emission wavelength spectrum of about 45 nm or less, about 40 nm or less, or about 30 nm or less, thereby further improving color purity and color reproducibility. Furthermore, the light emitted by the wavelength conversion material 183 can be emitted in all directions, regardless of the incident angle of the incident light. Therefore, the side visibility of the display device can be improved.

[0286] A portion of the light emitted from the light-emitting element LD is not converted into red light by the wavelength conversion material 183, but can be emitted through the wavelength conversion pattern 180. The component that is not converted by the wavelength conversion pattern 180 and incident on the color conversion filter 160 can be blocked by the color conversion filter 160. On the other hand, the red light converted by the wavelength conversion pattern 180 can be emitted to the outside through the color conversion filter 160. Therefore, the first emitted light emitted to the outside in the first color region can be red light.

[0287] The scattering material 185 may have a refractive index different from that of the base resin 181 and form an optical interface with the base resin 181. For example, the scattering material 185 may be light-scattering particles. There are no particular limitations on the scattering material 185, as long as it includes materials capable of scattering at least some of the transmitted light. For example, the scattering material 185 may be metal oxide particles or organic particles. Examples of metal oxides may be titanium oxide (TiO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), indium oxide (In2O3), zinc oxide (ZnO), tin oxide (SnO2), etc. Examples of organic materials may be acrolein resins, urethane resins, etc. Regardless of the incident direction of the incident light, the scattering material 185 can scatter light in several directions without substantially converting the wavelength of the light transmitted through the wavelength conversion pattern 180. Therefore, the path length of the light transmitted through the wavelength conversion pattern 180 can be increased, and the color conversion efficiency caused by the wavelength conversion material 183 can be improved.

[0288] The second capping layer 172 may be located above the wavelength conversion pattern 180. Together with the first capping layer 171, the second capping layer 172 may encapsulate the wavelength conversion pattern 180, and thus may prevent (or substantially prevent) the wavelength conversion pattern 180 from being damaged (or may reduce the chance of damage) or contaminated by the infiltration of impurities from the outside, such as moisture or air.

[0289] The second capping layer 172 may be made of an inorganic material. The second capping layer 172 may be made of the same material as the first capping layer 171, or may include at least one of the materials mentioned in the description of the first capping layer 171.

[0290] According to exemplary embodiments of this disclosure, the masking process can be minimized or reduced during the manufacturing process of a display device.

[0291] In addition, the step difference between pads in the display device can be minimized or reduced.

[0292] Exemplary embodiments have been disclosed herein, and while specific terminology has been used, such terminology is used and interpreted in a general and descriptive sense only and is not intended to be limiting. In some instances, it will be apparent to those skilled in the art at the time of filing this application that features, characteristics, and / or elements described in connection with particular embodiments may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments, unless specifically instructed otherwise. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of this disclosure as set forth in the appended claims and their equivalents.

Claims

1. A display device, comprising: The base layer has a display area and a non-display area, wherein the non-display area includes a pad area; The first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, and the fifth insulating layer are stacked sequentially on the base layer; as well as The first pad, located in the pad region on the first insulating layer. The first pad includes: The first pad pattern is on the first insulating layer; The second pad pattern is on the first pad pattern, and the second insulating layer is inserted between the second pad pattern and the first pad pattern; The third pad pattern is on the second pad pattern, and the third insulating layer is inserted between the third pad pattern and the second pad pattern; A fourth pad pattern is formed on the third pad pattern and the fourth insulating layer; and The fifth pad pattern is on the fourth pad pattern. The first to the fifth pad patterns are electrically connected to each other.

2. The display device according to claim 1, further comprising: A first electrode and a second electrode are disposed on the fourth insulating layer in the display area, and the first electrode and the second electrode are spaced apart from each other. Multiple light-emitting elements are located between the first electrode and the second electrode; A first contact electrode is electrically connected to a first end portion of at least one of the plurality of light-emitting elements. as well as The second contact electrode is electrically connected to the second end portion of the at least one light-emitting element.

3. The display device according to claim 2, wherein: The fifth pad pattern is located at the topmost part of the first pad; and The fifth pad pattern is made of the same material as the first contact electrode or the second contact electrode.

4. The display device according to claim 3, wherein, The fifth pad pattern includes ITO, IZO, or ITZO.

5. The display device according to claim 3, wherein, The fifth pad pattern includes a groove in its upper portion, and the width-to-depth ratio of the groove is 20 or greater.

6. The display device according to claim 5, wherein, The width of the groove is 20 μm or greater, and the depth of the groove is 1 μm or less.

7. The display device according to claim 2, wherein, The fourth pad pattern comprises the same material as the first electrode and the second electrode.

8. The display device according to claim 2, further comprising: A buffer layer is located between the base layer and the first insulating layer; Multiple transistors are located on the buffer layer; An interlayer insulating layer is located in the display area between the second insulating layer and the third insulating layer; as well as A conductive layer is located on the third insulating layer in the display area. Each of the transistors includes: The gate electrode is located on the first insulating layer; Semiconductor pattern, on the buffer layer; and The source electrode and drain electrode are located on the interlayer insulating layer.

9. The display device according to claim 8, wherein: The first pad pattern and the gate electrode are made of the same material; The second pad pattern comprises the same material as the source electrode and the drain electrode; and The third pad pattern comprises the same material as the conductive layer.

10. The display device according to claim 2, wherein: The fifth insulating layer is located on and covers the first and second contact electrodes in the display area; and The fifth insulating layer exposes a portion of the fifth pad pattern in the pad area.

11. The display device according to claim 2, further comprising: Color conversion layer and color filter on the plurality of light-emitting elements.

12. The display device according to claim 1, wherein, The second pad pattern and the fifth pad pattern have the same width.

13. The display device according to claim 1, wherein, The first pad pattern, the third pad pattern, and the fourth pad pattern have the same width.

14. The display device according to claim 1, wherein: The second pad pattern is electrically connected to the first pad pattern through the first contact hole in the second insulating layer; as well as The third pad pattern is electrically connected to the second pad pattern through the second contact hole in the third insulating layer.

15. The display device according to claim 1, wherein: The fifth pad pattern is surrounded by the fifth insulating layer; and The step difference between the fifth pad pattern and the fifth insulating layer is 0.6 μm to 2.0 μm.

16. The display device according to claim 15, wherein: The fifth insulating layer includes a region overlapping the edge of the fifth pad pattern; and The region has a width of 2 μm to 3 μm.

17. The display device according to claim 15, wherein, The fifth insulating layer has a thickness of 6000 Å or less.

18. The display device according to claim 1, further comprising a second pad, the second pad being spaced apart from the first pad in the pad region. in, The first pad is a gate pad, and the second pad is a data pad.

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