Display device

Abstract

A display device includes a thin film transistor layer; a first via layer; a second via layer having a via layer opening; a pixel electrode layer; a light emitting element; an organic partition wall; a reflective film covering the organic partition wall and including a protruding portion extending along a side surface of the second via layer exposed by the via layer opening and a top surface of the first via layer and protruding toward the light emitting element; and a first insulating film provided on a bottom surface of the reflective film. The protruding portion overlaps an edge of the pixel electrode layer in a thickness direction, and the pixel electrode layer and the reflective film are spaced apart from each other.

Description

[0001] This application claims priority and benefits to Korean Patent Application No. 10-2025-0003151, filed on January 9, 2025, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] This disclosure relates to display devices, and more specifically, to display devices comprising a reflective film covering an organic partition wall, a method of manufacturing the display device, and an electronic device. Background Technology

[0003] With technological advancements, the demand for various types of image display devices continues to grow. These display devices include flat panel displays such as liquid crystal displays, field emission displays, and light-emitting displays.

[0004] There are two main types of light-emitting displays: organic light-emitting display devices that use organic light-emitting diodes (OLEDs) and ultra-miniature light-emitting display devices that use micron-sized light-emitting diode elements (hereinafter referred to as micron-sized light-emitting elements). Because micron-sized light-emitting diode elements consist of inorganic materials, they have the advantage of longer lifespan due to less degradation compared to organic light-emitting diode elements. Summary of the Invention

[0005] The display device includes: a substrate; a thin-film transistor layer disposed on the substrate; a first via layer disposed on the thin-film transistor layer; a second via layer disposed on the first via layer and having a via layer opening; a pixel electrode layer disposed within the via layer opening and on the first via layer; a light-emitting element disposed on the pixel electrode layer; an organic partition wall disposed on the second via layer; a reflective film covering the organic partition wall and including a protruding portion extending along a side surface of the second via layer exposed by the via layer opening and a top surface of the first via layer and protruding toward the light-emitting element; and a first insulating film disposed on the bottom surface of the reflective film. The protruding portion overlaps with the edge of the pixel electrode layer in the thickness direction. The pixel electrode layer and the reflective film are spaced apart from each other.

[0006] The protruding part can be lower than the bottom of the light-emitting element.

[0007] The display device may further include: a second insulating film disposed on the top surface of the reflective film and surrounding the top and side surfaces of the protrusion.

[0008] The pixel electrode layer may include a pixel electrode and a protective film surrounding the side surface of the pixel electrode.

[0009] The protruding part can overlap with the protective film in the thickness direction.

[0010] The protruding portion can overlap with the edge of the pixel electrode in the thickness direction, and can be spaced apart from the pixel electrode.

[0011] The first insulating film and the pixel electrode, which are disposed on the bottom surface of the protruding part, can be spaced apart from each other.

[0012] The pixel electrode layer may include a pixel electrode and a protective film surrounding the side surface of the pixel electrode.

[0013] The display device may further include: a bonding electrode disposed between the light-emitting element and the pixel electrode, and extending between the bottom surface of the first insulating film and the top surface of the pixel electrode.

[0014] Organic partition walls can include single or multiple organic layers.

[0015] Organic separators can have an angle of inclination formed between an outer surface facing the light-emitting element and an imaginary surface extending parallel to the contact surface of the light-emitting element and the bonding electrode.

[0016] The tilt angle can be in the range of 120 degrees to 135 degrees, including both 120 degrees and 135 degrees.

[0017] The light-emitting element may include a protective film disposed on the side surfaces of the first semiconductor layer, the active layer, and the second semiconductor layer, wherein the light-emitting element does not have a reflective film disposed on the side surfaces of the first semiconductor layer, the active layer, and the second semiconductor layer on the protective film.

[0018] The display device may further include: a common electrode disposed on the top surface of the light-emitting element. The light-emitting element may be disposed on the pixel electrode.

[0019] The pixel electrode layer may further include a common electrode. The pixel electrode and the common electrode may be spaced apart from each other. A protective film may surround the side surfaces of the pixel electrode and the side surfaces of the common electrode. A light-emitting element may be disposed on the pixel electrode and the common electrode.

[0020] The light-emitting element may include a first contact electrode disposed on the pixel electrode and a second contact electrode disposed on the common electrode.

[0021] A method for manufacturing a display device includes: forming a pixel electrode and a protective film covering the pixel electrode on a first via layer of a substrate; covering the protective film on the first via layer with a second via material layer; forming an organic partition wall on the second via material layer; forming a second via layer having a first opening exposing the protective film by ashing a portion of the second via material layer; forming a first insulating layer and a reflective film covering the organic partition wall and exposing the protective film in the first opening; forming an insulating material layer surrounding the reflective film; first etching the insulating material layer in the first opening to form a second insulating layer; and then, after the first etching has been performed, second etching the protective film to expose the pixel electrode, and bonding a light-emitting element to the pixel electrode. The reflective film has a protruding portion extending along the top surface of the first via layer and protruding toward the light-emitting element and overlapping the edge of the pixel electrode layer in the thickness direction.

[0022] The first etching can be dry etching and the second etching can be wet etching, and the etchant for the first etching can be a material that etches the insulating material layer but not the protective film.

[0023] The bonding electrode can be placed between the light-emitting element and the pixel electrode, and the light-emitting element can be bonded to the pixel electrode by thermoforming.

[0024] The electronic device includes: a display panel; a window disposed on the display panel; and a bottom cover disposed below the display panel. The display panel includes: a substrate; a thin-film transistor layer disposed on the substrate; a first via layer disposed on the thin-film transistor layer; a second via layer disposed on the first via layer and having a via opening; a pixel electrode layer disposed within the via opening and on the first via layer; a light-emitting element disposed on the pixel electrode layer; an organic partition wall disposed on the second via layer; a reflective film covering the organic partition wall and including a protruding portion extending along a side surface of the second via layer exposed by the via opening and a top surface of the first via layer and protruding toward the light-emitting element; and a first insulating film disposed on the bottom surface of the reflective film. The protruding portion overlaps with the edge of the pixel electrode layer in the thickness direction, and the pixel electrode layer and the reflective film are spaced apart from each other. Attached Figure Description

[0025] A more complete understanding of this disclosure and its many accompanying aspects will be readily obtained as they become better understood by referring to the following detailed description taken in conjunction with the accompanying drawings.

[0026] Figure 1 This is a perspective view of a display device according to an embodiment.

[0027] Figure 2 This is a layout diagram of a display device according to an embodiment.

[0028] Figure 3 This is a block diagram illustrating a display device according to an embodiment.

[0029] Figure 4 This is an equivalent circuit diagram of a sub-pixel according to an embodiment.

[0030] Figure 5 This is a layout diagram of the pixels of the display area according to an embodiment.

[0031] Figure 6 It is a diagram and Figure 5 A cross-sectional view of an example of the display panel corresponding to line I-I' in the diagram.

[0032] Figure 7 Detailed illustrations Figure 6 A cross-sectional view of an example of region A.

[0033] Figure 8 It is a diagram. Figure 7 A cross-sectional view of the arrangement structure of the protruding area.

[0034] Figure 9 The illustration is based on an embodiment. Figure 7 A cross-sectional view of the arrangement structure of the protruding area.

[0035] Figure 10 It is a diagram. Figure 7 A plan view of the reflective film, pixel electrode, and light-emitting element.

[0036] Figure 11 Detailed illustrations Figure 6 A cross-sectional view of an example of region A.

[0037] Figure 12 This is a layout diagram of the pixels of the display area according to an embodiment.

[0038] Figure 13 It is a diagram and Figure 12 A cross-sectional view of an example of the display panel corresponding to line I2-I2' in the diagram.

[0039] Figure 14 Detailed illustrations Figure 13 A cross-sectional view of an example of zone B.

[0040] Figure 15 Detailed illustrations Figure 13 A cross-sectional view of an example of zone B.

[0041] Figure 16 This is a flowchart illustrating a method for manufacturing a display device according to an embodiment.

[0042] Figures 17 to 26 This is an exemplary diagram illustrating a method for manufacturing a display device according to an embodiment.

[0043] Figure 27 and Figure 28 This is an exemplary diagram illustrating a smartwatch including a display device according to an embodiment.

[0044] Figure 29 This is an exploded perspective view of a smartwatch including a display device according to an embodiment.

[0045] Figure 30 This is an example view of a virtual reality (VR) device including a display device according to one or more embodiments.

[0046] Figure 31 This is an example view of a VR device including a display device according to one or more embodiments.

[0047] Figure 32 This is an example view illustrating a vehicle dashboard and central instrument panel including a display device according to one or more embodiments.

[0048] Figure 33 This is an example view of a transparent display device including a display apparatus according to one or more embodiments. Detailed Implementation

[0049] See below and appendix Figure 1 The aspects and features of this disclosure, as well as the methods for implementing them, will become clear from the detailed description of the embodiments described below. However, this disclosure is not limited to the embodiments disclosed below, but can be implemented in many different forms, and these embodiments are provided to make the disclosure complete and to fully inform those skilled in the art of this disclosure of its scope.

[0050] The term "on" another element or layer includes both cases where the layer or element is directly on top of the other element or where other elements are inserted therebetween. Throughout the specification and drawings, the same reference numerals may refer to the same parts. The shapes, dimensions, ratios, angles, quantities, etc., disclosed in the drawings for the illustrated embodiments are exemplary, and therefore this disclosure is not necessarily limited to the illustrated matters.

[0051] Each feature of the various embodiments of this disclosure can be combined in part or in whole, or in part or in whole with each other, and can be technically interconnected and operable in various ways. Each embodiment can be implemented independently of each other, or can be implemented together in a related relationship. Specific embodiments are described below with reference to the accompanying drawings.

[0052] Embodiments of this disclosure relate to a novel structure and manufacturing method for a micron-sized light-emitting diode (micron-LED) display device. An architecture that increases front-side luminous efficiency is used by integrating a unique reflective and insulating layer configuration around the light-emitting element. The display device includes a substrate with a thin-film transistor layer, followed by a stacked via layer housing pixel electrodes and the light-emitting element. Organic partition walls are constructed around the light-emitting region, and a reflective film is coated with a specific geometry, overlapping yet remaining separate from the edges of the pixel electrodes. This arrangement (particularly the average tilt angle of 120 to 135 degrees for the organic partition walls) allows for better directionality of emitted light towards the front, enhancing brightness and efficiency.

[0053] The pixel electrode is located inside the opening of the via layer and is electrically connected to the transistor below. A reflective film extends along the exposed side surface of the via layer and protrudes towards the light-emitting element on top of and around this component. This reflective structure effectively recovers light that would otherwise be wasted by redirecting it forward. To ensure electrical insulation and mechanical stability, multiple insulating films surround and support the reflective film. The entire structure is optimized to minimize light absorption and leakage, thus increasing the light output and operating efficiency of the display device.

[0054] Protective films and bonding electrodes are used to facilitate a secure attachment of micron-sized LED elements to pixel electrodes. These layers also help maintain structural integrity during the transfer and alignment processes of the light-emitting elements. Protrusions in the reflective film, combined with organic separator walls, play a role in shaping the light path, preventing lateral light scattering, and contributing to a uniform and bright display performance. Furthermore, the display device may optionally include color filters and capping layers to ensure accurate color rendering and encapsulation.

[0055] The manufacturing method also reflects these goals through a combination of dry and wet etching techniques, hot pressing for bonding, and multi-step deposition of organic and inorganic layers. The manufacturing sequence emphasizes precise patterning and stacking to produce the desired structure with high alignment accuracy. This method can be applied to a range of electronic devices, including smartwatches, VR devices, vehicle displays, and other consumer electronics requiring high-performance display panels with excellent light output and durability. The structure not only increases efficiency but also allows for flexible and transparent display forms, providing broad applicability.

[0056] Figure 1 This is a perspective view of a display device according to an embodiment.

[0057] Reference Figure 1The display device 10 is a device for displaying video images or still images, such as those that can be used in portable electronic devices such as mobile phones, smartphones, tablet computers, smartwatches, watch phones, mobile communication terminals, electronic notebooks, e-books, portable multimedia players (PMPs), navigation systems, and ultra-mobile personal computers (UMPCs), as well as displays of various products such as televisions, laptops / notebook computers, computer monitors, digital billboards, and Internet of Things (IoT) devices.

[0058] Display device 10 may be an organic light-emitting display device, such as one utilizing an organic light-emitting diode (OLED), a quantum dot light-emitting display device including a quantum dot light-emitting layer, an inorganic light-emitting display device including inorganic semiconductors, or a miniaturized light-emitting display device utilizing micron-sized or nano-sized light-emitting diodes (micron-sized LEDs or nano-sized LEDs). In the following description, the focus is on the fact that display device 10 is a micron-sized light-emitting display device, but this disclosure is not necessarily limited thereto. On the other hand, for ease of explanation, ultra-small light-emitting diodes will be described hereinafter as light-emitting elements.

[0059] The display device 10 includes a display panel 100, a display driving circuit 250, a circuit board 300, and a power supply circuit 500.

[0060] The display panel 100 may have a rectangular plane having a pair of short sides, each extending primarily along a first direction DR1, and a pair of long sides, each extending primarily along a second direction DR2 intersecting the first direction DR1. The corners where the short sides on the first direction DR1 and the long sides on the second direction DR2 intersect may be rounded to have a predetermined curvature or may be formed at right angles. The planar shape of the display panel 100 is not limited to a rectangle, but may be formed into other polygonal, circular, or elliptical shapes. The display panel 100 may be formed flat, but is not limited to this. In the example, the display panel 100 may include curved portions with constant or varying curvature formed at the left and right ends. Additionally, the display panel 100 may be flexibly formed to be bent, folded, folded, or rolled to at least a perceptible degree without breaking or otherwise damaging it.

[0061] Display panel 100 may include a primary area MA and a secondary area SBA.

[0062] The main area MA may include a display area DA that displays an image and a non-display area NDA that surrounds the display area DA. The display area DA may include multiple pixels that display the image. Each pixel may include multiple sub-pixels. For example, each of the pixels may include a first sub-pixel that emits a first light, a second sub-pixel that emits a second light, and a third sub-pixel that emits a third light, but the embodiments of this disclosure are not limited thereto.

[0063] The secondary SBA can protrude from one side of the primary MA on the second direction DR2. Although Figure 1 The diagram shows an unfolded sub-area SBA, but the sub-area SBA can be bent and, in this case, can be positioned on the lower surface of the display panel 100. When the sub-area SBA is bent, it can overlap with the main area MA on a third direction DR3, which is the thickness direction of the display panel 100. The display driving circuit 250 can be disposed in the sub-area SBA.

[0064] The display driving circuit 250 can generate signals and voltages for driving the display panel 100. The display driving circuit 250 can be formed as an integrated circuit (IC) and attached to the display panel 100 using a chip-on-glass (COG) method, a chip-on-plastic (COP) method, or an ultrasonic bonding method, but is not limited to these methods. In an embodiment, the display driving circuit 250 can be attached to the circuit board 300 using a chip-on-film (COF) method.

[0065] The circuit board 300 can be attached to one end of the sub-region SBA of the display panel 100. In this way, the circuit board 300 can be electrically connected to the display panel 100 and the display driving circuit 250. The display panel 100 and the display driving circuit 250 can receive digital video data, timing signals, and driving voltages through the circuit board 300. The circuit board 300 can be a flexible printed circuit board, a rigid printed circuit board, or a flexible film such as a chip-on-film.

[0066] The power supply circuit 500 can generate multiple panel driving voltages based on the external power supply voltage. The power supply circuit 500 can be formed as an integrated circuit (IC) and attached to the circuit board 300 using the COF method.

[0067] Figure 2 This is a layout diagram of a display device according to an embodiment. Figure 2 The illustration shows that the sub-region SBA is expanded without being bent.

[0068] Reference Figure 2 The display panel 100 may include a primary area MA and a secondary area SBA.

[0069] The main area MA may include the display area DA that displays the image and the non-display area NDA that is the outer perimeter of the display area DA. The display area DA may occupy most of the area of ​​the main area MA. The display area DA may be placed at the center of the main area MA.

[0070] The display area DA includes multiple pixels PX for displaying images, and each of the multiple pixels PX can include multiple subpixels SPX. Pixel PX can be defined as a group of subpixels that is the smallest unit capable of representing white grayscale.

[0071] The non-display area NDA can be located adjacent to the display area DA. The non-display area NDA can be located outside the display area DA. The non-display area NDA can surround the display area DA. The non-display area NDA can be an edge area of ​​the display panel 100.

[0072] The first scan drive section SDC1 and the second scan drive section SDC2 can be located in the non-display area NDA. The first scan drive section SDC1 is located on one side of the display panel 100 (e.g., the left side), and the second scan drive section SDC2 is located on the other side of the display panel 100 (e.g., the right side), but are not necessarily limited thereto. Each of the first scan drive section SDC1 and the second scan drive section SDC2 can be electrically connected to the display drive circuit 250 via a scan fan-out line. Each of the first scan drive section SDC1 and the second scan drive section SDC2 can receive a scan control signal from the display drive circuit 250, generate scan signals according to the scan control signal, and output them to the scan line.

[0073] The secondary SBA can protrude from one side of the primary MA in the second direction DR2. The length of the secondary SBA in the second direction DR2 can be less than the length of the primary MA in the second direction DR2. The length of the secondary SBA in the first direction DR1 can be less than the length of the primary MA in the first direction DR1, or can be substantially equal to the length of the primary MA in the first direction DR1. The secondary SBA can be bent and can be positioned at the lower part of the display panel 100. In this case, the secondary SBA can overlap with the primary MA in the third direction DR3.

[0074] The sub-region SBA can include the connection area CA, the pad area PA, and the bend area BA.

[0075] The connecting area CA is a region that protrudes from one side of the main area MA in the second direction DR2. One side of the connecting area CA can contact the non-display area NDA of the main area MA, and the other side of the connecting area CA can contact the bending area BA.

[0076] The pad area PA is the area where the pads PD and the display driving circuit 250 are mounted. The display driving circuit 250 can be attached to the driving pads of the pad area PA using a conductive adhesive such as an anisotropic conductive film. The circuit board 300 can be attached to the pads PD of the pad area PA using a conductive adhesive such as an anisotropic conductive film. One side of the pad area PA can contact the bending area BA.

[0077] The bending region BA is the region that is bent. When the bending region BA is bent, the pad region PA can be positioned below the connector region CA and below the main region MA. The bending region BA can be positioned between the connector region CA and the pad region PA. One side of the bending region BA can contact the connector region CA, and the other side of the bending region BA can contact the pad region PA.

[0078] Figure 3 This is a block diagram illustrating a display device according to an embodiment.

[0079] Reference Figure 3 The display area DA includes multiple sub-pixels SPX, multiple scan lines SL, multiple emission control lines EL, and multiple data lines DL.

[0080] Multiple sub-pixels (SPX) can be arranged in a matrix on the first direction DR1 and the second direction DR2. Multiple scan lines (SL) and multiple emission control lines (EL) can extend on the first direction DR1 and be set on the second direction DR2. Multiple data lines (DL) can extend on the second direction DR2 and be set on the first direction DR1. The multiple scan lines (SL) can include multiple write scan lines (GWL), multiple control scan lines, multiple initialization scan lines (GIL), and multiple bias scan lines (GBL).

[0081] Each of the multiple sub-pixels (SPX) can be connected to one of the write scan lines (GWL), one of the control scan lines (GWL), one of the initialization scan lines (GIL), one of the bias scan lines (GBL), one of the emission control lines (EL), and one of the data lines (DL). Each of the multiple sub-pixels (SPX) can be supplied with a data voltage on the data line (DL) according to the write scan signal of the write scan line (GWL), and can emit light according to the data voltage.

[0082] The non-display area NDA includes a first scan drive section SDC1, a second scan drive section SDC2, and a display drive circuit 250.

[0083] Each of the first scan driving section SDC1 and the second scan driving section SDC2 may include a write scan signal output section 611, an initialization scan signal output section 612, a bias scan signal output section 613, and a transmit control signal output section 614. Each of the write scan signal output section 611, the initialization scan signal output section 612, the bias scan signal output section 613, and the transmit control signal output section 614 may receive a scan timing control signal SCS from the timing control circuit 251 (or the timing controller).

[0084] The write scan signal output section 611 can generate write scan signals according to the scan timing control signal SCS of the timing control circuit 251, and output them sequentially to the write scan line GWL.

[0085] The initial scan signal output section 612 can generate initial scan signals according to the scan timing control signal SCS, and output them sequentially to the initial scan line GIL.

[0086] The bias scan signal output section 613 can generate bias scan signals according to the scan timing control signal SCS, and output them sequentially to the bias scan line GBL. The transmit control signal output section 614 can generate transmit control signals according to the scan timing control signal SCS, and output them sequentially to the transmit control line EL.

[0087] The display driving circuit 250 includes a timing control circuit 251 and a data driving circuit 252 (or data driver).

[0088] The data driving circuit 252 can receive digital video data DATA and data timing control signal DCS from the timing control circuit 251. The data driving circuit 252 converts the digital video data DATA into analog data voltages according to the data timing control signal DCS and outputs them to the data line DL. In this case, the sub-pixel SPX is selected by the write scan signals of the first scan driving section SDC1 and the second scan driving section SDC2, and the data voltage can be supplied to the selected sub-pixel SPX.

[0089] The timing control circuit 251 can receive digital video data DATA and timing signals from an external source. Based on the timing signals, the timing control circuit 251 can generate a scan timing control signal SCS and a data timing control signal DCS for controlling the display panel 100. The timing control circuit 251 can output the scan timing control signal SCS to the first scan drive section SDC1 and the second scan drive section SDC2. The timing control circuit 251 can also output the digital video data DATA and the data timing control signal DCS to the data drive circuit 252.

[0090] The power supply circuit 500 (or power supply unit) can generate multiple panel driving voltages based on the power voltage supplied from an external source. For example, the power supply circuit 500 can generate a first power supply voltage VDD, a second power supply voltage VSS, a third power supply voltage VINT, and a fourth power supply voltage VAINT, and supply them to the display panel 100.

[0091] Figure 4 This is an equivalent circuit diagram of a sub-pixel according to an embodiment.

[0092] Reference Figure 4 According to the embodiment, the sub-pixel SPX can be connected to scan lines GWL, GIL, and GBL, emission control line EL, and data line DL. For example, the sub-pixel SPX can be connected to the write scan line GWL, the initialization scan line GIL, the bias scan line GBL, the emission control line EL, and the data line DL.

[0093] According to an embodiment, the sub-pixel SPX includes a driving transistor DT, a switching element, a capacitor C1, and a light-emitting element LE. The switching element includes first transistors to sixth transistors ST1, ST2, ST3, ST4, ST5, and ST6.

[0094] The driving transistor DT includes a gate electrode, a first electrode, and a second electrode. The driving transistor DT controls the drain-source current Ids (hereinafter referred to as the "driving current") flowing between the first and second electrodes according to the data voltage applied to the gate electrode.

[0095] The light-emitting element (LE) can be a micron-sized light-emitting diode.

[0096] The light-emitting element LE emits light according to the driving current Ids. The amount of light emitted from the light-emitting element LE is proportional to the driving current Ids. The anode electrode of the light-emitting element LE is connected to the first electrode of the fourth transistor ST4 and the second electrode of the sixth transistor ST6, and the cathode electrode can be connected to the point where a second power supply voltage is applied (…). Figure 3 The second power line VSL in VSS).

[0097] Capacitor C1 is formed at the gate electrode of the driving transistor DT and a first power supply voltage is applied to it. Figure 3 The capacitor C1 is connected between the first power supply line VDL and the second power supply line VDD. The first power supply voltage can be a voltage level higher than the second power supply voltage. One electrode of the capacitor C1 can be connected to the gate electrode of the driving transistor DT, and the other electrode can be connected to the first power supply line VDL.

[0098] like Figure 4 As shown, the first to sixth transistors ST1, ST2, ST3, ST4, ST5, and ST6, as well as the driving transistor DT, can all be formed as p-type MOSFETs. In this case, the active layer of each of the first to sixth transistors ST1, ST2, ST3, ST4, ST5, and ST6, as well as the driving transistor DT, can be formed of polysilicon.

[0099] The gate electrode of the first transistor ST1 and the gate electrode of the second transistor ST2 can be connected to the write scan line GWL, the gate electrode of the third transistor ST3 can be connected to the initialization scan line GIL, and the gate electrode of the fourth transistor ST4 can be connected to the bias scan line GBL. Since the first to sixth transistors ST1, ST2, ST3, ST4, ST5, and ST6 are formed as p-type MOSFETs, they can be turned on when the gate low voltage scan signal and the emitter control signal are applied to the initialization scan line GIL, the write scan line GWL, the bias scan line GBL, and the emitter control line EL, respectively. One electrode of the third transistor ST3 can be connected to a third power supply voltage applied to it (…). Figure 3 The first initialization voltage line VIL of the VINT), and one electrode of the fourth transistor ST4 can be connected to the fourth power supply voltage applied to it. Figure 3 The second initialization voltage line VAIL (VAINT) of the third power supply voltage. Figure 3 VINT) and the fourth power supply voltage ( Figure 3 The voltage (VAINT) can be different. Furthermore, a third supply voltage (VAINT) can also be used. Figure 3 VINT in the middle) and the fourth power supply voltage ( Figure 3 The VAINT in the middle can be at a voltage higher than the first power supply voltage. Figure 3 The voltage level of VDD is lower than that of the second power supply voltage. Figure 3 The voltage level of VSS in the system is the high level of the voltage.

[0100] Alternatively, the driving transistor DT, the second transistor ST2, the fourth transistor ST4, the fifth transistor ST5, and the sixth transistor ST6 can be formed of p-type MOSFETs, and the first transistor ST1 and the third transistor ST3 can be formed of n-type MOSFETs. In this case, the active layer of each of the driving transistors DT, ST2, ST4, ST5, and ST6 formed of p-type MOSFETs is formed of polysilicon, and the active layer of each of the first transistor ST1 and ST3 formed of n-type MOSFETs can be formed of oxide semiconductor. Furthermore, since the first transistor ST1 and the third transistor ST3 are formed of n-type MOSFETs, the first transistor ST1 can be turned on when a write scan signal with a gate high voltage is applied, and the third transistor ST3 can be turned on when an initialization scan signal with a gate high voltage is applied. Conversely, since the second transistor ST2, ST4, ST5, and ST6 are formed of p-type MOSFETs, they can be turned on when a scan signal with a gate low voltage and a transmit control signal are applied.

[0101] Alternatively, the fourth transistor ST4 can be formed as an n-type MOSFET, and the remaining transistors DT, ST1, ST2, ST3, ST5, and ST6 can be formed as p-type MOSFETs. In this case, the active layer of the fourth transistor ST4 can be formed as oxide semiconductor, and the active layer of each of the remaining transistors DT, ST1, ST2, ST3, ST5, and ST6 can be formed as polysilicon. Furthermore, the fourth transistor ST4 can be turned on when a scan signal with a gate high voltage is applied, while transistors ST1, ST2, ST3, ST5, and ST6 can be turned on when a scan signal with a gate low voltage and an emitter control signal are applied.

[0102] Alternatively, the first to sixth transistors ST1, ST2, ST3, ST4, ST5, and ST6, as well as the driving transistor DT, can all be formed as n-type MOSFETs. In this case, the active layer of each of the first to sixth transistors ST1, ST2, ST3, ST4, ST5, and ST6, as well as the driving transistor DT, is formed of oxide semiconductor, and the first to sixth transistors ST1, ST2, ST3, ST4, ST5, and ST6 can be turned on when a scan signal and a transmit control signal with gate high voltage are applied.

[0103] Figure 5 This is a layout diagram of the pixels of the display area according to an embodiment.

[0104] Reference Figure 5 Each of the plurality of pixels PX in the display area DA may include three sub-pixels SPX1, SPX2, and SPX3; however, embodiments of this disclosure are not limited thereto and may include four sub-pixels. When each of the plurality of pixels PX includes three sub-pixels, it may include a first sub-pixel SPX1, a second sub-pixel SPX2, and a third sub-pixel SPX3.

[0105] Multiple pixels PX can be arranged in a matrix. In each of the multiple pixels PX, a first sub-pixel SPX1, a second sub-pixel SPX2, and a third sub-pixel SPX3 can be arranged on a first direction DR1.

[0106] When each of the multiple pixels PX comprises three sub-pixels SPX1, SPX2, and SPX3, the first sub-pixel SPX1 can emit light of a first color, the second sub-pixel SPX2 can emit light of a second color, and the third sub-pixel SPX3 can emit light of a third color. The first color of light can be light in the red band, the second color of light can be light in the green band, and the third color of light can be light in the blue band. For example, the blue band can refer to light with a dominant peak wavelength in the band from approximately 370 nm to approximately 460 nm, the green band can refer to light with a dominant peak wavelength in the band from approximately 480 nm to approximately 560 nm, and the red band can refer to light with a dominant peak wavelength in the band from approximately 600 nm to approximately 750 nm.

[0107] Alternatively, when each of the multiple pixels PX comprises four sub-pixels, the first sub-pixel can emit light of a first color, the second and fourth sub-pixels can emit light of a second color, and the third sub-pixel can emit light of a third color. Alternatively, the first sub-pixel can emit light of the first color, the second sub-pixel can emit light of the second color, the third sub-pixel can emit light of the third color, and the fourth sub-pixel can emit light of a fourth color. In this case, the fourth color can be white light.

[0108] The first sub-pixel SPX1 includes a first pixel electrode PXE1 and multiple light-emitting elements LE. The second sub-pixel SPX2 includes a second pixel electrode PXE2 and multiple light-emitting elements LE. The third sub-pixel SPX3 includes a third pixel electrode PXE3 and multiple light-emitting elements LE.

[0109] The first sub-pixel SPX1's light-emitting element LE1 (see...) Figure 6 The first color of light can be emitted, and the second sub-pixel SPX2 has a light-emitting element LE2 (see...). Figure 6 It can emit light of a second color, and the third sub-pixel SPX3's light-emitting element LE3 (see...) Figure 6 It can emit light of a third color.

[0110] Each of the first pixel electrode PXE1, the second pixel electrode PXE2, and the third pixel electrode PXE3 can have a rectangular planar shape, having a pair of short sides extending primarily in the first direction DR1 and a pair of long sides extending primarily in the second direction DR2. The area of ​​the first sub-pixel SPX1, the area of ​​the second sub-pixel SPX2, and the area of ​​the third sub-pixel SPX3 can be set according to the luminous efficiency of the light-emitting element LE included in each sub-pixel SPX. For example, since the light conversion efficiency is low, the area of ​​the sub-pixel can be large.

[0111] For example, such as Figure 5 As shown, when the luminous efficiency of the light-emitting element LE2 of the second sub-pixel SPX2 is lower than that of the light-emitting element LE1 of the first sub-pixel SPX1 and the light-emitting element LE3 of the third sub-pixel SPX3, the area of ​​the second pixel electrode PXE2 can be larger than the area of ​​the first pixel electrode PXE1 and larger than the area of ​​the third pixel electrode PXE3.

[0112] Each of pixel electrodes PXE1, PXE2, and PXE3 can be electrically connected to at least one transistor via pixel connection holes CT1, CT2, and CT3. For example, each of pixel electrodes PXE1, PXE2, and PXE3 can be electrically connected to the fourth transistor of the corresponding sub-pixel. Figure 4 The first electrode and the sixth transistor (ST4) in the middle Figure 4 The second electrode of ST6 in the middle.

[0113] Multiple light-emitting elements (LEs) can be disposed on each of pixel electrodes PXE1, PXE2, and PXE3. The same number of light-emitting elements (LEs) can be disposed on each of pixel electrodes PXE1, PXE2, and PXE3. For example, two light-emitting elements (LEs) can be disposed on each of pixel electrodes PXE1, PXE2, and PXE3. Multiple light-emitting elements (LEs) can emit light of a third color (i.e., light in the blue band), but embodiments of this disclosure are not limited thereto.

[0114] Each of the plurality of light-emitting elements LE may have a circular planar shape, but embodiments of the present disclosure are not limited thereto. For example, each of the plurality of light-emitting elements LE may have a rectangular planar shape.

[0115] Figure 6 It is a diagram and Figure 5 A cross-sectional view of an example of the display panel corresponding to line I-I' in the diagram. Figure 7 Detailed illustrations Figure 6 A cross-sectional view of an example of region A. Figure 8 It is a diagram. Figure 7 A cross-sectional view of the arrangement structure of the protruding area. Figure 9 The illustration is based on an embodiment. Figure 7 A cross-sectional view of the arrangement structure of the protruding area. Figure 10 It is a diagram. Figure 7 A plan view of the reflective film, pixel electrode, and light-emitting element.

[0116] Reference Figure 6 and Figure 7The substrate SUB can be made of an insulating material such as glass or polymer resin. If the substrate SUB is made of polymer resin, it can be a flexible substrate that can be stretched. The polymer resin can be acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin, etc.

[0117] A barrier film (BR) can be disposed on a substrate (SUB). The barrier film (BR) is a film that protects the thin-film transistor (TFTL) layer from moisture that penetrates the moisture-permeable substrate (SUB). The barrier film (BR) can be formed from multiple inorganic films stacked alternately.

[0118] A thin-film transistor layer (TFTL) can be disposed on a barrier film (BR), and may include a thin-film transistor (TFT1). The thin-film transistor (TFT1) can be disposed on the barrier film (BR). The thin-film transistor (TFT1) can be... Figure 4 The fourth transistor ST4 or the sixth transistor ST6 is shown in the figure. The thin-film transistor TFT1 may include a first active layer ACT1 and a first gate electrode G1.

[0119] The first active layer ACT1 of the thin-film transistor TFT1 can be disposed on the barrier film BR. The first active layer ACT1 of the thin-film transistor TFT1 may include polycrystalline silicon (e.g., low-temperature polycrystalline silicon), monocrystalline silicon, or amorphous silicon. Alternatively, the first active layer ACT1 of the thin-film transistor TFT1 may include an oxide semiconductor comprising IGZO (indium (In), gallium (Ga), zinc (Zn), and oxygen (O)), IGZTO (indium (In), gallium (Ga), zinc (Zn), tin (Sn), and oxygen (O)) or IGTO (indium (In), gallium (Ga), tin (Sn), and oxygen (O)).

[0120] The first active layer ACT1 may include a first channel region CHA1, a first source region S1, and a first drain region D1. The first channel region CHA1 may be a region on the third direction DR3, which is the thickness direction of the substrate SUB, that overlaps with the first gate electrode G1. The first source region S1 may be disposed on one side of the first channel region CHA1, and the first drain region D1 may be disposed on the other side of the first channel region CHA1. The first source region S1 and the first drain region D1 may be regions on the third direction DR3 that do not overlap with the first gate electrode G1. The first source region S1 and the first drain region D1 may be conductive regions in which the semiconductor material is doped with ions.

[0121] The first gate insulating film 131 can be disposed on the first channel region CHA1, the first source region S1, and the first drain region D1 of the thin film transistor TFT1.

[0122] A first gate metal layer may be disposed on a first gate insulating film 131. The first gate metal layer may include a first gate electrode G1 and a first capacitor electrode CAE1 of a thin-film transistor TFT1. The first gate electrode G1 may overlap with the first active layer ACT1 on a third-direction DR3. Although the first gate electrode G1 and the first capacitor electrode CAE1 are... Figure 6 The diagram shows them spaced apart, but the first gate electrode G1 and the first capacitor electrode CAE1 can be connected to each other.

[0123] The second gate insulating film 132 can be disposed on the first gate electrode G1 and the first capacitor electrode CAE1 of the thin film transistor TFT1.

[0124] A second gate metal layer can be disposed on the second gate insulating film 132. The second gate metal layer may include a second capacitor electrode CAE2. The second capacitor electrode CAE2 may overlap with the first capacitor electrode CAE1 on the third-direction DR3. Since the second gate insulating film 132 has a predetermined dielectric constant, the capacitor ( Figure 4 C1 in the figure can be formed by a first capacitor electrode CAE1, a second capacitor electrode CAE2 and a second gate insulating film 132 disposed between them.

[0125] The interlayer insulating film 141 can be disposed on the second capacitor electrode CAE2.

[0126] A first data metal layer may be disposed on an interlayer insulating film 141. The first data metal layer may include a first source connection electrode PCE1. The first source connection electrode PCE1 may be connected to a first drain region D1 of the first active layer ACT1 through a first source contact hole PCT1 that penetrates the first gate insulating film 131, the second gate insulating film 132 and the interlayer insulating film 141.

[0127] The first planarization organic film 160 can be disposed on the first source connection electrode PCE1 to planarize the steps caused by the thin film transistor TFT1.

[0128] A second data metal layer may be disposed on the first planarized organic film 160. The second data metal layer may include a second source connection electrode PCE2. The second source connection electrode PCE2 may be connected to the first source connection electrode PCE1 through a second pixel contact hole PCT2 penetrating the first planarized organic film 160.

[0129] The first via layer 181 can be disposed on the second source connection electrode PCE2.

[0130] The second via layer 182 and the pixel electrode PXE can be disposed on the first via layer 181. The first via layer 181 and the second via layer 182 can be collectively referred to as via layer 180. The pixel electrode PXE may include a first pixel electrode PXE1, a second pixel electrode PXE2, and a third pixel electrode PXE3.

[0131] The barrier film BR, the first gate insulating film 131, the second gate insulating film 132, and the interlayer insulating film 141 can be made of, for example, silicon nitride (SiN). x ), silicon oxynitride (SiO) x N y ), silicon dioxide (SiO) x Titanium oxide (TiO) x ) or aluminum oxide (AlO x Inorganic membrane formation.

[0132] The first gate metal layer, the second gate metal layer, the first data metal layer, and the second data metal layer can be formed as a single layer or multiple layers of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or their alloys.

[0133] The first planarized organic film 160, the first via layer 181, and the second via layer 182 can be formed from an organic insulating film such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0134] Since the first via layer 181 also serves to planarize the steps caused by the second source connection electrode PCE2, it can also be called a planarization layer.

[0135] The pixel electrode layer can be disposed on the first via layer 181.

[0136] The pixel electrode layer may include a first pixel electrode PXE1, a second pixel electrode PXE2, and a third pixel electrode PXE3. Each of the pixel electrodes PXE1, PXE2, and PXE3 can be connected through a connection hole penetrating the first via layer 181. Figure 5 The pixel electrodes PXE1, PXE2, and PXE3 are connected to the second source connection electrode PCE2. Each of the pixel electrodes PXE1, PXE2, and PXE3 can be connected to the first source region S1 or the first drain region D1 of the thin-film transistor TFT1 via the first source connection electrode PCE1 and the second source connection electrode PCE2. Therefore, a voltage controlled by the thin-film transistor TFT1 can be applied to each of the pixel electrodes PXE1, PXE2, and PXE3.

[0137] Pixel electrodes PXE1, PXE2, and PXE3 can be formed from a single layer or multiple layers, which are made of one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or an alloy thereof. For example, the pixel electrode layer can be made of copper (Cu) with low surface resistance to reduce the resistance of each of the pixel electrodes PXE1, PXE2, and PXE3. Furthermore, when the pixel electrodes PXE1, PXE2, and PXE3 are formed as a multilayer structure, the pixel electrodes PXE1, PXE2, and PXE3 can include a first layer at the bottom made of one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or an alloy thereof, and a second layer on the first layer made of a highly reflective metallic material such as aluminum (Al).

[0138] The pixel electrode layer may include a protective film TPF (or protective layer) surrounding each side of the pixel electrodes PXE1, PXE2, and PXE3. The protective film TPF can be referred to as a sacrificial layer protecting the pixel electrodes PXE1, PXE2, and PXE3 during the process of forming the organic separator wall (BWL). After forming the protective film TPF to cover both the top and side surfaces of the pixel electrodes PXE1, PXE2, and PXE3, the protective film TPF disposed on the top surface of the pixel electrodes PXE1, PXE2, and PXE3 is removed, leaving only the protective film TPF on the side surfaces of the pixel electrodes PXE1, PXE2, and PXE3. Accordingly, the protective film TPF surrounds the side surfaces of the pixel electrodes PXE1, PXE2, and PXE3 and exposes the upper portion of the pixel electrodes PXE1, PXE2, and PXE3. The upper portion of the pixel electrodes PXE1, PXE2, and PXE3 is the surface on which the light-emitting element (LE) is subsequently disposed. In some embodiments (e.g., Figure 9 In the embodiment shown, the protective film TPF can cover the edges of the upper surfaces of the pixel electrodes PXE1, PXE2, and PXE3. Even in this case, the first protruding portion INS1-P, as described below, can protrude from the upper surface of the protective film TPF in the second direction DR2. The protective film TPF can be formed of metal oxides such as ITO (indium tin oxide), IGZO (indium gallium zinc oxide), and IZO (indium zinc oxide), but is not necessarily limited to these.

[0139] Reference Figures 7 to 10 The second via layer 182 can be further disposed on the first via layer 181.

[0140] The second via layer 182 may have a flat top surface. The second via layer 182 may cover the entire surface of the first via layer 181 except for the area where the pixel electrode layer is disposed. In the area where the pixel electrode layer is disposed, the second via layer 182 has a via layer opening OP1 that exposes the pixel electrode PXE and the protective film TPF. The area exposed by the via layer opening OP1 may be wider than the area of ​​the light-emitting element LE.

[0141] The via opening OP1 can expose not only the pixel electrode PXE and the protective film TPF, but also a first via layer 181 surrounding the pixel electrode PXE and the protective film TPF on the third-direction DR3. The first via layer 181 may have a recessed groove 181-h in the exposed area around the pixel electrode PXE and the protective film TPF. The exposed area of ​​the first via layer 181 around the pixel electrode PXE and the protective film TPF has a thinner thickness than other areas of the first via layer 181. In another modified example, the recessed groove 181-h of the first via layer 181 may be omitted.

[0142] The second via layer 182 may be composed of the same material as the first via layer 181. The second via layer 182 may include organic insulating materials such as polyacrylate resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, or benzocyclobutene (BCB).

[0143] Organic separator wall (BWL) can be set on the second via layer 182.

[0144] The organic separator wall BWL has a structure in which its width narrows towards the top. The organic separator wall BWL can be formed on the second via layer 182 at a first height h1. The top surface of the organic separator wall BWL can be disposed below the top surface of the light-emitting element LE. The first height h1 can be from about 5µm to about 8µm, but is not limited to this. When the upper end of the organic separator wall BWL is formed below the light-emitting element LE, it has the advantage of allowing the light-emitting element LE to be easily transferred during the transfer process of the light-emitting element LE.

[0145] The organic spacer wall (BWL) can have a closed-loop shape that surrounds and is spaced apart from the light-emitting element (LE) on a plane. The bottom surface of the organic spacer wall (BWL) can be the surface that contacts the second via layer 182, and the top surface of the organic spacer wall (BWL) can be the surface facing the bottom surface. The angle θ-B between the outer surface of the organic spacer wall (BWL) facing the light-emitting element (LE) and the reference plane can be approximately 120 degrees to approximately 135 degrees. In an embodiment, it can be approximately 125 degrees. Here, the reference plane can be an extension of the surface including the contact surface of the light-emitting element (LE) and the bonding electrode BOE (e.g., the lowermost end of the light-emitting element (LE)). As the angle between the outer surface and the reference surface increases, the organic spacer wall (BWL) can be formed more gently.

[0146] Organic separator walls (BWLs) can be formed from organic materials such as acrylic resins, epoxy resins, phenolic resins, polyamide resins, or polyimide resins.

[0147] A first insulating film INS1 (or a first insulating layer) is disposed on the outer side of the organic separator wall BWL. The first insulating film INS1 may cover both the side surface and the top surface of the organic separator wall BWL. The first insulating film INS1 may extend from the side surface of the organic separator wall BWL along the side surface of the second via layer 182 exposed by the via layer opening OP1. In addition, the first insulating film INS1 may extend from the side surface of the second via layer 182 to cover the upper part of the first via layer 181 exposed by the via layer opening OP1 and may cover the protective film TPF. The first insulating film INS1 may have a first protrusion portion INS1-P protruding from the upper part of the protective film TPF in a first direction DR1. The first protrusion portion INS1-P may overlap with a portion of the pixel electrode layer in a third direction DR3. For example, the first protrusion portion INS1-P may overlap with the protective film TPF in the third direction DR3 and may overlap with a portion (e.g., an edge) of the pixel electrodes PXE1, PXE2, and PXE3 in the third direction DR3, but is not limited thereto.

[0148] The first protruding portion INS1-P protrudes from the top of the protective film TPF in the first direction DR1, having a bottom surface INS1-PB facing the first via layer 181 and a top surface INS1-PT facing the bottom surface INS1-PB. The first protruding portion INS1-P overlaps with the pixel electrodes PXE1, PXE2, and PXE3 in the third direction DR3, but the first protruding portion INS1-P and the pixel electrodes PXE1, PXE2, and PXE3 are spaced apart from each other in the third direction DR3. A bonding electrode BOE is disposed between the bottom surface INS1-PB of the first protruding portion INS1-P and the top surface of the pixel electrodes PXE1, PXE2, and PXE3, and the bottom surface INS1-PB and the pixel electrodes PXE1, PXE2, and PXE3 are spaced apart from each other by the bonding electrode BOE.

[0149] The reflective film RF is disposed on the outside of the first insulating film INS1. The reflective film RF is disposed on the first insulating film INS1.

[0150] The reflective film RF includes a second protrusion RF-P, which extends along the side surface of the second via layer 182 exposed by the via layer opening OP1 and along the top surface of the first via layer 181.

[0151] The reflective film RF can be set on the entire surface of the pixel area, except for the area where the light-emitting element LE is set.

[0152] Because the reflective film RF has a constant thickness on the top and side surfaces of the organic separator wall BWL, it can have the same tilt angle as the organic separator wall BWL. Therefore, the angle formed between the outer surface of the reflective film RF and the reference surface has a tilt angle of approximately 120 degrees to approximately 135 degrees. In an embodiment, the angle formed between the outer surface of the reflective film RF and the reference plane can be approximately 125 degrees.

[0153] Additionally, the reflective film RF can extend from the side surface of the second via layer 182 on the top surface of the first insulating film INS1 to cover the upper portion of the first via layer 181 exposed by the via layer opening OP1, and can cover the protective film TPF. The reflective film RF can have a second protrusion RF-P protruding from the upper portion of the protective film TPF in a first direction DR1. The second protrusion RF-P can overlap with a portion of the pixel electrode layer in a third direction DR3. For example, the second protrusion RF-P can overlap with the protective film TPF in the third direction DR3, and can also overlap with a portion (e.g., an edge) of the pixel electrodes PXE1, PXE2, and PXE3 in the third direction DR3. The side surfaces of the second protrusion RF-P and the side surfaces of the first protrusion INS1-P can be aligned with each other. The bottom surface of the reflective film RF is the surface that contacts the first insulating film INS1, and the top surface of the reflective film RF is the surface facing the bottom surface.

[0154] The reflective film RF can include a metallic material with high reflectivity. The reflective film RF can be aluminum (Al), but is not limited to this.

[0155] Because the reflective film RF reflects light from the light-emitting element LE propagating in directions other than towards the top surface, and because the tops of the pixel electrodes PXE1, PXE2, and PXE3 also include reflective films, the pixel region essentially has a reflective film covering almost the entire surface in the plane. Since the reflective film is disposed across the entire surface of the pixel region, light can be emitted to the top surface of the light-emitting element LE. Therefore, the luminous efficiency of the light-emitting element LE can be increased by reducing light loss from the LE.

[0156] A second insulating film INS2 (or a second insulating layer) is disposed on the top surface of the reflective film RF. The second insulating film INS2 covers the entire reflective film RF. Therefore, the reflective film RF is surrounded by the first insulating film INS1 and the second insulating film INS2.

[0157] The second insulating film INS2 is disposed on the top surface of the reflective film RF, covering both the side and top surfaces of the organic separator wall BWL, and extends from the side surface of the organic separator wall BWL along the side surface of the second via layer 182 exposed by the via layer opening OP1.

[0158] The second insulating film INS2 can be disposed on the entire surface of the pixel area, excluding the area where the light-emitting element LE is disposed.

[0159] The second insulating film INS2 may extend from the side surface of the second via layer 182 on the top surface of the reflective film RF to cover the upper portion of the first via layer 181 exposed by the via layer opening OP1, and may cover the protective film TPF. The second insulating film INS2 may have a third protruding portion INS2-P that protrudes from the upper portion of the protective film TPF in a first direction DR1. The third protruding portion INS2-P may overlap with a portion of the pixel electrode layer in a third direction DR3. For example, the third protruding portion INS2-P may overlap with the protective film TPF in the third direction DR3, and may also overlap with a portion (e.g., an edge) of the pixel electrodes PXE1, PXE2, and PXE3 in the third direction DR3. The third protruding portion INS2-P may protrude further than the first protruding portion INS1-P and the second protruding portion RF-P in the first direction DR1, and may completely surround the second protruding portion RF-P. Therefore, the reflective film RF may be completely surrounded by the first insulating layer INS1 and the second insulating layer INS2. The bottom surface of the second insulating layer INS2 is the surface that contacts the reflective film RF, and the top surface of the second insulating layer INS2 is the surface that faces the bottom surface.

[0160] The area where the first protruding portion INS1-P of the first insulating film INS1, the second protruding portion RF-P of the reflective film RF, and the third protruding portion INS2-P of the second insulating film INS2 overlap in the thickness direction can be referred to as the protruding area.

[0161] The first insulating film INS1 and the second insulating film INS2 can be made of, for example, silicon nitride (SiN). x ), silicon oxynitride (SiO) x N y ), silicon dioxide (SiO) x Titanium oxide (TiO) x ) or aluminum oxide (AlO x Inorganic membrane formation.

[0162] Multiple light-emitting elements (LEs) can be disposed on pixel electrodes PXE1, PXE2, and PXE3. Figure 6 and Figure 7 In the illustration, each of the multiple light-emitting elements (LEs) is a vertical micron-sized LED extending on a third-direction DR3. A vertical micron-sized LED refers to an LED having a structure in which a first semiconductor layer (SEM1), an active layer (MQW), and a second semiconductor layer (SEM2) are sequentially arranged on a third-direction DR3, which is vertical.

[0163] Each of the plurality of light-emitting elements (LEs) can be formed of an inorganic material such as gallium nitride (GaN). Each of the plurality of light-emitting elements (LEs) can have a length of several μm to several hundred μm in a first direction DR1, a length in a second direction DR2, and a length in a third direction DR3. For example, each of the plurality of light-emitting elements (LEs) can have a length of approximately 6 μm to approximately less than 10 μm in the first direction DR1, a length in the second direction DR2, and a length in the third direction DR3.

[0164] Each of the multiple light-emitting elements (LEs) can be formed by growing on a semiconductor substrate such as a silicon substrate or a sapphire substrate. The multiple light-emitting elements (LEs) can be directly transferred from the semiconductor substrate to the pixel electrodes PXE1, PXE2, and PXE3 of the display panel 100. Alternatively, the multiple light-emitting elements (LEs) can be transferred to the pixel electrodes PXE1, PXE2, and PXE3 of the display panel 100 by an electrostatic method using an electrostatic head or by an imprinting method using an elastic polymer material such as polydimethylsiloxane (PDMS) or silicon as the transfer substrate.

[0165] The conductive layer E1, the first semiconductor layer SEM1, the active layer MQW, and the second semiconductor layer SEM2 can be referred to as a component rod.

[0166] The component rod may include a first component rod LD1 and a second component rod LD2.

[0167] The first element rod LD1 may include a first sidewall SS1 having a first cone angle θ1. The first cone angle θ1 of the first sidewall SS1 may be greater than 70 degrees and less than 90 degrees.

[0168] The first element bar LD1 may include a conductive layer E1, a first semiconductor layer SEM1, and an active layer MQW.

[0169] In this embodiment, the conductive layer E1 may be disposed on the bottom surface of the first semiconductor layer SEM1. Figure 7 In the illustration, the conductive layer E1 covers the entire bottom surface of the first semiconductor layer SEM1, but the embodiments of this disclosure are not limited to this. For example, the conductive layer E1 may be disposed on a portion of the bottom surface of the first semiconductor layer SEM1. The conductive layer E1 may include one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu).

[0170] The first semiconductor layer SEM1 can be disposed on the conductive layer E1. The first semiconductor layer SEM1 can be formed from a semiconductor material layer such as gallium nitride (GaN) and doped with a first conductivity type dopant such as magnesium (Mg), zinc (Zn), calcium (Ca), strontium (Sr), barium (Ba).

[0171] The active layer MQW can be disposed on the first semiconductor layer SEM1. The active layer MQW can emit light by causing electron-hole pairs to recombine according to an electrical signal applied through the first semiconductor layer SEM1 and the second semiconductor layer SEM2.

[0172] The active layer MQW can include materials having a single quantum well structure or a multiple quantum well structure. When the active layer MQW includes a material having a multiple quantum well structure, it can have a structure in which multiple well layers and multiple barrier layers are alternately stacked. In this case, the well layers can be formed of indium gallium nitride (InGaN), and the barrier layers can be formed of gallium nitride (GaN) or aluminum gallium nitride (AlGaN), but the embodiments disclosed herein are not limited to these.

[0173] Alternatively, the active layer MQW may have a structure in which semiconductor materials with high bandgap energy and semiconductor materials with low bandgap energy are stacked alternately, and may include other group III to group V semiconductor materials depending on the wavelength range of the emitted light.

[0174] In embodiments, when the active layer MQW comprises InGaN, the color of the emitted light can vary depending on the indium (In) content. For example, as the indium (In) content increases, the wavelength of the light emitted by the active layer MQW can shift to the red band, and as the indium (In) content decreases, the wavelength of the light emitted by the active layer MQW can shift to the blue band. For example, the indium (In) content in the active layer MQW of the light-emitting element LE emitting a third light (light in the blue band) can be approximately 10 wt% to approximately 20 wt%.

[0175] The second element rod LD2 is disposed on the first element rod LD1, and may include a second semiconductor layer SEM2.

[0176] The ratio of the height h11 of the first element bar LD1 to the height h21 of the second element bar LD2 can be 1:2. For example, the height h21 of the second element bar LD2 can be approximately twice the height h11 of the first element bar LD1.

[0177] The second element rod LD2 may include a second sidewall SS2 having a second cone angle θ2. The second cone angle θ2 of the second sidewall SS2 may be greater than 60 degrees and less than 80 degrees. Furthermore, the second cone angle θ2 may be smaller than the first cone angle θ1. Therefore, the second sidewall SS2 may be formed into a regular cone shape. The second element rod LD2 becomes wider as it moves further away from the first element rod LD1.

[0178] The second element rod LD2 may include a second semiconductor layer SEM2.

[0179] The second semiconductor layer SEM2 can be disposed on the active layer MQW. The second semiconductor layer SEM2 can be, for example, gallium nitride (GaN) or a semiconductor material layer doped with a second conductivity type dopant such as silicon (Si), germanium (Ge), tin (Sn).

[0180] An electron blocking layer can be disposed between the first semiconductor layer SEM1 and the active layer MQW. The electron blocking layer can be a layer used to suppress or prevent excessive electron flow into the active layer MQW. For example, the electron blocking layer can be aluminum gallium nitride (AlGaN) or p-type aluminum gallium nitride (AlGaN) doped with p-type magnesium (Mg). The electron blocking layer can be omitted.

[0181] A superlattice layer can be disposed between the active layer MQW and the second semiconductor layer SEM2. The superlattice layer can be used to alleviate stress between the second semiconductor layer SEM2 and the active layer MQW. For example, the superlattice layer can be aluminum gallium nitride (AlGaN) or p-type aluminum gallium nitride (AlGaN) doped with p-type magnesium (Mg). The superlattice layer can be omitted.

[0182] The shape of the light-emitting element LE can vary depending on the embodiment. The light-emitting element LE can have a substantially inverted tapered cross-sectional shape. For example, the light-emitting element LE can have an inverted tapered cross-sectional shape in which the width of the top surface is wider than the width of the bottom surface. The light-emitting element LE may include vertical side surfaces. For example, the light-emitting element LE can be patterned by vertical etching and can have a rectangular or square cross-sectional shape in which the width of the top surface and the width of the bottom surface are substantially the same.

[0183] The light-emitting element (LE) may further include a contact electrode (CTE) and an element protective layer (INS) (or element protective film).

[0184] The component protective layer INS can be a film used to protect the bottom and side surfaces of the light-emitting element LE. The component protective layer INS can be disposed on the bottom and side surfaces of component rods LD1 and LD2. For example, the component protective layer INS can be disposed on the bottom and side surfaces of the conductive layer E1, the side surface of the first semiconductor layer SEM1, the side surface of the active layer MQW, and the bottom and side surfaces of the second semiconductor layer SEM2. The component protective layer INS can be made of materials such as silicon nitride (SiN). x ), silicon oxynitride (SiO) x N y ), silicon dioxide (SiO) x Titanium oxide (TiO) x ) or aluminum oxide (AlO xThe inorganic film is formed. The light-emitting element LE may not have a reflective film disposed on any one of the side surfaces of the first semiconductor layer SEM1, the active layer MQW, and the second semiconductor layer SEM2 on the element protective layer INS.

[0185] The contact electrode CTE can be disposed on the bonding electrode BOE. The contact electrode CTE can be disposed between the conductive layer E1 and the bonding electrode BOE. The contact electrode CTE can be in contact with the conductive layer E1.

[0186] The contact electrode CTE can be connected to the conductive layer E1 that is exposed by the component protection layer INS but not covered by the component protection layer INS.

[0187] Contact electrode CTEs can include one of the following: molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). For example, multiple contact electrode CTEs can be formed as a two-layer structure of chromium (Cr) and gold (Au), a three-layer structure of titanium (Ti), aluminum (Al), and titanium (Ti), or a three-layer structure of indium tin oxide (ITO), silver (Ag), and indium tin oxide (ITO) to increase reflectivity.

[0188] The bonding electrode BOE can be disposed between the pixel electrodes PXE1, PXE2, and PXE3 and the contact electrode CTE of the corresponding light-emitting element LE. The bonding electrode BOE can act as a bonding metal for bonding the pixel electrodes PXE1, PXE2, and PXE3 to the corresponding light-emitting element LE. For example, the bonding electrode BOE can include at least one of gold (Au), copper (Cu), tin (Sn), silver (Ag), aluminum (Al), and titanium (Ti). For example, the bonding electrode BOE can include a 9:1 alloy, an 8:2 alloy, or a 7:3 alloy of gold and tin.

[0189] The third organic layer 211 can cover the side surface of multiple light-emitting elements LE and the second insulating layer INS2.

[0190] The third organic layer 211 is a layer used to planarize the steps caused by the lower structure comprising multiple light-emitting elements (LEs) and organic separator walls (BWLs). The height of the third organic layer 211 can cover most of the side surface of each of the multiple light-emitting elements (LEs), but in embodiments, it can cover the side surface of each of the multiple light-emitting elements (LEs) by multiple organic films.

[0191] The third organic layer 211 can be formed from organic materials such as acrylic resin, epoxy resin, phenolic resin, polyamide resin or polyimide resin.

[0192] The common electrode CE can be placed on the top surface of each of the multiple light-emitting elements LE.

[0193] The common electrode CE can be a common layer formed in the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3. The common electrode CE can be made of a transparent conductive material (TCM) such as indium tin oxide (ITO) and indium zinc oxide (IZO) that is capable of transmitting light.

[0194] Pixel electrodes PXE1, PXE2, and PXE3 can be referred to as anode electrodes or first electrodes, and the common electrode CE can be referred to as cathode electrodes or second electrodes.

[0195] The first capping layer CAP1 can be disposed on the common electrode CE. The first capping layer CAP1 can be used to encapsulate the components below.

[0196] The first capping layer CAP1 can be made of materials such as silicon nitride (SiN). x ), silicon oxynitride (SiO) x N y ), silicon dioxide (SiO) x Titanium oxide (TiO) x ) or aluminum oxide (AlO x Inorganic membrane formation.

[0197] A fourth organic layer 213 may be disposed on the first capping layer CAP1. Multiple color filters CF1, CF2, and CF3 may be disposed on the fourth organic layer 213. The multiple color filters CF1, CF2, and CF3 may include a first color filter CF1, a second color filter CF2, and a third color filter CF3.

[0198] The first color filter CF1, located in the first sub-pixel SPX1, can transmit light of the first color (light in the red band). Therefore, the first sub-pixel SPX1 can emit light of the first color (light in the red band).

[0199] The second color filter CF2, located in the second sub-pixel SPX2, can transmit light of the second color (light in the green band). Therefore, the second sub-pixel SPX2 can emit light of the second color (light in the green band).

[0200] The third color filter CF3, located in the third sub-pixel SPX3, can transmit light of the third color (light in the blue band). Therefore, the third sub-pixel SPX3 can emit light of the third color (light in the blue band).

[0201] The first color filter CF1, the second color filter CF2, and the third color filter CF3, which overlap on the third-direction DR3, can overlap with the organic separator wall BWL on the third-direction DR3.

[0202] The fifth organic layer 214 for planarization can be disposed on multiple color filters CF1, CF2 and CF3.

[0203] The fourth organic layer 213 and the fifth organic layer 214 can be formed from acrylic resin, epoxy resin, phenolic resin, polyamide resin or polyimide resin, etc.

[0204] Figure 11 Detailed illustrations Figure 6 A cross-sectional view of an example of region A.

[0205] Figure 11 Implementation examples and Figure 7 The difference in the embodiment is that the organic separator wall BWL includes a first organic layer 191 and a second organic layer 192. Figure 11 In relation to elements not described in detail in the figure, it is understood that such elements are at least similar to those already described elsewhere in this disclosure (such as those concerning...). Figure 7 The corresponding components described are similar.

[0206] Reference Figure 11 The organic separator wall (BWL) may include a first organic layer 191 and a second organic layer 192 disposed on the first organic layer 191.

[0207] The first organic layer 191 and the second organic layer 192 have different inclinations.

[0208] The first angle θ-B1 of the outer surface SL-B1 of the first organic layer 191 can be greater than the second angle θ-B2 of the outer surface SL-B2 of the second organic layer 192. For example, the first angle θ-B1 of the first organic layer 191 can be greater than 120 degrees, and the second angle θ-B2 of the second organic layer 192 can be less than 120 degrees. The average value of the angle of the outer surface SL-B1 of the first organic layer 191 (i.e., the first angle θ-B1) and the angle of the outer surface SL-B2 of the second organic layer 192 (i.e., the second angle θ-B2) can be from approximately 120 degrees to approximately 135 degrees.

[0209] The contact surfaces of the first organic layer 191 and the second organic layer 192 can be positioned higher than the contact surfaces of the active layer MQW and the second semiconductor layer SEM2 of the light-emitting element LE. Therefore, the top surface of the active layer MQW can be lower than the top surface of the first organic layer 191. The top surface of the first organic layer 191 is the surface that contacts the second organic layer 192, and the bottom surface of the first organic layer 191 is the surface facing the top surface. The top surface of the active layer MQW is the surface that contacts the second semiconductor layer SEM2, and the bottom surface of the active layer MQW is the surface facing the top surface.

[0210] Since a three-layer structure consisting of a first insulating film INS1, a reflective film RF, and a second insulating film INS2 is disposed on the outer surfaces of the first organic layer 191 and the second organic layer 192, for ease of explanation, the reflective film RF disposed on the outer surface of the first organic layer 191 is referred to as the first reflective film, and the reflective film RF disposed on the outer surface of the second organic layer 192 is referred to as the second reflective film. Furthermore, the angle of the outer surface SL-R1 of the first reflective film is the same as the angle of the outer surface of the first organic layer 191, and the angle of the outer surface SL-R2 of the second reflective film is the same as the angle of the outer surface of the second organic layer 192.

[0211] Therefore, the average angle of the outer surface SL-R1 of the first reflective film and the outer surface SL-R2 of the second reflective film is 120 degrees or more, preferably 120 to 135 degrees. Furthermore, the angle of the outer surface SL-R1 of the first reflective film is greater than the angle of the outer surface SL-R2 of the second reflective film. For example, the angle of the outer surface SL-R1 of the first reflective film can be 120 degrees or more, and the angle of the outer surface SL-R2 of the second reflective film can be less than 120 degrees.

[0212] Furthermore, the inflection point SP where the angle between the outer surfaces SL-R1 of the first reflective film and SL-R2 of the second reflective film abruptly changes can be located above the top surface of the active layer MQW of the light-emitting element LE. Therefore, the top surface of the active layer MQW can be located below the top surface of the first reflective film.

[0213] In an embodiment, when the top surface of the organic separator wall BWL is formed to be higher than the top surface of the light-emitting element LE, the reflective film RF disposed on the outside of the organic separator wall BWL is set to be higher than the top surface of the light-emitting element LE. This is advantageous because it can increase the luminous efficiency of the light-emitting element LE.

[0214] exist Figures 6 to 11 In the embodiments described, the organic separator wall BWL is formed as a single layer or two layers, but is not limited to this. For example, the organic separator wall BWL can be formed as three organic layers. Even when formed as three organic layers, the organic separator wall BWL can have a shape in which the width becomes narrower as it goes upward.

[0215] In the display device according to various embodiments, there is no reflective film directly disposed on the outside of the light-emitting element LE, and the bottom of the reflective film RF on the organic partition wall BWL is disposed below the bottom of the light-emitting element LE, so that the organic partition wall BWL can effectively reflect the side light of the light-emitting element LE. The reflective film directly disposed on the outside of the light-emitting element LE may refer to the reflective film that contacts the element protective layer INS of the light-emitting element LE.

[0216] although Figure 6The display device in the embodiments does not include a wavelength conversion layer, but in various modifications, a wavelength conversion layer may be included between the color filters CF1, CF2, and CF3 and the first capping layer CAP1. The wavelength conversion layer can convert incident light into light of a specific wavelength. For example, a first wavelength conversion layer that converts incident light into light of a first wavelength band may be disposed on a first light-emitting element that emits light of the first wavelength band, and a second wavelength conversion layer that converts incident light into light of a second wavelength band may be disposed on a second light-emitting element that emits light of the second wavelength band.

[0217] Figure 12 This is a layout diagram of the pixels of the display area according to an embodiment.

[0218] Figure 12 Implementation examples and Figure 5 The difference in the embodiment is that the light-emitting element LE is disposed on the pixel electrodes PXE1, PXE2, and PXE3 and the common electrode CE in each of the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3. Figure 12 In relation to elements not described in detail in the figure, it is understood that such elements are at least similar to those already described elsewhere in this disclosure (such as those concerning...). Figure 5 The corresponding components described are similar.

[0219] Reference Figure 12 The pixel electrodes PXE1, PXE2, and PXE3 and the common electrode CE in each of the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 can be arranged on the second direction DR2. Each of the pixel electrodes PXE1, PXE2, and PXE3 and the common electrode CE can have a rectangular planar shape, but the embodiments of this disclosure are not limited thereto.

[0220] In each of the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3, a light-emitting element LE is disposed on the pixel electrodes PXE1, PXE2, and PXE3 and the common electrode CE, such that the length of the light-emitting element LE in the second direction DR2 can be longer than the length of the light-emitting element LE in the first direction DR1.

[0221] Figure 13 It is a diagram and Figure 12 A cross-sectional view of an example of the display panel corresponding to line I2-I2' in the diagram. Figure 14 Detailed illustrations Figure 13 A cross-sectional view of an example of zone B.

[0222] Figure 13 and Figure 14 Implementation examples and Figure 6 and Figure 7The difference in this embodiment is that the light-emitting element LE is a flip-chip micron LED, and the common electrode CE is included in the pixel electrode layer. Figure 13 and Figure 14 In relation to elements not described in detail in the figure, it is understood that such elements are at least similar to those already described elsewhere in this disclosure (such as those concerning...). Figure 6 and Figure 7 The corresponding components described are similar.

[0223] Reference Figure 13 and Figure 14 The pixel electrode layer can be disposed on the first via layer 181. The pixel electrode layer may include pixel electrodes PXE1, PXE2, and PXE3 and a common electrode CE, and may further include a protective film TPF surrounding the side surfaces of the pixel electrodes PXE1, PXE2, and PXE3 and the side surface of the common electrode CE. The protective film TPF may also be disposed between the common electrode CE and the pixel electrodes PXE1, PXE2, and PXE3 corresponding to the common electrode.

[0224] A light-emitting element (LE) can be disposed on the first via layer 181. The light-emitting element LE can be a flip-chip micron LED. A flip-chip micron LED refers to an LED in which contact electrodes CTE1 and CTE2 are formed on one surface (e.g., the bottom surface) of the light-emitting element LE. The first contact electrode CTE1 can be disposed on pixel electrodes PXE1, PXE2, and PXE3, and the second contact electrode CTE2 can be disposed on the common electrode CE.

[0225] The bonding electrode BOE can be disposed between the first via layer 181 and the light-emitting element LE. The bonding electrode BOE can also be disposed between the pixel electrodes PXE1, PXE2, and PXE3 and the first contact electrode CTE1 of the corresponding light-emitting element LE, and between the common electrode CE and the second contact electrode CTE2 of the corresponding light-emitting element LE. The bonding electrode BOE can act as a bonding metal for bonding the pixel electrodes PXE1, PXE2, and PXE3 and the corresponding light-emitting element LE.

[0226] Reference Figure 14 The light-emitting element LE may include a conductive layer E1, a first semiconductor layer SEM1, an active layer MQW, a second semiconductor layer SEM2, a protective layer INS, a first contact electrode CTE1, and a second contact electrode CTE2. Furthermore, the light-emitting element LE may have a hole LEH that penetrates the conductive layer E1, the first semiconductor layer SEM1, and the active layer MQW to expose the second semiconductor layer SEM2. The hole LEH may have a circular planar shape, but embodiments of this disclosure are not limited to this. For example, the hole LEH may have an elliptical or polygonal planar shape such as a square.

[0227] Additionally, the component protection layer INS can be disposed on the sidewalls of the conductive layer E1 exposed by the via LEH, the sidewalls of the first semiconductor layer SEM1, the sidewalls of the active layer MQW, and the sidewalls of the second semiconductor layer SEM2. The component protection layer INS may not cover the second semiconductor layer SEM2 within the via LEH.

[0228] The first contact electrode CTE1 can be disposed on one surface of the conductive layer E1. Therefore, the first contact electrode CTE1 can be electrically connected to the conductive layer E1.

[0229] The second contact electrode CTE2 can be disposed on a surface of the conductive layer E1 at a certain distance from the first contact electrode CTE1. The second contact electrode CTE2 can be disposed on the element protection film INS disposed in the via LEH and on the second semiconductor layer SEM2 exposed in the via LEH but not covered by the element protection film INS. Therefore, the second contact electrode CTE2 can be electrically connected to the second semiconductor layer SEM2 in the via LEH.

[0230] The second via layer 182 can be further disposed on the first via layer 181.

[0231] The second via layer 182 may have a flat top surface. The second via layer 182 may cover the entire surface of the first via layer 181 except for the area where the pixel electrode layer is disposed. In the area where the pixel electrode layer is disposed, the second via layer 182 has a via layer opening OP1 that exposes the pixel electrode PXE, the common electrode CE, and the protective layer TPF. The area exposed by the via layer opening OP1 may be wider than the area of ​​the light-emitting element LE.

[0232] The via opening OP1 can expose not only the pixel electrode PXE, the common electrode CE, and the protective layer TPF on the third-direction DR3, but also a first via layer 181 surrounding the pixel electrode PXE and the protective layer TPF. The first via layer 181 may have a recessed groove 181-h that is recessed downwards in the area where the pixel electrode PXE, the common electrode CE, and the protective layer TPF are exposed. The first via layer 181 has a thinner thickness in the exposed area surrounding the pixel electrode PXE, the common electrode CE, and the protective layer TPF than in other areas of the first via layer 181. In other variations, the recessed groove 181-h of the first via layer 181 may be omitted.

[0233] Organic separator wall (BWL) can be set on the second via layer 182.

[0234] The organic separator wall (BWL) has a structure in which its width becomes narrower as it moves upward. A first insulating film (INS1), a reflective film (RF), and a second insulating film (INS2) can be disposed on the outside of the organic separator wall (BWL).

[0235] The first insulating film INS1, the reflective film RF, and the second insulating film INS2 may have protruding portions INS1-P, RF-P, and INS2-P that protrude from the upper part of the protective film TPF in a first direction DR1. The protruding portions INS1-P, RF-P, and INS2-P may overlap with a portion of the pixel electrode layer in a third direction DR3.

[0236] The third organic layer 211 can cover multiple light-emitting elements LE.

[0237] Figure 15 Detailed illustrations Figure 14 A cross-sectional view of an example of zone B.

[0238] Figure 15 Implementation examples and Figure 14 The difference in the embodiment is that the organic separator wall BWL includes a first organic layer 191 and a second organic layer 192. Figure 15 In relation to elements not described in detail in the figure, it is understood that such elements are at least similar to those already described elsewhere in this disclosure (such as those concerning...). Figure 14 The corresponding components described are similar.

[0239] Reference Figure 15 The organic separator wall (BWL) may include a first organic layer 191 and a second organic layer 192 disposed on the first organic layer 191.

[0240] The first organic layer 191 and the second organic layer 192 have different inclinations.

[0241] The first angle θ11 of the outer surface of the first organic layer 191 can be greater than the second angle θ12 of the outer surface of the second organic layer 192. For example, the first angle θ11 of the first organic layer 191 can be greater than 120 degrees, and the second angle θ12 of the second organic layer 192 can be less than 120 degrees. The average value of the first angle θ11 of the outer surface of the first organic layer 191 and the second angle θ12 of the outer surface of the second organic layer 192 can be from approximately 120 degrees to approximately 135 degrees.

[0242] The contact surfaces of the first organic layer 191 and the second organic layer 192 can be positioned higher than the contact surfaces of the active layer MQW and the second semiconductor layer SEM2 of the light-emitting element LE. Therefore, the top surface of the active layer MQW can be lower than the top surface of the first organic layer 191. The top surface of the first organic layer 191 is the surface that contacts the second organic layer 192, and the bottom surface of the first organic layer 191 is the surface facing the top surface. The top surface of the active layer MQW is the surface that contacts the second semiconductor layer SEM2, and the bottom surface of the active layer MQW is the surface facing the top surface.

[0243] Since a three-layer structure consisting of a first insulating film INS1, a reflective film RF, and a second insulating film INS2 is disposed on the outer surfaces of the first organic layer 191 and the second organic layer 192, for ease of explanation, the reflective film RF disposed on the outer surface of the first organic layer 191 is referred to as the first reflective film, and the reflective film RF disposed on the outer surface of the second organic layer 192 is referred to as the second reflective film. Furthermore, the angle of the outer surface of the first reflective film is the same as the angle of the outer surface of the first organic layer 191 (i.e., the first angle θ11), and the angle of the outer surface of the second reflective film is the same as the angle of the outer surface of the second organic layer 192 (i.e., the second angle θ12).

[0244] Therefore, the average angle of the outer surface of the first reflective film and the outer surface of the second reflective film is 120 degrees or more, preferably 120 to 135 degrees. Furthermore, the angle of the outer surface of the first reflective film is greater than the angle of the outer surface of the second reflective film. For example, the angle of the outer surface of the first reflective film may be 120 degrees or more, and the angle of the outer surface of the second reflective film may be less than 120 degrees.

[0245] Furthermore, the inflection point where the angle between the outer surfaces of the first and second reflective films suddenly changes can be located above the top surface of the active layer MQW of the light-emitting element LE. Therefore, the top surface of the active layer MQW can be positioned below the top surface of the first reflective film.

[0246] In an embodiment, when the top surface of the organic separator wall BWL is formed to be higher than the top surface of the light-emitting element LE, the reflective film RF disposed on the outside of the organic separator wall BWL is set to be higher than the top surface of the light-emitting element LE. This is advantageous because it can increase the luminous efficiency of the light-emitting element LE.

[0247] Figure 16 This is a flowchart illustrating a method for manufacturing a display device according to an embodiment. Figures 17 to 26 This is an exemplary diagram illustrating a method for manufacturing a display device according to an embodiment.

[0248] In the following text, it will be explained by Figure 16 and Figures 17 to 26 A method for manufacturing a display device according to an embodiment will be described in detail below. (Refer to...) Figures 17 to 26 The described method for manufacturing a display device may include reference to Figures 5 to 7 The display device described is a display panel. Figures 17 to 26 Is with Figure 7 A cross-sectional view of the corresponding display panel. Some accompanying drawings also include a plan view corresponding to the cross-sectional view for clarity.

[0249] First, a pixel electrode layer is formed on the circuit board. Figure 16 Step S110 in the process.

[0250] like Figure 17 As shown, the circuit board includes a first via layer 181, and a pixel electrode PXE is formed on the first via layer 181. For example, a conductive material layer is completely deposited on the first via layer 181, a mask pattern is formed on the conductive material layer, and the conductive material layer not covered by the mask pattern is etched. Subsequently, the mask pattern is removed by an ashing process to form the pixel electrode PXE.

[0251] Next, a protective layer TPF is formed over the pixel electrode PXE. The protective layer TPF covers both the top and side surfaces of the pixel electrode PXE to protect the pixel electrode PXE during subsequent processes.

[0252] In an embodiment, such as Figure 12 and Figure 13 As shown, the pixel electrode PXE and the common electrode CE can be formed as a pixel electrode layer on the first via layer 181. When the pixel electrode PXE and the common electrode CE are formed, the protective layer TPF is formed to cover both the top surface and the side surface of each of the pixel electrode PXE and the common electrode CE.

[0253] Second, a second via layer 182 with via openings OP1 and an organic separator wall BWL are formed. Figure 16 Step S120 in the process.

[0254] Reference Figure 18 Organic material is coated to a specific thickness on the first via layer 181 to form a second via material layer 182L.

[0255] Then, an organic separator wall (BWL) is formed on the second via material layer 182L. The organic separator wall (BWL) can be formed by patterning organic materials, but is not limited to this.

[0256] Reference Figure 19 After forming a protective film with photoresist on the organic separator wall BWL, the second via material layer 182L is ashed until the protective film TPF is exposed to form the via layer opening OP1. While the second via material layer 182L is ashed until the protective film TPF is exposed, the second via layer 182 can form a via in the via layer opening OP1, and a recessed groove 181-h can be formed in the portion of the first via layer 181 where the pixel electrode layer is not located. By adjusting the degree of ashing, the recessed groove 181-h may not be formed in a portion of the first via layer 181.

[0257] exist Figure 18 and Figure 19 In this process, the organic separatory wall (BWL) forms a monolayer, but it is not limited to this and can be as follows: Figure 11The diagram shows a multi-layered organic structure. When forming a multi-layered organic structure, a lower organic layer can be formed, and an upper organic layer can be formed on top of the lower organic layer. When forming a multi-layered organic structure, the average tilt angle of the multi-layered organic structure can be between 120 degrees and 135 degrees.

[0258] Third, a first insulating film INS1, a reflective film RF, and a second insulating film INS2 are formed. Figure 16 Step S130 in the process.

[0259] Reference Figure 20 An insulating material layer INS1L is formed on the entire surface of the first via layer 181 of the circuit board. Next, a reflective material layer RFL is deposited on the entire surface of the first via layer 181.

[0260] Reference Figure 21 The reflective material layer RFL is patterned to expose the protective film TPF, and the reflective material layer RFL and the insulating material layer INS1L are etched, thereby forming the first insulating film INS1 and the reflective film RF. The first insulating film INS1 and the reflective film RF can form a protruding area covering the edge of the pixel electrode PXE. When the reflective material layer RFL is patterned, the protective film TPF can protect the pixel electrode PXE from the etchant used.

[0261] Reference Figure 22 An insulating material layer INS2L is formed on the entire surface of the first via layer 181 of the circuit board. As a result, the reflective film RF can be encapsulated by the insulating material layer INS2L.

[0262] Reference Figure 23 The insulating material layer INS2L is dry-etched to form a second insulating film INS2, exposing the protective film TPF. At this point, a dry etchant that etches the insulating material layer INS2L but not the protective film TPF can be used. The protective film TPF protects the pixel electrode PXE during dry etching.

[0263] Next, the protective film TPF is etched to expose the top surface of the pixel electrode PXE. The etching of the protective film TPF can be performed using a wet etching process. At this time, since the first insulating layer INS1, the reflective film RF, and the second insulating layer INS2 have shapes protruding towards the light-emitting element LE, the protective film TPF disposed beneath the protruding portions of the first insulating layer INS1, the reflective film RF, and the second insulating layer INS2 can be incompletely removed and can be retained as a residual pattern between the pixel electrode PXE and the second via layer 182. Furthermore, at least a portion of the protective film TPF disposed beneath the protruding portions of the first insulating layer INS1, the reflective film RF, and the second insulating layer INS2 can be removed, thereby creating a gap between the first insulating layer INS1 and the pixel electrode PXE.

[0264] Fourth, integrate the light-emitting element (LE) onto the pixel electrode layer. Figure 16 Step S140 in the process.

[0265] Light-emitting elements (LEs) can be grown on a semiconductor substrate. The semiconductor substrate can be a silicon wafer substrate or a sapphire substrate.

[0266] Multiple semiconductor layers can be formed on a semiconductor substrate using epitaxial growth processes. As epitaxial growth processes, electron beam deposition, physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma laser deposition (PLD), dual-mode thermal evaporation, sputtering, and metal-organic chemical vapor deposition (MOCVD) can be used. Preferably, metal-organic chemical vapor deposition (MOCVD) can be used, but the embodiments of this disclosure are not limited to this. The multiple semiconductor layers may include a first semiconductor layer, an active layer, and a second semiconductor layer.

[0267] After the semiconductor layer is formed, a conductive layer and contact electrodes can be formed on the semiconductor layer.

[0268] Reference Figure 24 The light-emitting element (LE) can be directly transferred from the semiconductor substrate to the pixel electrode (PXE). Alternatively, the LE can be transferred to the PXE by an electrostatic method using an electrostatic head or by an imprinting method using an elastic polymer material such as PDMS or silicon as the transfer substrate.

[0269] The bonding electrode BOE can be placed between the contact electrode CTE of the light-emitting element LE and the pixel electrode PXE. Heat is then applied to the bonding electrode BOE to bond the light-emitting element LE to the pixel electrode PXE. The bonding electrode BOE becomes fluid by receiving heat, allowing its material to fill the gap created between the first insulating layer INS1 and the pixel electrode PXE during the wet process.

[0270] Fifth, a common electrode CE is formed on the upper part of the light-emitting element LE. Figure 16 Step S150 in the process.

[0271] Reference Figure 25 A third organic layer 211 is formed to fix the light-emitting element LE and flatten the step caused by the light-emitting element LE. The third organic layer 211 can expose the upper part of the light-emitting element LE.

[0272] Reference Figure 26 A common electrode CE is formed on the light-emitting element LE and the third organic layer 211. The common electrode CE can be in direct contact with the light-emitting element LE.

[0273] Then, as Figure 7As shown, at least one of the color filters CF1, CF2 and CF3 and the capping layer CAP1 can be additionally formed.

[0274] Figure 27 and Figure 28 This is an exemplary diagram illustrating a smartwatch including a display device according to an embodiment.

[0275] Reference Figure 27 and Figure 28 The display device 10_1 according to the embodiment can be applied to a smartwatch 1000_1, which is a type of smart device.

[0276] The flat shape of the display device 10_1 can be square or circular, but it is not limited to this and can be modified in various ways such as elliptical.

[0277] Figure 29 This is an exploded perspective view of a smartwatch including a display device according to an embodiment.

[0278] Reference Figure 29 The smartwatch 1000_1 may include a main unit BP and a wearable part BD.

[0279] The main unit BP may include a display panel 100 on which images are displayed, a cover window CW disposed on the display panel 100, a bottom cover BC disposed below the display panel 100, an intermediate frame MF disposed between the cover window CW and the bottom cover BC, and a battery BR disposed between the intermediate frame MF and the bottom cover BC. In addition to the battery BR, the main processor controlling the smartwatch 1000_1, a communication chipset for wireless communication with external devices, and a circuit board containing memory and other components may be additionally disposed between the intermediate frame MF and the bottom cover BC.

[0280] The main unit BP can sequentially include the bottom cover BC, battery BR, middle frame MF, display panel 100, and cover window CW.

[0281] A cover window (CW) is disposed on the upper part of the display panel 100 to protect the display panel 100 and transmit light emitted from the display panel 100. As described above, the cover window (CW) may include a light-blocking portion for blocking a portion of the light emitted from the display panel 100. The cover window (CW) may be made of a transparent plastic material or a glass material (e.g., a tempered glass material).

[0282] The cover window CW can overlap with the display panel 100 and cover the front side of the display panel 100. In terms of planarity, the cover window CW generally has a shape similar to that of the display panel 100, but its size can be larger than that of the display panel 100. For example, the cover window CW can protrude outward from the display panel 100. The planar shape of the cover window CW can be the same as the planar shape of the main unit BP. For example, the planar shape of the cover window CW can be generally circular, but is not limited to this, and can have various shapes such as polygons or ellipses, such as squares.

[0283] The intermediate frame MF is a joining element used to join the cover window CW and the bottom cover BC, and is disposed between the cover window CW and the bottom cover BC. For example, the intermediate frame MF may include a bracket.

[0284] The bottom cover BC is the outer casing located below the display panel 100.

[0285] The bottom cover BC may include a central cover portion BCP and an outer portion BS disposed around the central cover portion BCP.

[0286] The center cap portion BCP is positioned at the center of the bottom cap BC and can be generally flat.

[0287] The peripheral portion BS may surround the central cover portion BCP. The peripheral portion BS may be a bent and curved portion that extends from the central cover portion BCP. The peripheral portion BS may be bent from the edge of the central cover portion BCP. In some embodiments, the peripheral portion BS may include a curved surface with a predetermined curvature, and other portions may be flat. The degree (or angle) at which the peripheral portion BS bends from the central cover portion BCP may be obtuse, but is not limited to this, and may also be right angle or acute angle.

[0288] The storage space BC-S can be formed by the central cover portion BCP and the outer portion BS. The battery BR can be placed in the storage space BC-S.

[0289] The battery BR can be connected to a circuit board on which the main processor, etc., is mounted. The display panel 100 can be electrically connected to the circuit board to receive digital video signals, timing signals, and power, etc.

[0290] The bottom cover BC is placed on the outermost rear surface of the electronic device and may include at least one of plastic, metal, and glass materials, and may include a colored coating. For example, the bottom cover BC according to the example may be a flat glass with a transparent, translucent, or opaque colored coating.

[0291] The bottom cover BC according to the example may have the same shape as the cover window CW and may include glass material with a colored coating. For example, the bottom cover BC according to the example may have a structure symmetrical to the cover window CW with an intermediate frame MF therebetween, and may include a transparent, translucent, or opaque colored coating.

[0292] The wearable part BD is, for example, a part used to secure the main unit BP to the user's wrist, and can be one of a strap, chain, or bracelet.

[0293] Figure 30 This is an example view of a virtual reality (VR) device including a display device according to one or more embodiments.

[0294] Reference Figure 30 The head-mounted display device 1000_2 according to one or more embodiments includes a display device housing 1100, a housing cover 1200, a first eyepiece 1210, a second eyepiece 1220, and a head-mounted strap 1300.

[0295] The display device housing 1100 houses the display device. The head-mounted display device 1000_2 according to one or more embodiments further includes a first optical element disposed between the first display device and the first eyepiece 1210.

[0296] The housing cover 1200 is positioned to cover the open surface of the display device housing 1100. The housing cover 1200 may include a first eyepiece 1210 for placing the user's left eye and a second eyepiece 1220 for placing the user's right eye. Although the first eyepiece 1210 and the second eyepiece 1220 are... Figure 30 The first eyepiece 1210 and the second eyepiece 1220 may be set separately, but this disclosure is not limited to this.

[0297] The headband 1300 secures the display device housing 1100 to the user's head, such that the first eyepiece 1210 and the second eyepiece 1220 of the housing cover 1200 are held in place over the user's left and right eyes, respectively. When the display device housing 1100 is made lightweight and compact, the head-mounted display device 1000_2 may include, for example... Figure 31 The image shows eyeglass frames, not a headband 1300.

[0298] Additionally, the head-mounted display device 1000_2 may further include a battery for power supply, an external memory slot for accommodating external memory, and an external connection port and a wireless communication module for receiving image sources. The external connection port may be a Universal Serial Bus (USB) terminal, a display port, or a High Definition Multimedia Interface (HDMI) terminal, and the wireless communication module may be a 5G communication module, a 4G communication module, a Wi-Fi module, or a Bluetooth module.

[0299] Figure 31 This is an example view of a VR device including a display device according to one or more embodiments. Figure 31 The illustration shows a VR device 1000_3 using a display device 10_4 according to one or more embodiments.

[0300] Reference Figure 31 According to one or more embodiments, the VR device 1000_3 may be a device in the form of glasses. The VR device 1000_3 according to an embodiment may include a display device 10_4, a left lens 10a, a right lens 10b, a support frame 20, eyeglass temples 30a and 30b, a reflective element 40, and a display device housing 50.

[0301] exist Figure 31 The illustration shows a case where the VR device 1000_3 is an eyeglass-type display device including temples 30a and 30b as an example. For example, the VR device 1000_3 according to the embodiment is not necessarily limited to... Figure 31 The VR device shown in the image can be applied to various other electronic devices in various forms.

[0302] The display device housing 50 may include a display device 10_4 and a reflective element 40. The image displayed on the display device 10_4 can be reflected by the reflective element 40 and provided to the user's right eye via the right lens 10b. Accordingly, the user can view the VR image displayed on the display device 10_4 through their right eye.

[0303] Although the display device casing 50 is in Figure 31 The display device housing 50 is located at the right end of the support frame 20, but this disclosure is not limited to this. For example, the display device housing 50 may also be located at the left end of the support frame 20. In this case, the image displayed on the display device 10_4 can be reflected by the reflective element 40 and provided to the user's left eye through the left lens 10a. Accordingly, the user can view the VR image displayed on the display device 10_4 through their left eye. Alternatively, the display device housing 50 may be located at both the right and left ends of the support frame 20. In this case, the user can view the VR image displayed on the display device 10_4 through both their left and right eyes.

[0304] Figure 32 This is an example view of a vehicle dashboard and central instrument panel including a display device, according to one or more embodiments. Figure 32 The illustration shows a vehicle using display devices 10_a to 10_e according to one or more embodiments.

[0305] Reference Figure 32The display devices 10_a to 10_c according to the embodiments can be applied to a vehicle's dashboard, a vehicle's central instrument panel, or a central information display (CID) installed on the vehicle's instrument panel. Additionally, the display devices 10_d and 10_e according to the embodiments can be applied to interior mirror displays that replace the side mirrors of a vehicle.

[0306] Figure 33 This is an example view of a transparent display device including a display apparatus according to one or more embodiments.

[0307] Reference Figure 33 The display device 10_5 according to one or more embodiments can be applied to a transparent display device. The transparent display device can transmit light while displaying an image IM. Therefore, a user located in front of the transparent display device can view not only the image IM displayed on the display device 10_5, but also the object RS or background located behind the transparent display device. When the display device 10_5 is applied to a transparent display device, the substrate of the display device 10_5 may include a light-transmitting portion, or may be made of a light-transmitting material.

[0308] However, it should be understood that the aspects and features of embodiments of this disclosure are not limited to those set forth herein. The foregoing and other aspects of this disclosure will become more apparent to those skilled in the art upon reference to the claims and their equivalents, which should be included therein.

Claims

1. A display device, comprising: substrate; A thin-film transistor layer is disposed on the substrate; A first via layer is disposed on the thin-film transistor layer; A second via layer is disposed on the first via layer and has a via layer opening; A pixel electrode layer is disposed within the opening of the via layer and on the first via layer; A light-emitting element is disposed on the pixel electrode layer; An organic partition wall is disposed on the second through-hole layer; A reflective film, covering the organic partition wall, and including a protruding portion extending along the side surface of the second via layer exposed by the opening of the via layer and the top surface of the first via layer and protruding toward the light-emitting element; as well as A first insulating film is disposed on the bottom surface of the reflective film. Wherein, the protruding portion overlaps with the edge of the pixel electrode layer in the thickness direction, and The pixel electrode layer and the reflective film are spaced apart from each other.

2. The display device according to claim 1, wherein, The protruding portion is lower than the lower end of the light-emitting element.

3. The display device according to claim 1, further comprising: A second insulating film is disposed on the top surface of the reflective film and surrounds the top and side surfaces of the protrusion. The pixel electrode layer includes a pixel electrode and a protective film surrounding the side surface of the pixel electrode.

4. The display device according to claim 3, wherein, The protruding portion overlaps with the protective film in the thickness direction.

5. The display device according to claim 3, wherein, The protruding portion overlaps with the edge of the pixel electrode in the thickness direction and is spaced apart from the pixel electrode.

6. The display device according to claim 5, wherein, The first insulating film and the pixel electrode are spaced apart from each other on the bottom surface of the protruding portion.

7. The display device according to claim 6, further comprising: The electrode is disposed between the light-emitting element and the pixel electrode, and extends between the bottom surface of the first insulating film and the top surface of the pixel electrode.

8. The display device according to claim 1, wherein, The organic partition wall includes a single organic layer or multiple organic layers.

9. The display device according to claim 1, wherein, The organic separator has an angle of inclination formed between the outer surface facing the light-emitting element and an imaginary surface extending parallel to the contact surface of the light-emitting element and the bonding electrode. The tilt angle is in the range of 120 degrees to 135 degrees, including 120 degrees and 135 degrees.

10. The display device according to any one of claims 1 to 9, wherein, The light-emitting element includes a protective film disposed on the side surfaces of the first semiconductor layer, the active layer, and the second semiconductor layer, and The light-emitting element does not have a reflective film disposed on any of the side surfaces of the first semiconductor layer, the active layer, and the second semiconductor layer on the protective film.

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