Method for improving aei ovl monitoring
By optimizing the measurement pattern size and etching process, the resolution and morphology issues after germanium-silicon strip etching were resolved, improving the accuracy of AEI OVL monitoring and avoiding the use of additional processes.
Patent Information
- Application Number
- CN202610416941.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-03-31
- Publication Date
- 2026-07-10
AI Technical Summary
In the existing technology, after germanium-silicon strip etching, the front silicon strip has low resolution and poor morphology, resulting in inaccurate AEI OVL monitoring.
By optimizing the measurement pattern size, increasing the spacing of the second stripe and the length of the third stripe, a suitable etching process is formed, and AEI measurements are performed to monitor OVL.
It improves the resolution of the previous layer pattern and the morphology of the current layer pattern, enhances the accuracy of AEI OVL monitoring, avoids additional dry or wet stripping processes, and reduces the impact on the etching process.
Smart Images
Figure CN122373766A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to a method for manufacturing semiconductor integrated circuits, and more particularly to a method for improving monitoring of overlay (OVL) during after etching inspection (AEI). Background Technology
[0002] OVL is one of the important parameters in photolithography, and it is usually measured by Adaptive Development (ADI) OVL after photolithography. For some key layers of advanced nodes, OVL monitoring requires controlling ADI OVL and using AEI OVL as the final result to control shipment.
[0003] For example, in the silicon germanium (SiGe) process loop, the product is monitored by measuring the critical dimension (CD) between the edges of the silicon phosphorus (SiP) layer and the full-ring channel (CAA) stripe, calculating the center position deviation. However, in actual processes, after the SiP region is etched, it often cannot effectively receive signals, resulting in the inability to image and measure the front CAA layer under CD SEM.
[0004] When attempting measurements after dry stripping / wet stripping, the image contrast improved but the profile was abnormal, and normal products could not be measured using AEI OVL.
[0005] like Figure 1 The diagram shows the measurement pattern used in existing AEI OVL monitoring methods, including: silicon strip 101, polysilicon strip 103, and germanium-silicon strip 102. Silicon strip 101 and polysilicon strip 103 are perpendicular, and germanium-silicon strip 102 is located in the interval region between the polysilicon strips 103. The germanium-silicon strip 102 needs to be formed after photolithography etching of the germanium-silicon layer. After the etching process of the germanium-silicon layer is completed, AEI measurement is required. For example, the measurement... Figure 1 The edge spacings d1 and d2 are used to calculate the OVL (OVLy) between the germanium-silicon strip 102 and the bottom front layer pattern, i.e., the silicon strip 101, along the extension direction of the polysilicon strip 103, such as the y-direction. Specifically, the value is half the difference between d1 and d2. The region between the germanium-silicon strips 102 is typically the region where SiP strips are formed; the OVLy between the SiP strips and silicon strips can also be calculated by measuring the spacings d3 and d4.
[0006] However, in the existing method, after the germanium-silicon strip 102 is etched, the resolution of the silicon strip 101 in the previous layer is low in AEI measurement, so the edge of the silicon strip 101 cannot be measured; while the edge of the germanium-silicon strip 102 in the next layer is often inaccurate in AEI measurement due to the poor morphology of the germanium-silicon strip 102, so it is not possible to achieve good OVL monitoring.
[0007] To achieve good OVL monitoring, one existing improvement method is to add a dry lift-off process after etching the germanium-silicon strip 102. Dry lift-off improves the morphology of the germanium-silicon strip 102, but the resolution of the silicon strip 101 remains low. Another existing improvement method is to further add a wet lift-off process on top of the dry lift-off process. This increases the resolution of the silicon strip 101, but the morphology of the germanium-silicon strip 102 becomes very poor again. Summary of the Invention
[0008] The technical problem to be solved by the present invention is to provide a method for improving AEI OVL monitoring, which can simultaneously improve the resolution of the previous layer image and improve the morphology of the current layer image, thereby improving the accuracy of AEI OVL monitoring.
[0009] Therefore, the method for improving AEI OVL monitoring provided by the present invention includes: Step 1: Provide a measurement graphic and optimize the size settings of the measurement graphic.
[0010] The measurement pattern includes a front layer pattern comprising multiple parallel first stripes extending along a first direction; multiple parallel second stripes perpendicular to the first stripes, each second stripe covering the top surface and side surface of each first stripe along its extension direction; and a back layer pattern comprising multiple parallel third stripes extending along the first direction, each third stripe located directly above and extending to the outside of a corresponding first stripe.
[0011] The optimization settings include: increasing the first spacing between the second bars in the subsequent AEI to meet the resolution requirements of the first bars.
[0012] The length of the third strip is increased until the outline of the third strip in the AEI meets the requirements.
[0013] Step 2: Complete the etching process of the current layer pattern to form the third stripe.
[0014] Step 3: Perform AEI measurement to measure the distance between the edge of the first strip and the edge of the adjacent third strip on both sides of each first strip, thereby achieving OVL monitoring in the second direction.
[0015] A further improvement is that the first stripe is a convex stripe formed by patterning etching of a semiconductor substrate.
[0016] A further improvement is that, before the etching process of the current layer pattern in step two, the following is also included: A third strip of material layer is formed, which covers the area between each of the second stripes.
[0017] Photolithography defines the formation region of the third stripe.
[0018] A further improvement is that the third strip-shaped material layer includes a SiGe layer.
[0019] A further improvement is that the semiconductor substrate is made of Si.
[0020] A further improvement is that the second strip is a polycrystalline silicon strip.
[0021] A further improvement is that the area where the polysilicon strip intersects with the first strip is a polysilicon gate, and a gate dielectric layer is also spaced between the polysilicon gate and the surface of the first strip.
[0022] A further improvement is that the material of the gate dielectric layer includes an oxide layer.
[0023] A further improvement is that the first spacing is greater than 4000 Å.
[0024] A further improvement is that the length of the third stripe satisfies the requirement that the number of intersections with the second stripe is 5 or more.
[0025] A further improvement is that, in the measurement pattern, there is a first strip without a third strip between two adjacent third strips.
[0026] A further improvement is that, in a second direction perpendicular to the first direction, the width of the third stripe is equal to the width of the gap between the third stripes.
[0027] A further improvement is that the spacing between the third stripes is the region where the SiP layer is formed.
[0028] A further improvement is to rotate the measurement pattern by 90 degrees to achieve OVL monitoring in the first direction.
[0029] A further improvement is that, in step two, after completing part of the etching process of the current layer pattern, step three is performed.
[0030] This invention specifically addresses the structural design of the measurement pattern. Primarily, based on the requirements of AEI testing, the spacing of the second stripe (i.e., the first spacing) is increased. This increase ensures that the resolution requirements of the first stripe are met during AEI measurement, enabling the resolution of the preceding layer pattern. Simultaneously, the length of the third stripe is increased. Given a fixed width of the second stripe and a fixed first spacing, a longer third stripe results in a greater number of intersecting second stripes. Consequently, the morphology of the third stripe improves after the etching process of the layer pattern is completed. Therefore, this invention adjusts the morphology of the third stripe by adjusting its length. Thus, this invention simultaneously improves the resolution of the preceding layer pattern and enhances the morphology of the current layer pattern, thereby improving the accuracy of AEI OVL monitoring. Attached Figure Description
[0031] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments: Figure 1 It is the measurement pattern used in existing AEI OVL monitoring methods; Figure 2 This is a flowchart of the method for improving AEI OVL monitoring according to the present invention; Figure 3 This is the measurement pattern used in the method for improving AEI OVL monitoring in this invention. Detailed Implementation
[0032] like Figure 2 The diagram shown is a flowchart of a method for improving AEI OVL monitoring according to an embodiment of the present invention; as shown Figure 3 The image shown is a measurement pattern used in the method for improving AEI OVL monitoring according to an embodiment of the present invention; the method for improving AEI OVL monitoring according to an embodiment of the present invention includes: Step 1: Provide the measurement graphic and optimize its dimensions.
[0033] like Figure 3 As shown, the measurement pattern includes a front-layer pattern, which includes multiple parallel first bars 201 extending along a first direction. Figure 3 In the middle, the first direction is the left and right direction of the paper.
[0034] Multiple parallel second strips 203 are arranged perpendicularly to the first strips 201, and each second strip 203 covers the top surface and side surface of each first strip 201 in the direction of extension of the second strip 203.
[0035] The layer pattern includes multiple parallel third stripes 202, which extend along a first direction. Each third stripe 202 is located directly above the corresponding first stripe 201 and extends to the outside of the first stripe 201.
[0036] The optimization settings include: increasing the first spacing w101 between the second bars 203 in subsequent AEIs to meet the resolution requirements of the first bars 201.
[0037] The length w102 of the third strip 202 is increased to the outline of the third strip 202 in AEI to meet the requirements.
[0038] Step 2: Complete the etching process of the current layer pattern to form the third stripe 202.
[0039] In this embodiment of the invention, a first stripe 201 is formed on a semiconductor substrate (not shown) before the etching process of the current layer pattern. The first stripe 201 is a raised stripe formed by patterning etching of the semiconductor substrate.
[0040] It also formed a second stripe 203.
[0041] In some embodiments, the semiconductor substrate is made of Si.
[0042] The second strip 203 is a polysilicon strip. The area where the polysilicon strip intersects with the first strip 201 is a polysilicon gate, and a gate dielectric layer (not shown) is also spaced between the polysilicon gate and the surface of the first strip 201. The surface of the first strip 201 covered by the polysilicon gate is used to form an electrical channel, for example, a conductive channel may be formed on the side and / or top surface of the first strip 201. In some embodiments, the material of the gate dielectric layer includes an oxide layer.
[0043] In this embodiment of the invention, the etching process of the current layer pattern in step two further includes: A material layer is formed to form a third strip 202, which covers the region between each of the second strips 203. In some embodiments, the material layer of the third strip 202 is a SiGe layer. In other embodiments, the material layer of the third strip 202 may also be configured as other semiconductor material layers as needed, and the material of the third strip 202 is required to improve the channel carrier mobility of the device based on the material of the semiconductor substrate.
[0044] Photolithography defines the formation region of the third stripe 202.
[0045] Next, the etching process for the current layer pattern is performed. For example... Figure 3As shown, when the etching process of the layer pattern removes the material layer of the third strip 202 in the spacer region between the third strips 202, the material layer of the remaining third strip 202 forms the third strip 202.
[0046] In this embodiment of the invention, in the measurement pattern, there is a first strip 201 without a third strip 202 between two adjacent third strips 202.
[0047] In some embodiments, in a second direction perpendicular to the first direction, the width of the third strip 202 is equal to the width of the spacing region between the third strips 202.
[0048] In some embodiments, the first spacing w101 is 4000 Å or more.
[0049] The length w102 of the third stripe 202 satisfies that the number of intersections with the second stripe 203 is 5 or more. Figure 3 In the example, the first spacing w101 is 4000 Å, the length w102 of the third strip 202 intersects with the number of the second strip 203 by 5.
[0050] For comparison, please refer to the corresponding existing methods. Figure 1 As shown, in the existing method, the first spacing w1 is 1600 Å, and the length w2 of the germanium-silicon strip 102 only intersects with the three polysilicon strips 103. This results in a large aspect ratio in the spacing region of the germanium-silicon strip 102 after etching, for example, an aspect ratio of 1600 Å width and 1800 Å depth of the previous layer. Furthermore, the side profile of the germanium-silicon strip 102 is also affected. Such a profile and aspect ratio have a significant impact on the signal. Due to the influence of the profile aspect ratio, the signal cannot be effectively received, resulting in the inability to image and measure the previous layer CAA under CD SEM. In this embodiment of the invention, by specifically increasing the size of the first spacing w101 and increasing the size of the length w102 of the third strip 202, the technical problems existing in the existing method can be overcome.
[0051] Step 3: Perform AEI measurement to measure the distance between the edge of the first strip 201 and the edge of the adjacent third strip 202 on both sides of each first strip 201, thereby achieving OVL monitoring.
[0052] In this embodiment of the invention, taking the first stripe 201 in the first row as an example, the distances between the two sides of the first stripe 201 and the edge of the corresponding adjacent third stripe 202 are distances d1 and d2, respectively. The set values of d1 and d2 are equal. However, due to the existence of overprinting error, the measured values of d1 and d2 are actually different. The overprinting error in the second direction can be calculated from d1 and d2. Taking the first direction as the x-direction and the second direction as the y-direction as an example, OVLy, that is, the overprinting error in the second direction, is half the difference between d1 and d2.
[0053] Rotate the measurement graphic by 90 degrees to achieve OVL monitoring in the first direction.
[0054] In some embodiments, the spacing between the third stripes 202 is the region where the SiP layer is formed, and the SiP layer, once formed, serves as the SiP layer pattern. For example... Figure 3 As shown, the registration error between the SiP layer pattern and the first strip 201 in the y direction can also be measured. Specifically, the values of d3 and d4 are measured, and then half of the difference between d1 and d2 is taken as the registration error between the SiP layer pattern and the first strip 201 in the y direction.
[0055] This invention specifically addresses the structural design of the measurement pattern. Primarily, based on the requirements of AEI testing, the spacing of the second stripe (i.e., the first spacing) is increased. This increase ensures that the resolution requirements of the first stripe are met during AEI measurement, enabling the resolution of the preceding layer pattern. Simultaneously, the length of the third stripe is increased. Given a fixed width of the second stripe and a fixed first spacing, a longer third stripe results in a greater number of intersecting second stripes. Consequently, the morphology of the third stripe improves after the etching process of the layer pattern is completed. Therefore, this invention adjusts the morphology of the third stripe by adjusting its length. Thus, this invention simultaneously improves the resolution of the preceding layer pattern and enhances the morphology of the current layer pattern, thereby improving the accuracy of AEI OVL monitoring.
[0056] As can be seen, the embodiments of the present invention can simultaneously eliminate the defects of the first strip being indistinguishable and the third strip having poor morphology in the existing methods. Moreover, the embodiments of the present invention do not require additional dry stripping to improve the morphology of the third strip, nor do they require additional wet stripping to improve the resolution of the first strip. Furthermore, they can eliminate the defect that dry stripping and wet stripping can only improve one of the morphology of the third strip and the resolution of the first strip.
[0057] Furthermore, embodiments of the present invention do not require partial etching of the current layer pattern to improve the resolution of the first stripe; therefore, embodiments of the present invention do not affect the etching process of the current layer pattern. For example, some short-term improvement methods can perform AEI measurement after only partially etching the current layer pattern. For instance, in existing methods, after partial etching, the depth of the previous layer decreases from 1800 Å to 1100 Å. Figure 1 The aspect ratio in the spacing region between the corresponding germanium-silicon stripes 102 will decrease, thereby increasing the resolution of the silicon stripe 101 in the previous layer. At the same time, the side morphology of the germanium-silicon stripe 102 will also be improved. Therefore, in this embodiment of the invention, it is not necessary to partially etch the etching process of the current layer pattern to improve the resolution of the first stripe.
[0058] In some embodiments, step three can also be performed after partial etching of the current layer pattern has been completed.
[0059] The present invention has been described in detail above through specific embodiments, but these are not intended to limit the invention. Many modifications and improvements can be made by those skilled in the art without departing from the principles of the invention, and these should also be considered within the scope of protection of the present invention.
Claims
1. A method for improving AEI OVL monitoring, characterized in that, include: Step 1: Provide a measurement graphic and optimize the dimensions of the measurement graphic; The measurement pattern includes a front layer pattern comprising multiple parallel first stripes extending along a first direction; multiple parallel second stripes perpendicular to the first stripes, each second stripe covering the top surface and side surface of each first stripe along its extension direction; and a back layer pattern comprising multiple parallel third stripes extending along the first direction, each third stripe located directly above and extending to the outside of a corresponding first stripe. The optimization settings include: increasing the first spacing between the second bars in the subsequent AEI to meet the resolution requirements of the first bars; Increase the length of the third stripe until the outline of the third stripe in the AEI meets the requirements; Step 2: Complete the etching process of the current layer pattern to form the third stripe; Step 3: Perform AEI measurement to measure the distance between the edge of the first strip and the edge of the adjacent third strip on both sides of each first strip, thereby achieving OVL monitoring in the second direction.
2. The method for improving AEI OVL monitoring as described in claim 1, characterized in that: The first strip is a convex strip formed by patterning etching of a semiconductor substrate.
3. The method for improving AEI OVL monitoring as described in claim 2, characterized in that, Step two, prior to the etching process of the current layer pattern, also includes: A third strip of material layer is formed, which covers the area between each of the second stripes; Photolithography defines the formation region of the third stripe.
4. The method for improving AEI OVL monitoring as described in claim 3, characterized in that: The third strip-shaped material layer includes a SiGe layer.
5. The method for improving AEI OVL monitoring as described in claim 4, characterized in that: The semiconductor substrate is made of Si.
6. The method for improving AEI OVL monitoring as described in claim 5, characterized in that: The second strip is a polycrystalline silicon strip.
7. The method for improving AEI OVL monitoring as described in claim 6, characterized in that: The area where the polysilicon strip intersects with the first strip is a polysilicon gate, and a gate dielectric layer is also spaced between the polysilicon gate and the surface of the first strip.
8. The method for improving AEI OVL monitoring as described in claim 7, characterized in that: The material of the gate dielectric layer includes an oxide layer.
9. The method for improving AEI OVL monitoring as described in claim 6, characterized in that: The first spacing is 4000 Å or more.
10. The method for improving AEI OVL monitoring as described in claim 6, characterized in that: The length of the third stripe satisfies the requirement that it intersects with the second stripe in at least five ways.
11. The method for improving AEI OVL monitoring as described in claim 4, characterized in that: In the measurement pattern, there is a first strip without a third strip between two adjacent third strips.
12. The method for improving AEI OVL monitoring as described in claim 11, characterized in that: In a second direction perpendicular to the first direction, the width of the third strip is equal to the width of the gap between the third strips.
13. The method for improving AEI OVL monitoring as described in claim 12, characterized in that: The gaps between the third stripes are regions where SiP layers are formed.
14. The method for improving AEI OVL monitoring as described in claim 1, characterized in that: The measurement graphic is rotated 90 degrees to achieve OVL monitoring in the first direction.
15. The method for improving AEI OVL monitoring as described in claim 1, characterized in that: In step two, after completing part of the etching process of the current layer pattern, step three is performed.