Integrated circuit device structure and method of forming the same

Abstract

Embodiments of this application relate to integrated circuit device structures and methods of forming the same. A dual-protection-ring structure includes a first protection ring (e.g., a main protection ring) and a second protection ring (e.g., a secondary protection ring). The first protection ring is separate from and laterally adjacent to the second protection ring. The second protection ring overlaps with a gap in the first protection ring, such that the dual-protection-ring structure overlaps with the sidewall of a through-hole along the entire height of the dual protection rings. In some embodiments, the first protection ring and the second protection ring are respectively an outer protection ring and an inner protection ring. In some embodiments, the first protection ring and the second protection ring are respectively an inner protection ring and an outer protection ring. In some embodiments, the outer protection ring and the inner protection ring of the dual-protection-ring structure are formed by the first protection ring and the second protection ring.

Description

Technical Field

[0001] Embodiments of this application relate to integrated circuit device structures and methods of forming the same. Background Technology

[0002] The semiconductor integrated circuit (IC) industry has experienced rapid growth. Continuous advancements in semiconductor manufacturing processes have led to finer component dimensions and / or higher integration in semiconductor devices within integrated circuits (“ICs”). Functional density (i.e., the number of interconnect devices per IC chip area) has typically increased, while feature size (i.e., the smallest component that can be created using manufacturing processes) has decreased. This scaling down process generally provides benefits through increased production efficiency and reduced associated costs.

[0003] Advanced IC packaging technologies have been developed to further reduce IC density and / or improve IC performance. For example, IC packages have evolved to allow multiple ICs to be vertically stacked in three-dimensional (“3D”) packages or 2.5D packages (using an interposer). Through-silicon vias (also known as through-silicon vias (TSVs)) are a technology for connecting stacked ICs. Such technologies sometimes implement protective and / or shielding structures, such as guard rings, to improve the reliability and integrity of the TSVs. Improvements are needed in the design of these protective and / or shielding structures. Summary of the Invention

[0004] According to one aspect of the embodiments of this application, an integrated circuit device structure is provided, including: a through-hole disposed in an insulating layer; and a guard ring structure disposed in the insulating layer, wherein the guard ring structure is disposed around the through-hole, the guard ring structure includes a main guard ring and a secondary guard ring, the secondary guard ring is adjacent to and separate from the main guard ring, wherein the gap in the secondary guard ring overlaps with the gap in the main guard ring, and the gap corresponds to the sidewall portion of the through-hole, the sidewall portion does not overlap with the main guard ring.

[0005] According to another aspect of the embodiments of this application, an integrated circuit device structure is provided, including: a first chip attached to a second chip; a through-hole disposed in an insulating layer, wherein the through-hole is electrically connected to the first chip and the second chip; and a guard ring structure disposed in the insulating layer and surrounding the through-hole, wherein the guard ring structure includes a main guard ring and a secondary guard ring, the secondary guard ring being adjacent to and separate from the main guard ring, wherein the secondary guard ring overlaps with a first gap in the main guard ring, the main guard ring overlaps with a second gap in the secondary guard ring, and the first gap and the second gap do not overlap.

[0006] According to another aspect of the embodiments of this application, a method for forming an integrated circuit device structure is provided, comprising: forming a multilayer interconnect structure; forming a guard ring structure and a through-hole landing pad while forming the multilayer interconnect structure, wherein forming the multilayer interconnect structure and the guard ring structure includes performing a photolithography process, an etching process, and a deposition process, wherein the guard ring structure forms a ring around a region of an insulating layer, and the guard ring structure includes a primary guard ring and a secondary guard ring, the secondary guard ring being adjacent to the primary guard ring, separate from the primary guard ring, and overlapping a gap in the primary guard ring; and forming a through-hole extending through a region of the insulating layer to a through-hole landing pad, wherein the gap in the primary guard ring corresponds to a sidewall portion of the through-hole that does not overlap with the primary guard ring. Attached Figure Description

[0007] The various aspects of this disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard industry practice, the individual components are not drawn to scale and are for illustrative purposes only. For clarity of discussion, the dimensions of the individual components may be arbitrarily increased or decreased.

[0008] Figure 1A It is a partial or complete cross-sectional view of a stacked chip structure with an improved guard ring design according to various aspects of this disclosure.

[0009] Figure 1B Based on all aspects of this disclosure Figure 1A A cross-sectional view of part or all of a stacked chip structure and its circuitry.

[0010] Figure 2 Based on all aspects of this disclosure Figure 1A A magnified cross-sectional view of a portion of the stacked chip structure.

[0011] Figure 3 Based on all aspects of this disclosure Figure 1A An enlarged cross-sectional view of another part of the stacked chip structure.

[0012] Figure 4 and Figure 5 Based on all aspects of this disclosure Figure 3 A partial plan view of the stacked chip structure.

[0013] Figure 6 Based on all aspects of this disclosure Figure 3 An enlarged cross-sectional view of a portion of a stacked chip structure, depicting another via configuration that can be implemented in a stacked chip structure.

[0014] Figures 7A to 7G It is a partial or complete top view of the through-hole according to various aspects of this disclosure. Figures 8A to 8G It is possible Figure 1A A partial or complete top view of the protective rings implemented in the stacked chip structure.

[0015] Figure 9A Based on all aspects of this disclosure Figure 3 Enlarged cross-sectional view of a portion of a stacked chip structure with different through-hole contact configurations. Figure 9B Based on all aspects of this disclosure Figure 9A A partial plan view of the stacked chip structure.

[0016] Figure 10 It is yet another through-hole contact configuration according to various aspects of this disclosure. Figure 9A A partial plan view of the stacked chip structure.

[0017] Figures 11-15 Based on all aspects of this disclosure Figure 3 The enlarged cross-sectional view of a portion of the stacked chip structure depicts different guard ring configurations with an improved guard ring design.

[0018] Figures 16A-16L It is a partial or complete cross-sectional view of the device structure at various manufacturing stages of forming the through-hole and the guard ring having an improved guard ring design, according to various aspects of this disclosure.

[0019] Figure 17 It is based on various aspects of this disclosure for manufacturing protective rings and through holes (such as...) Figure 3 The flowcharts for some or all of the methods shown are shown. Detailed Implementation

[0020] This disclosure generally relates to integrated circuits (ICs) and / or semiconductor packages, and more specifically, to protective rings for through-holes.

[0021] The following disclosure provides numerous different embodiments or examples for implementing various features of this disclosure. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature on or above a second feature can include embodiments where the first and second features are in direct contact, or embodiments where an additional feature is formed between the first and second features. Furthermore, for the purpose of disclosing the relationship between one feature and another feature in this application, spatially relative terms such as “lower,” “upper,” “horizontal,” “vertical,” “above,” “below,” “lower,” “upper,” “top,” “bottom,” and their derivatives (e.g., “horizontally,” “downward,” “upward,” etc.) are used. Spatially relative terms are intended to cover different orientations of the device, including features. Additionally, when a number or range of numbers is described as “about,” “approximately,” “substantially,” etc., the term is intended to include numbers within a reasonable range to account for variations inherent in the manufacturing process as understood by those skilled in the art. For example, based on known manufacturing tolerances associated with the feature having the number, the number or range of numbers covers a reasonable range including the described number, such as within + / - 20% of the described number. For example, a material layer with a thickness of “about 5 nm” can include a size range of 4.5 nm to 5.5 nm, where the manufacturing tolerances associated with the deposited material layer are known to be + / - 10%. In another example, when two features are described as having “substantially identical” dimensions and / or “substantially” orientation in a particular direction and / or configuration (e.g., “substantially parallel”), this description may cover dimensional differences between the two features and / or slight orientation deviations inherent to, and not intentionally caused by, the manufacturing tolerances associated with manufacturing the two features. Furthermore, reference numerals and / or letters may be repeated in various examples of this disclosure. Such repetition is for simplicity and clarity and does not in itself determine the relationship between the various embodiments and / or configurations described herein.

[0022] Advanced IC packaging technologies have been developed to further improve the density and / or performance of integrated circuits (ICs) integrated into numerous electronic devices. For example, IC packaging has evolved to allow multiple ICs to be vertically stacked in a three-dimensional (“3D”) package or a 2.5D package (e.g., a package utilizing an interposer). Through-silicon vias (also known as through-silicon vias (TSVs)) are a technique for connecting stacked ICs. For example, in the case where a first chip is vertically stacked above a second chip, a TSV can be formed that extends vertically through the first chip to the second chip, where the TSV electrically connects a first conductive structure (e.g., a first wiring) of the first chip and / or physically connects it to a second conductive structure (e.g., a second wiring) of the second chip. The TSV is a conductive structure, such as a copper structure, and can pass through part or all of the first chip to extend to the second chip.

[0023] A guard ring is typically formed around a TSV to protect the TSV, improve TSV performance, enhance TSV structural stability, shield and / or reduce noise caused by the TSV that may negatively affect the first chip and / or the second chip, or a combination thereof. The guard ring can be formed during the formation of the back-end process (BEOL) structure of the first chip (e.g., the first wiring of the first chip). The first wiring (e.g., its front-side multilayer interconnect (MLI)) can be disposed on and connected to the first device substrate of the first chip, facilitating the operation and / or electrical communication of devices and / or structures on the first device substrate. The TSV can be formed after the formation of the BEOL structure. For example, the TSV can be formed by a TSV back-side fabrication process that may include flipping the first chip, etching through the first device substrate (e.g., from its back side to its front side) and the dielectric layer of the BEOL structure (e.g., in the region defined by the guard layer) to form a TSV trench, and filling the TSV trench with a conductive material. The first chip can then be bonded and / or attached to the second chip, and the TSV can be electrically connected to the second chip, for example, to the BEOL structure of the second chip. The BEOL structure of the second chip can be disposed on and connected to the second device substrate of the second chip, and the BEOL structure in the second chip can facilitate the operation and / or electrical communication of the devices and / or structures of the second device substrate.

[0024] This disclosure proposes a dual-guard ring design, which can improve device reliability and / or performance, for example, by preventing and / or reducing damage to device structure and / or device components during through-hole manufacturing. In some embodiments, the dual-guard ring structure includes a first guard ring (e.g., a primary guard ring) and a second guard ring (e.g., a secondary guard ring). The first guard ring is separate from and not connected to the second guard ring, and the second guard ring is laterally spaced from the first guard ring. The gaps between the second guard ring and the first guard ring overlap, such that the dual-guard ring structure overlaps with the sidewall of the through-hole along the entire height of the dual guard rings. This disclosure considers various configurations of the first and second guard rings. In some embodiments, the first guard ring and the second guard ring are respectively an outer guard ring and an inner guard ring. In some embodiments, the first guard ring and the second guard ring are respectively an inner guard ring and an outer guard ring. In some embodiments, the outer guard ring and the inner guard ring of the dual-guard ring structure are formed by the first guard ring and the second guard ring. This disclosure also considers positioning the second guard ring at any level of the dual-guard rings, depending on the location of the gap in the first guard ring. The dual guard ring structure disclosed herein can prevent and / or reduce moisture erosion of low-k dielectric materials and / or metallic materials (e.g., materials associated with multilayer interconnect structures), thereby improving device integrity. This document describes the proposed dual guard ring design, its corresponding TSV design, and / or details of its fabrication. Different embodiments may have different advantages, and no particular advantage is required in any embodiment.

[0025] Figure 1A It is a partial or complete cross-sectional view of a stacked chip structure 100 with an improved guard ring design according to various aspects of this disclosure. Figure 1B These are partial or complete cross-sectional views of the stacked chip structure 100 according to various aspects of this disclosure, showing its various electrical paths. Figure 2 This is an enlarged cross-sectional view of a portion of the stacked chip structure 100 according to various aspects of this disclosure. Figure 3 This is an enlarged cross-sectional view of another part of the stacked chip structure 100 according to various aspects of this disclosure. Figure 4 Based on all aspects of this disclosure Figure 3 A top view of part of the stacked chip structure 100 along line AA. Figure 5 Based on all aspects of this disclosure Figure 3 A top view of part of the stacked chip structure 100 along line BB. Figure 6 Based on all aspects of this disclosure Figure 3 Enlarged cross-sectional view of portions of the stacked chip structure 100 with different through-hole configurations. Figures 7A to 7G This is a partial or complete top view of through-holes that can be implemented in the stacked chip structure 100 according to various aspects of this disclosure. Figures 8A-8GThis is a top view of a protective ring according to various aspects of this disclosure, which may be partially or wholly formed around a through-hole and may be implemented in a stacked chip structure 100. Figure 9A Based on all aspects of this disclosure Figure 3 Enlarged cross-sectional view of portions of the stacked chip structure 100 with different contact configurations. Figure 9B It is based on the various aspects of this disclosure. Figure 9A A top view of the BB line portion of the stacked chip structure 100. Figure 10 Based on all aspects of this disclosure Figure 9A A top view of a portion of the stacked chip structure 100 along another contact configuration of its BB line. Figures 11-15 Based on all aspects of this disclosure Figure 3 Enlarged cross-sectional views of portions of the stacked chip structure 100 with different guard ring configurations are shown. For ease of description and understanding, this paper also discusses… Figure 1A , Figure 1B , Figures 2-6 , Figures 7A-7G , Figures 8A-8G , Figure 9A , Figure 9B and Figures 10-15 For clarity, the following has been simplified. Figure 1A , Figure 1B , Figures 2-6 , Figures 7A-7G , Figures 8A-8G , Figure 9A , Figure 9B and Figures 10-15 To better understand the inventive concept of this disclosure. Additional features may be added to the stacked chip structure 100, and some features described below may be replaced, modified, or eliminated in other embodiments of the stacked chip structure 100.

[0026] Reference Figure 1AThe stacked chip structure 100 includes chip 102 and chip 104, with chip 102 and chip 104 attached to form an IC (and / or semiconductor) package or a portion thereof. Chip 102 and chip 104 each include at least one functional IC, such as an IC configured to perform logic functions, memory functions, digital functions, analog functions, mixed-signal functions, radio frequency (RF) functions, input / output (I / O) functions, communication functions, power management functions, other functions, or combinations thereof. In some embodiments, chip 102 and chip 104 provide the same functionality (e.g., both may be a central processing unit (CPU)). In some embodiments, chip 102 and chip 104 provide different functions (e.g., one may be a CPU, while the other may be a graphics processing unit (GPU) or static random access memory (SRAM)). In some embodiments, chip 102 and / or chip 104 are system-on-a-chip (SoC), which generally refers to a single chip and / or die having multiple functions. In some embodiments, an SoC is a single chip having an entire system (e.g., a computer system) manufactured thereon. In some embodiments, the IC package (e.g., stacked chip structure 100) is an integrated system-on-a-chip (SoIC) package. The SoIC can have a multi-chip, mixed-node design, and chips 102 and 104 can have different functions (e.g., CPU, GPU, RF, SRAM, etc.) and can be manufactured according to different process nodes (e.g., 3nm (N3), N5, N65, 0.13 micrometers (µm) (C013), etc.), wherein the functions and process nodes can be selected according to design specifications (e.g., power, performance, area, and cost (PPAC) specifications).

[0027] Chip 102 and chip 104 may each include device layers, such as device layer DL1 and device layer DL2. Device layer DL1 includes a substrate 106 having circuitry fabricated on its front side and / or above it via front-end processing (FEOL), and device layer DL2 includes a substrate 108 having circuitry fabricated on its back side and / or above it via FEOL. For example, device layer DL1 and / or device layer DL2 may include various device components / parts, such as semiconductor substrates, doped wells (e.g., n-wells and / or p-wells), isolation components (e.g., shallow trench isolation (STI) structures and / or other suitable isolation structures), gates (e.g., gate stacks having gate electrodes and gate dielectrics), gate spacers along the gate sidewalls, source / drain (e.g., epitaxial source / drain), other suitable device components and / or device parts, or combinations thereof. In some embodiments, device layers DL1 and / or DL2 include planar transistors, wherein the channels of the planar transistors are formed in a semiconductor substrate (e.g., substrate 106 and / or substrate 108) between respective source / drain electrodes, and the respective gates are disposed on the channels (e.g., above a portion of the semiconductor substrate forming the channels). In some embodiments, device layers DL1 and / or DL2 include non-planar transistors having channels formed in respective semiconductor fins extending from the semiconductor substrate, the channels being between respective source / drain electrodes on / in the semiconductor fins, wherein the respective gates are disposed on and surround the channels of the semiconductor fins (i.e., the non-planar transistors are fin field-effect transistors (FinFETs)). In some embodiments, device layers DL1 and / or DL2 include non-planar transistors having channels formed in a semiconductor layer suspended above the substrate and extending between respective source / drain electrodes, wherein the respective gates are disposed on and at least partially surround the respective channels (i.e., the non-planar transistors are gate-all-around (GAA) transistors and / or fork-plate transistors). Depending on design requirements, the transistors in device layer DL1 and / or device layer DL2 may be configured as planar transistors and / or non-planar transistors. In some embodiments, device layer DL1 and / or device layer DL2 include stacked transistors, such as complementary field-effect transistors (CFETs) and / or other stacked transistors.

[0028] Device layers DL1 and / or DL2 may include various passive and / or active microelectronic devices, such as resistors, capacitors, inductors, diodes, p-type FETs (PFETs), n-type FETs (NFETs), metal-oxide-semiconductor (MOS) FETs (MOSFETs), complementary MOS (CMOS) transistors, bipolar junction transistors (BJTs), laterally diffused MOS (LDMOS) transistors, high-voltage transistors, high-frequency transistors, other suitable devices and / or components, or combinations thereof. These various microelectronic devices can be configured to provide functionally distinct regions of the IC, such as logic regions (i.e., core regions), memory regions, analog regions, peripheral regions (e.g., I / O regions), pseudo-regions, other suitable regions, or combinations thereof. Logic regions may be configured with standard cells, each providing a logic device and / or logic function, such as inverters, AND gates, NAND gates, OR gates, NOR gates, NOT gates, XOR gates, XNOR gates, other suitable logic devices, or combinations thereof. The memory region may be configured with memory cells, each memory cell providing a storage device and / or storage function, such as flash memory, non-volatile random access memory (NVRAM), SRAM, dynamic random access memory (DRAM), other volatile memory, other suitable memory, or combinations thereof. In some embodiments, the memory cell and / or logic cell includes transistors and interconnect structures that combine to provide the storage device / function and logic device / function, respectively.

[0029] refer to Figure 2 Provided Figure 1A An enlarged view of region I of the stacked chip structure 100, depicting portions of device parts and / or device assemblies of the device layer of the chip (e.g., device layer DL1 of chip 102). Figure 2In this configuration, device layer DL1 includes various transistors, such as transistor T1 and transistor T2, formed on / above substrate 106. Device layer DL2 may be configured similarly to device layer DL1, and device layer DL2 may include various transistors formed on / above its substrate 108. Transistor T1 and transistor T2 each include a corresponding gate structure 110 disposed between corresponding source / drain 112 (e.g., epitaxial source / drain) disposed in substrate 106, and transistors T1 and T2 each have a corresponding channel extending between the corresponding source / drain 112. Gate structure 110 may include a gate stack (e.g., a gate electrode disposed on a gate dielectric) and a gate spacer disposed along the sidewalls of the gate stack, and substrate 106 may be a semiconductor substrate (e.g., a silicon substrate). Device layer DL1 may also include an isolation structure 114, such as an STI structure, which separates and / or electrically isolates transistor T1 and / or transistor T2 from other transistors or devices in device layer DL1.

[0030] Device layer DL1 may also include insulating layers, such as dielectric layers 116 and 118, which may be similar to and fabricated similarly to the dielectric layers described herein. For example, dielectric layers 116 and 118 may have a multilayer structure. In some embodiments, dielectric layers 116 and 118 each include a respective interlayer dielectric (ILD) layer and / or a respective contact etch stop layer (CESL). Gate contact 122 is disposed in dielectric layers 118 and 116, source / drain contact 124 is disposed in dielectric layer 116, and source / drain via 126 is disposed in dielectric layer 118. In some embodiments, dielectric layer 116, dielectric layer 118, gate contact 122, source / drain contact 124, and source / drain via 126 form intermediate end process (MEOL) layer 130 and / or a portion thereof. Additional features may be added to device layer DL1 and / or device layer DL2, and some of the described features may be replaced, modified or eliminated in other embodiments of device layer DL1 and / or device layer DL2.

[0031] Return to reference Figure 1AChips 102 and 104 may each include a front-side multilayer interconnect (FMLI) structure, such as an FMLI-1 structure on the front side of substrate 106 and an FMLI-2 structure on the front side of substrate 108. Chips 102 and / or 104 may also each include a back-side multilayer interconnect (BMLI) structure, such as a BMLI-1 structure on the back side of substrate 106 and a BMLI-2 structure on the back side of substrate 108. Each of the FMLI-1, FMLI-2, BMLI-1, and BMLI-2 structures includes a dielectric layer (shown as insulating layer 140-1, insulating layer 140-2, insulating layer 140-1', and insulating layer 140-2', respectively) and a conductive layer (e.g., a patterned metal layer, each patterned metal layer being a set of metal lines, metal vias, metal contacts, or combinations thereof arranged in a desired pattern), which together form an interconnect (wiring) structure (i.e., an electrical connection). Interconnect structures may include vertically oriented conductive components, such as metal contacts and / or metal vias, that connect horizontally oriented conductive structures, such as metal wires, located in different levels / layers (or different planes) of the respective MLI structures. In some embodiments, the interconnect structure routes electrical signals between devices and / or components, external devices and / or components, or combinations thereof in device layers DL1, DL2, FMLI-1 structures, FMLI-2 structures, BMLI-1 structures, and BMLI-2 structures. In some embodiments, the interconnect structure distributes electrical signals (e.g., clock signals, voltage signals, ground signals, etc.) to devices and / or device components, external devices and / or components, or combinations thereof in device layers DL1, DL2, FMLI-1 structures, FMLI-2 structures, BMLI-1 structures, and BMLI-2 structures.

[0032] The FMLI-1 structure includes a device-level contact layer and / or via layer (collectively referred to as via zero layer (V0 level)), a metal zero layer (M0 level), a via one layer (V1 level), a metal one layer (M1 level), a via two layer (V2 level), a metal two layer (M2 level), and so on up to the via (X-1) layer (V(X-1) level), the metal (X-1) layer (M(X-1) level), the via X layer (VX level), and the metal X layer (MX level), where X is an integer (e.g., 2 to 10). Each layer of the FMLI-1 structure may include conductive components disposed in the insulating layer 140-1, such as metal lines 142 or metal vias 144. The metal lines 142 of the M0 level, M1 level, M2 level, ... M(X-1) level and MX level may be referred to as M0 lines, M1 lines, M2 lines, ... M(X-1) lines and MX lines. The metal vias 144 at the V0, V1, V2, ... V(X-1), and VX levels can be referred to as V0 vias, V1 vias, V2 vias, ... V(X-1), and VX vias. The metal vias 144 at the V0 level (i.e., device-level contact layers) may include source / drain contacts (e.g., source / drain contacts 124), source / drain vias (e.g., drain / source vias 126), gate vias (e.g., gate vias 122), or combinations thereof. The metal via 144 can electrically connect the lower metal line 142 (e.g., the corresponding M1 line) and the upper metal line 142 (e.g., the corresponding M2 line), the lower device-level contact (e.g., the source / drain contact) and the upper metal line 142 (e.g., the corresponding M0 line), or the lower device component (e.g., the gate and / or the source / drain) and the upper metal line 142 (e.g., the corresponding M0 line).

[0033] The FMLI-2 structure may be similar to the FMLI-1 structure. For example, the FMLI-2 structure includes corresponding V0 layers, corresponding M0 layers, corresponding V1 layers, corresponding M1 layers, corresponding V2 layers, corresponding M2 layers, and so on to via (Y-1) layers (V(Y-1) layers), metal (Y-1) layers (M(Y-1) layers), via Y layers (VY layers), and metal Y layers (MY layers), where Y is an integer (e.g., from 2 to 10). Y can be less than X, greater than X, or equal to X. Each layer of the FMLI-2 structure may include conductive components disposed in the insulating layer 140-2, such as metal wires 146 or metal vias 148. The metal wires 146 of the M0, M1, M2, ... M(Y-1) and MY layers may be referred to as M0 lines, M1 lines, M2 lines, ... M(Y-1) lines, and MY lines. Metal vias 148 at V0, V1, V2, ... V(Y-1) and VY levels can be referred to as V0 vias, V1 vias, V2 vias, ... V(Y-1) vias, and VY vias. Metal vias 148 can electrically connect a lower metal line 146 (e.g., the corresponding M1 line) to an upper metal line 46 (e.g., the corresponding M2 line), a lower device-level contact (e.g., a source / drain contact) to an upper metal line 146 (e.g., the corresponding M0 line), or a lower device component (e.g., a gate and / or source / drain) to an upper metal line 146 (e.g., the corresponding M0 line).

[0034] Gate contact 122 can electrically connect gate structure 110 (e.g., its gate stack) to FMLI-1 structure, and source / drain contact 124 and / or source / drain via 126 can electrically connect source / source 112 to FMLI-1 structure. Gate contacts of device layer DL2 can electrically connect its gate structure (e.g., gate stack) to FMLI-2 structure, and source / drain contacts and / or source / drain vias of device layer DL2 can connect their sources / drains to FMLI-2 structure. In some embodiments, gate contact 122, source / drain contact 124, and / or source / drain via 126 are electrically connected to FMLI-1 structure and / or form a portion of FMLI-1. For example, gate contact 122 and / or source / drain via 126 can form a portion of V0 layer, and gate contact 122 and / or source / drain via 126 are electrically connected to metal line 142 of M1 layer. In some embodiments, dielectric layers 116 and 118 form portions of insulating layer 140-1. In some embodiments, contacts may be disposed in dielectric layer 116 above a doped region in a portion of substrate 106 between transistors T1 and T2, and vias may be disposed in dielectric layer 118 above the contacts. Such contacts may be electrically connected to the doped region, and such vias may be electrically connected to and / or form portions of the FMLI-1 structure.

[0035] The BMLI-1 structure can be similar to the FMLI-1 structure. For example, the BMLI-1 structure may include a device-level contact layer and / or a device-level via layer (collectively referred to as via zero layer (BV0 level)), a metal zero layer (BM0 level), and so on down to the via BX' layer (BVX' level) and the metal BX' layer (BMX' level), where X' is an integer (e.g., from 1 to 10). X' can be less than X, greater than X, or equal to X. In some embodiments, X' equals 2, and the BMLI-1 structure may include BV0 level, BV1 level, BM1 level, BV2 level, and BM2 level. Each layer of the BMLI-1 structure may include conductive components, such as metal lines 142' or metal vias 144' disposed in the insulating layer 140-1' and / or the substrate 106. The metal lines 142' of the BM1 level and the BM2 level may be referred to as BM1 lines and BM2 lines, respectively. The metal vias 144' at the BV0, BV1, and BV2 levels can be referred to as BV0 vias, BV1 vias, and BV2 vias, respectively. In some embodiments, the BV0 vias (e.g., metal vias 144') at the BV0 level can be disposed in the substrate 106, electrically connecting the metal vias of the FMLI-1 structure (e.g., the metal vias 144 at its V0 level) to the BMLI-1 structure (e.g., the metal vias 144' at its BV1 level). In some embodiments, the metal vias 144' can electrically connect the lower metal line 142' (e.g., the corresponding BM1 line) and the upper metal line 142' (e.g., the corresponding BM2 line). In some embodiments, one or more metal lines 142' of the BMLI-1 structure can be power rails, which can be electrically connected to the transistors of the device layer DL1, for example, through a set of metal vias 144' and / or metal lines 142'. The BMLI-1 structure can have more or fewer layers / levels than depicted.

[0036] The BMLI-2 structure can be similar to the BMLI-1 structure. For example, the BMLI-2 structure may include corresponding BV0 layers, corresponding BM0 layers, corresponding BV1 layers, corresponding BM1 layers, corresponding BV2 layers, corresponding BM2 layers, and so on down to via (BY'-1) layers (V(BY'-1) level), metal (BY'-1) layers (M(BY'-1) level), via BVY' layers (BVY' level), and metal BY' layers (BMY' level), where Y' is an integer (e.g., 1 to 10). Y' can be less than, greater than, or equal to Y. Each layer of the BMLI-2 structure may include conductive components, such as metal lines 146' or metal vias 148' disposed in the insulating layers 140-2' and / or the substrate 108. Metal vias 148' can electrically connect lower metal lines 146' (e.g., corresponding BMO lines) and upper metal lines 146' (e.g., corresponding BMO lines), lower device-level contacts (e.g., source / drain contacts) and upper metal lines 146' (e.g., corresponding M0 lines), or lower device components (e.g., gate and / or source / drain) and upper metal lines 146' (e.g., corresponding M0 lines). In some embodiments, one or more metal lines 146' of the BMLI-2 structure can be power rails, which can be electrically connected to transistors in device layer DL2, for example, through a set of metal vias 148' and / or metal lines 146'. The BMLI-2 structure can have more or fewer layers / levels than depicted.

[0037] The device level (e.g., the bottom layer) of the FMLI-1 structure (e.g., V0 layer), FMLI-2 structure (e.g., V0 layer), BMLI-1 structure (e.g., BV0 layer), and BMLI-2 structure (e.g., BV0 layer) can be manufactured using intermediate-end process (MOL) technology, while the additional layers of the FMLI-1 structure (e.g., M0 layer and above), FMLI-2 structure (e.g., M0 layer and above), BMLI-1 structure (e.g., BM0 layer and above), and BMLI-2 structure (BM0 layer and above) can be manufactured using back-end process (BEOL) technology. Therefore, the V0 layer of chip 102 and chip 104 can be referred to as an MOL structure, and the M0 layer and above of chip 102 and chip 104 can be referred to as a BEOL structure. In some embodiments, the V0 layer and / or BV0 layer may include an MD layer formed by source / drain contacts and a VD / VG layer formed by source / drain vias and / or gate contacts. Furthermore, on the back side of device layer DL1, the BV0 level may include back-side source / drain contacts and / or back-side vias, both of which may extend into and / or through substrate 106. The back-side source / drain contacts and / or back-side vias may be disposed in electrically insulating portions of substrate 106, for example, in one or more back-side dielectric layers and / or their isolation structures. The back-side source / drain contacts can electrically connect the back side of the respective source / drain to the corresponding metal line 142' of the BMO level of the BMLI-1 structure. The back-side vias can electrically connect the corresponding metal line 142' of the BMO level of the BMLI-1 structure to the corresponding metal via 144 of the V0 level of the FMLI-1 structure.

[0038] Insulating layers 140-1, 140-1', 140-2, and 140-2' comprise electrically insulating materials. For example, insulating layers 140-1, 140-1', 140-2, and 140-2' comprise one or more dielectric materials, such as silicon oxide, tetraethyl orthosilicate (TEOS) oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), low-k dielectric materials (e.g., those with a dielectric constant less than that of silicon oxide (e.g., k < 3.9)), other suitable dielectric materials, or combinations thereof. Examples of low-k dielectric materials include fluorosilicate glass (FSG), carbon-doped oxides, xylene, aerogels, amorphous fluorinated carbon, parylene, polyimide, other low-k dielectric materials, or combinations thereof. In some embodiments, insulating layer 140-1, insulating layer 140-1', insulating layer 140-2, insulating layer 140-2', or a combination thereof comprises carbon-doped oxide and / or porous carbon-doped oxide (e.g., a very low-k dielectric material (e.g., k ≤ 2.5)).

[0039] In some embodiments, insulating layers 140-1, 140-1', 140-2, 140-2', or combinations thereof have a multilayer structure. For example, insulating layers 140-1, 140-1', 140-2, 140-2', or combinations thereof may each include at least one ILD layer, at least one CESL disposed between the corresponding ILD layers, and at least one CESL disposed between the corresponding ILD layer and the device substrate (e.g., substrate 106 and / or substrate 108). For example, refer to... Figure 3 Insulating layer 140-1 may include ILD layer 150 and CESL 152, and insulating layer 140-1' may include ILD layer 150' and CESL 152'. The composition of CESL 152 is different from that of ILD layer 150, and the composition of CESL 152' is different from that of ILD layer 150'. For example, ILD layer 150 and ILD layer 150' may include a low-k dielectric material comprising silicon and oxygen, and CESL 152 and CESL 152' may include silicon and nitrogen (e.g., silicon nitride, silicon oxynitride, silicon carbonitride, or combinations thereof) or other suitable dielectric materials (e.g., metal nitrides). ILD layer 150, ILD layer 150', CESL 152, CESL 152', or combinations thereof may have a multilayer structure and / or include multiple dielectric materials. In some embodiments, dielectric layer 116 and / or dielectric layer 118 form a portion of insulating layer 140-1.

[0040] In some embodiments, each layer of the FMLI-1 structure (e.g., a second layer including the M2 and V2 layers) may include a corresponding ILD layer 150 and / or a corresponding CESL 152 of the insulating layer 140-1, and corresponding metal lines 142 and metal vias 144 may be provided therein. In some embodiments, each layer of the BMLI-1 structure (e.g., a second layer including the BM2 and BV2 layers) may include a corresponding ILD layer 150' and / or a corresponding CESL 152' of the insulating layer 140-1', and corresponding metal lines 142' and metal vias 144' may be provided therein. In some embodiments, each layer of the FMLI-2 structure may include a corresponding ILD layer and / or a corresponding CESL of the insulating layer 140-2, and corresponding metal lines 146 and metal vias 148 may be provided therein. In some embodiments, each layer of the BMLI-2 structure may include a corresponding ILD layer and / or a corresponding CESL of the insulating layer 140-2', and corresponding metal lines 146' and metal vias 148' may be provided therein. In some embodiments, each of the M0 to MX layers in the FMLI-1 structure and / or the BMO to BMX' layers in the BMLI-1 structure may include a corresponding ILD layer and / or a corresponding CESL, and corresponding metal lines 142 and / or 142' may be provided therein. In some embodiments, each of the M0 to MY layers in the FMLI-2 structure and / or the BMO to BMY' layers in the BMLI-2 structure may include a corresponding ILD layer and / or a corresponding CESL, and corresponding metal lines 146 and / or 146' may be provided therein. In some embodiments, each of the V0 to VX layers in the FMLI-1 structure and / or the BV0 to BVX' layers in the BMLI-1 structure may include a corresponding ILD layer and / or a corresponding CESL, and corresponding metal vias 144 and / or 144' may be provided therein. In some embodiments, each of the V0 to VY layers of the FMLI-2 structure and / or the BV0 to BVY' layers of the BMLI-2 structure may include a corresponding ILD layer and / or a corresponding CESL, and a corresponding metal via 148 and / or a corresponding metal via 148' may be provided therein.

[0041] Metal line 142, metal via 144, metal line 142', metal via 144', metal line 146, metal via 148, metal line 146', metal via 148', source / drain contact (e.g., source / drain contact 124), source / drain via (e.g., source / drain via 126), gate contact (e.g., gate contact 122), or combinations thereof comprise conductive materials, which may include aluminum, copper, titanium, tantalum, tungsten, ruthenium, cobalt, iridium, palladium, platinum, nickel, tin, gold, silver, other suitable metals, alloys thereof, silicides thereof, or combinations thereof. In some embodiments, metal line 142, metal via 144, metal line 142', metal via 144', metal line 146, metal via 148, metal line 146', metal via 148', source / drain contact, source / drain via, gate contact, or combinations thereof comprise a bulk metal layer (also referred to as a metal filler layer, conductive plug, metal plug, etc.). In some embodiments, metal line 142, metal via 144, metal line 142', metal via 144', metal line 146, metal via 148, metal line 146', metal via 148', source / drain contact, source / drain via, gate contact, or combinations thereof comprise a barrier layer, adhesive layer, other suitable layer, or combination thereof disposed between the bulk metal layer and the corresponding insulating layer. The barrier layer may include titanium, titanium alloys (e.g., TiN), tantalum, tantalum alloys (e.g., TaN), other suitable barrier materials (e.g., materials that can prevent metallic components from diffusing from the bulk metal layer into the surrounding dielectric) or combinations thereof. In some embodiments, metal lines 142, metal vias 144, metal lines 142', metal vias 144', metal lines 146, metal vias 148, metal lines 146', metal vias 148', source / drain contacts, source / drain vias, gate contacts, or combinations thereof comprise different metallic materials. For example, the lower metal lines 142, metal vias 144, metal lines 142', metal vias 144', or combinations thereof closer to device layer DL1 may comprise tungsten, ruthenium, cobalt, or combinations thereof, while the upper metal lines 142, metal vias 144', metal lines 142', and metal vias 144' further away from device layer DL1 may comprise copper. In another example, the lower metal line 146, metal via 148, metal line 146', metal via 148', or combinations thereof closer to device layer DL2 may include tungsten, ruthenium, cobalt, or combinations thereof, while the upper metal line 146, metal via 148, metal line 146', metal via 148', or combinations thereof further away from device layer DL2 may include copper. In some embodiments, the metal line 142, metal via 144, metal line 142', metal via 144', metal line 146, metal via 148, metal line 146', metal via 148', source / drain contact, source / drain via, gate contact, or combinations thereof comprise the same metallic material.

[0042] A carrier substrate (wafer) 158 may be attached (bonded) to the front side of chip 104. In the depicted embodiment, the FMLI-2 structure is attached to the carrier substrate 158, for example, via a bonding / adhesion structure. The bonding / adhesion structure may include any suitable material (e.g., oxide) that facilitates bonding / adhesion of the carrier substrate 158 to the insulating layer 140-2 and / or metal lines 146 of the FMLI-2 structure. In some embodiments, the carrier substrate 158 comprises bulk silicon (e.g., the carrier substrate 156 may be a silicon substrate). In some embodiments, the carrier substrate 158 includes additional suitable material that provides sufficient rigidity and / or mechanical support for chip 104 and / or the stacked chip structure 100.

[0043] In the depicted embodiments, chips 102 and 104 are stacked and attached (bonded) in a front-to-back and / or face-to-back manner. For example, chip 102 has a front side FS1 formed of an FMLI-1 structure and a back side BS1 formed of a BMLI-1 structure, and chip 104 has a front side FS2 formed of an FMLI-2 structure and a back side BS2 formed of a BMLI-2 structure, with the FMLI-1 structure attached (bonded) to the BMLI-2 structure. The face-to-back bonding of chips 102 and 104 can be achieved through dielectric-to-dielectric bonding (e.g., oxide-to-oxide bonding), metal-to-metal bonding (e.g., copper-to-copper bonding), metal-to-dielectric bonding (e.g., copper-to-oxide bonding), other types of bonding, or combinations thereof. In some embodiments, chip 102 is mounted on chip 104 using hybrid bonding (i.e., using metal-to-metal bonding and non-metal-to-non-metal bonding), and chip 104 can be electrically connected to chip 102 via hybrid bonding, for example, through bonding / interconnection structure 160. For example, chip 102 and chip 104 may each include a non-metallic portion (e.g., bonding layer 162-1 and bonding layer 162-2, respectively) and a metallic portion (e.g., bonding pad 164-1 and bonding pad 164-2, respectively, also referred to as bonding pad metal (BPM)). The non-metallic portion of chip 102 may be bonded to the non-metallic portion of chip 104, and the metallic portion of chip 102 may be bonded to the metallic portion of chip 104. In some embodiments, bonding pad 164-1 is disposed in bonding layer 162-1, bonding pad 164-2 is disposed in bonding layer 162-2, bonding pad 164-1 may be bonded to bonding pad 164-2, and bonding layer 162-1 may be bonded to bonding layer 162-2. In some embodiments, as shown, bonding pad 164-1 may partially overlap with bonding pad 164-2 and partially overlap with bonding layer 162-2, and bonding pad 164-2 may partially overlap with bonding layer 162-2. The ground plane overlaps with and partially overlaps with the bonding pad 164-1 and the bonding layer 162-1. In some embodiments, chip 102 may include a bonding layer 166-1 and a bonding via 168-1 (also referred to as a bonding pad via (BPV)) disposed therein, and chip 104 may also include a bonding layer 166-2 and a bonding via 168-2 disposed therein. The bonding via 168-1 may be connected to the bonding pad 164-1, and the bonding via 168-2 may be connected to the bonding pad 164-2. In some embodiments, bonding layers 162-1, 162-2, 166-1, 166-2, or combinations thereof are polymer layers, which may include benzocyclobutene (BCB), polyimide (PI), polybenzoxazole (PBO), other polymer materials, or combinations thereof. In some embodiments, bonding layers 162-1, 162-2, 166-1, 166-2, or combinations thereof are dielectric layers.In some embodiments, bonding pads 164-1, 164-2, 168-1, 168-2, or combinations thereof comprise copper, aluminum, other suitable metals, alloys thereof, or combinations thereof. In some embodiments, bonding layers 162-1, 162-2, 166-1, 166-2, 164-1, 164-2, 168-1, 168-2, or combinations thereof have a multilayer structure.

[0044] Chip 102 and / or chip 104 may include additional structures facilitating connection thereto. For example, in the depicted embodiments, chip 102 may also include a top contact structure (and / or layer), such as a TC-1 structure, and a bottom contact structure (and / or layer), such as a BC-1 structure. The TC-1 structure may be disposed on the front side of device layer DL1, such as on top of FMLI-1 structure, and the BC-1 structure may be disposed on the back side of device layer DL1, such as on BMLI-1 structure. In some embodiments, the TC-1 structure is disposed on the topmost level / layer (i.e., its MX level) of FMLI-1 structure, and the BC-1 structure is disposed on the bottommost level / layer (i.e., its BMX' level) of BMLI-1 structure. The TC-1 structure includes an insulating layer 170-1 and conductive components, such as metal lines 172 and metal vias 174, arranged therein in a desired pattern. The BC-1 structure includes an insulating layer 170-1' and conductive components, such as metal lines 172' and metal vias, arranged in the insulating layer 170-1' in a desired pattern. In some embodiments, insulating layer 170-1 is a passivation layer, which may be formed of a material different from that of insulating layer 140-1 (e.g., its ILD layer). In some embodiments, insulating layer 170-1' is a passivation layer, which may be formed of a material different from that of insulating layer 140-1' (e.g., its ILD layer). In some embodiments, the dielectric constant of insulating layer 170-1 is greater than the dielectric constant of the topmost dielectric layer (e.g., the ILD layer) of the FMLI-1 structure, and insulating layer 170-1 may be formed and / or disposed on this layer. In some embodiments, the dielectric constant of insulating layer 170-1' is greater than the dielectric constant of the topmost dielectric layer (e.g., one of the ILD layers) of the BMLI-1 structure, and insulating layer 170-1' may be formed and / or disposed on this layer.

[0045] Insulating layers 170-1 and 170-1' comprise electrically insulating materials, such as polyimide, undoped silicate glass (USG), BCB, polybenzoxazole, silicon oxynitride, silicon nitride, silicon oxide, epoxy resin, other suitable insulating materials, or combinations thereof. For example, insulating layer 170-1 and / or insulating layer 170-1' may be a polyimide layer. In some embodiments, insulating layer 170-1 and / or insulating layer 170-1' has a multilayer structure and may comprise a variety of electrically insulating materials. For example, refer to... Figure 3 Insulating layer 170-1 may include insulating layers 170-1a, 170-1b, and 170-1c, and insulating layer 170-1' may include insulating layers 170-1'a, 170-1'b, and 170-1'c. Insulating layers 170-1a, 170-1b, and 170-1c may have the same or different compositions. In some embodiments, insulating layer 170-1c is a USG layer, insulating layer 170-1b is a silicon nitride layer, and insulating layer 170-1a is a dielectric layer having a different composition from insulating layers 170-1b and 170-1c, such as a hydrogen- and nitrogen-doped carbide layer. Insulating layers 170-1'a, 170-1'b, and 170-1'c may have the same or different compositions. In some embodiments, insulating layer 170-1'c is a USG layer, insulating layer 170-1'b is a silicon nitride layer, and insulating layer 170-1'a is a USG layer. In some embodiments, insulating layers 170-1a, 170-1b, 170-1c, 170-1'a, 170-1'b, and 170-1'c, or a combination thereof, are ESL.

[0046] In some embodiments, chip 102 may include a redistribution layer (RDL) structure, such as an RDL-1 structure, and / or chip 104 may include an RDL structure, such as an RDL-2 structure. The RDL-1 and RDL-2 structures electrically connect chip 102 and / or chip 104 (e.g., their components and / or devices, such as transistors) to external circuitry and / or external devices. For example, the RDL-2 structure may electrically connect chip 104 to chip 102 (e.g., a BMLI-2 structure connected to an FMLI-1 structure), and the RDL-1 structure may electrically connect chip 102 and / or the stacked chip structure 100 to external circuitry / devices. In some embodiments, the RDL-1 and / or RDL-2 structures redistribute the connection layout between devices and / or components of chip 102 and / or chip 104 to facilitate signal transmission and / or power transmission. In some embodiments, the RDL-1 structure and / or the RDL-2 structure redistribute the pads to different locations, for example, from peripheral locations to a uniform distribution on the surface of the stacked chip structure 100 (and / or its chip 102).

[0047] The RDL-1 structure includes an insulating layer 180-1 and conductive components, such as metal wires 182 and metal vias 184, arranged in a desired pattern within the insulating layer 180-1. The RDL-2 structure includes an insulating layer 180-2 and conductive components, such as metal wires 186 and metal vias 188, arranged therein in a desired pattern. Insulating layers 180-1 and 180-2 comprise electrically insulating materials, such as polyimide, USG, BCB, polybenzoxazole, silicon oxynitride, silicon nitride, silicon oxide, epoxy resin, other suitable insulating materials, or combinations thereof. In some embodiments, insulating layers 180-1 and / or 180-2 have a multilayer structure and may comprise various electrically insulating materials. Metal wire 172, metal via 174, metal wire 172', metal wire 182, metal via 184, metal wire 186, metal via 188, or combinations thereof comprise a conductive material, which may include aluminum, copper, titanium, tantalum, tungsten, ruthenium, cobalt, iridium, palladium, platinum, nickel, tin, gold, silver, other suitable metals, alloys thereof, silicides thereof, or combinations thereof. In some embodiments, metal wire 172, metal via 174, metal wire 172', metal wire 182, metal via 184, metal wire 186, metal via 188, or combinations thereof comprise a bulk metal layer. In some embodiments, metal wire 172, metal via 174, metal wire 172', metal wire 182, metal via 184, metal wire 186, metal via 188, or combinations thereof comprise a barrier layer, adhesive layer, other suitable layer, or combinations thereof disposed between the bulk metal layer and a corresponding insulating layer. The barrier layer may include titanium, titanium alloys (e.g., TiN), tantalum, tantalum alloys (e.g., TaN), other suitable barrier materials (e.g., materials that can prevent metallic components from diffusing from the bulk metal layer into the surrounding dielectric) or combinations thereof. Metal lines 172, metal vias 174, 172', 182, 184, 186, and 188 may include the same or different metallic materials.

[0048] In some embodiments, the stacked chip structure 100 includes a bump structure. For example, a bump structure may be formed on chip 102 (e.g., on its back side BS1), and the bump structure may electrically connect chip 102 and / or chip 104 to a power source. The bump structure may include an insulating layer 192 and a connector 194 disposed therein. In the depicted embodiment, the insulating layer 192 and the connector 194 are disposed on an RDL-1 structure, and the connector 194 is electrically connected to the RDL-1 structure (e.g., its metalline 182). The insulating layer 192 may include an electrically insulating material, such as the materials described herein. In some embodiments, the insulating layer 192 is a passivation layer. The connector 194 may include a corresponding under-bump metallization (UBM) pillar structure and a corresponding solder bump / cap. For example, the connector 194 may include a UBM pillar structure 195 and a bump 196. The UBM pillar structure 195 and the bump 196 may include a conductive material, such as the materials described herein. In some embodiments, connector 194 may be formed as a controlled collapse chip connection bump (C4 bump), ball grid array (BGA) bump, pad grid array (LGA) bump, pin grid array (PGA) bump, or microbump, etc.

[0049] The stacked chip structure 100 may also include a sealant 198 (also referred to as a molding compound, molding agent, and / or silicon oxide-based compound). Chips 102 and 104, and corresponding bonding and / or interconnect structures (e.g., bonding / interconnect structure 160, TC-1 structure, BC-1 structure, RDL-1 structure, RDL-2 structure, bump structures thereon, etc.) may be disposed in and / or covered by the sealant 198. For example, the sealant 198 may circumferentially surround chips 102 and / or 104. In some embodiments, the sealant 198 is disposed on the edges / sidewalls of chips 102 and / or 104. In some embodiments, the sealant 198 comprises organic materials, such as epoxy-based materials, and / or gap-filling materials (e.g., organic materials), such as oxide-based materials.

[0050] Reference Figure 1A , Figure 3 and Figure 4Chip 102 also includes one or more through-substrate vias (TSVs) 200 (also referred to as through-silicon vias or through-semiconductor vias). In the depicted embodiment, the TSV 200 extends from a corresponding metal line 172' of the BC-1 structure, through insulating layers 170-1', 140-1', device layer DL1 (including its substrate 106), and insulating layer 140-1, to a corresponding metal line 142 (e.g., its MX level) of the FMLI-1 structure. The TSV 200 has a dimension D, such as width or diameter, along the x and / or y directions, and a height H1 along the z direction. In some embodiments, the dimension D is substantially the same along the height H1. In some embodiments, the dimension D varies along the height H1. For example, the TSV 200 may have tapered sidewalls as shown, such that the dimension D decreases from the top of the TSV 200 (the corresponding one of the adjacent metal lines 172') to the bottom of the TSV 200 (the corresponding one of the adjacent metal lines 142). This disclosure envisions that the TSV 200 has any variation in dimension D along height H1 depending on its sidewall configuration.

[0051] The TSV 200 can have a circular shape in a top view, such as... Figure 4 and Figure 7A As shown. In such an embodiment, the TSV 200 can be a cylindrical structure, and the dimension D can be the diameter of the TSV 200. In some embodiments, the TSV 200 has different shapes in a top view, such as Figures 7B-7G As shown. For example, the TSV 200 can be square ( Figure 7B ),rectangle( Figure 7C ), rhombus, trapezoid, polygon, ellipse ( Figure 7D ),diamond( Figure 7E ),hexagon( Figure 7F ), octagon ( Figure 7G ), other suitable shapes or combinations thereof.

[0052] TSV 200 includes a conductive material, which may include aluminum, copper, titanium, tantalum, tungsten, ruthenium, cobalt, iridium, palladium, platinum, nickel, tin, gold, silver, other suitable metals, alloys thereof, silicides thereof, or combinations thereof. In some embodiments, such as Figure 3As shown, the TSV200 includes a conductive plug 202 (also referred to as a bulk metal layer, metal filler layer, metal plug, etc.) and a barrier layer 204. The barrier layer 204 is disposed between the conductive plug 202 and insulating layers 140-1, 140-1', and substrate 106 (e.g., its insulating portion). The barrier layer 204 may include titanium, titanium alloys (e.g., TiN), tantalum, tantalum alloys (e.g., TaN), other suitable barrier layer components and / or materials (e.g., materials that can prevent and / or reduce the diffusion of metal components (e.g., copper) from the TSV 200 into insulating layers 140-1, 140-1', and substrate 106), or combinations thereof. In some embodiments, the conductive plug 202 is a copper plug or a tungsten plug, and the barrier layer 204 is a metal nitride layer (e.g., a TaN layer and / or a TiN layer). In some embodiments, the conductive plug 202 is a polysilicon plug. In some embodiments, the conductive plug 202 and / or the barrier layer 204 have a multilayer structure. For example, the conductive plug 202 may include a bulk metal layer and a seed layer, the seed layer being disposed between the barrier layer 204 and the bulk metal layer. The seed layer may include copper, tungsten, other suitable metals (such as those described herein), alloys thereof, or combinations thereof.

[0053] In some embodiments, refer to Figure 6 An insulating pad 206 (e.g., a dielectric pad) is located between the TSV 200 and insulating layers 140-1, 140-1', and substrate 106 (e.g., its insulating portion). For example, the insulating pad 206 may be disposed along the sidewalls of the TSV 200 (e.g., sidewalls formed by barrier layer 204 and / or conductive plug 202), but not along the bottom of the TSV 200, such that the insulating pad 206 is located between the sidewalls of the TSV 200 and insulating layers 140-1, 140-1', and substrate 106. The insulating pad 206 comprises silicon oxide, silicon nitride, silicon carbide, other suitable dielectric materials, or combinations thereof. In some embodiments, the insulating pad 206 has a multilayer structure, such as a silicon nitride layer (e.g., a Si3N4 layer) and a silicon carbide layer (e.g., a SiC layer). The insulating pad 206 is formed by atomic layer deposition (ALD), chemical vapor deposition (CVD), thermal oxidation (e.g., in a dry oxygen environment), other suitable processes, or combinations thereof. Bonding the insulating pad 206 between the TSV 200 and its surrounding materials (e.g., insulating layer 140-1, insulating layer 140-1', and substrate 106) can improve the electrical insulation of the TSV 200 from nearby conductive structures / components (e.g., metal lines 142, metal lines 142', metal vias 144, metal vias 144', etc.), reducing capacitance, etc.

[0054] Refer again Figure 3The TSV 220 abuts the corresponding metal line 142 (e.g., at the MX layer) to facilitate electrical connections with chip 102 (e.g., its transistor in device layer DL1) and / or chip 104 (e.g., its transistor in device layer DL2). In some embodiments, the TSV 220 may extend and / or pass through its corresponding metal landing pad, rather than stopping at the metal line 142 (e.g., at the MX layer). For example, the end of the TSV 220 may include a contact via 210 extending to and / or passing through the corresponding metal line 142. In the depicted embodiment, the contact via 210 (which may be formed by conductive plug 202 and / or barrier layer 204) extends beyond its corresponding metal line 142 and into the insulating layer 170-1 of the TC-1 structure. In some embodiments, as Figure 5 As shown, metal landing pads (e.g., metal lines 142 of the MX layer (i.e., MX lines)) can be patterned to include contact via openings, such as contact via opening 142O, for forming contact vias 210. This disclosure contemplates TSV 220 having any number of contact vias 210; therefore, MX lines can be patterned as any number of contact via openings 142O. For example, refer to... Figure 9A and Figure 9B One or more TSVs 220 may include two contact vias 210 and a metal line 142, on which the metal line 142 is patterned to include two contact via openings 1420. In some embodiments, one or more TSVs 220 may include one to ten contact vias 210, thus any TSV 220 pad on the metal line 142 is patterned to include one to ten contact via openings 1420. For example, refer to... Figure 10One or more TSVs 220 may include four contact vias 210 and a metal wire 142 on which the TSV 220 rests, the metal wire 142 being patterned to include four contact via openings 1420. Forming the contact via openings 1420 concurrently with the fabrication of the metal wire 142 (i.e., during the fabrication of the FMLI-1 structure) can reduce and / or prevent stress-induced contact via overlay problems. For example, a higher metal density typically results in greater localized residual stress, which can cause localized warping and / or bending of the metal wire 142 and / or itself, thus reducing overlay accuracy. Therefore, inserting the contact via openings 1420 into the metal wire 142 can improve overlay accuracy by reducing the metal density of the metal wire 142. Furthermore, implementing multiple contact vias 210 can reduce overall contact resistance. In some embodiments, the contact resistance associated with each contact via 210 can be from about 0.01 Ω to about 0.05 Ω. In some embodiments, providing contact vias 210 (e.g., one to ten) for the TSV 220 can reduce contact resistance by about 5%. In some embodiments, the metal wire 142 is further patterned to include a pseudo-contact via opening 142o, such as Figure 10 As shown, this can further reduce its metal density and improve coverage. The pseudo-contact via opening 142o can then be filled with an insulating material, such as the insulating material of insulating layer 140-1 and / or the subsequently formed insulating layer 170-1.

[0055] Reference Figure 1A , Figure 3 and Figure 4 The chip 102 also includes one or more guard ring structures 220. In the depicted embodiment, the guard ring structure 220 extends through the insulating layer 140-1', through the device layer DL1 (including its substrate 106), and through the insulating layer 140-1, and the guard ring structure 220 extends from the insulating layer 170-1' of the BC-1 structure to the corresponding metal line 142 (e.g., its MX level) of the FMLI-1 structure. The guard ring structure 220 is spaced apart from and surrounds one or more TSVs 200, and the insulating layers 140-1, 140-1', and substrate 106 (e.g., its insulating portion) may fill the gap between the guard ring structure 200 and the corresponding TSV 200. In some embodiments, each TSV 200 has a corresponding guard ring structure 220. For example, refer to Figure 3 and Figure 4The protective ring structure 220 is spaced apart from and surrounds the corresponding TSV 200. Insulating layers 140-1, 140-1', and the substrate 106 (e.g., its insulating portion) can fill the gap between the protective ring structure 200 and the corresponding TSV 200. The height H2 of the protective ring structure 220 (e.g., along the z-direction) is less than the height H1 of the TSV 200. In a top plan view, the protective ring structure 220 can be square, providing a square ring around the TSV 200, such as... Figure 4 and Figure 8B As shown, in the illustrated embodiment, the protective ring structure 220 has a top profile with a different shape than its corresponding TSV 200. In some embodiments, the protective ring structure 220 has different shapes in the top view, such as... Figure 8A and Figures 8C-8G As shown. For example, the protective ring structure 220 can be a circular ring ( Figure 8A ), rectangular ring ( Figure 8C ), rhomboid ring, trapezoidal ring, polygonal ring, elliptical ring ( Figure 8D ), rhombus ring ( Figure 8E ), hexagonal ring ( Figure 8F ), octagonal ring ( Figure 8G ( ), other suitable ring shapes, or combinations thereof. In some embodiments, viewed from a top view, the protective ring structure 220 and its corresponding TSV 200 have the same shape (e.g., both may have a circular outline when viewed from above). In the depicted embodiments, viewed from a top view, the protective ring structure 220 extends continuously around its corresponding TSV 200. In some embodiments, the protective ring structure 220 is discontinuous around its corresponding TSV 200. For example, the protective ring structure 220 may be formed of discrete segments that combine together to form a ring around its corresponding TSV 200.

[0056] In some embodiments, the guard ring structure 220 is electrically connected to a voltage. In some embodiments, the guard ring structure 220 is electrically connected to an electrical ground. In some embodiments, the guard ring structure 220 is configured to spatially and / or electrically insulate / isolate its respective TSV 200 from the FMLI-1 structure (e.g., its metal line 142 and / or metal via 144), the BMLI-1 structure (e.g., its metal line 142' and / or metal via 144'), the device layer DL1 (e.g., substrate 106 and / or its devices), other features / components, or combinations thereof. In some embodiments, the guard ring structure 220 absorbs and / or reduces thermal and / or mechanical stresses from the TSV 200, the interior of the TSV 200, and / or the surrounding area of ​​the TSV 200. Such stresses may be caused by the different coefficients of thermal expansion (CTE) of the TSV 200, the device layer DL1 (e.g., its substrate 106), the FMLI-1 structure (e.g., its insulating layer 140-1), and the BMLI-1 structure (e.g., its insulating layer 140-1'). This stress may occur during and / or after the manufacture of the TSV 200. In some embodiments, the guard ring structure 220 provides structural support, integrity, reinforcement, or a combination thereof for the TSV 200. In some embodiments, the guard ring structure 220 is electrically connected to the substrate 106, for example, to a doped region therein (e.g., an n-well and / or a p-well).

[0057] One or more protective ring structures 220, for example Figure 3 and Figure 4 The guard ring structure 200 shown has a dual guard ring (DGR) structure. For example, the guard ring structure 220 includes a main guard ring 220A (also referred to as the main guard ring segment) and a secondary guard ring 220B (also referred to as the secondary guard ring segment). The main guard ring 220A is disposed in the insulating layer 140-1', the device layer DL1, and the insulating layer 140-1, and extends through the insulating layer 140-1. The secondary guard ring 220B is disposed in the insulating layer 140-1 and extends through the insulating layer 140-1. In some embodiments, from a top view ( Figure 4 As observed, the main protective ring 220A and the secondary protective ring 220B extend continuously around the TSV 200, and the main protective ring 220A and the secondary protective ring 220B have the same shape. For example, both are square rings. In some embodiments, when viewed from a top view (or bottom view), the main protective ring 220A and the secondary protective ring 220B may have different shaped profiles.

[0058] The main protective ring 220A and the secondary protective ring 220B can be manufactured together with the FMLI-1 structure and the BMLI-1 structure. The main protective ring 220A and the secondary protective ring 220B can be regarded as part of and / or formed by FMLI-1 and / or BMLI-1. For example, the main protective ring 220A and the secondary protective ring 220B can be formed by metal wire 142 and metal through hole 144, which can correspond to the various levels of the FMLI-1 structure, and / or formed by metal wire 142' and metal through hole 144', which can correspond to the various levels in the BMLI-1 structure. In the depicted embodiment, the main guard ring segment 220A extends from the BM2 level to the BV0 level, passes through the device layer DL1, and extends from the V0 level to the M0 level. The main guard ring 220A includes a front-side interconnect stack disposed in and extending through the insulating layer 140-1, a back-side interconnect stack disposed in and extending through the insulating layer 140-1', and a device-level interconnect structure disposed in and extending through the device layer DL1. To further implement the depicted embodiment, the secondary guard ring segment 220B extends from the M(X-1) level to the VX level. The secondary guard ring segment 220B includes a front-side interconnect stack disposed in and extending through the insulating layer 140-1. Each interconnect structure in the front-side interconnect stack may include a corresponding metal line 142 and a corresponding metal via 144, and each interconnect structure in the back-side interconnect stack may include a corresponding metal line 142' and a corresponding metal via 144'. In some embodiments, the interconnect structure of the device-level interconnect structure may be formed by metal vias 144 and / or 144' at the V0 level and / or BVO level, respectively, which may be disposed in and / or extend through the substrate 106. In some embodiments, the interconnect structure of the device-level interconnect structure may include conductive components (e.g., vias) that connect the corresponding metal vias 144 at the V0 level and the corresponding metal vias 144' at the BVO level. The front-side interconnect stack and / or the back-side interconnect stack may have more or fewer interconnect structures, and the number of interconnect structures in the front-side interconnect stack and / or the back-side interconnect stack may be greater than, less than, or equal to the number of FMLI-1 structures and the number of BMLI-1 structures, respectively.

[0059] The main guard ring 220A overlaps with the sidewalls of the TSV 220 in the BMLI-1 structure, the FMLI-1 structure, and the device layer DL1. Therefore, the main guard ring 220A is disposed between the sidewalls of the TSV 200 and the metal lines 142' / metal vias 144' of the BMLI-1 structure, the metal lines 142 / metal vias 144 of the FMLI-1 structure, and the devices in the device layer DL1. The main guard ring 220A has a height h1 (e.g., along the z-direction), and the height h1 is less than the height H2. Since the main guard ring 220A is configured to provide most of the spatial and / or electrical isolation provided by the guard ring structure 220 to the TSV 200, the height h1 is at least 50% of the height H2 (i.e., h1 ≥ 0.5 × H2). In some embodiments, the height h1 is about 75% to about 95% of the height H2 (i.e., 0.95 × H2 ≥ h1 ≥ 0.75 × H2). Furthermore, since height h1 is less than height H2, the main guard ring 220A includes a gap 222 along height H2 (the total height of the guard ring structure). In the depicted embodiment, the gap 222 is located between the end of the main guard ring 220A (e.g., its bottom formed by metal lines 142 of the M(X-1) level) and the metal landing pads of the TSV 200 (e.g., the corresponding metal lines 142 of the MX level). The height h2 of the gap 222 is less than height h1, and the sum of height h1 and height h2 is equal to height H2. In some embodiments, height h2 is about 5% to about 25% of height H2 (i.e., 0.25 × H2 ≥ h2 ≥ 0.05 × H2).

[0060] The gap 222 corresponds to the portion of the sidewall of the TSV 200 that does not overlap with the main protective ring 220A. For example, in Figure 3In this design, gap 222 is located at the VX level, such that the main guard ring 220A is not located between the metal via 144 of the VX level of the FMLI-1 structure and the sidewall portion of the TSV 200 disposed therein. Since the guard ring structure 220 is typically manufactured prior to the TSV 200 (e.g., together with the FMLI-1 and BMLI-1 structures), this disclosure recognizes that gap 222 can pose challenges to TSV manufacturing. For example, TSV manufacturing may include performing an etching process to remove portions of the insulating layer 140-1 to form TSV openings that expose the metal landing pads of the TSV 200 (e.g., the corresponding metal lines 142 of the MX level). During the etching process, moisture from the surrounding environment may be introduced into the TSV openings and undesirably diffuse into and interact with the insulating layer 140-1 (e.g., its ILD layer 150 and / or CESL 152) and / or the metal lines 142 / metal vias 144 of the FMLI-1 structure disposed therein. This disclosure recognizes that such moisture can diffuse and / or migrate from the TSV opening through gap 222, thereby attacking the low-k dielectric material (e.g., ILD layer 150) and / or metallic material (e.g., the barrier layer / pad of metal line 142 and / or metal via 144) of the FMLI-1 structure. In some cases, moisture may degrade the barrier layer / pad of metal line 142 and / or metal via 144, such as the barrier layer and pad of the metal landing pad of TSV200, which may lead to the formation of metallic nodules (e.g., copper nodules). Such degradation of the low-k dielectric material and / or metallic material may reduce the reliability and / or performance of the device. For example, damage to the barrier layer / pad of metal line 142 / metal via 144 may result in undesirable electromigration and / or insufficient time-related dielectric breakdown characteristics in the associated device.

[0061] To address these challenges, this disclosure provides a dual-protection ring structure comprising a primary protection ring and a secondary protection ring overlapping any gap in the primary protection ring. For example, in Figure 3In this structure, the secondary protective ring 220B is configured to overlap with the gap 222 of the primary protective ring 220A, such that the protective ring structure 220 overlaps with the sidewall of the TSV 200 along the entire height (i.e., height H2) of the protective ring structure 200. Therefore, in the FMLI-1 structure, the secondary protective ring 220B overlaps with the portion of the sidewall of the TSV 200 that does not overlap with the primary protective ring 220A. The secondary protective ring 220B is disposed between the sidewall of the TSV 200 and the metal through-hole 144 of the VX layer, and the secondary protective ring 220B can prevent moisture from diffusing and / or migrating into the FMLI-1 structure during the manufacturing process of the TSV 200 (e.g., through the gap 222 of the VX layer). The secondary protective ring 220B has a height h3 (e.g., along the z-direction), and the height h3 is less than the height H2. Since the secondary protective ring 220B is configured to "block" any gaps in the primary protective ring 220A (thus preventing moisture from diffusing outward and / or migrating through gap 222), the height h3 is at least equal to the height h2 (i.e., h3 ≥ h2), and the sum of height h3 and height h1 is at least equal to the height H2 (i.e., (h3 + h1) ≥ H2). In the depicted embodiment, height h3 is greater than height h2 to ensure sufficient overlap and / or "blocking" of gap 222, and the sum of height h3 and height h1 is greater than height H2 (i.e., (h3 + h1) > H2). In such an embodiment, the secondary protective ring 220B overlaps with the primary protective ring 220A, for example, in a portion of the M(X-1) layer, and the secondary protective ring 220B is also disposed between the sidewall of the TSV 200 and the metal wire 142 of the M(X-1) layer in the FMLI-1 structure. In some embodiments, height h3 is less than 50% of height H2, for example, about 10% to about 35% of height H2 (i.e., 0.35 × H2 ≥ h3 ≥ 0.10 × H2). Furthermore, since height h3 is less than height H2, the secondary guard ring 220B also includes a gap 224 along height H2. The gap 224 (of the secondary guard ring 220B) does not overlap with the gap 222 (of the primary guard ring 220A) to ensure sidewall coverage of the TSV 200. In the depicted embodiment, the gap 224 is located between the end of the secondary guard ring 220B (e.g., its top formed by metal wire 142 in the M(X-1) layer) and the top of the BMLI-1 structure (e.g., its top formed by the BM2 layer). The height of the gap 224 is less than height h1, and the sum of height h3 and the height of the gap 224 (e.g., along the z-direction) may be equal to height H2.

[0062] The secondary protective ring 220B is separate and independent from the primary protective ring 220A. In other words, although the secondary protective ring 220B may overlap with the primary protective ring 220A, it is not connected to the primary protective ring 220A. Instead, the secondary protective ring 220B is laterally positioned near the primary protective ring 220A, and a gap S (e.g., along the x and / or y directions) exists between the secondary protective ring 220B and the primary protective ring 220A. In some embodiments, the gap between protective rings (i.e., the gap S) is approximately 0.5 to 5 times the width of the metal wire 142 / metal wire 142' of the secondary protective ring 220B and / or the primary protective ring 220A. For example, the metal wire 142 / metal wire 142' of the primary protective ring 220A may have a width W1, and the gap S may be approximately 50% to approximately 500% of the width W1 (i.e., 5 × W1 ≥ S ≥ 0.50 × W1). In another example, the metal wire 142 / metal wire 142' of the secondary protective ring 220B may have a width W2, and the spacing S may be approximately 50% to approximately 500% of the width W2 (i.e., 5 × W2 ≥ S ≥ 0.50 × W2). In some embodiments, the width W1 is different from the width W2. In some embodiments, the width W1 is the same as the width W2. In some embodiments, as shown, no other metal components (e.g., metal wire 142 and / or metal through-hole 144) are provided between the secondary protective ring 220B and the main protective ring 220A.

[0063] Therefore, by using separate and independent guard ring segments (i.e., secondary guard ring 220B and primary guard ring 220A), instead of implementing a single guard ring extending to the TSV landing pad (e.g., primary guard ring 220V), the guard ring structure 220 overlaps the sidewall of the TSV 200 along the entire height (i.e., height H2) of the guard ring structure 200 (e.g., configuring height h1 to be equal to height H2 such that a single primary guard ring does not include any gaps along height H2). While attaching a single primary guard ring to the TSV landing pad can prevent moisture penetration, this disclosure recognizes that attaching a single primary guard ring to the TSV landing pad can result in device shock and / or plasma-induced damage (e.g., during the fabrication of the stacked chip structure 100, plasma may attack the devices in device layer DL1), and the disclosed dual guard ring configuration can also effectively prevent moisture penetration (e.g., by overlapping any gap 222 of the primary guard ring 220A with the secondary guard ring 220B) without the risk of device shock and / or plasma-induced damage.

[0064] In some embodiments, such as Figure 3As shown, the main protective ring 220A and the secondary protective ring 220B are respectively configured as the inner protective ring and outer protective ring of the protective ring structure 220. In such an embodiment, the protective ring structure 220 can be referred to as a double protective ring structure with an outer secondary protective ring (OGR). In some embodiments, such as Figure 11 As shown, the main guard ring 220A and the secondary guard ring 220B switch positions, and the main guard ring 220A and the secondary guard ring 220B are respectively configured as the outer guard ring and the inner guard ring of the guard ring structure 220. In such an embodiment, the guard ring structure 220 can be referred to as a double guard ring structure with an inner secondary guard ring (IGR). In such an embodiment, the width of the TSV metal landing pads on one or both sides of the TSV 200 and / or its contact via 210 can be reduced to improve back-side contact via coverage. For example, reducing the width can reduce the metal density of the TSV metal landing pads, which can further reduce and / or minimize the associated local stress, thereby improving coverage accuracy. In some embodiments, the width W4 of the TSV metal landing pads (e.g., the corresponding metal line 142 of the MX level) on either side of the TSV 200 and / or its contact via 210 is... Figure 11 The width of the TSV metal landing pad (W3) on either side of the TSV 200 and / or its contact via 210 can be less than the width of the TSV metal landing pad (W3). Figure 3 (in Chinese). It should also be noted that, in Figure 3 In this configuration, both the primary guard ring 220A and the secondary guard ring 220B are positioned completely above and overlap the TSV metal landing pads. In contrast, in... Figure 11 In this configuration, the secondary guard ring 220B is completely disposed above and overlaps the TSV landing pad, while the primary guard ring 220A is partially disposed above the TSV metal landing pad and extends beyond it. In some embodiments, the primary guard ring 220A may not be disposed above and / or overlap the TSV metal landing pad.

[0065] In some embodiments, the main protective rings 220A can be arranged in an alternating pattern (e.g., Figure 12 ), instead of being placed within the secondary protection ring 220B ( Figure 3 ) or installed within the main protective ring 220 ( Figure 11 In such an embodiment, such as Figure 12As shown, the main protective ring 220A and the secondary protective ring 220B can be positioned relative to each other on opposite sides of the TSV 200. For example, the main protective ring 220A forms an inner protective ring on the left side of the TSV 200 and an outer protective ring on the right side of the TSV 200, while the secondary protective ring 220B forms an outer protective ring on the left side of the TSV 200 and an inner protective ring on the right side of the TSV 200. In such an embodiment, the protective ring structure 220 can be referred to as a dual protective ring (DGR, OGR+IGR) structure with an outer secondary protective ring and an inner secondary protective ring. In some embodiments, this configuration can be switched, and the protective ring structure 220 can be referred to as a dual protective ring structure (DGR, IGR+OGR) with an inner secondary protective ring and an outer secondary protective ring.

[0066] In some embodiments, such as Figure 13 As shown, the gap 222 can be set inside the main protective ring 220A, rather than between the end of the main protective ring 220A and the TSV metal landing pad. Figure 3The gap 222 can be formed at any level of the FMLI-1 structure and / or BMLI-1 structure. For example, the gap 222 can be formed within the main guard ring 220A of the V1 level of the FMLI-1 structure. In this example, the main guard ring 220A includes main guard ring segments 220A-1, 220A-2, and the gap 222 between the main guard ring segments 220A-1 and 220A-2. The main guard ring segment 220A-1 is disposed in the BMLI-1 structure, the FMLI-1 structure, and the device layer DL1, and extends from the BM2 level to the BV0 level, through the device layer DL1, and from the V0 level to the M0 level. A primary guard ring segment 220A-2 is disposed in the FMLI-1 structure, extending from the M1 level to the VX level. The primary guard ring segment 220A-2 is disposed on and adjacent to the TSV metal landing pad (e.g., the corresponding metal line 142 of the MX level). The primary guard ring segment 220A-1 has a height h4 (e.g., along the z-direction), and the primary guard ring segment 220A-2 has a height h5 (e.g., along the z-direction), and the sum of heights h4 and h5 is equal to height h1. To further implement this example, a secondary guard ring 220B is disposed in the FMLI-1 structure and suspended above the TSV metal landing pad, and the secondary guard ring 220B overlaps with the gap 222 within the primary guard ring 220A. In the depicted embodiment, height h3 is greater than height h2, and the secondary protective ring 220B extends from level M0 to level M1, thereby overlapping with the main protective ring segment 220A-1 of level M0 and with the main protective ring segment 220A-2 of level M1. In such an embodiment, the protective ring structure 220 can be referred to as a dual protective ring structure (DGR, O+SGR) with an externally switchable / optional secondary protective ring, and the placement of the gap 222 within the main protective ring 220A (e.g., at different levels / layers) and based on the switchably positioned secondary protective ring 220B, flexible stress management can be provided.

[0067] In some embodiments, such as Figure 14As shown, the main protective ring 220A may include gaps 222 located at different heights, and the secondary protective ring 220B may include segments located at different heights based on the height of the gaps 222. For example, on the left side of the TSV 200, a first gap in the gaps 222 may be formed within the V1 level of the main protective ring 220A of the FMLI-1 structure, located between main protective ring segments 220A-1 and 220A-2; on the right side of the TSV 200, a second gap in the gaps 222 may be formed within the V(X-1) level of the main protective ring 220A of the FMLI-1 structure, located between main protective ring segments 220A-1 and 220A-2. In such an example, on the left side of the TSV 200, the main protective ring 220A may be similar to... Figure 13 The main guard ring 220A in the TSV 200 is configured as follows (e.g., main guard ring segment 220A-1 has a height h4, extends from the BM2 level to the BV0 level, passes through the device layer DL1, and extends from the V0 level to the M0 level; main guard ring segment 220A-2 has a height h5, extends from the M1 level to the VX level; and main guard ring segment 220A-2 is adjacent to the TSV metal landing pad). In contrast, on the opposite right side of the TSV 200, the main guard ring 220A has a different configuration. For example, main guard ring segment 220A-1 extends from the BM2 level to the BV0 level, passes through the device layer DL1, and extends from the V0 level to the M(X-2) level instead of the M0 level; main guard ring segment 220A-2 extends from the M(X-1) level to the VX level instead of the M1 level. Therefore, main protective ring sections 220A-1 and 220A-2 have different heights on the right side of TSV 200, for example, height h6 (e.g., along the z-direction) and height h7 (e.g., along the z-direction), respectively. In some embodiments, the sum of height h6 and height h7 is equal to the sum of height h4 and height h5. In some embodiments, the sum of height h6 and height h7 is different from the sum of height h4 and height h5, for example, when gap 222 has different heights.

[0068] According to this example, because the gap 222 is at different heights, the secondary guard ring 220B includes secondary guard ring segments 220B-1 and 220B-2. Both secondary guard ring segments 220B-1 and 220B-2 are located within the FMLI-1 structure and suspended above the TSV metal landing pads. Secondary guard ring segment 220B-1 is located on the left side of the TSV 200 and can be similar to... Figure 13The secondary protective ring 220B is configured such that (for example, secondary protective ring segment 220B-1 has a height h3 and extends from level M0 to level M1, such that secondary protective ring segment 220B-1 overlaps with gap 222 of level V1, and primary protective ring segment 220A-1 of level M0 and primary protective ring segment 220A-2 of level M1 overlap). Secondary protective ring segment 220B-2 is located on the right side of TSV 200, and secondary protective ring segment 220B-2 is set to a different height than secondary protective ring segment 220B-1. For example, the secondary protective ring segment 220B-2 extends from the M(X-2) level to the M(X-1) level, such that the secondary protective ring segment 220B-2 overlaps with the gap 222 of the V(X-1) level, and the main protective ring segment 2202-1 of the M(X-2) level overlaps with the main protective ring segment 220A-2 of the M(X-1) level. The height h8 of the secondary protective ring segment 220B-2 (e.g., along the z-direction) may be the same as or different from the height h3, and the height h9 of the gap 222 on the right side of the TSV 200 (e.g., along the z-direction) may be the same as or different from the height h2.

[0069] exist Figure 13 and Figure 14 In the illustrated embodiment, the secondary guard ring forms the outer guard ring of the guard ring structure 220 (i.e., a dual guard ring structure (DGR, O+SGR) with an external switchable / selectable secondary guard ring). In some embodiments, such as Figure 15 As shown, the main protective ring 220A and the secondary protective ring 220B are switched at their respective positions, with the secondary protective ring 220B forming the inner protective ring of the protective ring structure 220 (i.e., a dual protective ring structure (DGR, i+SGR) with an internally switchable / selectable secondary protective ring). In Figure 15 In the configuration of the main protective ring 220A, it can be similar to... Figure 14 The configuration of the main protective ring 220A and the secondary protective ring 220B can be similar to that of... Figure 14 The secondary protective ring 220B differs in that, since the secondary protective ring 220B is an inner protective ring, it is positioned between the TSV 200 and the main protective ring 220A. This disclosure considers various configurations of the main protective ring 220A, the secondary protective ring 220B, and the gap 222 to provide various configurations of the protective ring structure 220.

[0070] Refer again Figure 1A , Figure 1B , Figure 3 and Figure 4 The TSV 200 facilitates the electrical connections of the stacked chip structure 100. For example, refer to... Figure 1BVia path A, the left TSV 200 can be electrically connected to chip 102 and chip 104, chip 102 and external devices, chip 104 and external devices, or combinations thereof. In some embodiments, the left TSV 200 is electrically coupled to the corresponding connector 194 via an RDL-1 structure (e.g., its corresponding metal line 182 and corresponding metal via 184) and a BC-1 structure (e.g., its corresponding metal line 172'), and the left TSV 200 is also electrically connected to the device layer DL2 of chip 104 via an FMLI-1 structure (e.g., its corresponding metal line 142 provides a TSV metal landing pad), a TC-1 structure (e.g., its corresponding metal via 174 and metal line 172), a bonding structure 160, an RDL-2 structure (e.g., its corresponding metal line 186 and corresponding metal via 188), and a BMLI-2 structure (e.g., its corresponding metal line 146' and metal via 148'). In such an embodiment, the electrical coupling between the FMLI-1 structure and the TC-1 structure facilitates an electrical path from chip 102 to chip 104. In some embodiments, the left-side TSV 200 can be connected to a power source via its corresponding connector 194, and in some embodiments, connector 194 can be connected to chip 104 via path A.

[0071] Furthermore, via path B, the right-side TSV 200 can electrically connect chip 102 to an external device. In some embodiments, the right-side TSV 200 is electrically coupled to the corresponding connector 194 via an RDL-1 structure (e.g., its corresponding metal line 182 and corresponding metal via 184) and a BC-1 structure (e.g., its corresponding metal line 172'), and the right-side TSV 200 is also electrically coupled to the device layer DL1 of chip 102 via an FMLI-1 structure (e.g., the TSV metal landing pad provided by its corresponding metal line 142, and its corresponding metal line 141 and metal via 144). In such an embodiment, since no electrical coupling from the FMLI-1 structure to the TC-1 structure is provided (e.g., the corresponding metal line 142 connected to the MX layer of the right-side TSV 200 is not connected to the corresponding metal line 172 of the TC-1 structure), the TSV 200 facilitates an electrical path for current flow within chip 102, and this electrical path is isolated from chip 104. In some embodiments, the right-side TSV 200 can be connected to a power source via its corresponding connector 194, which can be connected to the chip 102.

[0072] In some embodiments, the stacked chip structure 100 is part of an advanced three-dimensional integrated circuit (3DIC) package. The TSV 200 of the stacked chip structure 100 may be electrically connected to a package substrate, an interposer, a printed circuit board (PCB), a printed circuit board, other package structures and / or a substrate, or a combination thereof. In some embodiments, the TSV 200 is connected to controlled collapse chip connections (C4 bonding) (e.g., solder bumps and / or solder balls) and / or microbumps (also referred to as microbonds, μbumps, and / or μbonds) (all of which may be provided by connector 194), which may be connected to the package structure.

[0073] Figures 16A-16I These are partial or complete cross-sectional views of the device structure 300 at various manufacturing stages according to various aspects of this disclosure, including the fabrication of the TSV and its corresponding guard ring. For ease of description and understanding, the following... Figures 16A-16I The discussion aims to fabricate the stacked device structure 100 or a portion thereof, including fabricating a corresponding one of the TSVs 200 and its corresponding guard ring structure 220. However, this disclosure contemplates implementations with... Figures 16A-16I Related processes are used to fabricate device structures with different configurations of TSV 200 and / or guard ring 220, as described herein. For clarity, Figures 16A-16I The invention has been simplified to better understand the inventive concepts of this disclosure. Additional features may be added to device architecture 300, and some features described below may be replaced, modified, or eliminated in other embodiments of device architecture 300.

[0074] Reference Figure 16A After undergoing FEOL processing, device structure 300 includes a device layer DL1 having device regions 302A and TSV regions 302B. Device layer DL1 (also referred to as device substrate) may include one or more devices 304 (e.g., transistors) forming in device regions 302A on and / or within substrate 106. Device layer DL1 may be fabricated on a carrier substrate 308, or attached and / or bonded to the carrier substrate 308 after fabrication. Carrier substrate 308 may be a silicon substrate.

[0075] refer to Figure 16BThe device structure 300 may undergo MEOL and / or BEOL processes to form an FMLI-1 structure (e.g., from V0 to VX and from M0 to MX levels) on the device layer DL1. For example, an insulating layer 140-1 with metal lines 142 and metal vias 144 disposed therein may be formed on the device layer DL1 (e.g., on its front side). The FMLI-1 structure may be connected to one or more devices 304 in the device region 302A. A guard ring structure 220 or a portion thereof may be formed on the TSV region 302B simultaneously with the formation of the FMLI-1 structure. For example, a first portion of the main guard ring 220A (e.g., a first portion disposed in the FMLI-1 structure) and a secondary guard ring 220B may be formed in the TSV region 302B, and the main guard ring 220 and / or the secondary guard ring 220 may define and / or surround an insulating region 310A of the insulating layer 140-1. As further described below, TSV 220 is formed to extend through insulating region 310A. In some embodiments, guard ring structure 220 may be connected to a doped region, such as an n-well or p-well, formed in substrate 106 in TSV region 302B. Furthermore, TSV landing pads (e.g., metal lines 142) may be formed on guard ring structure 220 in TSV region 302B concurrently with the formation of FMLI-1 structure. In some embodiments, as shown, TSV landing pads may be patterned to form TSV contact via openings (e.g., contact via openings 142O). Photolithography and / or etching processes may be performed to pattern the TSV landing pads. Contact vias 210 of TSV 200 may then be formed in contact via openings 142O, as described below. In some embodiments, insulating layer 140-1 may fill contact via openings 142O prior to TSV formation.

[0076] Reference Figure 16C and Figure 16DThe device structure 300 may undergo additional MEOL and / or BEOL processes to form a BMLI-1 structure (e.g., from the BV0 level to the BVX' level and from the BM0 level to the BMX' level) on the device layer DL1. For example, an insulating layer 140-1' with metal lines 142' and metal vias 144' disposed therein may be formed on the device layer DL1 (e.g., on its back side). The BMLI-1 structure may be connected to one or more devices 304 in the device region 302A. Concurrently with the formation of the BMLI-1 structure, a guard ring structure 220 or a portion thereof may also be formed above the TSV region 302B. For example, a second portion of the main guard ring 220A (e.g., disposed in the BMLI-1 structure) may be formed in the TSV region 302B, and any portion of the main guard ring 220A and / or the secondary guard ring 220B may also define and / or surround an insulating region 310B of the insulating layer 140-1. As further described below, the TSV 220 is formed to extend through the insulating region 310A. A guard ring structure 220, or a portion thereof, may also be formed on the TSV region 302B in the device layer DL1, such that a portion of the guard ring structure 220 can extend through the device layer DL1. In some embodiments, with Figure 16C and Figure 16D The associated processes may include attaching and / or bonding the FMLI-1 structure to a carrier substrate 315 (e.g., a silicon carrier) via a bonding layer / structure 316, removing the carrier substrate 308 from the device layer DL1 to expose its opposite side (e.g., the back side), and forming the BMLI-1 structure on the exposed opposite side of the device layer DL1. The device structure 300 may be flipped before or after removing the carrier substrate 308. In some embodiments, a thinning process (e.g., to reduce its thickness) may be performed on the substrate 106 prior to forming the BMLI-1 structure. In some embodiments, with Figure 16D Related processing may include forming additional device components and / or structures, such as portions of the insulating layer 170-1' of the BC-1 structure.

[0077] Reference Figures 16E-16KThe device structure 300 can be processed to form a TSV 200. This processing may include forming TSV trenches 320 in insulating regions 310A and 310B of insulating layers 140-1 and 140-1', respectively. The TSV trenches 320 extend through insulating layer 140-1', device layer DL1, and insulating layer 140-1 to reach the TSV landing pad (e.g., metal line 142). In the depicted embodiment, the TSV trenches 320 further extend through the TSV landing pad (i.e., by reopening the contact via opening 142O of the metal line 142, e.g., by removing insulating layer 140-1 therefrom) and extend to the bonding layer / structure 316, and the portion of the TSV trenches 320 extending into and / or through the TSV landing pad may be referred to as the TSV contact via opening 320o. In some embodiments, forming the TSV trench 320 includes forming a patterned mask layer 322 having an opening 322o that overlaps with and / or exposes the insulating region 310B and / or the insulating region 310A. Figure 16E ); Use patterned mask layer 322 as an etching mask to etch insulating layer 140-1', device layer DL1, insulating layer 140-1 or a combination thereof ( Figure 16F ); and during and / or after the formation of the TSV trench 320, the patterned mask layer 322 is removed ( Figure 16F The patterned mask layer 322 can be formed using a photolithography process, which may include photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., hard baking), other suitable processes, or combinations thereof. In some embodiments, the patterned mask layer 322 includes a patterned hard mask layer (e.g., a silicon nitride layer). In some embodiments, the patterned mask layer 322 includes a patterned photoresist layer. Etching may be a dry etching process, a wet etching process, other etching processes, or combinations thereof. As described herein, moisture from the surrounding environment may be introduced into the TSV trench 320 during the etching process and / or subsequent formation steps associated with the TSV 200. Therefore, the guard ring structure 220 has a dual guard ring design to prevent and / or block such moisture diffusion and / or migration into the insulating layers 140-1 and / or 140-1'. For example, because the gap 222 of the secondary guard ring 220B overlaps with that of the primary guard ring 220A, the guard ring structure 220 is positioned along the entire height of the guard ring structure 200 and / or along the entire sidewall of the TSV trench 220, and any moisture that might migrate into the device structure 300 via the gap 22 in the primary guard ring 200 is blocked and / or prevented by the secondary guard ring 220. In some embodiments, when forming the TSV trench 320, a Bosch process can be performed, for example, extending the TSV trench 320 into and / or through the device layer DL1 (e.g., its substrate 106).

[0078] This process may also include forming a TSV 200, for example, by filling the TSV trench 320 with a conductive material. In some embodiments, filling the TSV trench 320 includes depositing an insulating material 330 (e.g., SiN, SiCN, oxide, etc.) on the back side of the device structure 300 (e.g., on the back side of the device layer DL1), the insulating material 330 partially filling the TSV trench 320. Figure 16G ); Remove insulating material 330 from the bottom of TSV trench 320 (e.g., above the top of TSV landing pad) and the bottom of TSV contact via opening 320o to ensure adequate connection and / or adjacency of TSV 200 and TSV landing pad ( Figure 16H ); Deposit barrier material 332 (e.g., Ti, TiN, and / or TaN) on insulating material 330 that partially fills TSV trench 320. Figure 16I ); depositing a bulk conductive material 334 (e.g., Cu) on the barrier material 332 to fill the remaining portion of the TSV trench 320 ( Figure 16J ); and perform a planarization process (e.g., CMP) to remove excess blocking material 332 and excess bulk conductive material 334 ( Figure 16K This forms the barrier layer 204 and conductive plug 202 of the TSV 200, respectively. The insulating layer 140-1' and / or the insulating layer 170-1' can be used as planarization stop layers, and a planarization process can be performed until the insulating layer 140-1' and / or the insulating layer 170-1' are reached.

[0079] refer to Figure 16L Additional backside processing can be performed on device structure 300, such as additional processing associated with forming BC-1 structure (e.g., insulating layer 170-1' and its metal line 172') and forming RDL-1 structure. Furthermore, device structure 300 can undergo additional processing, such as forming TC-1 structure on FMLI-1 structure (after removing carrier substrate 315 and bonding layer 316 from it), attaching and / or bonding TC-1 structure to another chip (e.g., its RDL-2 structure) via bonding structure (e.g., bonding structure 160), and forming connector 194 (e.g., bump formation).

[0080] Figure 17This is a flowchart of part or all of method 400 for manufacturing guard rings and vias (e.g., guard ring 220 and TSV 200) according to various aspects of this disclosure. In block 410, method 400 includes forming a multilayer interconnect structure, such as an FMLI structure (e.g., an FMLI-1 structure) and / or a BMLI structure (e.g., a BMLI-1 structure). The multilayer interconnect structure may be a back-end process (BEOL) structure formed on a device layer / substrate (e.g., device layer DL1), and the BEOL structure may be formed on the front side, back side, or both of the device layer. In block 415, method 400 includes forming a double guard ring structure (e.g., guard ring structure 2220) and a via landing pad (e.g., metal line 142) while forming the multilayer interconnect structure. The double guard ring structure forms a ring around a region of an insulating layer (e.g., insulating layer 140-1 and / or insulating layer 140-1'). The dual-guard ring structure may include a primary guard ring (e.g., primary guard ring 220A) and a secondary guard ring (e.g., secondary guard ring 220B). The secondary guard ring may be adjacent to and independent of the primary guard ring, and may also overlap with a gap in the primary guard ring. In some embodiments, a contact via opening (e.g., contact via opening 142O) is provided in the via landing pad. In block 420, method 400 includes forming a via (e.g., TSV 200) extending through an insulating layer region to the via landing pad. The gap in the primary guard ring may correspond to a sidewall portion of the via that does not overlap with the primary guard ring. In some embodiments, the via includes a through-contact via (e.g., contact via 210) formed in the contact via opening, such that the via extends to and / or through the via landing pad. In some embodiments, the multilayer interconnect structure, the dual-guard ring structure, and the via form a portion of a first chip, and the first chip may be bonded / attached to a second chip to form a stacked chip structure (e.g., stacked chip structure 100), such as SoIC. Through-holes can electrically connect a first chip to a second chip, or they can electrically connect external devices / components to the first chip (e.g., transistors connected to a device layer). For clarity, Figure 17 The invention has been simplified to better understand the inventive concept of this disclosure. Additional steps may be provided before, during, and after method 400, and for additional embodiments of method 400, some of the described steps may be moved, replaced, or eliminated.

[0081] This disclosure provides numerous different embodiments. An exemplary integrated circuit device structure includes a through-hole disposed in an insulating layer and a guard ring structure disposed in the insulating layer. The guard ring structure is disposed around the through-hole. The guard ring structure includes a primary guard ring and a secondary guard ring, the secondary guard ring being adjacent to and separate from the primary guard ring, wherein the secondary guard ring overlaps with a gap in the primary guard ring, and the gap corresponds to a sidewall portion of the through-hole that does not overlap with the primary guard ring. In some embodiments, the primary guard ring is a first interconnect structure stack; and the secondary guard ring is a second interconnect structure stack. The first interconnect structure stack and / or the second interconnect structure stack may be disposed in an FMLI structure, a BMLI structure, a device layer disposed between the FMLI structure and the BMLI structure, a chip, and / or other layers / structures of a stacked chip structure (e.g., TC structure, BC structure, RDL structure, other interconnect structures, etc.) or combinations thereof.

[0082] In some embodiments, the protective ring structure has a first height; the main protective ring has a second height less than the first height; and the secondary protective ring has a third height less than the first height, wherein the third height is also less than the second height. In some embodiments, the main protective ring is an inner protective ring, and the secondary protective ring is an outer protective ring. In some embodiments, the main protective ring is an outer protective ring, and the secondary protective ring is an inner protective ring.

[0083] In some embodiments, on the first side of the through hole, the main protective ring is a first outer protective ring portion and the secondary protective ring is a first inner protective ring portion; and on the second side of the through hole opposite to the first side of the through hole, the main protective ring is a second inner protective ring portion and the secondary protective ring is a second outer protective ring portion.

[0084] In some embodiments, the integrated circuit device structure further includes metal pads, through-holes adjacent to metal landing pads, a secondary guard ring adjacent to the metal landing pads, and a gap located between the end of the primary guard ring and the metal landing pads. In these embodiments, the height of the secondary guard ring is greater than the height of the gap between the end of the primary guard ring and the metal landing pads, such that the secondary guard ring overlaps with the primary guard ring.

[0085] In some embodiments, the integrated circuit device structure further includes metal landing pads, wherein through-holes are adjacent to the metal landing pads; a gap is located between a first segment and a second segment of the main guard ring; and the first segment of the main guard ring is adjacent to the metal landing pads. In such an embodiment, the height of the secondary guard ring is greater than the height of the gap between the first segment and the second segment of the main guard ring, such that the secondary guard ring overlaps with the first segment and the second segment of the main guard ring.

[0086] Another exemplary integrated circuit device structure includes a first chip attached to a second chip, and a through-hole electrically connected to both the first and second chips. The through-hole is disposed in an insulating layer. The device structure also includes a guard ring structure disposed in the insulating layer and surrounding the through-hole. The guard ring structure includes a primary guard ring and a secondary guard ring. The secondary guard ring is adjacent to and separate from the primary guard ring. The secondary guard ring overlaps with a first gap in the primary guard ring, the primary guard ring overlaps with a second gap in the secondary guard ring, and the first gap and the second gap do not overlap. In some embodiments, the through-hole includes a contact via portion extending into a metal landing pad; and the primary or secondary guard ring is adjacent to the metal landing pad. In some embodiments, the insulating layer includes a first insulating layer and a second insulating layer of the first chip, wherein a device layer of the first chip is disposed between the first insulating layer and the second insulating layer, the first insulating layer being a portion of a front-side multilayer interconnect structure, the second insulating layer being a portion of a back-side multilayer interconnect structure, and the through-hole extending through the device layer. In such an embodiment, the primary guard ring is disposed in the second insulating layer, the first insulating layer, and the device layer.

[0087] In some embodiments, a primary protective ring is disposed within a secondary protective ring, and the sum of the first height of the primary protective ring and the second height of the secondary protective ring is greater than or equal to the third height of the protective ring structure, such that the protective ring structure overlaps the sidewall of the through-hole along the entire third height. In some embodiments, a secondary protective ring is disposed within a primary protective ring, and the sum of the first height of the primary protective ring and the second height of the secondary protective ring is greater than or equal to the third height of the protective ring structure, such that the protective ring structure overlaps the sidewall of the through-hole along the entire third height. In some embodiments, the primary protective rings are staggered relative to the secondary protective rings; and the sum of the first height of the primary protective ring and the second height of the secondary protective ring is greater than or equal to the third height of the protective ring structure, such that the protective ring structure overlaps the sidewall of the through-hole along the entire third height.

[0088] An exemplary method of forming an integrated circuit device structure includes forming a multilayer interconnect structure, and simultaneously forming a guard ring structure and a through-hole landing pad. Forming the multilayer interconnect structure and the guard ring structure includes performing photolithography, etching, and deposition processes. The guard ring structure forms a ring surrounding a region of an insulating layer. The guard ring structure includes a primary guard ring and a secondary guard ring. The secondary guard ring is adjacent to, separate from, and overlaps with a gap in the primary guard ring. The method also includes forming through-holes that extend through a region of the insulating layer to through-hole landing pads. The gap in the primary guard ring corresponds to a sidewall portion of the through-hole that does not overlap with the primary guard ring.

[0089] In some embodiments, the method further includes providing a contact via opening in a via landing pad and forming a via to include a through contact via located in the contact via opening, such that the via extends into the via landing pad. In some embodiments, forming a multilayer interconnect structure includes forming a front multilayer interconnect structure on the front side of the device layer and a back multilayer interconnect structure on the back side of the device layer, wherein a guard ring structure is formed simultaneously with the formation of the front multilayer interconnect structure and the back multilayer interconnect structure, and a via landing pad is formed simultaneously with the formation of the front multilayer interconnect structure.

[0090] Another exemplary method includes providing a semiconductor structure including a semiconductor substrate, forming an integrated circuit assembly on a first side of the semiconductor substrate, and forming a first interconnect structure on the integrated circuit assembly. The method further includes patterning the first interconnect structure to form a first stacked structure (e.g., a primary guard ring) extending partially through the first interconnect structure from the bottom toward the top of the first interconnect structure, and patterning the first interconnect structure to form a second stacked structure (e.g., a secondary guard ring) partially adjacent to the first stacked structure. The second stacked structure may be closer to the top of the first interconnect structure than the first stacked structure, and the first and second stacked structures may be spaced apart and electrically isolated from each other. The method may also include forming the second interconnect structure on a second side of the semiconductor substrate opposite to the first side of the semiconductor substrate. The method may further include patterning the second interconnect structure to form a third stacked structure connected to the first stacked structure within the first interconnect structure. The method may further include forming a through-substrate via (TSV) extending through the first and second interconnect structures. The first and third stacked structures may be laterally located next to the TSV.

[0091] In some embodiments, such as when viewed from a top view of a semiconductor structure, a first stacked structure surrounds a TSV, and a second stacked structure surrounds a first stacked structure. In some embodiments, the method further includes forming a first metallization structure in a first interconnect structure. The first metallization structure, the first stacked structure, and the second stacked structure may be formed simultaneously in the first interconnect structure. In some embodiments, the method further includes forming a second metallization structure in a second interconnect structure. The second metallization structure and the third stacked structure may be formed simultaneously in the second interconnect structure. In some embodiments, forming each of the first, second, and third stacked structures includes forming a first conductive component, stacking a second conductive component on the first conductive component, and overlapping with the first conductive component. The first and second conductive components may be perpendicularly aligned with each other. In some embodiments, the method further includes patterning the first interconnect structure to form a fourth stacked structure. The fourth stacked structure may be spaced apart from the first and second stacked structures in a first direction, and the fourth stacked structure may partially overlap with the first and second stacked structures in a second direction. In some embodiments, the second direction may be substantially perpendicular to the first direction.

[0092] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as the basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages of the embodiments described herein. Those skilled in the art will also recognize that such equivalent structures do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made to them within this disclosure without departing from its spirit and scope.

Claims

1. An integrated circuit device structure, comprising: Through-holes are set in the insulating layer; as well as A protective ring structure is disposed in the insulating layer, wherein the protective ring structure is disposed around the through hole, the protective ring structure includes a main protective ring and a secondary protective ring, the secondary protective ring is adjacent to the main protective ring and separate from the main protective ring, wherein the gap in the secondary protective ring overlaps with the gap in the main protective ring, and the gap corresponds to the sidewall portion of the through hole, the sidewall portion does not overlap with the main protective ring.

2. The integrated circuit device structure according to claim 1, wherein: The protective ring structure has a first height; The main protective ring has a second height that is less than the first height; and The secondary protective ring has a third height that is less than the first height, wherein the third height is also less than the second height.

3. The integrated circuit device structure according to claim 1, wherein: The main protective ring is an inner protective ring; and The secondary protective ring is the outer protective ring.

4. The integrated circuit device structure according to claim 1, wherein: The main protective ring is the outer protective ring; and The secondary protective ring is the inner protective ring.

5. The integrated circuit device structure according to claim 1, wherein: On the first side of the through hole, the main protective ring is the first outer protective ring portion, and the secondary protective ring is the first inner protective ring portion; and On the second side of the through hole, which is opposite to the first side of the through hole, the main protective ring is a second inner protective ring portion, and the secondary protective ring is a second outer protective ring portion.

6. The integrated circuit device structure according to claim 1, further comprising: Metal landing pad, wherein the through hole is adjacent to the metal landing pad; The secondary protective ring is adjacent to the metal landing pad; and The gap is located between the end of the main protective ring and the metal landing pad.

7. The integrated circuit device structure according to claim 6, wherein, The height of the secondary protective ring is greater than the height of the gap between the end of the primary protective ring and the metal landing pad, so that the secondary protective ring overlaps with the primary protective ring.

8. An integrated circuit device structure, comprising: The first chip is attached to the second chip; A through-hole is disposed in an insulating layer, wherein the through-hole is electrically connected to the first chip and the second chip; and A protective ring structure is disposed in the insulating layer and surrounds the through hole, wherein the protective ring structure includes a main protective ring and a secondary protective ring, the secondary protective ring is adjacent to the main protective ring and separate from the main protective ring, wherein the secondary protective ring overlaps with a first gap in the main protective ring, the main protective ring overlaps with a second gap in the secondary protective ring, and the first gap does not overlap with the second gap.

9. The integrated circuit device structure according to claim 8, wherein: The insulating layer includes a first insulating layer and a second insulating layer of the first chip, wherein the device layer of the first chip is disposed between the first insulating layer and the second insulating layer, the first insulating layer is part of a front-side multilayer interconnect structure, the second insulating layer is part of a back-side multilayer interconnect structure, and the through-hole extends through the device layer.

10. A method for forming an integrated circuit device structure, comprising: Forming a multi-layer interconnect structure; Concurrently forming the multilayer interconnect structure, a guard ring structure and through-hole landing pads are formed. The formation of the multilayer interconnect structure and the guard ring structure includes performing photolithography, etching, and deposition processes. The guard ring structure forms a ring surrounding a region of an insulating layer, and includes a primary guard ring and a secondary guard ring. The secondary guard ring is adjacent to the primary guard ring, separate from the primary guard ring, and overlaps with a gap in the primary guard ring. A through-hole is formed, the through-hole extending through the region of the insulating layer to the through-hole landing pad, wherein the gap in the main guard ring corresponds to the sidewall portion of the through-hole that does not overlap with the main guard ring.

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