Modular packaging structure utilizing an interposer with alignment features

Abstract

A package structure includes a first interposer, a second interposer, and a quantum chip. The first interposer includes a first alignment feature; the second interposer includes a second alignment feature. The quantum chip is bonded to the first interposer with an extended portion of the first quantum chip extending beyond a first edge of the first interposer. The first interposer and the second interposer are arranged for mutual engagement of the first alignment feature and the second alignment feature to enable alignment and coupling of one or more components on the extended portion of the first quantum chip with one or more components on the second interposer.

Description

Background Technology

[0001] This disclosure generally relates to superconducting quantum computing systems, and more specifically, to techniques for packaging multiple chips with qubits to construct modular quantum processors or quantum computers. Quantum computing systems can be implemented using a superconducting circuit quantum electrodynamics (cQED) architecture, which is constructed using quantum circuit components such as superconducting qubits and other types of superconducting quantum devices, controlled by microwave and / or magnetic flux bias control signals. Typically, a superconducting qubit is an electronic circuit implemented using components such as a superconducting tunnel junction (Josephson junction), a superconducting quantum interference device (SQUID), an inductor, and / or a capacitor, and when cooled to cryogenic temperatures, it behaves as a quantum mechanical anharmonic (nonlinear) oscillator with quantized states.

[0002] As quantum processors scale with increasing superconducting qubit counts and integration, a modular approach has emerged, where multiple smaller, high-yield qubit-containing chips are fabricated individually and packaged together to form larger-scale quantum processors. Smaller qubit-containing chips are easier to fabricate and can be defect-screened before being packaged together. While modular architectures allow for the construction of larger superconducting quantum processors from smaller modules, packaging individual qubit-containing chips together to provide a modular package structure with proper alignment is not straightforward. Summary of the Invention

[0003] Exemplary embodiments of this disclosure include packaging structures and techniques for constructing packaging structures by assembling modules (e.g., quantum computing modules) that include multiple quantum chips (with qubits) and packaging interposers with alignment features to achieve module alignment.

[0004] For example, an exemplary embodiment includes a packaging structure comprising a first interposer, a second interposer, and a quantum chip. The first interposer includes a first alignment feature. The second interposer includes a second alignment feature. The quantum chip is bonded to the first interposer, wherein an extension of the first quantum chip extends beyond a first edge of the first interposer. The first and second interposers are arranged such that the first alignment feature engages with the second alignment feature to achieve alignment and coupling of one or more components on the extension of the first quantum chip with one or more components on the second interposer.

[0005] Advantageously, the alignment features of the interposer are configured to engage corresponding first and second alignment features by physically adjaculating the first and second interposers, thereby achieving precise alignment of the packaged components and modules within very small tolerances. For example, the alignment features of the interposer enable precise alignment and coupling between a quantum chip (or a component thereof) on the first interposer and an inter-chip coupling component (e.g., a transmission line) on the second interposer, to achieve very small tolerance alignment and coupling between the quantum chip and the inter-chip coupling structure (e.g., alignment and coupling of the quantum chip on the first interposer and the transmission line on the second interposer).

[0006] In another exemplary embodiment, which may be combined with the foregoing paragraph, a first alignment feature includes a first edge of a first interposer layer, and a second alignment feature includes a second edge of a second interposer layer. The first and second edges are adjacent to each other to achieve alignment and coupling of one or more components on an extension of the quantum chip with one or more components on the second interposer layer.

[0007] In another exemplary embodiment, it may be combined with the foregoing paragraph, wherein the first alignment feature is fitted within the second alignment feature to achieve alignment and coupling of one or more components on the extension of the quantum chip with one or more components on the second intermediary layer.

[0008] In another exemplary embodiment, which may be combined with the foregoing paragraph, the first alignment feature includes a first alignment feature pattern, and the second alignment feature includes a second alignment feature pattern. The first alignment feature pattern and the second alignment feature pattern are interleaved to achieve alignment and coupling of one or more components on an extension of the quantum chip with one or more components on a second interposer layer.

[0009] Another exemplary embodiment includes a packaging structure comprising a first interposer, a second interposer, and a first quantum chip. The first interposer includes a first edge. The second interposer includes a second edge. The first quantum chip is bonded to the first interposer, wherein an extension of the first quantum chip extends beyond the first edge of the first interposer. The first and second interposers are arranged in a plane, and the first and second edges are adjacent to each other to achieve alignment and coupling of one or more components on the extension of the first quantum chip with one or more components on the second interposer.

[0010] In another exemplary embodiment, which may be combined with the preceding paragraph, the first intermediary layer includes a first shape at least partially defined by a first edge, and the second intermediary layer includes a second shape at least partially defined by a second edge, wherein the first shape and the second shape are different shapes.

[0011] In another exemplary embodiment, which may be combined with the preceding paragraph, the first intermediary layer includes a first shape at least partially defined by a first edge, and the second intermediary layer includes a second shape at least partially defined by a second edge, wherein the first shape and the second shape are the same shape.

[0012] In another exemplary embodiment, which may be combined with the preceding paragraph, the second intermediary layer includes a second quantum chip, one or more components on the second intermediary layer include transmission lines coupled to the second quantum chip, and one or more components on an extension of the first quantum chip include one or more qubits.

[0013] In another exemplary embodiment, which can be combined with the foregoing paragraphs, the packaging structure further includes a third interposer layer, the third interposer layer including a third edge. The first interposer layer includes a second edge, and the first quantum chip is bonded to the first interposer layer, wherein a second extension of the first quantum chip extends beyond the second edge of the first interposer layer. The third interposer layer is arranged in a plane with the first and second interposer layers. The second edge of the first interposer layer and the third edge of the third interposer layer are adjacent to each other to achieve alignment and coupling of one or more components on the second extension of the first quantum chip with one or more components on the third interposer layer.

[0014] In another exemplary embodiment, which may be combined with the foregoing paragraph, the first intermediary layer includes a first shape at least partially defined by a first edge and a second edge of the first intermediary layer, the second intermediary layer includes a second shape at least partially defined by a second edge of the second intermediary layer, and the third intermediary layer includes a third shape at least partially defined by a third edge of the third intermediary layer. The first shape, the second shape, and the third shape are the same shape.

[0015] In another exemplary embodiment, which may be combined with the foregoing paragraph, the first intermediary layer includes a first shape at least partially defined by a first edge and a second edge of the first intermediary layer, the second intermediary layer includes a second shape at least partially defined by a second edge of the second intermediary layer, and the third intermediary layer includes a third shape at least partially defined by a third edge of the third intermediary layer. The second shape and the third shape are the same shape, and the first shape is different from the second shape and the third shape.

[0016] In another exemplary embodiment, which may be combined with the foregoing paragraphs, the third intermediary layer includes a third quantum chip. One or more components on the third intermediary layer include transmission lines coupled to the third quantum chip, and one or more components on a second extension of the first quantum chip include one or more qubits.

[0017] Another exemplary embodiment includes a packaging structure comprising a first module and a second module. The first module includes a first interposer layer and a first quantum chip. The first interposer layer includes a first edge, and the first quantum chip is bonded to the first interposer layer, wherein an extension of the first quantum chip extends beyond the first edge of the first interposer layer. The second module includes a second interposer layer, a second quantum chip, and transmission lines. The second interposer layer includes a second edge, the second quantum chip is bonded to the second interposer layer, and the transmission lines are disposed on the second interposer layer and coupled to the second quantum chip. The first and second interposer layers are disposed in a plane, wherein the first edge and the second edge are adjacent to each other to achieve alignment and coupling of one or more components on the extension of the first quantum chip with one or more transmission lines on the second interposer layer coupled to the second quantum chip.

[0018] Another exemplary embodiment includes a method comprising: forming an interposer layer on a substrate; and dicing the substrate to separate the interposer layer into at least a first interposer layer including a first edge and a second interposer layer including a second edge. The first edge and the second edge are configured to align a structure on the first interposer layer with a structure on the second interposer layer when the first edge and the second edge are adjacent to each other and the first interposer layer and the second interposer layer are disposed in a plane.

[0019] Another exemplary embodiment includes a method comprising: constructing a first module including a first interposer layer and a first quantum chip, the first interposer layer including a first edge and the first quantum chip being bonded to the first interposer layer, wherein an extension of the first quantum chip extends beyond the first edge of the first interposer layer; constructing a second module including a second interposer layer, a second quantum chip, and a transmission line, the second interposer layer including a second edge, the second quantum chip being bonded to the second interposer layer, and the transmission line being disposed on the second interposer layer and coupled to the second quantum chip; and assembling the first module and the second module, wherein the first interposer layer and the second interposer layer are disposed in a plane and the first edge and the second edge are adjacent to each other to achieve alignment and coupling of one or more components on the extension of the first quantum chip to one or more transmission lines on the second interposer layer coupled to the second quantum chip.

[0020] Other embodiments will be described in detail in the following exemplary embodiments, which will be read in conjunction with the accompanying drawings. Attached Figure Description

[0021] Figure 1 A modular packaging structure according to an exemplary embodiment of the present disclosure is illustrated schematically.

[0022] Figure 2A , Figure 2B and Figure 2CA method for constructing a modular packaging structure according to an exemplary embodiment of the present disclosure is illustrated schematically.

[0023] Figure 3A and Figure 3B A modular packaging structure according to another exemplary embodiment of the present disclosure is illustrated schematically.

[0024] Figure 4A A modular packaging structure according to another exemplary embodiment of the present disclosure is illustrated schematically.

[0025] Figure 4B , Figure 4C and Figure 4D A method for constructing a modular packaging structure according to another exemplary embodiment of the present disclosure is illustrated schematically.

[0026] Figure 5A A modular packaging structure according to another exemplary embodiment of the present disclosure is illustrated schematically.

[0027] Figure 5B , Figure 5C and Figure 5D A method for constructing a modular packaging structure according to another exemplary embodiment of the present disclosure is illustrated schematically.

[0028] Figure 6A and Figure 6B A method for constructing an insert for a modular packaging structure according to an exemplary embodiment of the present disclosure is illustrated schematically.

[0029] Figure 7A and Figure 7B A method for constructing an intermediary layer for a modular encapsulation structure is illustrated schematically according to another exemplary embodiment of the present disclosure.

[0030] Figure 8A and Figure 8B A method for constructing an intermediary layer for a modular encapsulation structure is illustrated schematically according to another exemplary embodiment of the present disclosure.

[0031] Figure 9A , Figure 9B and Figure 9C A method for constructing an intermediary layer for a modular encapsulation structure is illustrated schematically according to another exemplary embodiment of the present disclosure.

[0032] Figure 10 A flowchart of a method for constructing a modular packaging structure according to an exemplary embodiment of the present disclosure is shown.

[0033] Figure 11A quantum computing system according to an exemplary embodiment of the present disclosure is schematically illustrated, which includes a quantum processor comprising a modular package structure constructed using multiple quantum modules. Detailed Implementation

[0034] Exemplary embodiments of this disclosure will now be described in more detail with reference to modular packaging structures and techniques for constructing modular packaging structures using quantum modules having packaging interposers designed with alignment features. The alignment features are configured such that one or more structures on one interposer are aligned with one or more structures on another interposer by physically engaging the alignment features of the interposers, thereby achieving minimal tolerance alignment of two or more interposers arranged in the same plane (e.g., the XY plane), wherein such minimal tolerance alignment is achieved in the first and second orthogonal lateral directions (e.g., the X and Y directions) of the plane (XY plane).

[0035] It should be understood that the various features shown in the accompanying drawings are schematic illustrations and are not drawn to scale. Furthermore, the same or similar reference numerals are used throughout the drawings to denote the same or similar features, elements, or structures; therefore, the same or similar features, elements, or structures will not be repeated for each figure in the drawings. Additionally, the term "exemplary" as used herein means "serving as an example, instance, or illustration." Any embodiment or design described herein as "exemplary" should not be construed as preferred or advantageous over other embodiments or designs.

[0036] Furthermore, it should be understood that the phrase “configured to” is used in conjunction with circuits, structures, elements, components, etc. that perform one or more functions or otherwise provide a certain function in order to cover embodiments in which the circuits, structures, elements, components, etc. are implemented in hardware, software, and / or combinations thereof, as well as implementations including hardware, wherein the hardware may include quantum circuit elements (e.g., qubits, tunable couplers, etc.), discrete circuit elements (e.g., transistors, inverters, etc.), programmable elements (e.g., application-specific integrated circuit (ASIC) chips, field-programmable gate array (FPGA) chips, etc.), processing devices (e.g., central processing unit (CPU), graphics processing unit (GPU), etc.), one or more integrated circuits and / or combinations thereof. Therefore, by way of example only, when a circuit, structure, element, component, etc. is defined as being configured to provide a particular function, it is intended to cover, but is not limited to, the following embodiments: wherein the circuit, structure, element, component, etc. consists of elements, processing devices, and / or integrated circuits that enable it to perform a particular function in an operational state (e.g., connected or otherwise deployed in a system, powered on, receiving input, and / or generating output); and embodiments that cover the circuit, structure, element, component, etc. in a non-operational state (e.g., not connected or otherwise not deployed in a system, not powered on, not receiving input, and / or not generating output) or in a partially operational state.

[0037] To provide spatial context for the different structural orientations of the semiconductor structures shown in the accompanying figures, XYZ Cartesian coordinates are illustrated. The terms “vertical” or “vertical direction” or “vertical height” as used herein refer to the Z-direction of the Cartesian coordinates shown in the accompanying figures, and the terms “horizontal,” “horizontal direction,” “lateral,” or “lateral direction” as used herein refer to the X-direction and / or Y-direction of the Cartesian coordinates shown in the accompanying figures.

[0038] Furthermore, as used herein, the term "quantum chip" refers to a bare die (e.g., a semiconductor bare die) that includes a superconducting electronic integrated circuit comprising various superconducting components such as qubits, tunable couplers, ground planes, signal coplanar waveguides, and resonators. Multiple bare dies with identical and / or different configurations of superconducting electronic integrated circuits can be fabricated on a wafer (e.g., a semiconductor wafer), where the individual dies can be diced (cut) from the wafer using a die dicing process to provide separated dies that can be packaged together to construct a modular quantum processor architecture. The terms "quantum chip" and "quantum bare die" are synonymous and are used interchangeably herein. The terms "quantum computing module," "quantum module," or "module" as used herein are synonymous and refer to an interposer component of a quantum chip having one or more interposers bonded to an interposer. Furthermore, the term "non-current coupling" or "non-current connection" as used herein refers to a non-direct electrical connection, such as a connection achieved via capacitive coupling, inductive coupling, optical coupling, or combinations thereof.

[0039] Figure 1 A modular packaging structure according to exemplary embodiments of the present disclosure is illustrated schematically. More specifically, Figure 1 This is a schematic top view of a modular packaging structure 100, which includes multiple quantum modules, namely a first module 110, a second module 120, and a third module 130. The first module 110 includes a first interposer layer 111 and a quantum chip 112 bonded to the surface of the first interposer layer 111. The first interposer layer 111 includes a first edge 111-1 and a second edge 111-2. The second module 120 includes a second interposer layer 121 and a quantum chip 122 bonded to the surface of the second interposer layer 121. The second interposer layer 121 includes a first edge 121-1. The third module 130 includes a third interposer layer 131 and a quantum chip 132 bonded to the surface of the third interposer layer 131. The third interposer layer 131 includes a first edge 131-1.

[0040] like Figure 1 As further shown, the quantum chip 112 includes a first portion 112-1 (optionally referred to herein as a first extension portion) extending beyond a first edge 111-1 of the first interposer layer 111 and overlapping a portion of the second interposer layer 121. Additionally, the quantum chip 112 includes a second portion 112-2 (optionally referred to herein as a second extension portion) extending beyond a second edge 111-2 of the first interposer layer 111 and overlapping a portion of the third interposer layer 131. The first extension portion 112-1 includes one or more components aligned and coupled to one or more components on the second interposer layer 121. The second extension portion 112-2 includes one or more components aligned and coupled to one or more components on the third interposer layer 131.

[0041] For example, in some embodiments, the first extension 112-1 includes one or more qubits aligned and capacitively coupled to one or more transmission lines on the second interposer 121. Similarly, in some embodiments, the second extension 112-2 includes one or more qubits aligned and capacitively coupled to one or more transmission lines on the third interposer 131. In some embodiments, the capacitive coupling of components (e.g., qubits) on the quantum chip 112 to components (e.g., transmission lines) on the second and third interposers 121 and 131 provides a non-current connection, allowing the quantum chip to be coupled to the second and third interposers 121 and 131 without additional bonding steps. This provides greater flexibility for assembling modular quantum processors comprising multiple independent quantum chips mounted on different interposers and operatively coupled together to achieve modular package structures with large qubit arrays.

[0042] Figure 1 An exemplary embodiment is shown, wherein minimal tolerance alignment of the first module 110 and the second module 120 is achieved by adjaculating the first edge 111-1 of the first intermediary layer 111 with the first edge 121-1 of the second intermediary layer 121. Furthermore, minimal tolerance alignment of the first module 110 and the third module 130 is achieved by adjaculating the second edge 111-2 of the first intermediary layer 111 with the first edge 131-1 of the third intermediary layer 131. Figure 1 In an exemplary embodiment, the first interposer layer 111, the second interposer layer 121, and the third interposer layer 131 are arranged on the same plane (XY plane). In this exemplary packaging configuration, the first edge 111-1 of the first interposer layer 111 and the first edge 121-1 of the second interposer layer 121 include corresponding alignment features that are joined (e.g., physically adjacent) to achieve, for example, alignment of qubits on the first extension 112-1 of the quantum chip 112 with transmission lines in the overlapping region of, for example, the second interposer layer 121 (e.g., achieving minimal tolerance alignment in the X and Y (orthogonal) lateral directions of the XY plane), thereby enabling the quantum chip 112 of the first module 110 to be correctly aligned with the second module 120. Similarly, the second edge 111-2 of the first interposer layer 111 and the first edge 131-1 of the third interposer layer 131 include corresponding alignment features that are joined (e.g., physically adjacent) to achieve, for example, alignment of qubits on the second extension 112-2 of the quantum chip 112 with transmission lines in the overlapping region of the third interposer layer 131 (e.g., self-alignment in the X and Y (orthogonal) lateral directions of the XY plane), thereby enabling the quantum chip 112 of the first module 110 to be correctly aligned with the third module 130.

[0043] Figure 2A , Figure 2B and Figure 2C A method for constructing a modular packaging structure according to exemplary embodiments of the present disclosure is illustrated schematically. Specifically, Figure 2A , Figure 2B and Figure 2C The illustration shows the process of manufacturing. Figure 1 A method for an exemplary modular encapsulation structure 100. Figure 2A The initial stage 200 of the manufacturing process is shown, which begins with a substrate 102, which is divided (or defined) into a first region 111a, a second region 121a, and a third region 131a based on a first dicing line 102-1 and a second dicing line 102-2. The first, second, and third regions 111a, 121a, and 131a correspond to the first, second, and third interposers 111, 121, and 131, respectively.

[0044] The substrate 102 is formed of any suitable material used to form the quantum hardware chip, such as single-crystal silicon (Si), silicon germanium (SiGe), sapphire, glass, etc. The lateral (XY) dimensions of the substrate 102 can depend on the size, number, and / or layout of the interposers required to construct a given package structure. For example, in an exemplary non-limiting embodiment, the substrate 102 can be a semiconductor wafer (e.g., a 300 mm diameter silicon wafer (12-inch diameter silicon wafer) with a thickness ranging from 10 micrometers to 1000 micrometers) or a panel (e.g., an 800 x 800 mm square panel with a thickness ranging from 10 micrometers to 1000 micrometers).

[0045] According to the given packaging design requirements, a metallization process is performed to form patterned metallized structures on different interposer regions 111a, 121a, and 131a on the surface of substrate 102. This metallization process includes depositing and patterning metal / metal materials to form planar transmission lines (for data and control signals), ground layers, chip bonding pads, and other patterned metal elements fabricated for superconducting quantum computing applications. The metal / metal materials include superconducting metal / metal materials, including but not limited to niobium, aluminum, titanium, tungsten, molybdenum, nitrides of the above materials, combinations thereof, and / or similar materials. A superconducting material is any material that exhibits superconducting properties (e.g., zero resistance, repulsion of magnetic fields when in a superconducting state) at or below the superconducting critical temperature.

[0046] In some embodiments, the metallization layer formed on the surface of substrate 102 includes a single-layer wiring network. In other embodiments, to support higher integration density, the metallization layer may be a multilayer wiring structure formed on the surface of substrate 102, wherein the multilayer wiring structure includes multiple patterned superconducting metallization layers, dielectric layers, and interlayer metallized vias. These structures can be fabricated using, for example, back-end processing (BEOL), a process typically used to build wiring network structures on the active surface of a semiconductor chip.

[0047] Furthermore, in some embodiments, holes may be drilled in areas of the substrate 102 to provide through-holes for mounting multiple connectors (e.g., clip-on connectors) to the surface of the substrate 102. For example, the through-holes in the substrate 102 may be formed using a precision-machined backplate placed on the surface of the substrate 102, the backplate having openings of various shapes corresponding to the shapes and openings to be cut into the substrate 102 to facilitate the mounting of connectors and the precise placement of the substrate 102 onto the backplate.

[0048] Next, Figure 2B The result of cutting process 201 is schematically shown, where along... Figure 2A The first dicing line 102-1 and the second dicing line 102-2 shown are used to cut the substrate 102 to separate the first, second, and third interposer regions 111a, 121a, and 131a into separate first, second, and third interposers 111, 121, and 131, each having an associated metallization layer and a cut shape / opening for mounting connectors. In some embodiments, the cutting process uses state-of-the-art water-guided laser cutting technology for precision cutting, or other suitable wafer cutting processes. The cut along the first dicing line 102-1 separates the second interposer 121 from the substrate 102, and the cut along the second dicing line 102-2 separates the first interposer 111 and the third interposer 131 from the substrate 102. In this exemplary embodiment, the total area of ​​the first, second, and third interposers 111, 121, and 131 substantially encompasses the entire area of ​​the original substrate 102.

[0049] like Figure 2BAs schematically shown, the cut along the first cutting line 102-1 results in the formation of a first edge 111-1 of the first intermediary layer 111 and a first edge 121-1 of the second intermediary layer 121, wherein these edges 111-1 and 121-1 include corresponding alignment features (e.g., alignment edges), which are formed simultaneously as a result of the cut, enabling minimal tolerance alignment of the first and second intermediary layers 111 and 121 in the X and Y lateral directions by physically adjoining the edges 111-1 and 121-1 in an interlocking manner. Similarly, the cutting along the second cutting line 102-2 results in the formation of the second edge 111-2 of the first interposer layer 111 and the first edge 131-1 of the third interposer layer 131, wherein these edges 111-2 and 131-1 include corresponding alignment features (e.g., alignment edges), which are formed simultaneously as a result of the cutting process, enabling the first and third interposer layers 111 and 131 to be physically mated in an interlocking manner with minimal tolerance alignment in the X and Y lateral directions.

[0050] Figure 2B An exemplary embodiment is shown, wherein a first intermediary layer 111 includes a first shape at least partially defined by its first edge 111-1 and second edge 111-2. Furthermore, a second intermediary layer 121 includes a second shape at least partially defined by its first edge 121-1, wherein the first and second shapes of the first and second intermediary layers 111 and 121 are different. Furthermore, a third intermediary layer 131 includes a third shape at least partially defined by its first edge 131-1, wherein the shapes of the second and third intermediary layers 121 and 131 are identical.

[0051] Next, Figure 2C The process of constructing multiple quantum modules by bonding one or more quantum chips to each of the separated first, second, and third intermediate layers 111, 121, and 131 is schematically illustrated. Specifically, in Figure 2C In an exemplary embodiment, a first module 110 is formed by bonding a quantum chip 112 to bonding pads on a first interposer layer 111, a second module 120 is formed by bonding a quantum chip 122 to bonding pads on a second interposer layer 121, and a third module 130 is formed by bonding a quantum chip 132 to bonding pads on a third interposer layer 131. The quantum chip 112 is bonded to the first interposer layer 111, wherein a first portion 112-1 extends beyond a first edge 111-1 of the first interposer layer 111, and a second portion 112-2 extends beyond a second edge 111-2 of the first interposer layer 111.

[0052] In some embodiments, quantum chips 112, 122, and 132 are flip-chip bonded to corresponding interposers 111, 121, and 131 using solder bumps 140 (e.g., indium solder bumps). While exemplary modules 110, 120, and 130 are each shown as being constructed with a single quantum chip, it should be understood that, depending on the application, quantum modules can be fabricated with two or more quantum chips. Quantum chips 112, 122, and 132 each include a superconducting electronic integrated circuit device that includes various superconducting components such as qubits, tunable couplers, ground planes, signal coplanar waveguides, and readout resonators. Qubits can include various types of superconducting qubits, such as transmon qubits, fluxonium qubits, multimode qubits (e.g., double-junction qubits or tunably coupled qubits), and other suitable types of fixed-frequency or tunable-frequency qubits. Tunable couplers can be implemented using frequency-tunable qubits that do not encode quantum information but are used to control / regulate the interactions between superconducting qubits (e.g., entanglement gate operation).

[0053] Then, the first module 110, the second module 120, and the third module 130 are assembled together to construct an exemplary package structure 100, such as... Figure 1As shown above, the first module 110, the second module 120, and the third module 130 are assembled by arranging modules 110, 120, and 130 adjacent to each other in the same plane, and (i) achieving minimal tolerance alignment of the first module 110 and the second module 120 by abutting the first edge 111-1 of the first interposer layer 111 with the first edge 121-1 of the second interposer layer 121, and (ii) achieving minimal tolerance alignment of the first module 110 and the third module 130 by abutting the second edge 111-2 of the first interposer layer 111 with the first edge 131-1 of the third interposer layer 131. The edges 111-1 and 121-1 of the first and second interposer layers 111 and 121 include corresponding alignment edges, which are joined (e.g., physically adjacent) to achieve high-precision alignment of components (e.g., qubits) on the first extension 112-1 of the quantum chip 112 with components (e.g., transmission lines) on the second interposer layer 121. Similarly, the edges 111-2 and 131-1 of the first and third interposers 111 and 131 include corresponding alignment edges that are joined (e.g., physically adjacent) to achieve high-precision alignment of components (e.g., qubits) on the second extension 112-2 of the quantum chip 112 with components (e.g., transmission lines) on the third interposer 131. In this configuration, the components (e.g., qubits) on the first and second extensions 112-1 and 112-2 of the quantum chip 112 are precisely aligned with the corresponding components (e.g., transmission lines) on the second and third interposers 121 and 131 in the X and Y lateral directions within the XY plane, thereby enabling the quantum chip 112 of the first module 110 to be correctly aligned and coupled with the second and third modules 120 and 130.

[0054] Figure 3A and Figure 3B A modular packaging structure according to another exemplary embodiment of this disclosure is schematically illustrated. Specifically, Figure 3A This is a schematic 3D view of the modular packaging structure 300. Figure 3B It is along Figure 3AThe image shows a schematic cross-sectional view of a modular packaging structure 300, taken from a portion of line XX. The modular packaging structure 300 includes multiple quantum modules, including a first module 310, a second module 320, and a third module 330. The first module 310 includes a first interposer layer 311 and a quantum chip 312 bonded to the surface of the first interposer layer 311. The first interposer layer 311 includes a first edge 311-1 and a second edge 311-2. The second module 320 includes a second interposer layer 321 and a quantum chip 322 bonded to the surface of the second interposer layer 321. The second interposer layer 321 includes a first edge 321-1. The third module 330 includes a third interposer layer 331 and a quantum chip 332 bonded to the surface of the third interposer layer 331. The third interposer layer 331 includes a first edge 331-1.

[0055] The exemplary modular packaging structure 300 is architecturally similar to... Figure 1 The modular packaging structure 100 is similar because the first, second, and third interposers 311, 321, and 331 include the same or similar shapes as the first, second, and third interposers 111, 121, and 131 of the modular packaging structure 100. Furthermore, similar to... Figure 1 The quantum chip 112 shown includes a first extension portion 312-1 that extends beyond the first edge 311-1 of the first interposer layer 311 and overlaps with a portion of the second interposer layer 321. Furthermore, the quantum chip 312 includes a second extension portion 312-2 that extends beyond the second edge 311-2 of the first interposer layer 311 and overlaps with a portion of the third interposer layer 331.

[0056] The exemplary modular packaging structure 300 also includes a plurality of connectors 313 mounted on the surface of a first interposer 311, a plurality of connectors 323 mounted on the surface of a second interposer 321, and a plurality of connectors 333 mounted on the surface of a third interposer 331. Connectors 313 are configured to enable the transmission of I / O signals (data and control signals) between the quantum chip 312 on the first interposer 311 and a remote computing system or control electronics device. Similarly, connectors 323 are configured to enable the transmission of I / O signals (data and control signals) between the quantum chip 322 on the second interposer 321 and a remote computing system or control electronics device. Furthermore, connectors 333 are configured to enable the transmission of I / O signals (data and control signals) between the quantum chip 332 on the third interposer 331 and a remote computing system or control electronics device. Connectors 323 and 333 can be implemented using any type of connector suitable for superconducting quantum computing.

[0057] Figure 3BAn exemplary embodiment is schematically illustrated, wherein quantum chips 312, 322, and 332 are flip-chip bonded to corresponding interposers 311, 321, and 331 using corresponding solder bump arrays 314, 324, and 334. Furthermore, the modular package structure 300 includes various metallization layers located on the surfaces of the first, second, and third interposers 311, 321, and 331, including but not limited to planar signal transmission lines 325 and 335 (e.g., coplanar waveguides (CPWs)), which are configured to connect the quantum chips (e.g., quantum chips 322 and 332) to the corresponding interposers (e.g., the second and third interposers 321 and 331, such as…). Figure 3B The connectors (e.g., connectors 323 and 333, as shown in the specific illustration) on the connectors are as follows: Figure 3B Transmit I / O signals between (as shown in the specific diagram).

[0058] also, Figure 3B The first extension 312-1 of the quantum chip 312 is schematically shown overlapping a portion of the second interposer 321. The first extension 312-1 includes a metallization layer 314, which is aligned with and capacitively coupled to a metallization layer 327 on the second interposer 321 by adjoining the edges 311-1 and 321-1 of the first and second interposers 311, as shown. Furthermore, the second extension 312-2 of the quantum chip 312 is shown overlapping a portion of the third interposer 331. The second extension 312-2 includes a metallization layer 315, which is aligned with and capacitively coupled to a metallization layer 337 on the third interposer 331 by adjoining the edges 311-2 and 331-1 of the first and third interposers 311, as shown. In some embodiments, the metallization layers 314 and 315 of the first and second extension portions 312-1 and 312-2 include quantum components, such as qubits, and the metallization layers 327 and 337 on the second and third interposers 321 and 331 include transmission lines that are non-currently coupled to the qubits via a vacuum gap capacitor structure.

[0059] Figure 4A A modular packaging structure according to another exemplary embodiment of this disclosure is schematically illustrated. More specifically, Figure 4AThis is a schematic top view of a modular packaging structure 400, which includes multiple quantum modules, including a first module 410 and a second module 420. The first module 410 includes a first interposer layer 411, a first quantum chip 412 bonded to the surface of the first interposer layer 411, and a second quantum chip 413 bonded to the surface of the first interposer layer 411. The second module 420 includes a quantum chip 422 bonded to the surface of a second interposer layer 421. The second quantum chip 413 of the first module 410 overlaps with and is coupled to a portion of the second interposer layer 421.

[0060] Figure 4A An exemplary embodiment is schematically illustrated, wherein a first intermediary layer 411 includes a first alignment feature 411-1, and a second intermediary layer 421 includes a second alignment feature 421-1. The first alignment feature 411-1 includes a first feature pattern (e.g., a first finger element and a groove pattern), and the second alignment feature 421-1 includes a second feature pattern (e.g., a second finger element and a groove pattern). The first and second alignment features 411-1 and 421-1 have corresponding opposing patterns that are interleaved and interlocked by abutting the edges of the first and second intermediary layers 411 and 421, thereby achieving alignment of one or more structures on the first intermediary layer 411 with one or more structures on the second intermediary layer 421.

[0061] Figure 4B , Figure 4C and Figure 4D A method for constructing a modular packaging structure 400 according to another exemplary embodiment of the present disclosure is illustrated schematically. Figure 4B The initial stage of the manufacturing process is schematically illustrated, beginning with a substrate 402 (e.g., a portion of a semiconductor wafer), which is divided (or defined) into a first region 411a and a second region 421a based on dicing line 402-1. The first region 411a and the second region 421a correspond to a first interposer 411 and a second interposer 421, respectively. The substrate 402 may include a silicon substrate or other types of materials as discussed above. Depending on the requirements of a given package design, a metallization process is performed to form patterned metallization structures on the surfaces of the different interposer regions 411a and 421a of the substrate 402.

[0062] Next, Figure 4CThe result of the dicing process is schematically illustrated, wherein substrate 402 is diced along dicing line 402-1 to separate first interposer region 411a and second interposer region 421a into separate first interposer 411 and second interposer 421. The dicing along dicing line 402-1 creates a first alignment feature 411-1 of the first interposer 411 and a corresponding second alignment feature 421-1 of the second interposer 421. The first alignment feature 411-1 includes a first finger element and a groove pattern that forms a first meandering edge of the first interposer 411. The second alignment feature 421-1 includes a second finger element and a groove pattern that forms a second meandering edge of the second interposer 421. The first and second alignment features 411-1 and 421-1 have corresponding opposite finger and groove patterns that interlock and cross each other by abutting the first and second meandering edges of the first and second interposers 411 and 421, thereby aligning one or more structures on the first interposer 411 with one or more structures on the second interposer 421. The corresponding first and second alignment features 411-1 and 421-1 are formed simultaneously by cutting the substrate 402 along the dicing line 402-1. This enables the first and second interposers 411 and 421 to be aligned with minimal tolerance in the X and Y lateral directions by interlocking the corresponding fingers and trenches of the first and second alignment features 411-1 and 421-1 and abutting the first and second meandering edges of the first and second interposers 411 and 421.

[0063] Next, Figure 4D The process of constructing first and second quantum modules 410 and 420 by bonding one or more quantum chips to each of the separated first and second intermediate layers 411 and 421 is illustrated schematically. Specifically, in Figure 4D In the exemplary embodiment shown, a first module 410 is formed by bonding a first quantum chip 412 to bonding pads on a first interposer layer 411 and a second quantum chip 413 to bonding pads on the first interposer layer 411 (including bonding pads located on one or more of the finger elements of the first alignment feature 411-1). A second module 420 is formed by bonding a quantum chip 422 to bonding pads on a second interposer layer 421.

[0064] The first module 410 and the second module 420 are then assembled together to construct an exemplary package structure 400 (such as...). Figure 4A(As shown in the diagram). For example, the first module 410 and the second module 420 are assembled by arranging modules 410 and 420 adjacent to each other in the same plane, and by inserting and fitting finger elements of the first and second alignment features 411-1 and 421-1 into corresponding grooves of the first and second alignment features 411-1 and 421-1, and by abutting the first and second meandering edges of the first and second interposers 411 and 421, thereby achieving minimal tolerance alignment of the first module 410 and the second module 420. This process enables minimal tolerance alignment of the qubits on the portion of the second quantum chip 413 that does not overlap with the first interposer 411 with signal transmission lines located in the groove of the second alignment feature 421-1 and other areas on the surface of the second interposer 421 over which the second quantum chip 413 overlaps, and these transmission lines are coupled to the qubits on the quantum chip 422 on the second interposer 421.

[0065] Figure 5A A modular packaging structure according to another exemplary embodiment of this disclosure is schematically illustrated. More specifically, Figure 5A This is a schematic top view of a modular packaging structure 500, which includes multiple quantum modules, including a first module 510 and a second module 520. The first module 510 includes a first interposer layer 511, a first quantum chip 512 bonded to the surface of the first interposer layer 511, and a second quantum chip 513. The second module 520 includes a first quantum chip 522 bonded to the surface of a second interposer layer 521 and a second quantum chip 523. The second quantum chip 513 of the first module 510 includes an extension 513-1 that extends beyond the edge of the first interposer layer 511 and is coupled to a region in the second interposer layer 521 that overlaps with the extension 513-1 of the quantum chip 513.

[0066] Figure 5A An exemplary embodiment is schematically illustrated, wherein a first intermediary layer 511 includes a first alignment feature 511-1 formed at its edge E1, and a second intermediary layer 521 includes a corresponding second alignment feature 521-1 formed at its edge E2. The first alignment feature 511-1 includes a tongue-shaped feature, and the second alignment feature 521-1 includes a corresponding groove-shaped feature. In some embodiments, such as Figure 5AAs shown, the first and second alignment features 511-1 and 521-1 include triangular or V-shaped features. When edges E1 and E2 are physically adjacent, the first alignment feature 511-1 inserts into and fits into the second alignment feature 521-1 to interlock the first and second interposer layers 511 and 521, thereby aligning one or more structures on the first interposer layer 511 with one or more structures on the second interposer layer 521. For example, aligning the extension 513-1 of the quantum chip 513 with the bonding pads on the second interposer layer 521 in the area overlapping with the extension 513-1 of the quantum chip 513. It should be noted that although the first and second alignment features 511-1 and 521-1 are shown as V-shaped features, in other embodiments, the first and second alignment features 511-1 and 521-1 may have other corresponding shapes, such as rectangular features, hemispherical features, etc.

[0067] Figure 5B , Figure 5C and Figure 5D This schematically illustrates a method for constructing according to another exemplary embodiment of the present disclosure. Figure 5A The method of modular packaging structure 500. Figure 5B The initial stage of the manufacturing process is schematically illustrated, beginning with a substrate 502 (e.g., a portion of a semiconductor wafer) that is divided (or defined) into multiple regions based on dicing lines 502-1 and 502-2, including regions 511a, 521a, 531a, and 541a, etc. For illustrative purposes, regions 511a and 521a correspond to the first and second interposer layers 511 and 521, respectively. The substrate 502 may include a silicon substrate or other types of materials as discussed above. Depending on the requirements of a given package design, a metallization process is performed to form patterned metallization structures on the surfaces of the different interposer regions 511a, 521a, 531a, and 541a of the substrate 502.

[0068] Next, Figure 5C The result of the dicing process is schematically illustrated, wherein substrate 502 is diced along dicing lines 502-1 and 502-2 to separate interposer regions 511a, 521a, 531a, and 541a into separate interposer layers, including, for example, separate first and second interposer layers 511 and 521. The dicing along dicing line 502-1 simultaneously forms a first alignment feature 511-1 on the edge E1 of the first interposer layer 511 and a corresponding second alignment feature 521-1 on the edge E2 of the second interposer layer 521. The corresponding first and second alignment features 511-1 and 521-1 are formed simultaneously while dicing substrate 502 along dicing line 502-1.

[0069] Next, Figure 5DThe process of constructing first and second quantum modules 510 and 520 by bonding one or more quantum chips to separated first and second interposer layers 511 and 521 is illustrated schematically. Specifically, in Figure 5D In the exemplary embodiment shown, the first module 510 is formed by bonding quantum chips 512 and 513 to a first interposer layer 511, wherein the extension portion 513-1 extends beyond the edge E1 of the first interposer layer. The second module 520 is formed by bonding quantum chips 522 and 523 to a second interposer layer 521.

[0070] Subsequently, the first module 510 and the second module 520 are assembled together to construct an exemplary package structure 500, such as... Figure 5A As shown. For example, the first module 510 and the second module 520 are assembled by arranging modules 510 and 520 adjacent to each other in the same plane, and achieving self-alignment of the first module 510 and the second module 520 by inserting and fitting a first alignment feature 511-1 into a second alignment feature 521-1, and by making the edges E1 and E2 of the first and second interposer layers 511 and 521 adjacent. This process enables the qubits arranged on the extension 513-1 of the second quantum chip 513 to be closely aligned with, for example, transmission lines located in the region of the second interposer layer 521 that overlaps with the extension 513-1 of the quantum chip 513.

[0071] It should be understood that other types of intermediary layer patterns and shapes can be implemented to achieve self-alignment in two or more orthogonal lateral directions (e.g., the X and Y directions) by having the edges of two or more intermediary layers arranged in the same plane (e.g., the XY plane) adjacent to each other, which will now be combined Figure 6A , Figure 6B , Figure 7A , Figure 7B , Figure 8A , Figure 8B , Figure 9A and Figure 9B Let us discuss its exemplary embodiments. Specifically, Figure 6A and Figure 6B A method for constructing an intermediary layer for a modular packaging structure is illustrated schematically according to exemplary embodiments of the present disclosure. Figure 6A A substrate 600 (e.g., a portion of a semiconductor wafer) is schematically shown, which is divided (or defined) into multiple interposer regions based on dicing lines (as shown by dashed lines), such as interposer regions 611a, 621a, and 631a. Each interposer region comprises a hexagonal polygon (e.g., a hexagon) of the same size and shape.

[0072] Figure 6BThe result of the dicing process is illustrated schematically, in which a semiconductor substrate 600 is diced along dicing lines to separate the interposer region into individual interposers. For example, Figure 6B Three separate intermediary layers 611, 621, and 631 are shown, which correspond to Figure 6A Exemplary interposer regions 611a, 621a, and 631a are shown in the figure. In this configuration, three separate interposer layers 611, 621, and 631 can be used to form a modular packaging structure, wherein self-alignment in the X and Y directions is achieved by making the edges of the three separate interposer layers 611, 621, and 631 adjacent (as shown). In this regard, the hexagonal interposer layers enable the use of at least three hexagonal interposer layers (e.g., interposer layers 611, 621, and 631) to achieve extremely small tolerance alignment of quantum modules (such as...). Figure 6B As shown), thus achieving an interlocking pattern with minimal tolerance alignment of the intermediate layer.

[0073] Next, Figure 7A and Figure 7B A method for constructing an intermediary layer for a modular encapsulation structure according to exemplary embodiments of the present disclosure is illustrated schematically. Specifically, Figure 7A A semiconductor substrate 700 (e.g., a portion of a semiconductor wafer) is schematically shown, which is divided (or defined) into multiple interposer regions based on dicing lines (as shown by dashed lines), such as interposer regions 711a, 721a, 731a, 741a, 751a, and 761a. Each interposer region includes a triangular region of the same size.

[0074] Figure 7B The result of the dicing process is illustrated schematically, in which a semiconductor substrate 700 is diced along dicing lines to separate the interposer region into individual interposers. For example, Figure 7B Six separate triangular intermediate layers 711, 721, 731, 741, 751, and 761 are shown, which correspond to Figure 7A The exemplary interposer regions 711a, 721a, 731a, 741a, 751a, and 761a are shown in the figure. In this configuration, six separate interposer layers 711, 721, 731, 741, 751, and 761 can be used to construct a modular encapsulation structure, wherein self-alignment in the X and Y directions is achieved by making the edges of the six separate interposer layers 711, 721, 731, 741, 751, and 761 adjacent (as shown). In this regard, the triangular interposer layers enable the use of at least six triangular interposer layers 711, 721, 731, 741, 751, and 761 to achieve minimal tolerance alignment of quantum modules (such as...). Figure 7B As shown), thus achieving an interlocking pattern with minimal tolerance alignment of the intermediate layer.

[0075] Next, Figure 8A and Figure 8B A method for constructing an intermediary layer for a modular encapsulation structure according to exemplary embodiments of the present disclosure is illustrated schematically. Specifically, Figure 8A A substrate 800 (e.g., a portion of a semiconductor wafer) is schematically illustrated, which is divided (or defined) into multiple interposer regions based on dicing lines (as shown by dashed lines), such as interposer regions 811a, 821a, 831a, 841a, and 851a. A first plurality of interposer regions (e.g., regions 811a, 821a, 831a, 841a) each comprises an octagonal polygon (e.g., an octagon) of the same size and shape, and a second plurality of interposer regions (e.g., region 851a) comprises a square interposer region of the same size and shape.

[0076] Figure 8B The result of the dicing process is illustrated schematically, in which a semiconductor substrate 800 is diced along dicing lines to separate the interposer region into individual interposers. For example, Figure 8B Four separate octagonal intermediate layers 811, 821, 831, and 841 are shown (they correspond to...) Figure 8A The exemplary interposer regions 811a, 821a, 831a, and 841a are shown in the figure, along with a square interposer layer 851 (corresponding to interposer region 851a). In this configuration, five separate interposer layers 811, 821, 831, 841, and 851 can be used to form a modular packaging structure, wherein self-alignment in the X and Y directions is achieved by making the edges of the five separate interposer layers 811, 821, 831, 841, and 851 adjacent (as shown). In this regard, the different shapes of the interposer layers enable the use of at least four octagonal interposer layers 811, 821, 831, and 841 and one square interposer layer 851 to achieve minimal tolerance alignment of the quantum module (e.g., ...). Figure 8B As shown), thus achieving an interlocking pattern with minimal tolerance alignment of the intermediate layer.

[0077] Next, Figure 9A , Figure 9B and Figure 9C A method for constructing an intermediary layer for a modular encapsulation structure according to another exemplary embodiment of this disclosure is schematically illustrated. Specifically, Figure 9A A semiconductor substrate 900 (e.g., a portion of a semiconductor wafer) is schematically shown, which is divided (or defined) into multiple interposer regions based on dicing lines (as shown by dashed lines), such as interposer regions 911a, 921a, 931a, 941a, and 951a. Each interposer region includes a herringbone region of the same size.

[0078] Figure 9BThe result of the dicing process is illustrated schematically, where the substrate 900 is cut along a dicing line to separate the interposer region into individual interposers. For example, Figure 9B Three separate intermediary layers 911, 921, and 931 are shown, which correspond to Figure 9A The exemplary interposer regions 911a, 921a, and 931a are shown in the figure. In this configuration, three separate interposer layers 911, 921, and 931 can be used to form a modular packaging structure, wherein self-alignment in the X and Y directions is achieved by making the edges of the three separate interposer layers 911, 921, and 931 adjacent (as shown). Figure 9C Further examples are shown, in which two separate intermediary layers 941 and 951 (corresponding to...) Figure 9A The exemplary interposer regions 941a and 951a in the figure can be used to form a modular packaging structure in which self-alignment in the X and Y directions is achieved by making the edges of two separate interposers 941 and 951 adjacent (as shown). In this regard, the herringbone interposer makes it possible to use at least two interposers (e.g., interposers 911 and 921). Figure 9B ), and intermediary layers 941 and 951 ( Figure 9C This enables the alignment of quantum modules with minimal tolerance, thereby achieving the interlocking pattern of minimal tolerance alignment of the intermediate layer.

[0079] The exemplary modular packaging structures discussed in this article can be manufactured using state-of-the-art semiconductor manufacturing technologies. For example, Figure 10 A flowchart of a method 1000 for constructing a modular package structure according to an exemplary embodiment of the present disclosure is shown. Multiple quantum chips are fabricated on a first semiconductor wafer (quantum chip wafer) (box 1001), and multiple interposers are fabricated on a second semiconductor wafer (interposer wafer) (box 1002). For example, various qubit dies are fabricated on the quantum chip wafer, each qubit die including various components such as superconducting qubits, tunable couplers, ground layers, signal coplanar waveguides, coupler drive lines, qubit drive lines, readout resonators, coupling capacitor pads, coupling inductors, solder bump bonding pads, etc., which are formed by photolithographically defined patterns of superconducting material on the qubit wafer, for example by deposition, optical lithography, etching, and stripping steps.

[0080] Furthermore, on a given interposer wafer, various interposer regions (or interposer dies) are fabricated as discussed above, each interposer die comprising various components such as wiring for signal I / O, ground layers, solder bump bonding pads, package I / O traces and interconnect transmission lines, and bonding pads, etc. These components include photolithographically defined patterns formed on the interposer wafer using superconducting materials, for example, through deposition, optical lithography, etching, and lift-off steps. The interposer and metallization layers on the quantum chip wafer can be formed using various types of superconducting materials suitable for a given application, including but not limited to elemental metals such as niobium (Nb), aluminum (Al), tantalum (Ta), and compounds such as titanium nitride (TiN), niobium nitride (NbN), and titanium niobium nitride (NbTiN).

[0081] A first semiconductor wafer is diced to create a single quantum chip (or a single qubit die) (box 1003), and a second semiconductor wafer is diced to create a single interposer (box 1004). Then, as discussed above, one or more quantum chips are flip-chip bonded to each of the plurality of interposers to create a quantum module (box 1005). In some embodiments, flip-chip bonding of a given quantum chip to a given interposer is performed by depositing and patterning indium solder bumps on the given interposer, and then using, for example, a thermoforming bonding process to flip-chip bond the given quantum chip to the given interposer to form a current connection between the quantum chip and the interposer.

[0082] Next, electrical tests are performed on individual quantum modules to identify and select modules that function as expected and meet performance requirements (box 1006). Electrical tests may include tests performed at room temperature. Alternatively, electrical tests may be performed at cryogenic temperatures in a cryostat (e.g., a dilution refrigeration system) to test the functionality of superconducting qubits and other superconducting quantum components on the quantum chip. The selected individual quantum modules are then used to form a modular package structure (box 1007), where a given modular package structure is constructed by assembling two or more individual quantum modules together as discussed above, wherein self-alignment of the quantum modules is achieved by utilizing the alignment features of the corresponding intermediate layers.

[0083] Figure 11 A quantum computing system according to an exemplary embodiment of the present disclosure is schematically illustrated. The quantum computing system includes a quantum processor comprising a modular packaging structure constructed using multiple quantum modules. Specifically, Figure 11A quantum computing system 1100 is schematically illustrated, comprising a quantum computing platform 1110, a control system 1120, and a quantum processor 1130. In some embodiments, the control system 1120 includes a multi-channel arbitrary waveform generator (AWG) 1122 and a qubit readout control system 1124. In an exemplary embodiment, the quantum processor 1130 includes at least one modular package structure 1132, which can be implemented using any of the exemplary modular package structures discussed above, depending on the requirements of a given application or quantum system configuration.

[0084] In some embodiments, the control system 1120 and the quantum processor 1130 are arranged within a dilution cooling system 1140, which generates a cryogenic environment sufficient to operate the components of the control system 1120 to support quantum computing applications. For example, the quantum processor 1130 may need to be cooled to near absolute zero (e.g., 10⁻¹⁵ milliklvin (mK)) to allow superconducting qubits to exhibit quantum behavior. In some embodiments, the dilution cooling system 1140 includes a multi-stage dilution refrigerator, wherein the components of the control system 1120 can be maintained at different cryogenic temperatures as needed. For example, the quantum processor 1130 may need to be cooled to, for example, 10⁻¹⁵ mK, while the circuit components of the control system 1120 can operate at cryogenic temperatures above 10⁻¹⁵ mK, depending on the configuration of the quantum computing system. In other embodiments, some or all of the components of the control system 1120 may include electronic components arranged and operated at room temperature.

[0085] In some embodiments, the multi-channel AWG 1122 and other suitable microwave pulse signal generators are configured to generate microwave control pulses applied to the qubit drive lines and coupler drive lines to control the operation of the superconducting qubits and associated qubit coupler circuitry while performing various gate operations to run a given quantum information processing algorithm. In some embodiments, the multi-channel AWG 1122 includes multiple AWG channels that control corresponding superconducting qubits on a quantum chip within the modular package structure 1132 of the quantum processor 1130. In some embodiments, each AWG channel includes a baseband signal generator, a digital-to-analog converter (DAC) stage, a filter stage, a modulation stage, an impedance matching network, and a phase-locked loop system for generating local oscillator (LO) signals (e.g., quadrature LO signals LO_I and LO_Q) for the corresponding modulation stage of the corresponding AWG channel.

[0086] In some embodiments, the multi-channel AWG 1122 includes an orthogonal AWG system configured to process orthogonal signals, wherein the orthogonal signals include in-phase (I) signal components and quadrature (Q) signal components. In each AWG channel, a baseband signal generator is configured to receive baseband data as input (e.g., from a quantum computing platform) and generate digital quadrature signals I and Q representing the input baseband data. During this process, the baseband data input to the baseband signal generator of a given AWG channel is separated into two orthogonal digital components, including an in-phase (I) baseband component and a quadrature (Q) baseband component. The baseband signal generator of a given AWG channel generates the desired digital quadrature baseband IQ signals to generate an analog waveform (e.g., a sinusoidal voltage waveform) with a target center frequency, which is configured to operate or otherwise control one or more qubits coupled to the output of the given AWG channel.

[0087] The DAC stage of a given AWG channel is configured to convert a digital baseband signal (e.g., a digital IQ signal output from a baseband signal generator) into an analog baseband signal (e.g., analog baseband signals I(t) and Q(t)) having baseband frequencies. The filter stage of a given AWG channel is configured to filter the IQ analog signal components output from the DAC stage to generate a filtered analog IQ signal. The modulation stage of a given AWG channel is configured to perform analog IQ signal modulation (e.g., single-sideband (SSB) modulation) by mixing the filtered analog signals I(t) and Q(t) output from the filter stage with quadrature LO signals (e.g., in-phase LO signals (LO_I) and quadrature LO signals (LO_Q)) to generate and output an analog RF signal (e.g., a SSB-modulated RF output signal).

[0088] In some embodiments, the qubit readout control system 1124 includes: a microwave pulse signal generator configured to apply a microwave pulse tone to a given readout resonator line of a given superconducting qubit to perform a readout operation, thereby reading the state of the given superconducting qubit; and circuitry configured to process the readout signal generated by the readout resonator line to determine the state of the given superconducting qubit, utilizing techniques known to those skilled in the art. For example, in some embodiments, the qubit readout line of the given qubit includes a coplanar waveguide resonator configured to have a resonant frequency detuned to the transition frequency of the given qubit, thereby enabling a dispersive readout operation for reading the quantum state of the given qubit coupled to the given readout resonator. The dispersive readout operation involves applying an RF readout control signal (RF_RO) to the given readout resonator and detecting / processing the readout signal reflected back from the given readout resonator. The RF readout control signal applied to the given readout resonator has a single frequency tone that is the same as or similar to the resonant frequency of the readout resonator, a pulse envelope having a given pulse shape (e.g., a Gaussian pulse envelope), and a given pulse duration. In the dispersion region of the qubit-resonator coupling, the RF readout control signal interacts with a given qubit / resonator system, and the resulting output readout signal reflected from a given readout resonator includes information (e.g., phase and / or amplitude) that depends on the qubit state.

[0089] The quantum computing platform 1110 includes software and hardware platforms, comprising various software layers configured to perform various functions, including but not limited to: generating and implementing various quantum applications using a suitable quantum programming language, configuring and implementing various quantum gate operations, compiling quantum programs into quantum assembly language, and implementing and utilizing a suitable quantum instruction set architecture (ISA). Furthermore, the quantum computing platform 1110 includes a hardware architecture such as a processor and memory, configured to control the execution of quantum applications and interfaced with a control system 1120 to: (i) generate digital control signals, which are converted by the control system 1120 into analog microwave control signals to control the operation of the quantum processor 1130 when executing a given quantum application; and (ii) acquire and process digital signals received from the control system 1120, representing the processing results generated by the quantum processor 1130 when executing various gate operations of a given quantum application.

[0090] In some exemplary embodiments, the quantum computing platform 1110 of the quantum computing system 1100 may be implemented using any suitable computing system architecture configured to implement methods supporting quantum computing operations by executing computer-readable program instructions embodied on a computer program product, the computer program product including one or more computer-readable storage media having such computer-readable program instructions thereon for causing a processor to execute the control methods discussed herein.

[0091] The description of various embodiments of this disclosure has been presented for illustrative purposes and is not intended to be exhaustive, nor is it limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles of the embodiments, practical applications of the prior art, or technical improvements, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A packaging structure, comprising: A first intermediary layer, the first intermediary layer including a first alignment feature; A second intermediary layer, the second intermediary layer including a second alignment feature; as well as A quantum chip, said quantum chip being bonded to the first interposer layer, wherein an extension of the first quantum chip extends beyond a first edge of the first interposer layer; The first interposer layer and the second interposer layer are arranged such that the first alignment feature and the second alignment feature are engaged to achieve alignment and coupling of one or more components on the extension portion of the first quantum chip with one or more components on the second interposer layer.

2. The packaging structure according to claim 1, wherein: The first interposer layer and the second interposer layer are arranged in a plane; and The first alignment feature engages with the second alignment feature to achieve alignment in the first orthogonal direction and the second orthogonal direction of the plane.

3. The packaging structure according to any one of the preceding claims, wherein: The first alignment feature includes the first edge of the first intermediary layer; The second alignment feature includes the second edge of the second intermediary layer; as well as The engagement of the first alignment feature and the second alignment feature includes the first edge being adjacent to the second edge to achieve the alignment and coupling of the one or more components on the extension portion of the quantum chip with the one or more components on the second interposer layer.

4. The packaging structure according to any of the preceding claims, wherein the first alignment feature is fitted within the second alignment feature to achieve the alignment and coupling of the one or more components on the extension portion of the quantum chip with the one or more components on the second interposer layer.

5. The packaging structure according to any one of the preceding claims, wherein: The first alignment feature includes a groove feature; The second alignment feature includes a tongue-shaped feature; and The second alignment feature is fitted within the first alignment feature to achieve the alignment and coupling of the one or more components on the extension portion of the quantum chip with the one or more components on the second intermediary layer.

6. The packaging structure according to claim 5, wherein the groove feature and the tongue feature include corresponding V-shaped features.

7. The packaging structure according to any one of the preceding claims, wherein: The first alignment feature includes a first alignment feature pattern; The second alignment feature includes a second alignment feature pattern; and The first alignment feature pattern and the second alignment feature pattern are interleaved to achieve the alignment and coupling of the one or more components on the extension portion of the quantum chip with the one or more components on the second interposer layer.

8. A packaging structure, comprising: A first intermediary layer, the first intermediary layer including a first edge; A second intermediary layer, the second intermediary layer including a second edge; as well as A first quantum chip, the first quantum chip being bonded to the first interposer layer, wherein an extension portion of the first quantum chip extends beyond the first edge of the first interposer layer; The first interposer layer and the second interposer layer are arranged in a plane having adjacent first and second edges to achieve alignment and coupling of one or more components on the extension of the first quantum chip with one or more components on the second interposer layer.

9. The packaging structure of claim 8, wherein the first edge and the second edge are adjacent to each other to achieve the alignment in a first orthogonal direction and a second orthogonal direction of the plane.

10. The packaging structure according to any one of claims 8 to 9, wherein: The first intermediary layer includes a first shape that is at least partially defined by the first edge; The second intermediate layer includes a second shape at least partially defined by the second edge; and The first shape and the second shape are different shapes.

11. The packaging structure according to any one of claims 8 to 10, wherein: The first intermediary layer includes a first shape that is at least partially defined by the first edge; The second intermediate layer includes a second shape at least partially defined by the second edge; and The first shape and the second shape are the same shape.

12. The packaging structure according to any one of claims 8 to 11, wherein: The second intermediary layer includes a second quantum chip; The one or more components on the second intermediary layer include transmission lines coupled to the second quantum chip; and The one or more components on the extension portion of the first quantum chip include one or more qubits.

13. The packaging structure according to any one of claims 8 to 12 further comprises a third interposer layer, the third interposer layer including a third edge, wherein: The first intermediary layer includes a second edge; The first quantum chip is bonded to the first interposer layer, wherein a second extension portion of the first quantum chip extends beyond the second edge of the first interposer layer; The third intermediary layer is arranged on the plane along with the first and second intermediary layers; as well as The second edge of the first interposer layer and the third edge of the third interposer layer are adjacent to each other to achieve alignment and coupling of one or more components on the second extension of the first quantum chip with one or more components on the third interposer layer.

14. The packaging structure according to claim 13, wherein: The first intermediary layer includes a first shape that is at least partially defined by the first edge and the second edge of the first intermediary layer; The second intermediary layer includes a second shape that is at least partially defined by the second edge of the second intermediary layer; The third intermediary layer includes a third shape at least partially defined by the third edge of the third intermediary layer; and The first shape, the second shape, and the third shape are the same shape.

15. The packaging structure according to claim 13, wherein: The first intermediary layer includes a first shape that is at least partially defined by the first edge and the second edge of the first intermediary layer; The second intermediary layer includes a second shape that is at least partially defined by the second edge of the second intermediary layer; The third intermediary layer includes a third shape that is at least partially defined by the third edge of the third intermediary layer; The second shape and the third shape are the same shape; and The first shape is different from the second shape and the third shape.

16. The packaging structure according to claim 13, wherein: The third intermediary layer includes a third quantum chip; The one or more components on the third intermediary layer include transmission lines coupled to the third quantum chip; and The one or more components on the second extension of the first quantum chip include one or more qubits.

17. A packaging structure, comprising: A first module includes a first interposer layer and a first quantum chip. The first interposer layer includes a first edge, and the first quantum chip is bonded to the first interposer layer, wherein an extension portion of the first quantum chip extends beyond the first edge of the first interposer layer. as well as The second module includes a second interposer layer, a second quantum chip, and a transmission line. The second interposer layer includes a second edge. The second quantum chip is bonded to the second interposer layer. The transmission line is disposed on the second interposer layer and coupled to the second quantum chip. The first and second interposers are arranged in a plane, wherein the first and second edges are adjacent to each other to achieve alignment and coupling of one or more components on the extension of the first quantum chip with one or more transmission lines on the second interposer, the one or more transmission lines being coupled to the second quantum chip.

18. The packaging structure of claim 17, wherein the first edge and the second edge are adjacent to each other to achieve alignment in a first orthogonal direction and a second orthogonal direction of the plane.

19. The packaging structure according to any one of claims 17 to 18, wherein: The first intermediary layer includes a first shape that is at least partially defined by the first edge; The second intermediate layer includes a second shape at least partially defined by the second edge; and The first shape and the second shape are one of different shapes and the same shape.

20. The packaging structure according to any one of claims 17 to 19, wherein the first module further comprises: A third quantum chip bonded to the first interposer layer, and a transmission line disposed on the first interposer layer, the transmission line coupling the first quantum chip and the third quantum chip.

21. A method comprising: An intermediate layer is formed on the substrate; as well as The substrate is cut to separate the interposer layer into at least a first interposer layer and a second interposer layer, the first interposer layer including a first edge and the second interposer layer including a second edge; Wherein, when the first edge and the second edge are adjacent and the first intermediary layer and the second intermediary layer are arranged in a plane, the first edge and the second edge are configured to achieve alignment of the structure on the first intermediary layer with the structure on the second intermediary layer.

22. The method according to claim 21, wherein: The first intermediary layer includes a first shape that is at least partially defined by the first edge; The second intermediate layer includes a second shape at least partially defined by the second edge; and The first shape and the second shape are different shapes.

23. The method according to any one of claims 21 to 22, wherein: The first intermediary layer includes a first shape that is at least partially defined by the first edge; The second intermediate layer includes a second shape at least partially defined by the second edge; and The first shape and the second shape are the same shape.

24. A method comprising: A first module is constructed, the first module including a first intermediary layer and a first quantum chip, the first intermediary layer including a first edge, the first quantum chip being bonded to the first intermediary layer, wherein an extension portion of the first quantum chip extends beyond the first edge of the first intermediary layer; A second module is constructed, which includes a second intermediary layer, a second quantum chip, and a transmission line. The second intermediary layer includes a second edge, the second quantum chip is bonded to the second intermediary layer, and the transmission line is arranged on the second intermediary layer and coupled to the second quantum chip. as well as Assemble the first module and the second module, wherein the first interposer layer and the second interposer layer are arranged in a plane having adjacent first edges and second edges to achieve alignment and coupling of one or more components on the extension portion of the first quantum chip with one or more transmission lines on the second interposer layer, the one or more transmission lines being coupled to the second quantum chip.

25. The method of claim 24, wherein: The first intermediary layer includes a first shape that is at least partially defined by the first edge; The second intermediate layer includes a second shape at least partially defined by the second edge; and The first shape and the second shape are one of different shapes and the same shape.

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