Metastable state simulation method in pre-silicon simulation and electronic device

Abstract

The application provides a metastable state simulation method in pre-silicon simulation and electronic equipment, and relates to the chip design technical field. The method comprises the following steps: locating first-stage registers of each asynchronous flip-flop in a register transfer level code. The sampling exception probability value and the probability adjustment strategy of each first-stage register are configured, and a loop process is executed until the pre-silicon simulation is finished, so as to obtain a simulation result. The loop process comprises the following steps: in each clock cycle, it is judged whether the current input value of the first-stage register is same as the current output value; if yes, the current output value of the first-stage register is updated to the current input value; if not, it is randomly determined according to the sampling exception probability value whether the current sampling is normal updating or keeping the current output value, and the random result is recorded, and the sampling exception probability value is updated according to the random result and the probability adjustment strategy, and is used for next sampling. The technical scheme can improve the detection coverage and verification efficiency of the asynchronous path defects.

Description

Technical Field

[0001] This application relates to the field of chip design technology, and more specifically, to a metastable simulation method and electronic device in chip pre-simulation. Background Technology

[0002] In the chip design process, pre-simulation (i.e., register-transfer level simulation) is a crucial step in verifying the correctness of the design logic. Among these steps, asynchronous paths across clock domains (CDC) are a major risk factor leading to chip malfunctions, with metastability being the most typical problem. Metastability refers to the situation where asynchronous signals, when sampled at the clock edge, fail to meet the register's setup or hold time requirements, resulting in an unstable state at the register output. This instability may cause the register to maintain its original output instead of sampling correctly, thus triggering subsequent circuit malfunctions.

[0003] To simulate the impact of metastability on chip functionality, existing pre-simulation techniques mainly employ the following methods: injecting metastable simulation signals with a fixed probability into the first-stage register of the asynchronous beater, or simply inserting a fixed delay to simulate hardware physical characteristics, thereby achieving metastability simulation. While this approach can simulate metastability to some extent, due to the fixed probability of anomalies, it cannot adapt to different hardware operating conditions such as continuous, bursty, and balanced metastability. This results in poor consistency between the pre-simulation results and the actual metastable behavior of the hardware, easily overlooking some hidden asynchronous path defects that only surface under specific probability modes. Furthermore, this method has low simulation accuracy; simply injecting signals or inserting delays cannot accurately reproduce the metastable behavior in the hardware, making it difficult to detect real asynchronous defects in advance during the pre-simulation stage.

[0004] Therefore, how to accurately and comprehensively simulate metastable behavior in the pre-simulation stage to improve the detection coverage and verification efficiency of asynchronous path defects is a technical problem that urgently needs to be solved in this field. Summary of the Invention

[0005] The purpose of this application is to provide a metastable simulation method and electronic device in chip pre-simulation, which can accurately and comprehensively simulate metastable behavior in the pre-simulation stage, thereby improving the detection coverage and verification efficiency of asynchronous path defects.

[0006] This application is implemented as follows: Firstly, this application provides a metastable state simulation method in chip pre-simulation, comprising the following steps: Locating the first-level registers of each asynchronous beater in the register transfer stage code. Configuring the sampling anomaly probability value and probability adjustment strategy for each first-level register, wherein the sampling anomaly probability value is the probability that the first-level register maintains its current output value when the current input value of the first-level register differs from the current output value, and the probability adjustment strategy is a rule for adjusting the sampling anomaly probability in the next sampling based on the current random result. Executing a loop process until the pre-simulation ends to obtain the simulation result. The loop process includes: in each clock cycle, determining whether the current input value and current output value of the first-level register are the same; if they are the same, updating the current output value of the first-level register to the current input value; if they are different, randomly determining whether the current sampling is a normal update or maintaining the current output value based on the sampling anomaly probability value, recording the random result, and updating the sampling anomaly probability value based on the random result and the probability adjustment strategy for the next sampling.

[0007] In some implementations, the probability adjustment strategy is one of three: a propensity to maintain, a propensity to adopt new values, or a propensity to be fair. Specifically, a propensity to maintain is a strategy that keeps the first-level register at its current output value, used to simulate scenarios where metastability persists; a propensity to adopt new values ​​is a strategy that updates the output of the first-level register to its current input value, used to simulate scenarios where correct sampling is prioritized; and a propensity to be fair is a strategy that balances the probability of the first-level register maintaining its current output value with the probability of it being updated to its current input value, used to simulate scenarios where metastability is balanced.

[0008] In some implementations, the probability adjustment strategy is one of a hold-for-maintenance strategy, a new-adoption strategy, or a fairness-oriented strategy. The step of updating the sampling anomaly probability value based on the current random result and the probability adjustment strategy includes: When the current random result is a normal update: if the probability adjustment strategy is a hold-for-maintenance strategy, increase the sampling anomaly probability value for the next sampling; if the probability adjustment strategy is a new-adoption strategy, maintain or decrease the sampling anomaly probability value for the next sampling; if the probability adjustment strategy is a fairness-oriented strategy, increase the sampling anomaly probability value for the next sampling. When the current random result is to maintain the current output value: if the probability adjustment strategy is a hold-for-maintenance strategy, maintain or increase the sampling anomaly probability value for the next sampling; if the probability adjustment strategy is a new-adoption strategy, decrease the sampling anomaly probability value for the next sampling; if the probability adjustment strategy is a fairness-oriented strategy, decrease the sampling anomaly probability value for the next sampling.

[0009] In some implementations, configuring the sampling anomaly probability value of each first-level register includes setting the initial value of the sampling anomaly probability value of each first-level register to 50%.

[0010] In some implementations, when updating the sampling anomaly probability value, the adjustment range is a preset fixed value or a dynamically configurable value, and the updated sampling anomaly probability is limited to the range of 0% to 100%.

[0011] In some implementations, the metastable simulation method in the chip pre-simulation also includes: during the execution loop, when the current random result maintains the current output value and causes subsequent circuit functions to malfunction, outputting a defect alarm and corresponding sampling log.

[0012] In some implementations, the metastable simulation method in the pre-simulation of the chip also includes: in response to the end of the current pre-simulation, generating a coverage report based on the simulation results. The coverage report contains at least one of the following information: full path information of each first-level register, the number of times each first-level register performs a normal update, and the number of times each first-level register performs an operation to maintain the current output value.

[0013] In some implementations, the metastable simulation method in the chip pre-simulation also includes: in the second and subsequent pre-simulations, based on the simulation results and coverage report obtained at the end of the previous pre-simulation, using a preset neural network model to adaptively update the initial sampling anomaly probability value and probability adjustment strategy for the next pre-simulation.

[0014] In some implementations, the steps of adaptively updating the initial sampling anomaly probability value and probability adjustment strategy for the next pre-simulation include: if the previous pre-simulation did not detect a functional anomaly, adjusting the initial sampling anomaly probability value for the next pre-simulation based on the difference between the number of normal updates and the number of times the current output value was held in the coverage report, so that the next pre-simulation tends to cover sampling result types with fewer coverage occurrences; if the previous pre-simulation detected a functional anomaly, switching the probability adjustment strategy to a hold-forward strategy or a new sampling strategy based on the difference between the number of normal updates and the number of times the current output value was held in the coverage report, so that the next pre-simulation tends to maintain the sampling trend that triggered the functional anomaly.

[0015] In a second aspect, this application provides an electronic device including a memory for storing one or more programs; a processor; and, when the one or more programs are executed by the processor, implementing the method as described in any one of the first aspects above.

[0016] Compared with the prior art, this application has at least the following advantages or beneficial effects: First, this application determines whether the current input value and the current output value of the first-level register are the same in each clock cycle, and randomly determines whether the current sampling is a normal update or maintains the current output value based on the sampling anomaly probability value when they are different. This accurately reproduces the core behavior of the hardware where metastability causes the register to maintain the original output and cannot be sampled correctly. Its simulation accuracy is significantly better than simple injection of metastable analog signals or insertion of fixed delay schemes.

[0017] Secondly, this application configures a probability adjustment strategy and dynamically updates the sampling anomaly probability value for the next sampling based on each random result, so that the sampling anomaly probability can adapt to the simulation process. This makes it easier to adapt to the defects of different hardware conditions such as metastable continuous, burst, and equilibrium, and can improve the consistency between the pre-simulation results and the actual hardware behavior.

[0018] In addition, this application records each random result during the loop process, thereby providing a data basis for the number of normal updates and the number of times the current output value is maintained for subsequent verification coverage analysis. This makes it easier for technicians to judge the comprehensiveness of the verification coverage and optimize the design accordingly. Attached Figure Description

[0019] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a flowchart of an embodiment of a metastable state simulation method in chip pre-simulation according to this application; Figure 2 This is a flowchart of yet another embodiment of a metastable state simulation method in chip pre-simulation according to this application; Figure 3 This is a flowchart of another embodiment of a metastable state simulation method in chip pre-simulation according to this application; Figure 4 This is a structural block diagram of an electronic device provided in an embodiment of this application.

[0021] Icons: 201, Processor; 202, Memory; 203, Communication Interface. Detailed Implementation

[0022] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. It should be understood that this application is not limited to the exemplary embodiments described herein.

[0023] In this document, relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, without necessarily requiring or implying any such actual relationship or order between these entities or operations.

[0024] To facilitate understanding of the technical solutions provided in this application, some concepts will be introduced below.

[0025] 1. Pre-simulation of a chip: This refers to the process of verifying the logic function of a chip design using computer software after the code has been written but before it has been converted into an actual physical circuit. Its main purpose is to confirm whether the design function is correct, without focusing on the physical delay or other characteristics of the circuit.

[0026] 2. Register-Transfer Level (RTL) code: This refers to the code that uses a hardware description language (such as Verilog or VHDL) to describe the data flow and logic functions of a digital circuit. At this level, chip design is abstracted into the data storage and transfer between registers, and the processing of this data by combinational logic. It is the core output of chip front-end design and the primary object of pre-simulation.

[0027] 3. Metastability: This refers to the unstable state at the output of a flip-flop in a digital circuit when the input signal changes near the clock edge during sampling, causing it to fail to meet the setup or hold time requirements. This state may eventually stabilize randomly at a high or low level, thus causing subsequent circuit malfunctions.

[0028] 4. Asynchronous beater: This refers to a circuit structure used to handle the synchronization of signals across clock domains. It is usually composed of two or more flip-flops connected in series. Its function is to reduce the probability of metastability propagation and enable signals from one clock domain to be sampled stably and reliably by another clock domain.

[0029] 5. First-level register: This refers to the first flip-flop in the asynchronous beater that directly receives the input signal from the asynchronous clock domain. This first-level register is where metastability first occurs and is also the most critical sampling node in the cross-clock domain synchronization process.

[0030] In the pre-simulation stage of the chip, to simulate the impact of metastability on chip functionality, existing solutions mainly inject metastable analog signals with a fixed probability at the first-stage register of the asynchronous beater, or simply insert a fixed delay to simulate the physical characteristics of the hardware, thereby achieving metastability simulation. However, the inventors found through analysis that existing solutions have the following drawbacks: the sampling anomaly probability is fixed, which cannot adapt to the continuous, burst, and balanced changes in metastability under different hardware operating conditions, resulting in poor consistency between simulation results and actual hardware behavior, and easily overlooking hidden asynchronous path defects; at the same time, the simulation accuracy is low, and it cannot accurately reproduce the core behavior in the hardware where metastability causes the register to maintain its original output and fail to sample correctly.

[0031] To address the problems existing in existing solutions, this application provides a metastable state simulation method and electronic device in chip pre-simulation. By configuring dynamically adjustable sampling anomaly probability values ​​and a probability adjustment strategy based on random result feedback for the first-level register of the asynchronous beater, and triggering random sampling decisions and probability updates based on input-output differences in each clock cycle, metastable behavior can be accurately and comprehensively simulated in the pre-simulation stage. This effectively improves the consistency between simulation and hardware and accelerates the convergence of verification coverage, thereby improving the detection coverage and verification efficiency of asynchronous path defects.

[0032] After introducing the basic principles of this application, various non-limiting embodiments of this application will be described in detail below with reference to the accompanying drawings. Unless otherwise specified, the various embodiments and features described below can be combined with each other.

[0033] Please see Figure 1 The metastable simulation method in the pre-simulation of this chip includes the following steps: Step S101: Locate the first-level registers of each asynchronous beater in the register transfer level code.

[0034] In the pre-simulation environment, scan and identify all asynchronous beater circuit structures used for cross-clock domain signal synchronization in the register transfer level code (project teams typically require the use of standard asynchronous beater cells), and further locate the first-stage register in each asynchronous beater. This first-stage register is the sampling point that directly receives the asynchronous input signal and is also the node where metastability is most likely to occur.

[0035] Step S102: Configure the sampling anomaly probability value and probability adjustment strategy for each first-level register. The sampling anomaly probability value is the probability that the first-level register will maintain the current output value when the current input value of the first-level register is different from the current output value. The probability adjustment strategy is the rule for adjusting the sampling anomaly probability of the next sampling based on the current random result.

[0036] Before proceeding with the pre-simulation, two parameters need to be configured for each identified first-level register. The first parameter is the sampling anomaly probability value, which represents the probability that the register will choose to maintain the current output value (i.e., simulate sampling failure caused by metastability) when the current input value of the first-level register differs from the current output value. The second parameter is the probability adjustment strategy, which defines the specific rules for adjusting the sampling anomaly probability value for the next sampling based on the random result of the current sampling.

[0037] In other words, step S102 enables differentiated simulation control of different asynchronous paths by independently configuring sampling anomaly probability values ​​and probability adjustment strategies for each first-level register, and provides initial conditions and adjustment basis for subsequent dynamic probability adjustment, making the simulation process configurable and flexible.

[0038] Step S103: Execute the loop process until the pre-simulation ends to obtain the simulation results. The loop process includes: in each clock cycle, determining whether the current input value and current output value of the first-level register are the same; if they are the same, updating the current output value of the first-level register to the current input value; if they are different, randomly determining whether the current sampling is a normal update or maintaining the current output value based on the sampling anomaly probability value, recording the random result, and updating the sampling anomaly probability value based on the random result and the probability adjustment strategy for the next sampling.

[0039] During the pre-simulation process, the following operations are performed on each Level 1 register within each clock cycle: First, it is determined whether the current input value and current output value of the Level 1 register are the same. If they are the same, there is no risk of metastability, and the register performs the sampling action normally, updating the current output value to the current input value. If they are different, there is a risk of metastability, and a random decision mechanism is triggered: based on the currently configured sampling anomaly probability value, it is randomly decided whether to perform a normal update (i.e., update the current output value to the current input value) or to maintain the current output value (i.e., simulate sampling failure caused by metastability). After the random decision is completed, the random result (i.e., whether the current sampling is a normal update or maintains the current output value) is recorded. Subsequently, based on the random result and the preset probability adjustment strategy, the sampling anomaly probability value is calculated and updated. This updated probability value will be used for the random decision in the next sampling (sampling in the next clock cycle). The above process is repeated in each clock cycle until the entire pre-simulation process ends, finally obtaining the simulation results containing the sampling behavior records of each Level 1 register. Generally, the criteria for determining the end of a pre-simulation process are usually that the simulation time reaches the preset test case execution time or the simulator receives a specific completion / end instruction.

[0040] As can be seen, step S103 introduces a random judgment based on the sampling anomaly probability value when the input and output values ​​differ. This allows the proposed solution to accurately reproduce the core behavior of metastability in hardware, where registers maintain their original outputs and fail to sample correctly, effectively improving the accuracy of metastability simulation. Furthermore, by dynamically updating the sampling anomaly probability value based on the random result in each clock cycle, the simulation process can adaptively adapt to different hardware conditions such as persistent, bursty, and balanced metastability, improving the consistency between pre-simulation results and actual hardware behavior. Simultaneously, each recorded random result can not only be used for subsequent targeted updates to the sampling anomaly probability value to adjust the next sampling, but also provide a data foundation for subsequent verification coverage analysis and design optimization.

[0041] In summary, this application, by locating the first-stage registers of the asynchronous beater and configuring dynamically adjustable sampling anomaly probability values ​​and a probability adjustment strategy based on random result feedback for each first-stage register, enables accurate dynamic simulation of metastable behavior during pre-simulation. That is, instead of using fixed probabilities, this application determines the sampling behavior based on the current sampling anomaly probability value in each clock cycle during pre-simulation. When maintaining the current output value (i.e., simulating sampling failures caused by metastability), the probability value for the next sampling is updated in real-time based on the current random result, thereby accurately simulating the changing characteristics of metastability under different operating conditions.

[0042] In other words, through the aforementioned dynamic adjustment mechanism, this application can effectively solve the shortcomings of existing schemes that use fixed probabilities, which cannot adapt to different hardware operating conditions such as continuous metastability, sudden bursts, and equilibrium. At the same time, it can effectively reproduce the core behavior of the hardware where metastability causes the register to maintain its original output and fail to sample correctly, thereby improving the consistency between the pre-simulation results and the actual hardware behavior, and increasing the detection coverage of asynchronous path defects.

[0043] Based on the aforementioned scheme, in some implementations of this application, the probability adjustment strategy is one of a tendency to maintain, a tendency to adopt new values, or a tendency to be fair. Specifically, the tendency to maintain is a strategy that keeps the first-level register at its current output value, used to simulate scenarios where metastability persists; the tendency to adopt new values ​​is a strategy that updates the output of the first-level register to its current input value, used to simulate scenarios where correct sampling is prioritized; and the tendency to be fair is a strategy that balances the probability of the first-level register maintaining its current output value with the probability of it being updated to its current input value, used to simulate scenarios where metastability is balanced.

[0044] Understandably, this implementation introduces three selectable mutually exclusive strategies as probability adjustment strategies, enabling pre-simulation to select the corresponding simulation mode for different hardware operating conditions. In other words, this implementation concretizes the probability adjustment strategy into a tendency to maintain, a tendency to adopt new methods, or a tendency to be fair, corresponding to three scenarios: persistent metastable states, priority to correct sampling, and balanced metastable states, respectively. Through this approach, this implementation can overcome the shortcomings of existing technologies that use a single fixed probability, which cannot adapt to different hardware operating conditions. It can also accurately simulate the metastable behavior of actual hardware under different operating conditions, thereby improving the consistency between pre-simulation and actual hardware behavior.

[0045] It should be noted that the probability adjustment strategy can be implemented by configuring three simulation parameters: the tendency to maintain Q parameter, the tendency to sample new D parameter, and the tendency to be fair DQ parameter. The tendency to maintain Q parameter corresponds to the tendency to maintain strategy, which biases the first-stage register in maintaining the original output signal Q value during sampling, simulating a scenario where metastability persists. The tendency to sample new D parameter corresponds to the tendency to sample new strategy, which biases the first-stage register in updating to the input signal D value during sampling, simulating a scenario where correct sampling is prioritized. The tendency to be fair DQ parameter corresponds to the tendency to be fair strategy, which balances the tendency of the first-stage register during sampling, making the probabilities of successful and failed sampling tend to be balanced, simulating a scenario where metastability is balanced.

[0046] The three simulation parameters are mutually exclusive, meaning only one parameter can be valid at any given time to avoid conflicting adjustment directions. In practical applications, users can determine which simulation parameter is valid as needed, allowing them to select one strategy as the probabilistic adjustment strategy for the current simulation. The configuration of the three simulation parameters can be dynamically passed through a general verification methodology configuration library (e.g., the config_db mechanism in the UVM configuration library), supporting real-time adjustments during simulation to adapt to the metastable simulation requirements of different scenarios.

[0047] Based on the aforementioned scheme, in some implementations of this application, the probability adjustment strategy is one of a strategy favoring preservation, a strategy favoring adoption of new features, or a strategy favoring fairness. The step of updating the sampling anomaly probability value according to the current random result and the probability adjustment strategy includes: When the current random result is a normal update: if the probability adjustment strategy is a strategy favoring preservation, then increase the sampling anomaly probability value for the next sampling; if the probability adjustment strategy is a strategy favoring adoption of new features, then maintain or decrease the sampling anomaly probability value for the next sampling; if the probability adjustment strategy is a strategy favoring fairness, then increase the sampling anomaly probability value for the next sampling. When the current random result is to maintain the current output value: if the probability adjustment strategy is a strategy favoring preservation, then maintain or increase the sampling anomaly probability value for the next sampling; if the probability adjustment strategy is a strategy favoring adoption of new features, then decrease the sampling anomaly probability value for the next sampling; if the probability adjustment strategy is a strategy favoring fairness, then decrease the sampling anomaly probability value for the next sampling.

[0048] Understandably, this implementation determines whether to increase, maintain, or decrease the sampling anomaly probability value based on whether the current random result is a normal update or the current output value is maintained, combined with the currently selected probability adjustment strategy type. This enables targeted dynamic adjustment of the sampling anomaly probability value. This avoids the problems of existing solutions that cannot dynamically adjust probabilities and lack a basis for adjustment direction. In other words, this implementation establishes a rule corresponding to the combination of random results and strategy types, allowing the sampling anomaly probability value to change in a predetermined direction, thereby accurately simulating the probability evolution characteristics under different hardware conditions such as continuous metastable states, priority correct sampling, or metastable equilibrium.

[0049] In this implementation, assuming the probability adjustment strategy is as described above, implemented by configuring three simulation parameters (these three simulation parameters are mutually exclusive): a tendency to maintain Q parameter, a tendency to sample new D parameter, and a tendency to ensure fairness DQ parameter. Therefore, in this implementation, after each random judgment, the sampling anomaly probability for the next sampling will be adjusted synchronously based on the current random result and the three preset simulation parameters. The specific adjustment rules are as follows: (1) If the current random result is a normal update, that is, the current random result is "update Q to the value of D" (sampling successful): If the FairDQ parameter is configured to be in an effective state, the probability of sampling anomaly P in the next sampling will be increased, thereby increasing the probability of sampling failure in the next sampling and making the probability of sampling failure and sampling success more balanced. If the configuration bias towards acquiring the new D parameter (UpdateD) is in a valid state, then the sampling anomaly probability P of the next sampling is maintained or reduced, and the first-level register continues to be biased towards correctly acquiring the current input signal D; If the configuration tends to keep the Q parameter (KeepQ) in a valid state, the sampling anomaly probability P of the next sampling is increased, thereby increasing the probability of the next sampling failure to simulate the sudden occurrence of metastability.

[0050] (2) If the current random result is to keep the current output value, that is, if the current random result is "keep the current Q value" (sampling failed): If the FairDQ parameter is configured to be in an effective state, the reverse probability of the sampling failure probability P in the next sampling (i.e. the sampling success probability) is increased, and the probability of the next sampling failure is decreased, so that the sampling failure and sampling success probabilities tend to be balanced. If the configuration favors the new D parameter (UpdateD) to be in a valid state, it further reduces the probability of sampling anomalies P in the next sampling and increases the probability of successful sampling, tending to allow the first-level register to correctly acquire the current input signal D in the next sampling. If the configuration tends to keep the Q parameter (KeepQ) in a valid state, then the sampling anomaly probability P of the next sampling will be maintained or increased, tending to keep the first-level register in its original state to simulate a continuous metastable scenario.

[0051] Based on the aforementioned scheme, in some implementations of this application, configuring the sampling anomaly probability value of each first-level register includes configuring the initial value of the sampling anomaly probability value of each first-level register to 50%.

[0052] Understandably, this implementation sets the initial sampling anomaly probability value to 50%, providing a neutral starting point for subsequent dynamic adjustments. This 50% initial probability means that when the current input value and the current output value in the first-level register differ, maintaining the current output value and updating to the current input value have equal chances. This 50% initial probability ensures the simulation starts from an equilibrium state, neither favoring frequent sampling failures nor frequent sampling successes, providing a fair benchmark for subsequent evolution in different directions based on the probability adjustment strategy.

[0053] Based on the aforementioned scheme, in some implementations of this application, when updating the sampling anomaly probability value, the adjustment range is a preset fixed value or a dynamically configurable value, and the updated sampling anomaly probability is limited to the range of 0% to 100%.

[0054] Understandably, when updating the sampling anomaly probability value, the increment or decrement can be preset to a fixed value (e.g., 10%), or dynamically configured according to actual conditions. This allows for control over the adjustment range, preventing drastic fluctuations in the probability value that could lead to simulation distortion. Furthermore, by limiting the updated sampling anomaly probability value to a closed interval of 0% to 100%, it ensures that the sampling anomaly probability value always retains its probabilistic meaning, avoiding negative values ​​or invalid values ​​exceeding 100%, thus enabling accurate simulation of metastable behavior.

[0055] Based on the aforementioned scheme, in some implementations of this application, the metastable simulation method in the chip pre-simulation also includes: during the execution loop, when the current random result is to maintain the current output value and cause subsequent circuit functions to malfunction, outputting a defect alarm and corresponding sampling log.

[0056] Understandably, if a failure to sample the first-level register (maintaining the original Q value) during pre-simulation leads to functional abnormalities in subsequent circuits, it can be determined that there is a design flaw in the corresponding asynchronous path. Therefore, when a sampling failure triggers a functional abnormality, an alarm message can be proactively output, enabling real-time detection and location of asynchronous path defects. This facilitates designers in quickly identifying design problems. The sampling log records relevant sampling information when the abnormality is triggered. After receiving a defect alarm, designers can analyze this sampling log to accurately determine which first-level register failed to sample at what time, causing the functional abnormality, thereby quickly locating and repairing design flaws in the asynchronous path.

[0057] Based on the aforementioned solution, please refer to Figure 2 In some implementations of this application, the metastable simulation method in the chip pre-simulation further includes: step S104: in response to the end of this pre-simulation, a coverage report is generated based on the simulation results. The coverage report includes at least one of the following information: full path information of each first-level register, the number of times each first-level register performs normal updates, and the number of times each first-level register performs operations to maintain the current output value.

[0058] Understandably, this implementation provides quantitative data support for verification integrity analysis and design optimization by generating a coverage report after simulation. Since the coverage report records the full path information of each first-level register, as well as the number of normal updates and the number of times the current output value is maintained, designers can objectively assess the comprehensiveness of the verification.

[0059] It should be noted that in the existing pre-simulation verification process, the coverage report mainly includes code coverage, functional coverage, and assertion coverage. These measures the sufficiency of the design code execution and whether preset functional scenarios are triggered. It does not involve statistics on the sampling behavior of the asynchronous beat timer's first-level registers (such as the number of normal updates and the number of times the current output value is held), nor does it include the full path information of each first-level register. Code coverage is automatically collected by EDA tools (Electronic Design Automation software tools) and mainly includes line coverage (which lines of code were executed), branch coverage (the execution status of conditional branches), toggle coverage (whether signals underwent 0 and 1 transitions), and state machine coverage (whether the states and state transitions of the state machine were accessed). Functional coverage measures which functional characteristics in the design are covered by test cases. Assertion coverage counts the number of times user-written assertion attributes were successfully verified or failed during simulation, answering the question of whether key timing relationships and assumptions in the design are true at any given time.

[0060] Therefore, technicians cannot determine the adequacy of metastability verification for each asynchronous path based solely on existing coverage reports, nor can they optimize the design accordingly. However, in this implementation, the metastability simulation method in pre-simulation of the chip proposed in this application can generate a coverage report containing richer information, clearly recording the full path information and sampling behavior statistics of each first-level register. Through effective analysis of the coverage report in this application, technicians can accurately identify which asynchronous paths have insufficient coverage of sampling failure scenarios, thereby allowing them to supplement test cases or optimize probability adjustment strategies in a targeted manner, improving verification efficiency.

[0061] Based on the aforementioned scheme, in some implementations of this application, the metastable simulation method in the chip pre-simulation further includes: in the second and subsequent pre-simulations, based on the simulation results and coverage report obtained at the end of the previous pre-simulation, using a preset neural network model to adaptively update the initial sampling anomaly probability value and probability adjustment strategy for the next pre-simulation.

[0062] In practical applications, simulation results and a coverage report are obtained after the first pre-simulation. When a second or subsequent pre-simulation is required, this implementation uses a pre-defined neural network model to analyze the simulation results and coverage report obtained at the end of the previous pre-simulation. Based on the analysis results, it adaptively updates the initial sampling anomaly probability value and probability adjustment strategy for the next pre-simulation. In this way, each simulation can be optimized based on previous learning outcomes. In other words, through the intelligent analysis and adjustment of the neural network model, this implementation allows subsequent simulations to more specifically explore insufficiently covered verification scenarios, thereby efficiently covering hidden asynchronous defects and improving verification efficiency.

[0063] Based on the aforementioned scheme, in some implementations of this application, the steps of adaptively updating the initial sampling anomaly probability value and probability adjustment strategy for the next pre-simulation include: if the previous pre-simulation did not detect a functional anomaly, then adjusting the initial sampling anomaly probability value for the next pre-simulation according to the difference between the number of normal updates and the number of times the current output value is held in the coverage report, so that the next pre-simulation tends to cover sampling result types with fewer coverage times; if the previous pre-simulation detected a functional anomaly, then switching the probability adjustment strategy to a strategy that tends to hold or a strategy that tends to adopt new sampling according to the difference between the number of normal updates and the number of times the current output value is held in the coverage report, so that the next pre-simulation tends to maintain the sampling trend that triggered the functional anomaly.

[0064] Understandably, this implementation distinguishes between two scenarios: whether or not a functional anomaly is detected. When no anomaly is detected, the focus is on addressing coverage gaps; when an anomaly is detected, the sampling trend that triggers the anomaly is strengthened to facilitate problem reproduction and localization. In other words, by employing different adjustment rules based on anomaly detection scenarios, it can proactively address coverage gaps when verification is insufficient, and strengthen advantageous trends to accelerate problem reproduction when defects are detected, thereby improving verification efficiency and defect detection capabilities.

[0065] Specifically, if the previous pre-simulation did not detect a functional anomaly, it means that the simulation under the current probability adjustment strategy did not trigger the asynchronous path defect. In this case, based on the difference between the number of normal updates and the number of times the current output value was held in the coverage report, the initial sampling anomaly probability value for the next pre-simulation is adjusted. This makes the next pre-simulation tend to cover sampling result types with fewer coverage occurrences, thus compensating for weaknesses in verification coverage. If the previous pre-simulation detected a functional anomaly, it means that the current sampling trend successfully triggered a hidden defect. In this case, based on the difference between the number of normal updates and the number of times the current output value was held in the coverage report, the probability adjustment strategy is switched to a strategy favoring holding or a strategy favoring new sampling. This makes the next pre-simulation tend to maintain the sampling trend that triggered the functional anomaly, in order to reproduce the problem more efficiently.

[0066] For example, such as Figure 3 As shown, in practical applications, if the previous simulation result indicates a test case failure (a functional anomaly was detected), it means that an asynchronous problem was randomly triggered. The calculation logic for updating the initial sampling anomaly probability value P of the next simulation can be: if comp(KeepQ,UpdateD) > 0, then P = 50% + L; otherwise, P = 50% - L. Conversely, if the previous simulation result indicates a test case pass (no functional anomaly was detected), the calculation logic for updating the initial sampling anomaly probability value P of the next simulation can be: if comp(KeepQ,UpdateD) < 0, then P = 50% - L; otherwise, P = 50% + L.

[0067] The `comp(KeepQ, UpdateD)` function calculates the difference between `KeepQ` and `UpdateD` to determine how large the difference is. `KeepQ` refers to the number of times the current output value is maintained, as recorded in the coverage file, while `UpdateD` refers to the number of times the data is updated normally, as recorded in the coverage file. In other words, `KeepQ` represents the number of sampling failures caused by the first-level register failing to maintain the current output value during the execution loop, i.e., the number of times metastability occurs and the register fails to sample correctly. `UpdateD` represents the number of times the first-level register updates the current output value to the current input value during the execution loop, i.e., the number of times sampling is successful and the register correctly acquires the input signal.

[0068] L = Threshold(|KeepQ-UpdateD| / (KeepQ+UpdateD)), where the Threshold function determines the adjustment step size L based on the difference between KeepQ and UpdateD. Here, the denominator KeepQ+UpdateD is the total number of samples taken by the first-level register, and the numerator |KeepQ-UpdateD| is the absolute value of the difference between the number of keep-Q samples and the number of update samples. Dividing the two gives the difference percentage. This percentage can be mapped to a preset multi-level threshold range using the Threshold function. Conventional processing maps it to a preset five-level threshold range; for example, a difference percentage between 0% and 5% corresponds to level 1, 5% to 10% to level 2, and so on. Each level corresponds to an increase or decrease of 10% in the adjustment step size, meaning L can take values ​​of 0%, 10%, 20%, 30%, or 40%. The greater the difference, the larger the adjustment step size, thus correcting coverage deviations more quickly.

[0069] In other words, during the actual adaptive adjustment process, the `comp(KeepQ, UpdateD)` function determines the adjustment direction, i.e., whether the initial sampling anomaly probability value should be increased or decreased. The `Threshold` function determines the adjustment magnitude, i.e., how many percentage points should be adjusted. Combining these two functions allows calculation of the initial sampling anomaly probability value for the next simulation. For example, if the difference value `diff = comp(KeepQ, UpdateD)` is positive, and the threshold calculation yields L = 20%, then the new initial sampling anomaly probability value is 50% + 20% = 70%, meaning the next simulation will be more inclined to maintain the current output value to compensate for insufficient holding times previously. Conversely, if the difference value `diff` is negative, the initial sampling anomaly probability value becomes 50% - 20% = 30%, meaning the next simulation will be more inclined to normal updates.

[0070] To enable those skilled in the art to more intuitively understand this application, a specific example will be provided below. This example is an exemplary demonstration combining the overall technical paradigm of this application with some optional implementation details. It should be noted that the following demonstration is intended to aid understanding and does not constitute an exhaustive list of all embodiments of this application, nor does it imply that this application must include all the details described below in its specific implementation.

[0071] This example method is applied to a pre-chip simulation (i.e., register-transfer-level simulation, or RTL simulation) environment. For an asynchronous beater used for cross-clock domain signal synchronization, it simulates sampling failures caused by metastability by modifying the sampling behavior of the first-stage register of the asynchronous beater, and dynamically adjusts the sampling anomaly probability. Please refer to [link to relevant documentation]. Figure 3 The method specifically includes the following steps: initialization configuration step, sampling behavior modification step, probability dynamic adjustment step, and simulation verification and defect detection step.

[0072] 1. Initialization Configuration Steps In the register-transfer level simulation environment, locate (using static CDC analysis tools such as SpyGlass CDC) all asynchronous beaters corresponding to cross-clock domain asynchronous paths (project teams typically require the use of standard asynchronous beater cells), and determine the first-stage register of each asynchronous beater. Configure three mutually exclusive simulation parameters: a tendency to hold (Q parameter), a tendency to sample new (D parameter), and a tendency to be fair (DQ parameter), to control the adjustment direction of the subsequent sampling anomaly probability P. The tendency to hold (Q parameter) indicates a bias towards holding the current output value of the first-stage register to simulate a persistent metastable scenario; the tendency to sample new (D parameter) indicates a bias towards updating the output of the first-stage register to the current input value to prioritize correct sampling; and the tendency to be fair (DQ parameter) indicates a bias towards balancing the probabilities of successful and failed sampling. Simultaneously, initialize the sampling anomaly probability P of the first-stage register to an initial value of 50%. This sampling anomaly probability P is defined as the probability that the first-stage register will hold its current output value when the current input signal D of the first-stage register differs from the current output signal Q, i.e., the probability of sampling failure and simulating metastability. The three simulation parameters mentioned above are mutually exclusive, meaning that only one parameter is valid at any given time to avoid conflicting adjustment directions. Parameter configurations can be dynamically passed through a general verification methodology configuration library, supporting real-time adjustments during simulation to adapt to the metastable simulation requirements of different scenarios.

[0073] 2. Steps to modify the sampling behavior of the first-level register Modify the register transfer level (RTL) code logic of the first-level register to ensure its sampling behavior meets the following requirements: At each sampling clock edge, first determine if the current input signal D and the current output signal Q of the first-level register are the same. If they are the same, the first-level register samples normally, updating the current output signal Q to the value of the current input signal D. If they are different, a random decision is triggered, randomly selecting to maintain the current output value or update it to the current input value based on the current sampling anomaly probability P. Maintaining the current output value indicates sampling failure and simulation of metastability, while updating to the current input value indicates successful sampling. The register transfer level code of the first-level register supports enabling and disabling the metastability simulation function via a simulation switch; when this simulation function is disabled, the first-level register resumes normal sampling behavior, updating the current output value to the current input value each clock cycle without affecting regular pre-simulation verification.

[0074] 3. Steps for dynamically adjusting the sampling anomaly probability P After each random judgment, the sampling anomaly probability P for the next sampling is adjusted synchronously based on the current random result and the three preset simulation parameters. The biased fairness DQ parameter is the default randomization strategy, and this strategy supports an AI mode to accelerate coverage convergence. The AI ​​mode can automatically adapt to test case execution results and coverage data without requiring an additional randomization strategy. The specific adjustment rules are as follows.

[0075] When the random result is to maintain the current output value, i.e., sampling failure: (1) If the simulation parameter currently in effect is a fair DQ parameter, then increase the reverse probability of the sampling anomaly probability P in the next sampling (i.e., the sampling success probability 1-P), reduce the probability of the next sampling failure, and make the sampling failure and sampling success probabilities tend to be balanced. (2) If the simulation parameter currently in effect is a new D parameter, then further reduce the sampling anomaly probability P in the next sampling, increase the sampling success probability, and make the first-level register tend to correctly sample the current input signal D in the next sampling. (3) If the simulation parameter currently in effect is a Q parameter, then maintain or increase the sampling anomaly probability P in the next sampling, and make the first-level register tend to continue to maintain the current output value to simulate the scenario of continuous metastability.

[0076] When the random result is updated to the current input value, i.e., the sampling is successful: (1) If the current effective simulation parameter is a fair DQ parameter, the sampling anomaly probability P of the next sampling is increased, increasing the probability of the next sampling failure, so that the probability of sampling failure and sampling success tends to be balanced. (2) If the current effective simulation parameter is a new D parameter, the sampling anomaly probability P of the next sampling is maintained or decreased, so that the first-level register continues to be inclined to correctly sample the current input signal D. (3) If the current effective simulation parameter is a Q parameter, the sampling anomaly probability P of the next sampling is increased, increasing the probability of the next sampling failure, so as to simulate the sudden occurrence of metastability.

[0077] The adjustment range of the sampling anomaly probability P can be a preset fixed value, such as 5% to 10%, or it can be dynamically adjusted according to the current simulation scenario. The updated sampling anomaly probability P is limited to the range of 0% to 100% to avoid simulation distortion caused by the probability exceeding the reasonable range.

[0078] 4. Simulation Verification and Defect Detection Steps Initiate register transfer level simulation, traverse the operating scenarios of all asynchronous paths of the chip, and record the sampling behavior of the first-level register. If, during the simulation, the first-level register fails to sample and thus maintains the current output value, causing subsequent circuit malfunctions, a design flaw is identified in the corresponding asynchronous path. A flaw alarm and corresponding sampling log are output, thus enabling early detection of asynchronous problems.

[0079] After the simulation, a verification coverage report is generated synchronously. This coverage report includes the full path information of the first-stage registers of all asynchronous timing circuits, the number of times each first-stage register correctly acquired the current input signal D value, and the number of times each first-stage register maintained the current output signal Q value unchanged, i.e., the number of sampling failures. This information provides data support for verification integrity analysis, design optimization, and adjusting the random strategy of AI mode.

[0080] The random strategy and initial probability adjustment rules in AI mode can be as follows: (1) In the first simulation, the initial sampling anomaly probability P is 50%, the default random strategy is a fair strategy, and the AI ​​mode can be enabled.

[0081] (2) In the second and subsequent simulations, the default randomization strategy and initial probability are adaptively adjusted based on the results of the previous simulation (test case pass / fail results) and coverage report feedback. For example, the initial probability (the initial sampling anomaly probability value of the first-level register) can be adjusted using the functions L=Threshold(|KeepQ-UpdateD| / (KeepQ+UpdateD)) and comp(KeepQ,UpdateD). The specific calculation logic and process are described above and will not be repeated here.

[0082] Specifically, if the previous simulation test case passed and AI mode was enabled, the direction is adjusted to improve coverage: if the number of times the current input signal D value was correctly acquired in the previous simulation is much less than the number of times the current output value was maintained (a threshold can be set for comparison), the probability of correctly acquiring the current input signal D value in the second simulation is increased to more than 50% by default; otherwise, the probability of maintaining the current output value is increased to more than 50% by default.

[0083] If the previous simulation test case failed, it indicates that an asynchronous problem was randomly triggered this time. The AI ​​mode will maintain its current advantageous random trend: based on the difference between the number of times the current input signal D value was correctly acquired and the number of times the current output value was held in the coverage report, if the number of times the current input signal D value was correctly acquired is greater than the number of times the current output value was held, the random strategy will be switched to a strategy that favors acquiring new values ​​to prioritize acquiring the current input signal D value; if the number of times the current output value was held is greater than the number of times the current input signal D value was correctly acquired, the random strategy will be switched to a strategy that favors holding values. This will efficiently reproduce asynchronous defects and accelerate coverage convergence.

[0084] Please see Figure 4 This application provides an electronic device including at least one processor 201 and at least one memory 202. The processor 201 and memory 202 are directly connected to each other, or communicate with each other through a communication interface 203, or are electrically connected through one or more communication buses or signal lines to achieve data transmission or interaction. The memory 202 stores program instructions executable by the processor 201, which can call and execute the program instructions to implement any of the metastable simulation methods in chip pre-simulation provided by the various implementation methods described above. For example, implementing: The first-level registers of each asynchronous beater in the location register transfer level code are configured. The sampling anomaly probability value and probability adjustment strategy for each first-level register are configured. The sampling anomaly probability value is the probability that the first-level register will maintain its current output value when the current input value differs from the current output value. The probability adjustment strategy is a rule for adjusting the sampling anomaly probability for the next sampling based on the current random result. A loop process is executed until the pre-simulation ends to obtain the simulation results. The loop process includes: in each clock cycle, determining whether the current input value and current output value of the first-level register are the same; if they are the same, updating the current output value of the first-level register to the current input value; if they are different, randomly determining whether the current sampling should be a normal update or maintaining the current output value based on the sampling anomaly probability value, recording the random result, and updating the sampling anomaly probability value based on the random result and probability adjustment strategy for the next sampling.

[0085] The memory 202 may be, but is not limited to, random access memory (RAM), read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), etc.

[0086] The processor 201 can be an integrated circuit chip with signal processing capabilities. The processor 201 can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it can also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components.

[0087] Understandable. Figure 4 The structure shown is for illustrative purposes only; the electronic device may also include components that are more advanced than those shown. Figure 4 The more or fewer components shown, or having the same Figure 4 The different configurations shown. Figure 4 The components shown can be implemented using hardware, software, or a combination thereof.

[0088] It will be apparent to those skilled in the art that this application is not limited to the details of the exemplary embodiments described above, and that this application can be implemented in other specific forms without departing from the spirit or essential characteristics of this application. Therefore, the embodiments should be considered illustrative and non-limiting in all respects, and the scope of this application is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within this application. No reference numerals in the claims should be construed as limiting the scope of the claims.

Claims

1. A metastable state simulation method in chip pre-simulation, characterized in that, The method includes: The first-level registers of each asynchronous beater in the positioning register transfer level code; Configure the sampling anomaly probability value and probability adjustment strategy for each first-level register, wherein the sampling anomaly probability value is the probability that the first-level register will maintain the current output value when the current input value of the first-level register is different from the current output value, and the probability adjustment strategy is the rule for adjusting the sampling anomaly probability of the next sampling based on the current random result; The loop continues until the pre-simulation ends, in order to obtain the simulation results; The loop process includes: in each clock cycle, determining whether the current input value and the current output value of the first-level register are the same; if they are the same, updating the current output value of the first-level register to the current input value; if they are different, randomly determining whether the current sampling is a normal update or maintaining the current output value based on the sampling anomaly probability value, recording the random result, and updating the sampling anomaly probability value based on the random result and the probability adjustment strategy for the next sampling.

2. The method according to claim 1, characterized in that, The probability adjustment strategy is one of the following: a tendency to maintain the existing strategy, a tendency to adopt a new strategy, or a tendency to adopt a fair strategy. The preferred strategy is to keep the first-level register at its current output value, which is used to simulate a scenario where metastability persists. The preferred sampling strategy is to update the output of the first-level register to the current input value, which is used to simulate a scenario where correct sampling is prioritized. The preferred fairness strategy is to make the probability of the first-level register keeping its current output value and the probability of updating it to the current input value in a normal manner tend to be balanced, which is used to simulate a scenario where metastability is balanced.

3. The method according to claim 1, characterized in that, The probability adjustment strategy is one of a strategy that favors maintaining the status quo, a strategy that favors adopting new approaches, or a strategy that favors fairness; the step of updating the sampling anomaly probability value based on the current random result and the probability adjustment strategy includes: When the current random result is a normal update: if the probability adjustment strategy is a strategy that favors maintaining the status quo, then the sampling anomaly probability value for the next sampling is increased; if the probability adjustment strategy is a strategy that favors adopting new status, then the sampling anomaly probability value for the next sampling is maintained or decreased; if the probability adjustment strategy is a strategy that favors fairness, then the sampling anomaly probability value for the next sampling is increased. When the current random result is to maintain the current output value: if the probability adjustment strategy is a strategy that favors maintaining the current value, then the sampling anomaly probability value for the next sampling will be maintained or increased; if the probability adjustment strategy is a strategy that favors adopting new values, then the sampling anomaly probability value for the next sampling will be decreased; if the probability adjustment strategy is a strategy that favors fairness, then the sampling anomaly probability value for the next sampling will be decreased.

4. The method according to any one of claims 1-3, characterized in that, Configuring the sampling anomaly probability value of each first-level register includes setting the initial value of the sampling anomaly probability value of each first-level register to 50%.

5. The method according to any one of claims 1-3, characterized in that, When updating the sampling anomaly probability value, the adjustment range is either a preset fixed value or a dynamically configurable value, and the updated sampling anomaly probability is limited to the range of 0% to 100%.

6. The method according to claim 1, characterized in that, The method further includes: during the execution of the loop, when the current random result is to maintain the current output value and cause subsequent circuit functions to malfunction, outputting a defect alarm and corresponding sampling log.

7. The method according to claim 1, characterized in that, The method further includes: In response to the end of this pre-simulation, a coverage report is generated based on the simulation results. The coverage report includes at least one of the following information: full path information of each first-level register, the number of times each first-level register performs a normal update, and the number of times each first-level register performs an operation to maintain the current output value.

8. The method according to claim 7, characterized in that, The method further includes: In the second and subsequent pre-simulations, based on the simulation results and coverage report obtained at the end of the previous pre-simulation, the initial sampling anomaly probability value and probability adjustment strategy for the next pre-simulation are adaptively updated using a preset neural network model.

9. The method according to claim 8, characterized in that, The steps of adaptively updating the initial sampling anomaly probability value and probability adjustment strategy for the next pre-simulation include: If no functional anomaly was detected in the previous pre-simulation, the initial sampling anomaly probability value for the next pre-simulation will be adjusted based on the difference between the number of normal updates and the number of times the current output value was held in the coverage report, so that the next pre-simulation will tend to cover sampling result types with fewer coverage times. If the previous pre-simulation detected a functional anomaly, the probability adjustment strategy will be switched to either a hold-forward strategy or a new sampling strategy based on the difference between the number of normal updates and the number of times the current output value was held in the coverage report, so that the next pre-simulation will tend to maintain the sampling trend that triggered the functional anomaly.

10. An electronic device, characterized in that, include: Memory, used to store one or more programs; processor; When the one or more programs are executed by the processor, the method as described in any one of claims 1-9 is implemented.

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