A fuse array, redundancy control circuit and memory

Abstract

The embodiments of the present disclosure provide a fuse array, a redundancy control circuit and a memory. The fuse array comprises at least one first fuse group and at least one second fuse group. Each of the first fuse group and the second fuse group comprises B fuses. Each second fuse group shares M fuses in a first fuse group with the first fuse group. Each fuse is used to store a fuse sub-signal. The B fuse sub-signals stored by the first fuse group correspond to the address of a defective cell in a normal storage layer. The (B-M) fuse sub-signals stored by the remaining (B-M) fuses in the second fuse group which are not shared with the first fuse group correspond to the address of another normal storage layer to be repaired. Each first fuse group and each second fuse group correspond to a redundancy control circuit. The embodiments of the present disclosure can reduce the number of fuses and improve the integration of the memory.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more particularly to a fuse array, a redundant control circuit, and a memory. Background Technology

[0002] DRAM (Dynamic Random Access Memory) arrays typically consist of normal storage areas and redundant storage areas. When a cell in a normal storage area cannot provide normal read / write or storage functionality, a cell in the redundant storage area can be used to replace the defective cell, ensuring the memory functions properly. Summary of the Invention

[0003] This disclosure provides a fuse array, a redundant control circuit, and a memory.

[0004] In a first aspect, embodiments of this disclosure provide a fuse array configured in a memory including a normal storage region and a redundant storage region, wherein the normal storage region includes multiple normal storage layers and the redundant storage region includes multiple redundant storage layers.

[0005] The fuse array includes at least one first fuse group and at least one second fuse group. Both the first fuse group and the second fuse group include B fuses, and each second fuse group shares M fuses in the first fuse group with one first fuse group. B and M are both positive integers, and M is less than B. Each fuse is used to store one bit of fuse sub-signal.

[0006] Wherein, the B-bit fuse sub-signal stored in the first fuse group corresponds to the address of a defective cell in a normal storage layer, and the (BM)-bit fuse sub-signal stored in the remaining (BM) fuses in the second fuse group that are not shared with the first fuse group corresponds to the address of another normal storage layer to be repaired.

[0007] In some embodiments, a portion of the multi-layer redundant storage layer is used to repair the defective unit, and another portion of the multi-layer redundant storage layer is used to repair the normal storage layer to be repaired.

[0008] In some embodiments, in the first fuse group, the fuse sub-signals stored in the shared M fuses are the lower M-bit fuse sub-signals among the B fuse sub-signals.

[0009] In some embodiments, the normal storage layer includes a plurality of address units, each address unit including at least one address line, and the defective unit is an address unit including at least one defective address line; the redundant storage layer includes a plurality of repair units, each repair unit including at least one redundant address line.

[0010] When the defective unit includes an address line, the address line is a defective address line;

[0011] When the defective unit includes multiple address lines, at least one of the multiple address lines is a defective address line;

[0012] Each address unit in the normal storage layer to be repaired is a defective unit, or the proportion of defective units in the normal storage layer to be repaired exceeds a preset proportion threshold.

[0013] In some embodiments, the normal storage layer includes N address lines, and the defective cell corresponding to the first fuse group contains 2 address lines. K 1, N=2 M+K , where K is an integer greater than or equal to 0.

[0014] In some embodiments, the number of the at least one first fuse group and the number of the at least one second fuse group are the same.

[0015] In some embodiments, the number of the second fuse groups is the same as the number of normal storage layers to be repaired.

[0016] In a second aspect, embodiments of this disclosure provide a redundancy control circuit configured in a memory including a normal storage region and a redundant storage region, wherein the normal storage region includes multiple normal storage layers, and the redundant storage region includes multiple redundant storage layers, and the redundancy control circuit includes:

[0017] The address comparison circuit is used to receive the B-bit input sub-signal and the B-bit fuse sub-signal; the B-bit fuse sub-signal is the B-bit fuse sub-signal stored in the first fuse group or the second fuse group in the fuse array as described in any one of the first aspects;

[0018] The address comparison circuit is also used to compare the B-bit input sub-signal and the B-bit fuse sub-signal to obtain B comparison signals; output the M comparison signals corresponding to the shared M-bit fuse sub-signal to the address selection circuit, and output the remaining (BM) comparison signals to the address control circuit.

[0019] The address selection circuit is used to select the M comparison signals or the corresponding M input sub-signals as M address selection signals based on the selection control signal, and output them to the address control circuit.

[0020] The address control circuit is used to perform logical processing on the M address selection signals and the remaining (BM) comparison signals to output an activation signal for whether to activate the repair unit corresponding to the B-bit fuse sub-signal.

[0021] In some embodiments, the address comparison circuit includes M comparison sub-circuits, each comparison sub-circuit's first input terminal receiving one bit of the input sub-signal, each comparison sub-circuit's second input terminal receiving one bit of the fuse sub-signal, and each comparison sub-circuit's output terminal outputting the comparison signal.

[0022] The comparator circuit is used to compare the input sub-signal and the fuse sub-signal of the corresponding bit, and output the corresponding comparison signal.

[0023] In some embodiments, the address selection circuit includes M selection sub-circuits, each selection sub-circuit receiving a comparison signal at its first input terminal, receiving an input sub-signal at its second input terminal, receiving a selection control signal at its control terminal, and outputting the address selection signal at its output terminal.

[0024] The selection sub-circuit is used to output the comparison signal or the input sub-signal as the address selection signal based on the control of the selection control signal.

[0025] In some embodiments, the address control circuit includes three levels of sub-control modules, each of which includes at least one logic unit;

[0026] Each logic unit of the first-level sub-control module is connected to two outputs of the address selection circuit; or, each logic unit of the first-level sub-control module is connected to one output of the address selection circuit and one output of the address comparison circuit; or, each logic unit of the first-level sub-control module is connected to two outputs of the address comparison circuit.

[0027] Each logic unit of the second-level sub-control module is connected to an output terminal of the first-level sub-control module and a fuse control signal;

[0028] The logic unit of the third-level sub-control module is connected to the output of the second-level sub-control module.

[0029] In some embodiments, the logic units in the first-level sub-control module and the second-level sub-control module are NAND gates, and the logic units in the third-level sub-control module are AND gates.

[0030] Thirdly, embodiments of this disclosure provide a memory, including: a normal storage region, a redundant storage region, a fuse array as described in any one of the first aspects, and a plurality of redundant control circuits as described in any one of the second aspects; the normal storage region includes multiple normal storage layers; the redundant storage region includes multiple redundant storage layers;

[0031] The redundant control circuit is used to output an activation signal for whether to activate the repair unit corresponding to the B-bit fuse sub-signal based on the B-bit input sub-signal and the B-bit fuse sub-signal; the B-bit fuse sub-signal is the B-bit fuse sub-signal stored in the first fuse group or the second fuse group.

[0032] In some embodiments, each of the first fuse group and each of the second fuse group corresponds to one of the redundant control circuits;

[0033] The M fuses shared in the first fuse group are connected to a first redundant control circuit and a second redundant control circuit;

[0034] The (BM) fuses that are not shared in the first fuse group are connected to the first redundant control circuit;

[0035] The remaining (BM) fuses in the second fuse group that are not shared with the first fuse group are connected to the second redundant control circuit;

[0036] The first redundant control circuit is the redundant control circuit corresponding to the first fuse group, and the second redundant control circuit is the redundant control circuit corresponding to the second fuse group.

[0037] In some embodiments, in the redundant control circuit corresponding to the first fuse group, the B-bit fuse sub-signal is the B-bit fuse sub-signal stored in the first fuse group, and the selection control signal instructs the address selection circuit to select the M comparison signals as the M address selection signals;

[0038] In the redundant control circuit corresponding to the second fuse group, the B-bit fuse sub-signal is the B-bit fuse sub-signal stored in the second fuse group, and the selection control signal instructs the address selection circuit to select M input sub-signals as the M address selection signals.

[0039] In some embodiments, in the redundancy control circuit corresponding to the first fuse group, the M address selection signals are the M comparison signals. The address control circuit is used to output an activation signal for activating the repair unit corresponding to the B-bit fuse sub-signal when the B comparison signals indicate that the B-bit input sub-signal and the B-bit fuse sub-signal are both matched; otherwise, it outputs an activation signal for not activating the repair unit corresponding to the B-bit fuse sub-signal.

[0040] In the redundant control circuit corresponding to the second fuse group, the M address selection signals are the M input sub-signals. The address control circuit is used to shield the M input sub-signals and, when the (BM) bit input sub-signals and (BM) bit fuse sub-signals corresponding to the remaining (BM) comparison signals are all matched, output an activation signal to activate the repair unit corresponding to the B bit fuse sub-signal; otherwise, output an activation signal not to activate the repair unit corresponding to the B bit fuse signal.

[0041] This disclosure provides a fuse array, a redundant control circuit, and a memory. The fuse array is used to store the addresses of defective cells in a normal storage layer. For a normal storage layer that does not require full-layer repair but only has some defective cells that need repair, the addresses of the defective cells are completely stored by a first fuse group (i.e., the B-bit fuse sub-signals stored in the first fuse group are the addresses of the corresponding defective cells). For a normal storage layer that needs full-layer repair, when storing the addresses of its defective cells, the corresponding second fuse group only stores the (BM)-bit fuse sub-signals related to the addresses of the defective cells. The other M-bit signals are shared M-bit fuse sub-signals from the first fuse group, where (BM)-bit signals are shared by the first fuse group. The M-bit fuse sub-signal corresponds to the address of the normal memory layer that has been fully repaired. There's no need to further precisely store the addresses of defective cells within that normal memory layer. That is, the M-bit fuse sub-signal used to locate specific defective cells shares the addresses of defective cells in other normal memory layers. Thus, for the first and second fuse groups with a sharing relationship, storing the address of each defective cell completely would require 2B fuses. However, with this shared fuse method, only 2B-M fuses are needed. Clearly, the number of fuses required in the memory array is reduced, saving the number of fuses in the fuse array and consequently saving the area of ​​the fuse array, which is beneficial for the miniaturization and integration of 3D memories. Furthermore, based on this method, a fully repaired normal memory layer can be repaired entirely, while defective cells in a partially repaired normal memory layer can still be repaired individually without affecting the normal repair process of the memory. Attached Figure Description

[0042] Figure 1 This is a schematic diagram of the structure of a 3D memory provided in an embodiment of the present disclosure;

[0043] Figure 2 This embodiment of the present disclosure provides a schematic diagram of repairing defective address lines. Figure 1 ;

[0044] Figure 3 A schematic diagram of the composition structure of an address hit circuit provided in an embodiment of this disclosure;

[0045] Figure 4 A schematic diagram of repairing defective address lines provided in the disclosed embodiments. Figure 2 ;

[0046] Figure 5 A schematic diagram showing the correspondence between a fuse group and a redundant control circuit, provided for a disclosed embodiment;

[0047] Figure 6 A schematic diagram illustrating the correspondence between a fuse group and an address hit circuit, provided for a disclosed embodiment;

[0048] Figure 7 A schematic diagram of the composition structure of a redundant control circuit provided in an embodiment of this disclosure;

[0049] Figure 8 A detailed structural schematic diagram of a redundant control circuit provided in an embodiment of this disclosure;

[0050] Figure 9 A schematic diagram of the composition structure of a memory provided in an embodiment of this disclosure;

[0051] Figure 10 This is a schematic diagram of the composition structure of an electronic device provided in an embodiment of this disclosure. Detailed Implementation

[0052] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the disclosure. Furthermore, it should be noted that, for ease of description, only the parts relevant to the disclosure are shown in the accompanying drawings.

[0053] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of this disclosure only and is not intended to be limiting of this disclosure.

[0054] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0055] It should be noted that the terms "first, second, third" used in the embodiments of this disclosure are merely to distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first, second, third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of this disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0056] Before providing a further detailed description of the embodiments of this disclosure, the nouns and terms used in the embodiments of this disclosure will be explained. The nouns and terms used in the embodiments of this disclosure shall be interpreted as follows:

[0057] Dynamic Random Access Memory (DRAM);

[0058] Three-dimensional dynamic random access memory (3D DRAM);

[0059] Word line (WL);

[0060] Bit Line (BL);

[0061] Electronic fuse (eFuse);

[0062] Memory Array Tile (MAT);

[0063] Capacitor (CAP);

[0064] Sub-word line (SWL);

[0065] Redundancy Sub Word Line (RSWL);

[0066] Redundancy Sub Bit Line (RSBL);

[0067] eFuse Box;

[0068] Static Random Access Memory (SRAM);

[0069] Dynamic Random Access Memory (DRAM);

[0070] Synchronous Dynamic Random Access Memory (SDRAM);

[0071] Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM);

[0072] Double Data Rate (DDR).

[0073] Low-power DDR (LPDDR).

[0074] Advances in manufacturing technology and the ever-growing demand for data processing and storage capacity have driven the development of 3D DRAM. 3D DRAM overcomes the limitations of the planar structure in traditional two-dimensional (2D) DRAM and improves the density and performance of memory cells. Furthermore, the vertical stacking method of 3D DRAM increases signal transmission speed and reduces power consumption, making it suitable for small electronic devices.

[0075] In 3D DRAM technology, stacking multiple word lines and multiple bit lines can cause various defects, such as: defects in only one word line and / or bit line (or failures, due to chip, disconnection, etc.), defects in multiple consecutive word lines and / or bit lines (due to chip), defects in single or multiple word lines and / or bit lines due to mixed bonding failure, etc.

[0076] In memory, when a defective memory cell is included in a normal memory area, a repair process can be performed by replacing the defective memory cell with a redundant memory cell from a redundant memory area. For example, when a process defect exists in a normal memory area of ​​a 3D DRAM stack structure, the defective address lines (word lines / bit lines) can be replaced with redundant address lines (word lines / bit lines) for repair.

[0077] When repairing memory, fuses, such as eFuses, are used. eFuses, also known as one-time programmable memory, can improve the operating efficiency of the circuitry in a chip by thousands of times when applied to the chip. Furthermore, eFuses are low-cost and the stored information is not lost due to power failure.

[0078] In related technologies, when dealing with defective address lines, after the external input address signal and the fuse address signal are matched, the redundant address lines can only be activated one-to-one for repair. This one-to-one activation of redundant address lines results in a large number of fuses and a large fuse array size, leading to high costs and hindering the miniaturization and integration of 3D DRAM.

[0079] Based on this, embodiments of this disclosure provide a fuse array, a redundant control circuit, and a memory. The fuse array stores the addresses of defective cells in a normal storage layer. For a normal storage layer that does not require full-layer repair but only has some defective cells that need repair, the addresses of the defective cells are completely stored in a first fuse group (i.e., the B-bit fuse sub-signals stored in the first fuse group are the addresses of the corresponding defective cells). For a normal storage layer that requires full-layer repair, when storing the addresses of its defective cells, the corresponding second fuse group only stores the (BM)-bit fuse sub-signals related to the addresses of the defective cells. The remaining M-bit signals are shared M-bit fuse sub-signals from the first fuse group. The (BM)-bit fuse sub-signal corresponds to the address of the normal memory layer that has been fully repaired. There is no need to further precisely store the addresses of defective cells within this normal memory layer. That is, the M-bit fuse sub-signal used to locate specific defective cells shares the addresses of defective cells in other normal memory layers. Thus, for the first and second fuse groups with a sharing relationship, storing the address of each defective cell completely would require 2B fuses. However, with this shared fuse method, only 2B-M fuses are needed. Clearly, the number of fuses required in the memory array is reduced, saving the number of fuses in the fuse array and consequently saving the area of ​​the fuse array, which is beneficial for the miniaturization and integration of 3D memories. Furthermore, based on this method, a fully repaired normal memory layer can be repaired entirely, while defective cells in a partially repaired normal memory layer can still be repaired individually without affecting the normal repair process of the memory.

[0080] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0081] In one embodiment of this disclosure, see [link to embodiment]. Figures 1 to 3 , Figure 1 A schematic diagram of the three-dimensional structure of a three-dimensional memory provided in an embodiment of this disclosure is shown; Figure 2 The illustration shows a schematic of a method for repairing defective address lines according to a disclosed embodiment. Figure 1 ; Figure 3 A schematic diagram of the composition structure of an address hit circuit provided in an embodiment of this disclosure is shown.

[0082] like Figure 1 As shown, in 3D memory, one of the word line and bit line is stepped. If 1-1 is a word line (WL), then 1-2 is a stepped bit line (BL); if 1-1 is a bit line (BL), then 1-2 is a stepped word line (WL). Both word lines and bit lines are made of metal contact structures. Figure 1The cylindrical structure in the middle) leads out the connection; 1-3 is the memory cell including capacitor CAP; 1-4 represents the memory layer containing N word lines or N bit lines (or N memory cells). The dashed line outlines three memory layers (which can be referred to as memory layer 1, memory layer 2 and memory layer 3 respectively). The word lines or bit lines (or memory cells) in them need to be repaired (1-5); the address of the word line / bit line (or memory cell) that needs to be repaired is stored in the fuse box (1-6).

[0083] It should be noted that, for ease of distinction and description, the original storage area in the memory is referred to as the normal storage area, the storage layer within it as the normal storage layer, and the address lines (word lines / bit lines) within it as normal address lines. The storage area used for repair is referred to as the redundant storage area, the storage layer within it as the redundant storage layer, and the address lines (word lines / bit lines) within it as redundant address lines. In the redundant storage area, two redundant address lines can be used to form a repair unit. For example, a repair unit includes redundant address line 0 and redundant address line 1. If there is a defective address line (or a failed address line / abnormal address line, etc.) in the normal storage area, the two redundant address lines in the repair unit in the redundant storage area can be used to replace the damaged address line and the two address lines adjacent to it, for a total of two address lines.

[0084] like Figure 2 As shown, taking a normal memory storage area of ​​1MAT and address lines as word lines (specifically, sub-word lines SWL) as an example, this MAT contains 1k = 2 10 = 1024 sub-word lines SWL<1024:1>, or, it can be sorted starting from 0, denoted as SWL<1023:0>. A normal memory layer includes N sub-word lines, and one MAT consists of 1024 / N normal memory layers. Figure 1 In the diagram, only the normal storage layer 1 is labeled, which is a layer containing N sub-word lines, meaning the number of vertically stacked sub-word lines is N, hence it is also denoted as N-Tier; among them, the N sub-word lines (SWL) in normal storage layer 1 <1> ~SWL <n>All of these are defective address lines; additionally, four defective address lines (SWL) in the remaining normal memory layers are also shown. <61> SWL <63> SWL <64> SWL <1023> .

[0085] Correspondingly, Figure 2 The diagram shows redundant storage layer 1 and redundant storage layer 2 used for repair. Each redundant storage layer includes N redundant subword lines RSWL. The N redundant subword lines in redundant storage layer 1 are denoted as RSWL1. <1> ~RSWL1 <n>The N redundant subword lines in redundant storage layer 2 are denoted as RSWL2. <1> ~RSWL2 <n>Since all N address lines in normal storage layer 1 are defective address lines, meaning the entire normal storage layer 1 is defective, redundant storage layer 1 is used to repair the entire normal storage layer 1; and redundant subword lines in redundant storage layer 2 are used to repair the remaining defective subword lines respectively. Figure 2 In this context, a normal address line is an address line without any defects.

[0086] Taking a repair unit comprising 2 redundant subword lines as an example, each redundant storage layer comprises N / 2 repair units (for ease of description, in this embodiment, N is always described as an even number). Figure 2 The arrows in the diagram indicate the replacement process, specifically RSWL1 in redundant storage layer 2. <1> and RSWL1 <2> The repair unit is used to repair SWL in the normal storage layer. <61> and SWL <62> Repair the defective units that make up the structure, and so on for the rest. I will not go into details here.

[0087] like Figure 2 As shown, each repair unit corresponds to an address hit circuit. The address hit circuits corresponding to each repair unit in redundant storage layer 1 are respectively denoted as address hit circuit T1. <1> ~Address hit circuit T1 <n 2>The corresponding fuse address signals are denoted as eFuse Add T1 1[1:B]~eFuse Add T1N / 2[1:B] respectively; the address hit circuits corresponding to the repair units in the redundant storage layer 2 are denoted as address hit circuits T2 respectively. <1> ~Address hit circuit T2 <n 2>The corresponding fuse address signals are denoted as eFuse Add T2 1[1:B]~eFuse Add T2 N / 2[1:B].

[0088] Each address hit circuit receives the input address signal External Add[1:B] (i.e., the externally input address signal) and the corresponding fuse address signal (i.e., the address signal stored in the fuse). Here, since one repair unit corresponds to two address lines, the least significant bit sub-signal is not required during repair. For example, the address signal of each address line includes B+1 bits of sub-signal, where B is a positive integer, i.e., Add[0:B], in SWL <61> For example, the least significant sub-signal Add[0] is used to distinguish whether the address line is SWL

[61] or SWL. <62> Due to SWL

[61] and SWL <62> They are repaired simultaneously, and whether the least significant sub-signal Add[0] matches does not affect the activation of the redundant address lines in the corresponding repair unit. When SWL <61> When a fault occurs, RSWL2 will be activated simultaneously. <1> and RSWL2 <0> Therefore, both the input address signal and the fuse address signal include B-bit sub-signals. The B-bit input sub-signals included in the input address signal are: External Add[1] to External Add[B], denoted as External Add[1:B], without External Add[0]. The B-bit fuse sub-signals included in the fuse address signal are: eFuse Add[1] to eFuse Add[B], denoted as eFuse Add[1:B], without eFuse Add[0]. When the number of redundant address lines contained in the repair unit is other than a certain number, the number of sub-signals changes accordingly.

[0089] In other words, the input address signal represents the address being accessed, and the fuse address signal represents the address of the defective unit that the corresponding repair unit repairs. For example... Figure 1 As shown, assuming storage layer 1 needs to be repaired as a whole, the fuse address signals are stored in fuse boxes. Fuse boxes 1[0] to 1[N / 2] respectively store the addresses of N / 2 defective units, and each defective unit includes 2 defective address lines. Thus, each fuse box contains B fuses to store B fuse sub-signals. The other fuse boxes are similar, and will not be described in detail here. In this way, every two WL / BL correspond to one fuse box for simultaneous repair. When repairing a storage layer with N defective address lines, it is necessary to know each piece of information stored in the N / 2 fuse boxes.

[0090] like Figure 3 As shown, the address hit circuit 10 includes an address comparison circuit 11 and an address control circuit 12. The address comparison circuit 11 includes B XOR gates 111. Figure 3 Only one label 111 is shown. The first input of each XOR gate 111 receives a one-bit input sub-signal External Add[i] (i is a positive integer and satisfies: 1≤i≤B). The second input of each XOR gate 111 receives the corresponding bit's fuse sub-signal eFuse Add[i]. The output of each XOR gate 111 outputs a comparison signal Hit Add[i]. Because each repair unit includes two redundant address lines, the repair can be achieved without the participation of the least significant bit signal (External Add[0] and eFuse Add[0]). Thus, B XOR gates 111 are used to compare the corresponding bit's input sub-signal External Add[i] and the fuse sub-signal eFuse Add[i]. Here, we take 1 to B as 1, 2, ..., 9, A, B as an example.

[0091] Address control circuit 12 is used to output an activation signal RSWL Enable, indicating activation of the corresponding repair unit, when each input sub-signal and fuse sub-signal are the same (or matched). Figure 3 As shown, the address control circuit 12 includes five first NAND gates 121 ( Figure 3 Only one label 121 is shown, and five second NAND gates 122 are shown. Figure 3 Only one label 122, one third NAND gate 123, and one NOT gate 124 are shown. Each first NAND gate 121 has two inputs connected to the outputs of two XOR gates 111 respectively; each second NAND gate 122 has its first input connected to the output of one first NAND gate 121, and its second input receives the fuse control signal eFuse_en. The five second NAND gates 122 output hit signals Hit

[12] , Hit

[34] , Hit

[56] , and Hit

[78] respectively; multiple inputs of the third NAND gate 123 are connected to the outputs of multiple second NAND gates 122 respectively; the input of the NOT gate 124 is connected to the output of the third NAND gate 123, and the output of the NOT gate 124 outputs the activation signal RSWL Enable.

[0092] It should be noted that the two inputs of each first NAND gate 121 receive the comparison signals of adjacent bits. For example, the two inputs of the first first NAND gate 121 receive the comparison signals Hit Add[1] and Hit Add[2], the two inputs of the second first NAND gate 121 receive the comparison signals Hit Add[3] and Hit Add[4], and so on. The fuse control signal eFuse_en can be in a high-level state (logic "1"), so that when each input sub-signal and fuse sub-signal are matched, the output activation signal RSWL Enable is in a high-level state, indicating that the repair unit corresponding to the fuse address signal is activated.

[0093] In other words, if repairs from SWL are needed due to process issues or other problems... <1> To SWL <n>All defects, then all redundant address lines (RWL1) in redundant storage layer 1. <1> ~RWL1 <n>All faulty address lines (such as SWL) are used, and the address information of all defective cells must be stored in each fuse box. <61> SWL <63> SWL <64> and SWL <1023> ), and will use the repair unit in redundant storage layer 2 to perform a single repair in a normal manner.

[0094] The address hit circuit compares the input address signal and the fuse address signal latched by the XOR gate (if the two values ​​are the same, the output is "H", i.e., high level 1). After passing through the AND gate logic, if the value of all hit signals is "H", the corresponding repair unit can be activated.

[0095] It can be seen that, in Figures 1 to 3 In the example shown, each repair unit requires B fuses to store B-bit fuse sub-signals, resulting in a large number of fuses needed, which is not conducive to the miniaturization and integration of 3D DRAM.

[0096] Therefore, in another embodiment of this disclosure, an alternative method for storing fuse address signals and a corresponding address hit circuit are provided. To distinguish it from the aforementioned address hit circuit, subsequent... Figure 7 The provided address hit circuit is denoted as the redundancy control circuit. See also... Figure 4 It illustrates a schematic diagram of repairing defective address lines according to a disclosed embodiment. Figure 2 Examples of normal storage layer and redundant storage layer are shown below. Figure 2 The same applies, so I won't go into details here.

[0097] like Figure 4 As shown, taking a repair unit in the redundant storage layer that includes two redundant address lines as an example, for ease of description, for redundant storage layer 1, RSWL1 can be... <1> and RSWL1 <2> The repair unit is denoted as repair unit 1. <1> RSWL1 <3> and RSWL1 <4> The repair unit is denoted as repair unit 1. <2> ... and RSWL1 <n-1>and RSWL1 <n>The repair unit is denoted as repair unit 1. <n 2>For redundant storage layer 2, RSWL2 can be used. <1> and RSWL2 <2> The resulting repair unit is denoted as Repair Unit 2. <1> RSWL2 <3> and RSWL2 <4> The resulting repair unit is denoted as Repair Unit 2. <2> ... and RSWL2 <n-1>and RSWL2 <n>The resulting repair unit is denoted as Repair Unit 2. <n 2>Repair Unit 1 <1> ~Repair Unit 1 <n 2>With redundant control circuit T1 <1> ~Redundant control circuit T1 <n 2>One-to-one correspondence, repair unit 2 <1> ~Repair Unit 2 <n 2>With redundant control circuit T2 <1> ~Redundant control circuit T2 <n 2>One-to-one correspondence.

[0098] like Figure 4 As shown, redundant control circuit T1 <j>and redundant control circuit T2 <j>The first to the Mth bits of the received fuse sub-signal are shared, where j is an integer greater than or equal to 1 and less than or equal to N / 2, i.e., eFuse Add T1 j[1:M] = eFuse Add T2 j[1:M]. Since the redundant storage layer 2 is not used for whole-layer repair but for repairing a single defect unit, the shared bits are the M-bit fuse sub-signal of the defect unit corresponding to the repair unit in the redundant storage layer 2.

[0099] With its redundant control circuit T1 <1> and redundant control circuit T2 <1> For example, Figure 5 As shown, redundant control circuit T2 <1> The fuses in the corresponding fuse box are designated as the first fuse group, and the redundant control circuit T1... <1> The fuses in the corresponding fuse box are denoted as the second fuse group. Assuming B=9 and M=6, the first fuse group plus the second fuse group actually includes a total of 9+9-6=12 fuses. The first fuse group is used to store the fuse sub-address eFuse Add T2 1[1:9], where the dotted lines represent shared fuses. The stored fuse sub-address eFuse Add T2 1[1:6] is a shared fuse sub-address, which is simultaneously input to the redundancy control circuit T1. <1> and redundant control circuit T2 <1> The black dashed lines represent non-shared fuses in the first fuse group, where the stored fuse sub-address eFuseAdd T2 1[7:9] is input to the redundant control circuit T2. <1> The black solid lines represent fuses in the second fuse group that are not shared with the first fuse group, where the stored fuse sub-address eFuseAdd T1 1[7:9] is input to the redundancy control circuit T1. <1> In other words, the shared fuses actually belong to the first fuse group, and the second fuse group is equivalent to "borrowing" M shared fuses from the first fuse group to form a complete second fuse group with its own (BM) fuses.

[0100] Thus, during the repair process, redundant storage layer 1 replaces and repairs the entire normal storage layer 1. Therefore, the N / 2 redundant control circuits corresponding to redundant storage layer 1 do not need to locate the specific defective unit to be repaired. As long as the address unit corresponding to the current external input address is confirmed to be the address unit in normal storage layer 1, the corresponding repair unit needs to be activated. For redundant storage layer 2, it is still necessary to compare the B fuse sub-addresses one by one to determine whether the corresponding repair unit needs to be activated.

[0101] In comparison, Figure 6 In order to be in Figure 2 Based on this, address hit circuit T1 <1> and address hit circuit T2 <1> An example of the received fuse address signal, here, the address hit circuit T1. <1> The fuses in the corresponding fuse box are designated as fuse group 1, and the address is matched to circuit T2. <1> The fuses in this group are designated as fuse group 2. Both fuse group 1 and fuse group 2 contain 9 fuses, and there are no shared fuses. Therefore, fuse group 1 plus fuse group 2 actually contains a total of 9 + 9 = 18 fuses. In comparison, Figure 4 and Figure 5 The solution shown only requires 12 fuses, saving 6 fuses.

[0102] Based on the foregoing Figure 4 and Figure 5 The described solution, in this disclosure embodiment, provides a fuse array configured in a memory including a normal storage region and a redundant storage region, wherein the normal storage region includes multiple normal storage layers and the redundant storage region includes multiple redundant storage layers.

[0103] The fuse array includes at least one first fuse group and at least one second fuse group. Both the first and second fuse groups include B fuses, and each second fuse group shares M fuses in the first fuse group with one first fuse group. B and M are both positive integers, and M is less than B. Each fuse is used to store one bit of fuse sub-signal.

[0104] In this context, the B-bit fuse sub-signal stored in the first fuse group corresponds to the address of a defective cell in a normal storage layer, and the (BM)-bit fuse sub-signal stored in the remaining (BM) fuses in the second fuse group that are not shared with the first fuse group corresponds to the address of another normal storage layer to be repaired.

[0105] In some embodiments, the normal storage layer includes a plurality of address units, each address unit including at least one address line, and the defective unit is an address unit including at least one defective address line; the redundant storage layer includes a plurality of repair units, each repair unit including at least one redundant address line.

[0106] When a defective unit includes an address line, the address line is the defective address line.

[0107] When a defective unit includes multiple address lines, at least one of the multiple address lines is a defective address line;

[0108] Every address unit in the normal storage layer to be repaired is a defective unit, or the proportion of defective units in the normal storage layer to be repaired exceeds a preset proportion threshold.

[0109] It should be noted that a defective cell includes at least one defective address line; if a defective cell includes only one address line, then that address line is a defective address line; if a defective cell includes multiple address lines, then at least one of those address lines is a defective address line. Figure 4 In this context, a defective address line and its adjacent address line (which may or may not be defective) constitute a defective cell, for example, SWL. <1> and SWL <2> Forming a defective cell, SWL <61> and SWL <62> This constitutes a defective unit.

[0110] A normal storage layer awaiting full repair (which can be referred to as a defective storage layer) means that every address unit in this normal storage layer needs to be repaired. For example... Figure 4 In one example, all address lines in normal storage layer 1 are defective address lines, requiring full-layer repair. Alternatively, in other examples, most address lines in a normal storage layer may be defective, or all odd-numbered lines or all even-numbered lines may be defective. In these cases, full-layer repair of the normal storage layer may also be necessary. Another approach is to set a preset percentage threshold. If the number of defective address lines in a normal storage layer exceeds this threshold, the entire normal storage layer is considered to require repair. This preset percentage threshold can be set based on specific circumstances, such as 85%, 90%, 95%, etc.

[0111] In some embodiments, a portion of the multi-layer redundant storage layer is used to repair defective units, and another portion of the multi-layer redundant storage layer is used to repair normal storage layers that need to be repaired in their entirety.

[0112] It should be noted that if a redundant storage layer is used to repair a defective storage layer, then the redundant storage layer will not be used to repair defective units in other normal storage layers. In other words, the repaired units in the redundant storage layer correspond one-to-one with the address units in the corresponding repaired defective storage layer. Similarly, if a redundant storage layer is used to repair defective units in multiple normal storage layers, then the redundant storage layer will not be used to repair other defective storage layers undergoing full-layer repair. In other words, the repaired units used for repair in the redundant storage layer correspond one-to-one with the multiple defective units they repair. These multiple defective units are usually located in different normal storage layers, or in a normal storage layer that does not require full-layer repair (in this case, the number of repaired units in the redundant storage layer is less than the number of address units in the normal storage layer, or the number of repaired units in the redundant storage layer is equal to the number of address units in the normal storage layer, but some repaired units are not used for repair and are idle).

[0113] It should also be noted that defective cells are repaired by repair cells in a redundant storage layer, while normal storage layers awaiting full repair are fully repaired by another redundant storage layer. The number of redundant address lines in the repair cells equals the number of address lines in the defective cells, thus achieving the repair of the defective cells. For example, in Figure 4 In the middle, RSWL2 <1> and RSWL2 <2> The repair unit is used to repair SWL <61> and SWL <62> Defective units that make up the composition. For example, in... Figure 4 In this context, the normal storage layer to be repaired is called normal storage layer 1, and the redundant memory used for repairing it is called redundant storage layer 1.

[0114] In some embodiments, in the first fuse group, the fuse sub-signals stored in the shared M fuses are the lower M-bit fuse sub-signals among the B fuse sub-signals.

[0115] It should be noted that the address signal is usually decoded from the high bit to the low bit to the smallest address unit. Therefore, the shared low bit M-bit fuse sub-signal is specifically the M-bit sub-signal used to locate the specific address unit in the normal memory layer.

[0116] In some embodiments, the normal storage layer includes N address lines, and the defective cell corresponding to the first fuse group contains 2 address lines. K 1, N=2 M+K , where K is an integer greater than or equal to 0.

[0117] It should be noted that each first fuse group corresponds to a defective cell and a repair unit for repairing that defective cell. The corresponding defective cell can be addressed based on the fuse address signals stored in the first fuse group. For example, assume a normal memory layer includes 128 address lines (128 = 2^32). 7 If the defective cell contains 1 address line, then decoding within the normal storage layer to locate an address line requires 7 address sub-signals Add[0:6]. For example, if the defective cell contains 1 address line, i.e. 2... K =1, K=0, M=7, 128=2 0+7 If all 7 address sub-signals need to be shared, then Add[0:6] will be programmed into the 7 shared fuses of the first fuse group as shared fuse sub-signals; if the defective unit contains 2 address lines, that is... Figure 4 Example 2 shown K =2, K=1, M=6, 128=2 1+6 If the 6-bit address sub-signal Add[1:6] is shared, then Add[1:6] will be programmed into the 6 shared fuses of the first fuse group as shared fuse sub-signals; if the defective unit contains 8 address lines, 2 K =8, K=3, M=4, 128=2 3+4 If the 4-bit address sub-signal Add[3:6] is shared, then Add[3:6] will be programmed into the 3 shared fuses of the first fuse group as shared fuse sub-signals.

[0118] In some embodiments, the number of at least one first fuse group and the number of at least one second fuse group are the same.

[0119] It should be noted that, as Figure 4 As shown, taking a repair unit comprising two address lines as an example, in this example, the number of the first fuse group and the second fuse group are both N / 2. One first fuse group corresponds to one repair unit in the redundant storage layer 2 and one redundant control circuit T2; one second fuse group corresponds to one redundant control circuit T1 and one repair unit in the redundant storage layer 1. The redundant storage layer 1 is used for full-layer repair of the normal storage layer 1, and the redundant storage layer 2 is used for individual repair (non-full-layer repair) of defective units in the remaining normal storage layers.

[0120] In some embodiments, the number of second fuse groups is the same as the number of normal storage layers to be repaired.

[0121] It should be noted that, as analyzed above, the following is still taken as... Figure 4 For example, for each redundant control circuit T1, the received (BM) bit fuse sub-signal is used to decode to the normal storage layer 1. No further confirmation of the specific address unit is needed to activate the corresponding repair unit. Therefore, all redundant control circuits T1 corresponding to redundant storage layer 1 can actually share the same (BM) bit fuse sub-signal, further saving the number of fuses. To avoid excessive pressure caused by multiple redundant control circuits being connected to the same second fuse group, multiple identical second fuse groups can be set for each defective storage layer, with some redundant control circuits sharing one second fuse group (in the previous implementation, each redundant control circuit had its own second fuse group).

[0122] In this way, the two redundant storage layers (with at least one of them used for whole-layer repair) can share a fuse, effectively saving the number of fuses and the area / volume of the fuse array, which is beneficial to the miniaturization and integration of 3D memory.

[0123] This disclosure also provides a redundancy control circuit, which is configured in a memory including a normal storage region and a redundant storage region. The normal storage region includes multiple normal storage layers, and the redundant storage region includes multiple redundant storage layers, such as... Figure 7 As shown, the redundancy control circuit 20 includes:

[0124] Address comparison circuit 21 is used to receive B-bit input sub-signal and B-bit fuse sub-signal; the B-bit fuse sub-signal is the B-bit fuse sub-signal stored in the aforementioned first fuse group or second fuse group;

[0125] The address comparison circuit 21 is also used to compare the B-bit input sub-signal and the B-bit fuse sub-signal to obtain B comparison signals, output the M comparison signals corresponding to the shared M-bit fuse sub-signal to the address selection circuit 22, and output the remaining (BM) comparison signals to the address control circuit 23.

[0126] Address selection circuit 22 is used to select M comparison signals or corresponding M input sub-signals as M address selection signals based on the selection control signal, and output them to address control circuit 23;

[0127] Address control circuit 23 is used to perform logical processing on M address selection signals and the remaining (BM) comparison signals to output an activation signal for whether to activate the repair unit corresponding to the B-bit fuse sub-signal.

[0128] It should be noted that this redundancy control circuit 20 can be applied to 3D DRAM to solve the problem of address line damage caused by process defects in the address line lead-out process.

[0129] In this embodiment, the input address signal is represented by External Add, which includes the B-bit input sub-signal External Add[B:1]; the fuse address signal is represented by eFuse Add, which includes the B-bit fuse sub-signal eFuse Add[B:1]; the comparison signal is represented by Hit Add[i] (1≤i≤B, and i is an integer); the selection control signal is represented by NFuse_en[q] (1≤q≤M, and q is an integer); the address selection signal is represented by Hit Add Nen[q]; and the activation signal is represented by RSWL Enable. Furthermore, the selection control signal can be applied from an external device of the redundant control circuit 20, or it can be stored in the fuse (not the aforementioned first fuse group or second fuse group), and this is not limited.

[0130] As mentioned above, the repair unit includes at least one redundant address line, which will not be repeated here.

[0131] Address comparison circuit 21 compares the b-th bit input sub-signal and the b-th bit fuse sub-signal. If they are equal, it outputs the b-th comparison signal in the first level state; if they are not equal, it outputs the b-th comparison signal in the second level state. Here, the first level state and the second level state are different. For example, the first level state is a low logic 0, and the second level state is a high logic 1, or vice versa. No specific limitation is made here.

[0132] It should also be noted that for the M comparison signals corresponding to the shared M-bit fuse sub-signals, the address selection circuit 22 selects either to output the M comparison signals to the address control circuit 23, or to output the corresponding M input sub-signals to the address control circuit 23.

[0133] More specifically, in the memory, each first fuse group and each second fuse group corresponds to a redundant control circuit 20; the redundant control circuit 20 corresponding to the first fuse group is denoted as the first redundant control circuit, and the redundant control circuit 20 corresponding to the second fuse group is denoted as the second redundant control circuit.

[0134] The M fuses shared in the first fuse group are connected to the first redundant control circuit and the second redundant control circuit.

[0135] The (BM) fuses that are not shared in the first fuse group are connected to the first redundant control circuit;

[0136] The remaining (BM) fuses in the second fuse group that are not shared with the first fuse group are connected to the second redundant control circuit.

[0137] In the redundant control circuit 20 (first redundant control circuit) corresponding to the first fuse group, the B-bit fuse sub-signal is the B-bit fuse sub-signal stored in the first fuse group, and the selection control signal indicates that the address selection circuit 22 selects M comparison signals as M address selection signals;

[0138] In the redundant control circuit 20 (second redundant control circuit) corresponding to the second fuse group, the B-bit fuse sub-signal is the B-bit fuse sub-signal stored in the second fuse group, and the selection control signal indicates that the address selection circuit 22 selects M input sub-signals as M address selection signals.

[0139] In other words, for the first redundant control circuit, these M comparison signals are required to participate in subsequent logic processing; for the second redundant control circuit, these M comparison signals are not required to participate in subsequent logic processing.

[0140] It should also be noted that the address control circuit 23 confirms the state of the activation signal based on the output of the address selection circuit 22 and the remaining (BM) comparison signals. When the activation signal is enabled, the repair unit needs to be activated, and the repair unit replaces the defective unit addressed by the B-bit fuse sub-signal. When the activation signal is not enabled, the repair unit does not need to be activated, that is, the B-bit input sub-signal does not correspond to the defective unit, and no repair is required.

[0141] The enabled state can be the first level state, and the disabled state can be the second level state.

[0142] More specifically, in the redundant control circuit 20 corresponding to the first fuse group, the M address selection signals are M comparison signals. The address control circuit 23 is used to output an activation signal for the repair unit corresponding to the B-bit fuse sub-signal when the B comparison signals indicate that the B-bit input sub-signal and the B-bit fuse sub-signal are both matched; otherwise, it outputs an activation signal for not activating the repair unit corresponding to the B-bit fuse sub-signal.

[0143] In the redundant control circuit 20 corresponding to the second fuse group, the M address selection signals are the M input sub-signals. The address control circuit 23 is used to shield the M input sub-signals and, when the (BM) bit input sub-signals and (BM) bit fuse sub-signals corresponding to the remaining (BM) comparison signals are all matched, outputs the activation signal for the repair unit corresponding to the B bit fuse sub-signal; otherwise, outputs the activation signal for the repair unit corresponding to the B bit fuse sub-signal not to be activated.

[0144] It should be noted that the redundant storage layer where the repair unit corresponding to the first fuse group is located does not need to perform a full-layer repair on a normal storage layer. Therefore, in the first redundancy control circuit, it is necessary to ensure that the B-bit input sub-signal and the B-bit fuse sub-signal are matched one by one before the corresponding repair unit is activated.

[0145] The redundant storage layer where the repair unit corresponding to the second fuse group is located needs to perform a full-layer repair on a normal storage layer. Therefore, in the second redundancy control circuit, it is only necessary to ensure that the high-order (BM) bit input sub-signal and the (BM) bit fuse sub-signal are matched one by one to activate the corresponding repair unit.

[0146] Whether to block the corresponding signal can be determined by the eFuse_en control signal of each fuse.

[0147] See Figure 8 This illustration shows a detailed structural diagram of a redundant control circuit provided in an embodiment of this disclosure. Figure 8 As shown, in some embodiments, the address comparison circuit 21 includes M comparison sub-circuits 211 ( Figure 8 Only one label 211 is shown in the figure. The first input terminal of each comparator sub-circuit 211 receives a bit of input sub-signal External Add[b], the second input terminal of each comparator sub-circuit 211 receives a bit of fuse sub-signal eFuse Add[b], and the output terminal of each comparator sub-circuit 211 outputs a comparison signal Hit Add[b].

[0148] Comparator circuit 211 is used to compare the input sub-signal External Add[i] of the corresponding bit with the fuse sub-signal eFuse Add[i] and output the corresponding comparison signal Hit Add[i].

[0149] It should be noted that, as Figure 8 As shown, the comparator circuit 211 can be an XOR gate 211. For example, M = 8, and the remaining (BM) bits of the sub-signals are sub-signals [A] and [B], respectively. Specifically, if the input sub-signal External Add[i] is different from the corresponding bit's fuse sub-signal eFuse Add[i], the output comparator signal Hit Add[i] is high; if the input sub-signal External Add[i] is the same as the corresponding bit's fuse sub-signal eFuse Add[i] and they match, the output comparator signal Hit Add[i] is low. In other examples, the comparator circuit 211 can also be an XNOR gate, which will not be elaborated here.

[0150] like Figure 8 As shown, in some embodiments, the address selection circuit 22 may include: N selection sub-circuits 221 ( Figure 8 Only one label 221 is shown. The first input terminal (L terminal) of each selection sub-circuit 221 receives a comparison signal, the second input terminal (H terminal) of each selection sub-circuit 221 receives a bit input sub-signal, the control terminal of each selection sub-circuit 221 receives a selection control signal, and the output terminal of each selection sub-circuit 221 outputs an address selection signal.

[0151] Selector circuit 221 is used to output a comparison signal or input sub-signal as an address selection signal based on the control of the selection control signal.

[0152] It should be noted that, as Figure 8 As shown, the selection sub-circuit 221 can specifically be a 2-input data selector. Each selection sub-circuit 221 can receive its own selection control signal NFuse_en[q] (in this case, the M selection control signals NFuse_en[q] of the same redundant control circuit have the same level state), or the M selection sub-circuits can receive the same selection control signal NFuse_en.

[0153] For example, when the first selection control signal NFuse_en[1] is in a first level state (e.g., low level state), the comparison signal Hit Add[1] is selected from the comparison signal Hit Add[1] and the corresponding input address signal External Add[1] as the first address selection signal Hit Add Nen[1]; and when the first selection control signal NFuse_en[1] is in a second level state (e.g., high level state), the input address signal External Add[1] is selected from the comparison signal Hit Add[1] and the corresponding input address signal External Add[1] as the nth address selection signal Hit Add Nen[1].

[0154] In some embodiments, the address control circuit 23 may include: a three-level sub-control module (a first-level sub-control module 231, a second-level sub-control module 232, and a third-level sub-control module 233, respectively), each sub-control module including at least one logic unit;

[0155] Each logic unit of the first-level sub-control module 231 is connected to two outputs of the address selection circuit 22; or, each logic unit of the first-level sub-control module 231 is connected to one output of the address selection circuit 22 and one output of the address comparison circuit 21; or, each logic unit of the first-level sub-control module 231 is connected to two outputs of the address comparison circuit 21.

[0156] Each logic unit of the second-level sub-control module 232 is connected to an output terminal of the first-level sub-control module 231 and a fuse control signal;

[0157] The logic unit of the third-level sub-control module 233 is connected to the output of the second-level sub-control module 232 and one output of the address comparison circuit 21.

[0158] For example, such as Figure 8 As shown, the first-level sub-control module 231 includes 5 logic units, the second-level sub-control module 232 includes 5 logic units, and the third-level sub-control module 233 includes 2 logic units.

[0159] It should be noted that the fuse control signal eFuse_en can control whether to shield the signal at the other input terminal of the corresponding logic unit. When shielded, the output of the logic unit is not affected by the signal at the other input terminal; when not shielded, the output of the logic unit is determined by both input terminals. In addition, the fuse control signal can be applied from an external device of the redundant control circuit 20, or it can be stored in the fuse (not the fuse in the aforementioned first fuse group or second fuse group), without specific limitations.

[0160] Specifically, such as Figure 8 As shown, the logic units in the first-level sub-control module 231 and the second-level sub-control module 232 are NAND gates, and the logic units in the third-level sub-control module 233 are AND gates (NAND gate + NOT gate). The NAND gate in the first-level sub-control module 231 is denoted as the first NAND gate a1 ( Figure 8 Only one label (a1) is shown in the diagram. The NAND gate in the second-level sub-control module 232 is denoted as the second NAND gate (b1). Figure 8 Only one label (b1) is shown. The AND gate in the third-level sub-control module 233 consists of a third NAND gate u1 and a NOT gate u2. The input of the NOT gate u2 is connected to the output of the third NAND gate u1, and the output of the NOT gate u2 outputs the activation signal RSWL Enable. In other embodiments, the NAND gate can be replaced with an AND gate, the AND gate can be replaced with a NAND gate, or they can be combined, etc. Here, only one label (b1) is shown. Figure 8 For example, as shown in the figure.

[0161] It should also be noted that this example uses B as an even number. If B is an odd number, the higher bit (BM) can be used as one bit of the comparison signal (e.g., bit B) and directly input into the third NAND gate 223.

[0162] Here, the level of the fuse control signal eFuse_en received by each second NAND gate b1 is related to whether the output of the first NAND gate a1 needs to be shielded (that is, whether the input of the first NAND gate a1 needs to be shielded). The signal Hit output by the second NAND gate can be recorded as the hit signal.

[0163] Combination Figure 5 and Figure 8 As shown, the information of the shared fuse sub-signal eFuse Add T2 j[1:M] is input together into the redundant control circuits T1<1:N / 2> and T2<1:N / 2>. Each redundant control circuit T1 utilizes the redundant address line RSWL1. <0> ~RSWL1 <n>Repairing defective address lines SWL <0> ~SWL <n>In this scenario, when the selection control signal NFuse_en (which contains fuse information for each redundant storage layer) changes to "H", the input sub-signal is selected instead of the comparison signal, and the input sub-signal is output as the address selection signal. Since eFuseAdd[1:M] is not used, the fuse boxes of the two fuse storage layers can share these M-bit fuse sub-signals and achieve individual repair. Here, M+1 bits and / or more fuse sub-signals are input differently to each redundant control circuit.

[0164] In this way, every two redundant memory layers can share fuse sub-signals, thus reducing the total number of fuses and the number of latches required for decoding. For example, if the number of address lines in the memory layer N=2 7 =128, M=6, a repair unit includes two redundant address lines, and the fuse address signal of an address unit is 11 bits: eFuse Add[1:11]. If the fuse sub-signals are not shared, the number of fuses / latches required for 2 redundant storage layers is: 11×64×2 = 1408, where 11 is the number of fuses in a fuse group / fuse, 64 is the number of repair units in a redundant storage layer, and 2 is the number of two redundant storage layers. After sharing the 6-bit fuse sub-signal eFuseAdd[1:6], the required number of fuses / latches is: (5×64×2)+(6×64×1)=1024, where 5 is the number of non-shared fuse sub-signals, which is still calculated in the aforementioned way, and 6 is the number of shared fuse sub-signals, which is halved based on the aforementioned calculation method. The final fuse reduction effect is (1408-1024) / 1408=27%, and this calculation result is only for the case where one of the two redundant layers is repaired and the other layer is repaired separately.

[0165] In summary, this disclosure provides a memory layer repair scheme for 3D DRAM. When repairing an entire WL or BL layer in 3D DRAM due to manufacturing process issues, the number of fuses is reduced by sharing fuse sub-signals used to distinguish each WL / BL in the memory layer. In short, to address process faults caused by 3D stacked WL / BL, all redundant WL / BL layers should be used, requiring eFuses to store addresses. For a large number of redundant WL / BL layers, a large number of eFuses are needed. For layers with the aforementioned defects, existing methods use a one-to-one redundant WL / BL repair method. However, in this disclosure, when the entire memory layer is defective due to a process fault caused by 3D stacked WL / BL layers, the total number of eFuses is reduced by sharing eFuses. Thus, when process defects exist in the early stages of 3D DRAM development, the two fuse boxes in the redundant memory layer share fuses to control the number of fuses, which has the advantages of reducing fuse array area / volume and improving layout convenience.

[0166] In another embodiment of this disclosure, see Figure 9 This illustration shows a schematic diagram of the composition structure of a memory provided in an embodiment of this disclosure. For example... Figure 9 As shown, the memory 30 includes: a normal storage area 31, a redundant storage area 32, a fuse array 33, and multiple redundant control circuits 20; the normal storage area 31 includes multiple normal storage layers; the redundant storage area 32 includes multiple redundant storage layers.

[0167] The redundant control circuit 20 is used to output an activation signal for whether to activate the repair unit corresponding to the B-bit fuse sub-signal based on the B-bit input sub-signal and the B-bit fuse sub-signal; the B-bit fuse sub-signal is the B-bit fuse sub-signal stored in the first fuse group or the second fuse group.

[0168] It should be noted that the specific implementation and function of each component in the memory 30 can be understood by referring to the description of the foregoing embodiments, and will not be repeated here.

[0169] For memory 30, it can be SRAM, DRAM, SDRAM, DDR SDRAM, etc., and there is no specific limitation here.

[0170] Furthermore, in some embodiments, the memory 30 may include a DRAM chip. The DRAM chip may conform to memory specifications such as DDR, DDR2, DDR3, DDR4, DDR5, and DDR6, as well as LPDDR, LPDDR2, LPDDR3, LPDDR4, LPDDR5, and LPDDR6; no specific limitation is made here.

[0171] In this embodiment of the disclosure, for the memory 30, since it includes the aforementioned redundant control circuit 20 and fuse array, in the 3D DRAM structure, unused fuse sub-signals during full-layer repair of the memory layer can be shared by two fuse boxes to reduce the total number of fuses and save memory area.

[0172] In another embodiment of this disclosure, see [reference needed]. Figure 10 This illustration shows a schematic diagram of the structural composition of an electronic device provided in an embodiment of this disclosure. For example... Figure 10 As shown, the electronic device 40 includes the aforementioned memory 30.

[0173] It should be noted that electronic device 40 can be such as a computer, smartphone, tablet computer, laptop computer, handheld computer, wearable device, etc., without specific limitations.

[0174] The above description is merely a preferred embodiment of this disclosure and is not intended to limit the scope of protection of this disclosure.

[0175] It should be noted that, in this disclosure, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0176] The sequence numbers of the embodiments disclosed above are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0177] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0178] The features disclosed in the several product embodiments provided in this disclosure can be combined arbitrarily without conflict to obtain new product embodiments.

[0179] The features disclosed in the several method or device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method or device embodiments.

[0180] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure.< / n> < / n> < / j> < / j> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n>

Claims

1. A fuse array, characterized in that, The fuse array is configured in a memory that includes a normal storage region and a redundant storage region, wherein the normal storage region includes multiple normal storage layers and the redundant storage region includes multiple redundant storage layers. The fuse array includes at least one first fuse group and at least one second fuse group. Both the first fuse group and the second fuse group include B fuses, and each second fuse group shares M fuses in the first fuse group with one first fuse group. B and M are both positive integers, and M is less than B. Each fuse is used to store one bit of fuse sub-signal. Wherein, the B-bit fuse sub-signal stored in the first fuse group corresponds to the address of a defective cell in a normal storage layer, and the (BM)-bit fuse sub-signal stored in the remaining (BM) fuses in the second fuse group that are not shared with the first fuse group corresponds to the address of another normal storage layer to be repaired.

2. The fuse array according to claim 1, characterized in that, A portion of the multi-layer redundant storage layer is used to repair the defective unit, and another portion of the multi-layer redundant storage layer is used to repair the normal storage layer that needs to be repaired in its entirety.

3. The fuse array according to claim 1, characterized in that, In the first fuse group, the fuse sub-signals stored in the shared M fuses are the lower M-bit fuse sub-signals among the B fuse sub-signals.

4. The fuse array according to claim 1, characterized in that, The normal storage layer includes multiple address units, each address unit including at least one address line, and the defective unit is an address unit including at least one defective address line; the redundant storage layer includes multiple repair units, each repair unit including at least one redundant address line. When the defective unit includes an address line, the address line is a defective address line; When the defective unit includes multiple address lines, at least one of the multiple address lines is a defective address line; Each address unit in the normal storage layer to be repaired is a defective unit, or the proportion of defective units in the normal storage layer to be repaired exceeds a preset proportion threshold.

5. The fuse array according to claim 4, characterized in that, The normal storage layer includes N address lines, and the defective cell corresponding to the first fuse group contains 2 address lines. K 1, N=2 M+K , where K is an integer greater than or equal to 0.

6. The fuse array according to any one of claims 1 to 5, characterized in that, The number of the at least one first fuse group is the same as the number of the at least one second fuse group.

7. The fuse array according to any one of claims 1 to 5, characterized in that, The number of the second fuse group is the same as the number of the normal storage layers to be repaired.

8. A redundant control circuit, characterized in that, The redundancy control circuit is configured in a memory including a normal storage region and a redundant storage region, wherein the normal storage region includes multiple normal storage layers, and the redundant storage region includes multiple redundant storage layers. The redundancy control circuit includes: An address comparison circuit is used to receive a B-bit input sub-signal and a B-bit fuse sub-signal; the B-bit fuse sub-signal is the B-bit fuse sub-signal stored in the first fuse group or the second fuse group in the fuse array as described in any one of claims 1 to 7; The address comparison circuit is also used to compare the B-bit input sub-signal and the B-bit fuse sub-signal to obtain B comparison signals; output the M comparison signals corresponding to the shared M-bit fuse sub-signal to the address selection circuit, and output the remaining (BM) comparison signals to the address control circuit. The address selection circuit is used to select the M comparison signals or the corresponding M input sub-signals as M address selection signals based on the selection control signal, and output them to the address control circuit. The address control circuit is used to perform logical processing on the M address selection signals and the remaining (BM) comparison signals to output an activation signal for whether to activate the repair unit corresponding to the B-bit fuse sub-signal.

9. The redundancy control circuit according to claim 8, characterized in that, The address comparison circuit includes M comparison sub-circuits. The first input terminal of each comparison sub-circuit receives one bit of the input sub-signal, the second input terminal of each comparison sub-circuit receives one bit of the fuse sub-signal, and the output terminal of each comparison sub-circuit outputs the comparison signal. The comparator circuit is used to compare the input sub-signal and the fuse sub-signal of the corresponding bit, and output the corresponding comparison signal.

10. The redundancy control circuit according to claim 8, characterized in that, The address selection circuit includes M selection sub-circuits. The first input terminal of each selection sub-circuit receives a comparison signal, the second input terminal of each selection sub-circuit receives a bit of the input sub-signal, the control terminal of each selection sub-circuit receives the selection control signal, and the output terminal of each selection sub-circuit outputs the address selection signal. The selection sub-circuit is used to output the comparison signal or the input sub-signal as the address selection signal based on the control of the selection control signal.

11. The redundancy control circuit according to claim 8, characterized in that, The address control circuit includes three levels of sub-control modules, and each level of the sub-control module includes at least one logic unit. Each logic unit of the first-level sub-control module is connected to two outputs of the address selection circuit; or, each logic unit of the first-level sub-control module is connected to one output of the address selection circuit and one output of the address comparison circuit; or, each logic unit of the first-level sub-control module is connected to two outputs of the address comparison circuit. Each logic unit of the second-level sub-control module is connected to an output terminal of the first-level sub-control module and a fuse control signal; The logic unit of the third-level sub-control module is connected to the output of the second-level sub-control module.

12. The redundancy control circuit according to claim 11, characterized in that, The logic units in the first-level sub-control module and the second-level sub-control module are NAND gates, and the logic units in the third-level sub-control module are AND gates.

13. A memory, characterized in that, include: The system includes a normal storage region, a redundant storage region, a fuse array as described in any one of claims 1 to 7, and a plurality of redundant control circuits as described in any one of claims 8 to 12; the normal storage region includes multiple normal storage layers; the redundant storage region includes multiple redundant storage layers. The redundant control circuit is used to output an activation signal for whether to activate the repair unit corresponding to the B-bit fuse sub-signal based on the B-bit input sub-signal and the B-bit fuse sub-signal; the B-bit fuse sub-signal is the B-bit fuse sub-signal stored in the first fuse group or the second fuse group.

14. The memory according to claim 13, characterized in that, Each of the first fuse group and each of the second fuse groups corresponds to one of the redundant control circuits; The M fuses shared in the first fuse group are connected to a first redundant control circuit and a second redundant control circuit; The (BM) fuses that are not shared in the first fuse group are connected to the first redundant control circuit; The remaining (BM) fuses in the second fuse group that are not shared with the first fuse group are connected to the second redundant control circuit; The first redundant control circuit is the redundant control circuit corresponding to the first fuse group, and the second redundant control circuit is the redundant control circuit corresponding to the second fuse group.

15. The memory according to claim 14, characterized in that, In the redundant control circuit corresponding to the first fuse group, the B-bit fuse sub-signal is the B-bit fuse sub-signal stored in the first fuse group, and the selection control signal instructs the address selection circuit to select the M comparison signals as the M address selection signals; In the redundant control circuit corresponding to the second fuse group, the B-bit fuse sub-signal is the B-bit fuse sub-signal stored in the second fuse group, and the selection control signal instructs the address selection circuit to select M input sub-signals as the M address selection signals.

16. The memory according to claim 14, characterized in that, In the redundant control circuit corresponding to the first fuse group, the M address selection signals are the M comparison signals. The address control circuit is used to output an activation signal that activates the repair unit corresponding to the B-bit fuse signal when the B comparison signals indicate that the B-bit input sub-signal and the B-bit fuse sub-signal are both matched. Otherwise, the output will not activate the repair unit corresponding to the B-bit fuse sub-signal; In the redundant control circuit corresponding to the second fuse group, the M address selection signals are the M input sub-signals. The address control circuit is used to shield the M input sub-signals and, when the (BM) bit input sub-signals and (BM) bit fuse sub-signals corresponding to the remaining (BM) comparison signals are all matched, output an activation signal to activate the repair unit corresponding to the B bit fuse sub-signal; otherwise, output an activation signal not to activate the repair unit corresponding to the B bit fuse signal.

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